UNITED INTERNATIONAL UNIVERSITY (UIU)

Dept. Of Electrical & Electronic Engineering (EEE)

Final Assignment, Trimester: Spring, Year: 2020
Course: EEE 441 (Sec – A), Title: VLSI Design
Marks: 80

• There are 4 questions. Answer them all. Figures in the right-hand margin indicate full
marks.
• Answer all the subparts of a particular question in one place of your answer script. Marks
will be deducted for answering subparts in a scattered manner.

1. a) Write the truth table of the Verilog code below. [08]

module counter16bit ( q, rco, clr, ld, in, en, clk );

output reg [15:0] q; Module Ports:
output rco; q = output
input clk, clr, ld, en; rco = ripple carry output
input [15:0] in; clr = clear
ld = load
assign rco = (q == 0); in = input
always @ ( posedge clk or negedge clr ) begin en = enable
if( ~clr ) clk = clock
q = 16'hffff;
else if ( ld )
q = in;
else if ( en )
q = q - 1;
else
q = q;
end
endmodule

b) Use the counter16bit module in Q1(a) to write 32-bit hierarchical structural Verilog [08]
module: counter32bit having the same functionality.

c) Write a test bench for your code at Q1(b) to create a free flowing modulo-X down [08]
counter where X=UIU_ID (i.e. the counter will load your UIU ID as starting value and
countdown to 0 (zero), then load again and continue).

d) The modulo-X counter in Q1(c) may be used as timer for interrupt controller and [06]
generate interrupt signals every time the counter hits zero(0). Assuming the clock is
running at 4GHz:
i) Calculate the delay between each interrupt signal.
ii) Calculate the value of X needed to create the interrupt signal every 50 ms.

2. a) True/False: [05]
i) Both ROM and RAM are random access memory
ii) EPROM can be programmed only once while EEPROM can be
programmed multiple times.
 iii) Flash memories are a type of EEPROM.
iv) DRAM is volatile while SRAM is non-volatile.
v) CAM can be used to build cache memory.

b) For the circuit shown, determine a test vector for detecting the fault (if testable) [10]
i) β stuck-at-1
ii) β stuck-at-0
w
●
f
x ● x● ●
β
g
y ●
z

3. Draw schematic and stick diagram for Domino CMOS PLA implementation of [20]

𝑤 = 𝐴𝐵𝐶 + 𝐵 𝐷
𝑥 = 𝐴 + 𝐶𝐷
𝑦 = 𝐴𝐵 + 𝐶𝐷 + 𝐵 𝐷
𝑧 = 𝐴𝐵𝐶 + 𝐴𝐵 + 𝐶𝐷 + 𝐵 𝐷 = 𝑤 + 𝐴𝐵 + 𝐶𝐷

(Note: You do not need to include the optional input inverters used to perform true and
complement pairs for the input signals.)

4. a) Draw block diagram of a 32-bit Carry Select Adder with 4-bit Ripple Carry Adder and [05]
2-to-1 Multiplexer.

b) Gate level circuits of 1-bit Full Adder and 2-to-1 Mux are given below:

HA HA
2-to-1 MUX
1-bit Full Adder

Gate delays are: XOR = 200ps, NAND = 125ps and NOT = 50ps

Calculate the maximum frequency of the circuit in Q4(a) [10]

   
(VGS − VT )2
2
VDS
I DS ,triode =  (VGS − VT )VDS −  I DS , P.O. = VT = VT 0 +  VSB g m =  .(VGS − VT )
2
 2 

2 Z pd VOUT , no pass =
98 9/4
VIN = VT 1 − VT 2 = VT 1 − VT 2 VOUT , pass =
1 Z pu Z pu Z pd Z pu / Z pd

 Z pu   Z pu   2   2   W 2 L2  1 W L 
  =2    =
1
    =  2 2 
Z  Z 
 pd  pass  pd  no pass  1  pass 2  1  no pass  W1 L1  pass 2  W1 L1  no pass

P
VTN + (VDD + VTP ) S = ABC + COUT ( A + B + C ) C OUT = AB + C ( A + B)
N
VIN =
P L
1+ R = RS . Z  = RS .  1 sq = 2  2
N W
 ox 3.45 10 −11 F / m 3.C L 3.C L
Cox = =  0.9 fF / m 2 t rise , NMOS  t fall , NMOS 
tox 400 10 m−10
 2 .Vdd 1 .Vdd
4C L 4C L
2t p t rise , CMOS  t fall , CMOS 
   PVdd  N Vdd
rc
2C L 2 2C L 2
t PHL  = R gateN C L R gateN = t PLH  = R gateP C L R gateP =
 N Vdd  N Vdd  PVdd  PVdd
4C L 2C L 2C L 4C L
t PLH , NMOS pass = t PHL , NMOS pass = t PLH , PMOS pass = t PHL , PMOS pass =
 N Vdd  N Vdd  PVdd  PVdd

t PHL(trans) = ( R gateN || 2 R gateP )C L t PLH (trans) = (2 R gateN || R gateP )C L

WN  ins 0  N WP  ins 0  P
N = KN , and KN = P = KP , and KP =
LN D LP D

COUT = Cdiff + Cm1 CIN = Cpoly + Cm1 + Cgate

Cdiff = Cja [WL] + Cjp [perimeter] Cgate = Kgate [WL]
Cm1 = Km1 [WL] Cpoly = Kpoly [WL]

P N
I SD = VSG − | VTP |2 I DS = VGS − VTN 2
2 2