Verilog (About Tool and Steps)
Verilog (About Tool and Steps)
ABOUT TOOL
In VLSI field, hardware description language (HDL) is a specific coding used to portray the
structure and conduct of electronic circuits, and most ordinarily, advanced digital circuits.
Hardware description language empowers an exact, formal description of an electronic circuit
that takes into account the computerized examination and recreation of an electronic circuit. It
additionally considers the blend of an HDL depiction into a netlist (a detail of physical electronic
parts and how they are associated together), which would then be able to be set and steered to
deliver the arrangement of veils used to make a coordinated circuit.
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to
model electronic systems. It is most commonly used in the design and verification of digital
circuits at the register-transfer level of abstraction. It is also used in the verification of analog
circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the
Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE
Standard 1800-2009. Since then, Verilog is officially part of the SystemVerilog language. The
current version is IEEE standard 1800-2017.
Steps of Simulation:-
3. In the next window click on verilog file and module. Also click on verilog 2005 (below)
and then click on Next.
4. Now fill in module name (should not be a keyword). Click on Finish.
5. Now the main window opens where the code has to be written. Write your and save it to
check any error.
6. Simulate the code.
7. Then Modelsim window will open.
Figure 1. Modelsim Main Window
8. Click on view---object
9. Now in the object window click on Add---Wave---signals in design (as shown
below)
10. Now click on a signal and the click: edit -> force . You can change the value from U
(Undefined) to 0 or 1.(as shown below). Similarly you can give values to all the input
signals so that you can verify from the output signal whether they behave according to
the logic.
Figure 3. Assigning value to the variable
11. You can also directly change the value by right clicking on the variable---force.