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Verilog (About Tool and Steps)

Verilog is a hardware description language used to model digital circuits. It allows modeling at the register-transfer level of abstraction. Modelsim is a simulator used to simulate Verilog code and view waveforms of signals. HDL Designer is a tool used for writing, managing, and checking Verilog code. It helps accelerate RTL reuse. Precision RTL is a synthesis tool used to synthesize Verilog code into a gate-level netlist. The steps involve writing Verilog code in HDL Designer, simulating it in Modelsim to view waveforms, then synthesizing the code using Precision RTL.

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51 views

Verilog (About Tool and Steps)

Verilog is a hardware description language used to model digital circuits. It allows modeling at the register-transfer level of abstraction. Modelsim is a simulator used to simulate Verilog code and view waveforms of signals. HDL Designer is a tool used for writing, managing, and checking Verilog code. It helps accelerate RTL reuse. Precision RTL is a synthesis tool used to synthesize Verilog code into a gate-level netlist. The steps involve writing Verilog code in HDL Designer, simulating it in Modelsim to view waveforms, then synthesizing the code using Precision RTL.

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uday
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
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Verilog Programming [ECE424]

ABOUT TOOL
In VLSI field, hardware description language (HDL) is a specific coding used to portray the
structure and conduct of electronic circuits, and most ordinarily, advanced digital circuits.
Hardware description language empowers an exact, formal description of an electronic circuit
that takes into account the computerized examination and recreation of an electronic circuit. It
additionally considers the blend of an HDL depiction into a netlist (a detail of physical electronic
parts and how they are associated together), which would then be able to be set and steered to
deliver the arrangement of veils used to make a coordinated circuit.
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to
model electronic systems. It is most commonly used in the design and verification of digital
circuits at the register-transfer level of abstraction. It is also used in the verification of analog
circuits and mixed-signal circuits, as well as in the design of genetic circuits. In 2009, the
Verilog standard (IEEE 1364-2005) was merged into the SystemVerilog standard, creating IEEE
Standard 1800-2009. Since then, Verilog is officially part of the SystemVerilog language. The
current version is IEEE standard 1800-2017.

The following tools are used to model electronic system:


Modelsim SE simulator ( version 10.2b):- ModelSim is a multi-language HDL reenactment
tool by Mentor Graphics, for recreation of equipment portrayal dialects, for example, Verilog,
VHDL and SystemC, and incorporates an inherent C debugger. ModelSim can be utilized freely,
or related to Intel Quartus Prime, Xilinx ISE or Xilinx Vivado. Reenactment is performed
utilizing the graphical UI (GUI), or consequently utilizing contents.
HDL Designer (version 2017.1a) :- HDL Designer combines deep analysis capabilities,
advanced creation editors, and complete project and flow management, to deliver a powerful
HDL design environment that increases the productivity of individual engineers and teams (local
or remote) and enables a repeatable and predictable design process.
Key Benefits:
 Manages complex ASIC or FPGA designs in VHDL, Verilog and SystemVerilog
 Accelerates RTL Reuse
 Extensive design checking rules and rulesets
 Interactive HDL visualization and creation tools
 Automatic documentation features and reporting
 Intelligent debug and analysis
 Concurrent design entry and checking

Precision RTL Synthesis (version 2012b.10) :- High-level synthesis (HLS), sometimes


referred to as C synthesis, electronic system-level (ESL) synthesis, algorithmic synthesis,
or behavioral synthesis, is an automated design process that interprets an algorithmic description
of a desired behavior and creates digital hardware that implements that behavior. The code is
analyzed, architecturally constrained, and scheduled to transcompile into a register-transfer
level (RTL) design in a hardware description language (HDL), which is in turn commonly
synthesized to the gate level by the use of a logic synthesis tool. Precision RTL is Mentor
Graphics’ entry-level FPGA synthesis solution offering excellent quality of results and part of
Mentor Graphics’ comprehensive FPGA vendor independent solution.

Steps of Simulation:-

1. Open HDL designer software. Then go to FILE---NEW---PROJECT


2. Then a window will open. Fill in the necessary details like project name, etc as shown
below. Click on Next button.

3. In the next window click on verilog file and module. Also click on verilog 2005 (below)
and then click on Next.
4. Now fill in module name (should not be a keyword). Click on Finish.
5. Now the main window opens where the code has to be written. Write your and save it to
check any error.
6. Simulate the code.
7. Then Modelsim window will open.
Figure 1. Modelsim Main Window

8. Click on view---object
9. Now in the object window click on Add---Wave---signals in design (as shown
below)

Figure 2. Signal Design Window

10. Now click on a signal and the click: edit -> force . You can change the value from U
(Undefined) to 0 or 1.(as shown below). Similarly you can give values to all the input
signals so that you can verify from the output signal whether they behave according to
the logic.
Figure 3. Assigning value to the variable

11. You can also directly change the value by right clicking on the variable---force.

Figure 4. Output/Wave Window

We can also change the background colour in modelsim window---Tools---Edit preference.

12. Now synthesis needs to be done by Precision RTL sythesis


13. Once the synthesis is done different reports needs to be generated along with RTL
schematic and Tech Schematic.

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