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1 1

Compal Confidential
Pixar AMD M/B LA-9851P Schematics Document
2 2

AMD Richland APU / Bolton FCH M3

Date : 2012-11-07

Version T0.1
3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 1 of 47
A B C D E
 A B C D E

Compal Confidential
Model Name : VPU00 AMD

1 1

AMD Richland
APU HDMI
HDMI Conn. (UMA / Muxless)
page 19 AMD Richland APU Memory BUS(DDR3)
eDPX2 DP2 204pin DDRIII-SO-DIMM X2
2 CH Dual Channel BANK 0, 1, 2, 3 Page 11,12
LVDS Trinity FP2
1.5V DDRIII 1333/1600MHz
2 CH Translator
DP0 BGA 813- Ball
LVDS Conn. RTD2136S 27mm x 31mm
page 20
page 18 P_GPP x 3
Page 6~10
GEN1 DP1
Daughter board
Transformer / RJ45 NIC GPP0 UMI USB20 USB30 CMOS WWAN
2
page 24
RTL8151GSH-CG
page 24 USB Charger M/B*2 2
Camera NGFF SIM
page 24
page 27 page 26 page 20 page 21

USB 2.0 Port 10 Port 5 Port 6

GPP1 GPP3 USB 3.0 Port 0,1
USB USB 2.0 Port 10,11
SD/ MMC slot FCH 3.3V 48MHz
USB 2.0 Port 8 MINI Card 1 page 25
(Wireless LAN with BT) Bolton M3
SATA3.0 reserve
page 23 uFCBGA-656
X1

Card Reader SATA repeater

RTS5239-GR Page 13~17 page 22
Sub board
Gen3 6Gb/s
LPC BUS port 0
3
3.3MHz HD Audio 3

3.3V 24MHz SATA HDD

page 22
G-Sensor
ENE
LED KBC9012
page 32
HDA Codec SPK Accelerometer
page 38 IDT 92HD91 page 31 HP3DC2
page 28
Page 36
SMBus (FCH)
RTC CKT. Touch Pad Int.KBD
page 13 Daughter board page 33 page 33
HP Amp Sub Woofer
page 30 Amp page 29 BIOS ROM
Power On/Off CKT. Power/B FAN/LED
page 34
page 34 Sub board SPI SYS BIOS (4M)
page 14
Combo Sub Woofer
Fan Control jack page 31 page 31
4
page 34 4

DC/DC
Interface CKT.page 37 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
SCHEMATIC, MB A9851
Power Circuit THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size
B
Document Number Rev
A
page 38~46 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019NK
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 2 of 47
A B C D E
 5 4 3 2 1

CLOCK DISTRIBUTION DISPLAY OUTPUT

B_SODIMM

A_SODIMM
D D
MEM_MB_CLK7_P/N
MEM_MB_CLK1_P/N

MEM_MA_CLK7_P/N
MEM_MA_CLK1_P/N
1066~1866MHz

1066~1866MHz

LVDS CONN

APU_TXOUT[0:2]+/-
APU_TXOUT_CLK+/-
APU_TZOUT[0:2]+/-
APU_TZOUT_CLK+/-
APU_LVDS_CLK/DATA

APU_DISP_CLKP/N

C AMD 100MHz AMD LVDS_OUT C

ANX3112
APU FP2 SOCKET
FCH DP_IN
APU_CLKP/N Hudson-M2/M3
100MHz Internal CLK GEN

DP0_AUX GPP_CLK
100MHz

LVDS Transtator 32.768KHz 25MHz

DP0_TXP/N[0:1]
DP0_AUXP/N

B
GPP4 GPP3 GPP2 GPP1 GPP0 DP0 B

WLAN WLAN PCIE_GFX[0:15]

USB30 M/B USB30 SUS/B
OPT PCI Socket Mini PCI Socket
GbE LAN APU
DP1 DP2

25MHz

HDMI CONN
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
SCHEMATIC, MB A9851
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 3 of 47
5 4 3 2 1
 A B C D E

Voltage Rails
SIGNAL
Power Plane Description S1 S3 S5 STATE SLP_S1# SLP_S3# SLP_S4# SLP_S5# +VALW +V +VS Clock

VIN Adapter power supply (19V) N/A N/A N/A Full ON HIGH HIGH HIGH HIGH ON ON ON ON
B+ AC or battery power rail for power circuit. N/A N/A N/A
S1(Power On Suspend) LOW HIGH HIGH HIGH ON ON ON LOW
+CPU_CORE Core voltage for CPU ON OFF OFF

1
+CPU_CORE_NB Voltage for On-die VGA of APU ON OFF OFF S3 (Suspend to RAM) LOW LOW HIGH HIGH ON ON OFF OFF 1

+VGA_CORE 0.95-1.2V switched power rail ON OFF OFF

S4 (Suspend to Disk) LOW LOW LOW HIGH ON OFF OFF OFF
+VDDCI 0.95-1.2V switched power rail ON OFF OFF
+0.75VS 0.75V switched power rail for DDR terminator ON ON OFF S5 (Soft OFF) LOW LOW LOW LOW ON OFF OFF OFF
+1.0VSG 1.0V switched power rail for VGA ON OFF OFF
+1.1ALW 1.1V switched power rail for FCH ON ON ON* Board ID / SKU ID Table for AD channel
+1.1VS 1.1V switched power rail for FCH ON OFF OFF Vcc 3.3V +/- 5%
+1.2VS 1.2V switched power rail for APU ON OFF OFF Ra/Rc/Re 100K +/- 5%
+1.5V 1.5V power rail for CPU VDDIO and DDR ON ON OFF Board ID Rb / Rd / Rf V AD_BID min V AD_BID typ V AD_BID max
+1.5VS 1.5V switched power rail ON OFF OFF 0 0 0 V 0 V 0 V
+1.8VSG 1.8V switched power rail ON OFF OFF 1 8.2K +/- 5% 0.216 V 0.250 V 0.289 V
+2.5VS 2.5V for CPU_VDDA ON OFF OFF 2 18K +/- 5% 0.436 V 0.503 V 0.538 V USB Port Table
+3VALW 3.3V always on power rail ON ON ON* 3 33K +/- 5% 0.712 V 0.819 V 0.875 V 1 External
+3V_LAN 3.3V power rail for LAN ON ON ON
USB 2.0 USB 1.1 Port
4 56K +/- 5% 1.036 V 1.185 V 1.264 V USB Port
+3VS 3.3V switched power rail ON OFF OFF 5 100K +/- 5% 1.453 V 1.650 V 1.759 V 0 USB2.0 (left side)
+5VALW 5V always on power rail ON ON ON*
UHCI0
6 200K +/- 5% 1.935 V 2.200 V 2.341 V 1
2
+5VS 5V switched power rail ON OFF OFF 7 NC 2.500 V 3.300 V 3.300 V 2 2

+VSB VSB always on power rail ON ON ON*

UHCI1
3
+RTCVCC RTC power ON ON ON
EHCI1
4
Note : ON* means that this power plane is ON only with AC power available, otherwise it is OFF.
UHCI2
BOM Option Table BOM Config 5 Camera
6
BOM UHCI3
Audio Codec SSID Structure Description UMA 7
V 8 BT
UHCI4
Platform Platform ID 9
Evora 1.0 UMA 0x18DE
10 USB2.0 (Right side)
EHCI2 UHCI5
11 USB2.0 (Right side)
12
UHCI6
13
x = 1 is read cmd, x= 0 is writee cmd.

External PCI Devices 1 External

USB 3.0 Port
USB Port
Device IDSEL# REQ#/GNT# Interrupts
0 USB3.0 (Right side)
3 1 USB3.0 (Right side) 3

2
3

SMBUS Control Table

EC SM Bus1 address EC SM Bus2 address
EC_SMB_CK2 EC_SMB_CK1
Device Address HEX Device Address HEX BATT Charger G-Sensor TP
SOURCE HP Amp MINI3 SODIMM EC_SMB_DA2 EC_SMB_DA1
Smart Battery 0001 011X b 16H ADI ADM1032 (GPU) 1001 101X b 9AH
SB-TSI (APU) 1001 100X b 98H
LVDS TR( RTD-2132S) 1010 100X b A8H
EC_SMB_CK1
EC_SMB_DA1
KB932 V V V
VGA Internal Thermal 1000 001X b 82H
EC_SMB_CK2
EC_SMB_DA2
KB932 V
FCH_SCLK0
FCH FCH FCH_SDATA0 FCH V
4 SM Bus 0 address SM Bus 1 address FCH_SCLK1 FCH 4

Device Address HEX Device Address HEX

FCH_SDATA1 V
DDR DIMM1 1101 000X b 90
DDR DIMM2 1101 001X b 94
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 4 of 47
A B C D E
 5 4 3 2 1

AMD APU FS1R2

BATTERY BATT+ PU21 PU27 +CPU_CORE
12.6V CHARGER ISL6277HRTZ-T 0.7~1.475V VDD CORE 60A
+CPU_CORE
BQ24725RGRR 0.7~1.475V VDDNB 37A
+CPU_CORE_NB +CPU_CORE_NB
+2.5VS +2.5VS VDDA 750mA
+2.5VS
+1.5V VDDIO 3.2A
PU26 +1.5V +1.5V
D AC ADAPTOR VIN RT8207MZQW +1.2VS VDDR 8.5A D
19V 90W +0.75VS PU15 +1.2VS
APL5508
RAM DDRIII SODIMMX2
PU17 +1.2VS +1.5V VDD_MEM 4A
RT8209MGQW
B+ +0.75VS VTT_MEM 0.5A

+0.75VS
+0.75VS
VGA ATI
+VGA_CORE Whistler/Seymour/Granville
PU10
+VGA_CORE 0.85~1.1V VDDC 47A
TPS51218DSCR
+VDDCI
0.9~1.0V VDDCI 4.6A
+VDDCI
+1.0VSG DPLL_VDDC: 125 mA
PU14 SPV10: 120 mA
G9731G11U +1.0VSG PCIE_VDDC: 2000 mA
DP[A:E]_VDD10: 680 mA
+1.5VSG VRAM 512/1GB/2GB
U41
+1.5VSG VDDR1: 3400 mA 64M / 128Mx16 * 4 / 8
AO4430L
PU5 +1.1VALW
RT8209MGQW PLL_PVDD: 75 mA +1.5VSG 2.4 A
TSVDD: 20 mA
AVDD: 70 mA
C VDD1DI: 100 mA C
VDD2DI: 50 mA
A2VDDQ: 1.5 mA
PU2 +3VALW
VDD_CT: 110 mA
RT8205EGQW U40 PU7
VDDR4: 170 mA
+5VALW SI4800 SY8033BDBC +1.8VSG +1.8VSG
+1.8VSG
PCIE_PVDD: 40 mA
MPV18: 150 mA
SPV18: 75 mA

+3VS
PCIE_VDDR: 400 mA
DP[A:F]_VDD18: 920 mA
DP[A:F]_PVDD: 120 mA
+INVPWR_B+

+3VS
JUMP +3VSG A2VDD: 130 mA
U38 +3VSG +3VSG VDDR3: 60 mA
SI4800

LCD panel +5VS FCH AMD Hudson M2/M3

15.6"
VDDPL_11_DAC: 7 mA
VDDAN_11_ML: 226 mA
B+ 300mA U39 VDDCR_11: 1007 mA
AO4430L +1.1VS +1.1VS
+3.3 350mA +1.1VS VDDAN_11_CLK: 340 mA
VDDAN_11_PCIE: 1088 mA
VDDAN_11_SATA: 1337 mA

+5VS VDDAN_11_USB_S: 140 mA

FAN Control VDDCR_11_USB_S: 197 mA
B APL5607 +1.1VALW +1.1VALW VDDAN_11_SSUSB_S: 282 mA B
VDDCR_11_SSUSB_S: 424 mA
VDDCR_11_S: 187 mA
+5VS 500mA VDDPL_11_SYS: 70 mA
Q63
SI2301
U54 +5VALW VDDIO_33_PCIGP: 131 mA
TPA2301DRG4 VDDPL_33_SYS: 47 mA
+USB_VCCA
VDDPL_33_DAC: 20 mA
+3VS VDDPL_33_ML: 20 mA
+3VS +3VS VDDAN_33_DAC: 200 mA
VDDPL_33_PCIE: 43 mA
USB X3 VDDPL_33_SATA: 93 mA
+1.5VS

VDDIO_AZ_S: 26 mA
+5V
Dual+1
2.5A +3VALW VDDPL_33_SSUSB_S: 20 mA
+3VALW VDDPL_33_USB_S: 17 mA
VDDAN_33_USB_S: 658 mA
+3VALW
VDDIO_33_S: 59 mA
VDDXL_33_S: 5 mA
SATA Audio Codec EC LAN VDDAN_33_HWM_S: 12 mA
HDD*1 ALC271X ENE KB930 BCM57785 Mini Card*2
ODD*1
VDDIO_33_GBE_S
+5V 3A +5V 45mA +3.3VALW 30mA +3.3VALW 201mA +1.5VS 500mA VDDCR_11_GBE_S
+3.3VS 3mA +3.3VS 1A GND VDDIO_GBE_S
+3.3V +3.3VS 25mA +3.3VALW 330mA

RTC
A
Bettary RTC BAT VDDBT_RTC_G A

Security Classification Compal Secret Data

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
SCHEMATIC, MB A9851
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 5 of 47
5 4 3 2 1
 A B C D E

UCPU1A
AP1 AN1
AP2 P_GFX_RXP[0] P_GFX_TXP[0] AN2
AM1 P_GFX_RXN[0] P_GFX_TXN[0] AM4
AM2 P_GFX_RXP[1] P_GFX_TXP[1] AM3
1 AK3 P_GFX_RXN[1] P_GFX_TXN[1] AK2 1
AK4 P_GFX_RXP[2] P_GFX_TXP[2] AK1
AJ1 P_GFX_RXN[2] P_GFX_TXN[2] AH1
AJ2 P_GFX_RXP[3] P_GFX_TXP[3] AH2
AH4 P_GFX_RXN[3] P_GFX_TXN[3] AF3
AH3 P_GFX_RXP[4] P_GFX_TXP[4] AF4
AF2 P_GFX_RXN[4] P_GFX_TXN[4] AE1
AF1 P_GFX_RXP[5] P_GFX_TXP[5] AE2
AD1 P_GFX_RXN[5] P_GFX_TXN[5] AD4
P_GFX_RXP[6] P_GFX_TXP[6]
GPU AD2
AB3 P_GFX_RXN[6] P_GFX_TXN[6]
AD3
AB2

GRAPHICS
P_GFX_RXP[7] P_GFX_TXP[7]
Delete GPU AB4
AA1 P_GFX_RXN[7] P_GFX_TXN[7]
AB1
Y1
Delete GPU GPU
1202 Calvin P_GFX_RXP[8] P_GFX_TXP[8] 1202 Calvin
AA2 Y2
Y4 P_GFX_RXN[8] P_GFX_TXN[8] V3
Y3 P_GFX_RXP[9] P_GFX_TXP[9] V4
V2 P_GFX_RXN[9] P_GFX_TXN[9] U1
V1 P_GFX_RXP[10] P_GFX_TXP[10] U2
T1 P_GFX_RXN[10] P_GFX_TXN[10] T4
T2 P_GFX_RXP[11] P_GFX_TXP[11] T3
P3 P_GFX_RXN[11] P_GFX_TXN[11] P2
P4 P_GFX_RXP[12] P_GFX_TXP[12] P1
N1 P_GFX_RXN[12] P_GFX_TXN[12] M1
N2 P_GFX_RXP[13] P_GFX_TXP[13] M2
M4 P_GFX_RXN[13] P_GFX_TXN[13] K3
M3 P_GFX_RXP[14] P_GFX_TXP[14] K4
K2 P_GFX_RXN[14] P_GFX_TXN[14] J1
K1 P_GFX_RXP[15] P_GFX_TXP[15] J2
P_GFX_RXN[15] P_GFX_TXN[15]
AH5 AG7 PCIE_FTX_DRX_P0 CC1 1 2 .1U_0402_16V7K
24 PCIE_DTX_C_FRX_P0 P_GPP_RXP[0] P_GPP_TXP[0] PCIE_FTX_C_DRX_P0 24
GLAN 24 PCIE_DTX_C_FRX_N0
AH6
AG5 P_GPP_RXN[0] P_GPP_TXN[0]
AG8
AE7
PCIE_FTX_DRX_N0
PCIE_FTX_DRX_P1
CC2
CC3
1
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
PCIE_FTX_C_DRX_N0 24 GLAN
23 PCIE_DTX_C_FRX_P1 P_GPP_RXP[1] P_GPP_TXP[1] PCIE_FTX_C_DRX_P1 23
2
WLAN 23 PCIE_DTX_C_FRX_N1
AG6
AE6 P_GPP_RXN[1] P_GPP_TXN[1]
AE8
AD7
PCIE_FTX_DRX_N1 CC4 1 2 .1U_0402_16V7K
PCIE_FTX_C_DRX_N1 23 WLAN 2

AE5 P_GPP_RXP[2] P_GPP_TXP[2] AD8

AD6 P_GPP_RXN[2] P_GPP_TXN[2] AB6 PCIE_FTX_DRX_P3 CC5 1 2 .1U_0402_16V7K

GPP
25 PCIE_DTX_C_FRX_P3 P_GPP_RXP[3] P_GPP_TXP[3] PCIE_FTX_C_DRX_P3 25
Card reader 25 PCIE_DTX_C_FRX_N3
AD5
P_GPP_RXN[3] P_GPP_TXN[3]
AB5 PCIE_FTX_DRX_N3 CC6 1 2 .1U_0402_16V7K
PCIE_FTX_C_DRX_N3 25 Card reader
AM10 AN6 UMI_FTX_MRX_P0 CC7 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_P0 P_UMI_RXP[0] P_UMI_TXP[0] UMI_FTX_C_MRX_P0 13
AN10 AM6 UMI_FTX_MRX_N0 CC8 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_N0 P_UMI_RXN[0] P_UMI_TXN[0] UMI_FTX_C_MRX_N0 13
AN8 AP6 UMI_FTX_MRX_P1 CC9 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_P1 P_UMI_RXP[1] P_UMI_TXP[1] UMI_FTX_C_MRX_P1 13
UMI 13 UMI_MTX_C_FRX_N1
AM8
P_UMI_RXN[1] P_UMI_TXN[1]
AR6 UMI_FTX_MRX_N1 CC10 1 2 .1U_0402_16V7K
UMI_FTX_C_MRX_N1 13
13 UMI_MTX_C_FRX_P2
AP8
AR8 P_UMI_RXP[2] P_UMI_TXP[2]
AP4
AR4
UMI_FTX_MRX_P2
UMI_FTX_MRX_N2
CC11
CC12
1
1
2
2
.1U_0402_16V7K
.1U_0402_16V7K
UMI_FTX_C_MRX_P2 13 UMI
13 UMI_MTX_C_FRX_N2 P_UMI_RXN[2] P_UMI_TXN[2] UMI_FTX_C_MRX_N2 13
AR7 AP3 UMI_FTX_MRX_P3 CC13 1 2 .1U_0402_16V7K
13 UMI_MTX_C_FRX_P3 P_UMI_RXP[3] P_UMI_TXP[3] UMI_FTX_C_MRX_P3 13
AP7 AR3 UMI_FTX_MRX_N3 CC14 1 2 .1U_0402_16V7K

UMI
13 UMI_MTX_C_FRX_N3 P_UMI_RXN[3] P_UMI_TXN[3] UMI_FTX_C_MRX_N3 13

+1.2VS 1 2 P_ZVDDP AR11 AP11 P_ZVSS 1 2

RC1 196_0402_1% P_ZVDDP P_ZVSS RC2 196_0402_1%
RICHLAND-A8-SERIES_BGA813

10/4 Eric chagne back on RC1 & RC2.

L P_ZVSS W/S=8/12 mil, <3000mil

L P_ZVDDP W/S=8/12 mil, <3000mil

3 3

+3VS CPU THERMAL SENSOR

0.1U_0402_16V4Z

1
CC173

2
UC1 SA00003PU00
1 8 EC_SMB_CK2
VDD SCLK EC_SMB_CK2 18,30,32,8
H_THERMDA 2 7 EC_SMB_DA2
D+ SDATA EC_SMB_DA2 18,30,32,8
CC174
1 2 H_THERMDC 3 6 THERMAL_ALERT# 2 1 +3VS
2200P_0402_50V7K D- ALERT# RC105 10K_0402_5%
CPU_THERM# 4 5
THERM# GND
+3VS 1 2
THERMAL_ALERT# 32
RC106 33K_0402_5% ADM1032ARMZ-2REEL_MSOP8

Address:0100_1100 EMC1402-1
Address:0100_1101 EMC1402-2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 6 of 47
A B C D E
 A B C D E

UCPU1C
UCPU1B 12 DDRB_SMA[15..0] DDRB_SDQ[63..0] 12
DDRB_SMA0 Y33 C16 DDRB_SDQ0
11 DDRA_SMA[15..0] DDRA_SDQ[63..0] 11 MB_ADD[0] MB_DATA[0]
DDRA_SMA0 AA28 F15 DDRA_SDQ0 DDRB_SMA1 R32 B17 DDRB_SDQ1
DDRA_SMA1 R29 MA_ADD[0] MA_DATA[0] E15 DDRA_SDQ1 DDRB_SMA2 T31 MB_ADD[1] MB_DATA[1] B20 DDRB_SDQ2
DDRA_SMA2 T30 MA_ADD[1] MA_DATA[1] H19 DDRA_SDQ2 DDRB_SMA3 P33 MB_ADD[2] MB_DATA[2] C20 DDRB_SDQ3
DDRA_SMA3 R28 MA_ADD[2] MA_DATA[2] F19 DDRA_SDQ3 DDRB_SMA4 P32 MB_ADD[3] MB_DATA[3] A16 DDRB_SDQ4
1 DDRA_SMA4 R26 MA_ADD[3] MA_DATA[3] E14 DDRA_SDQ4 DDRB_SMA5 P31 MB_ADD[4] MB_DATA[4] B16 DDRB_SDQ5 1
DDRA_SMA5 P26 MA_ADD[4] MA_DATA[4] H15 DDRA_SDQ5 DDRB_SMA6 N32 MB_ADD[5] MB_DATA[5] B19 DDRB_SDQ6
DDRA_SMA6 P27 MA_ADD[5] MA_DATA[5] E17 DDRA_SDQ6 DDRB_SMA7 M33 MB_ADD[6] MB_DATA[6] A20 DDRB_SDQ7
DDRA_SMA7 P30 MA_ADD[6] MA_DATA[6] D18 DDRA_SDQ7 DDRB_SMA8 M32 MB_ADD[7] MB_DATA[7]
DDRA_SMA8 P29 MA_ADD[7] MA_DATA[7] DDRB_SMA9 L32 MB_ADD[8] B22 DDRB_SDQ8
DDRA_SMA9 M28 MA_ADD[8] G20 DDRA_SDQ8 DDRB_SMA10 AB31 MB_ADD[9] MB_DATA[8] C22 DDRB_SDQ9
DDRA_SMA10 AB26 MA_ADD[9] MA_DATA[8] E20 DDRA_SDQ9 DDRB_SMA11 M31 MB_ADD[10] MB_DATA[9] A26 DDRB_SDQ10
DDRA_SMA11 M26 MA_ADD[10] MA_DATA[9] H23 DDRA_SDQ10 DDRB_SMA12 K32 MB_ADD[11] MB_DATA[10] B26 DDRB_SDQ11
DDRA_SMA12 M29 MA_ADD[11] MA_DATA[10] G23 DDRA_SDQ11 DDRB_SMA13 AF33 MB_ADD[12] MB_DATA[11] B21 DDRB_SDQ12
DDRA_SMA13 AE27 MA_ADD[12] MA_DATA[11] E19 DDRA_SDQ12 DDRB_SMA14 K33 MB_ADD[13] MB_DATA[12] A22 DDRB_SDQ13
DDRA_SMA14 L26 MA_ADD[13] MA_DATA[12] H20 DDRA_SDQ13 DDRB_SMA15 J32 MB_ADD[14] MB_DATA[13] C24 DDRB_SDQ14
DDRA_SMA15 L27 MA_ADD[14] MA_DATA[13] E22 DDRA_SDQ14 MB_ADD[15] MB_DATA[14] B25 DDRB_SDQ15
MA_ADD[15] MA_DATA[14] D22 DDRA_SDQ15 DDRB_SBS0# AB33 MB_DATA[15]
MA_DATA[15] 12 DDRB_SBS0# MB_BANK[0]
DDRA_SBS0# AB27 DDRB_SBS1# AA32 A28 DDRB_SDQ16
11 DDRA_SBS0# MA_BANK[0] 12 DDRB_SBS1# MB_BANK[1] MB_DATA[16]
DDRA_SBS1# AA29 H25 DDRA_SDQ16 DDRB_SBS2# K31 B28 DDRB_SDQ17
11 DDRA_SBS1# MA_BANK[1] MA_DATA[16] 12 DDRB_SBS2# MB_BANK[2] MB_DATA[17]
DDRA_SBS2# M30 F25 DDRA_SDQ17 B31 DDRB_SDQ18
11 DDRA_SBS2# MA_BANK[2] MA_DATA[17] 12 DDRB_SDM[7..0] MB_DATA[18]
D28 DDRA_SDQ18 DDRB_SDM0 C18 A32 DDRB_SDQ19
11 DDRA_SDM[7..0] MA_DATA[18] MB_DM[0] MB_DATA[19]
DDRA_SDM0 D16 D29 DDRA_SDQ19 DDRB_SDM1 B23 C26 DDRB_SDQ20
DDRA_SDM1 D20 MA_DM[0] MA_DATA[19] E23 DDRA_SDQ20 DDRB_SDM2 C28 MB_DM[1] MB_DATA[20] B27 DDRB_SDQ21
DDRA_SDM2 E25 MA_DM[1] MA_DATA[20] D24 DDRA_SDQ21 DDRB_SDM3 D31 MB_DM[2] MB_DATA[21] A30 DDRB_SDQ22
DDRA_SDM3 F30 MA_DM[2] MA_DATA[21] D26 DDRA_SDQ22 DDRB_SDM4 AM31 MB_DM[3] MB_DATA[22] C30 DDRB_SDQ23
DDRA_SDM4 AK29 MA_DM[3] MA_DATA[22] D27 DDRA_SDQ23 DDRB_SDM5 AN30 MB_DM[4] MB_DATA[23]
DDRA_SDM5 AL25 MA_DM[4] MA_DATA[23] DDRB_SDM6 AR24 MB_DM[5] B33 DDRB_SDQ24
DDRA_SDM6 AM20 MA_DM[5] G28 DDRA_SDQ24 DDRB_SDM7 AN18 MB_DM[6] MB_DATA[24] C32 DDRB_SDQ25
DDRA_SDM7 AM16 MA_DM[6] MA_DATA[24] G29 DDRA_SDQ25 MB_DM[7] MB_DATA[25] F33 DDRB_SDQ26
MA_DM[7] MA_DATA[25] H27 DDRA_SDQ26 DDRB_SDQS0 B18 MB_DATA[26] F32 DDRB_SDQ27
MA_DATA[26] 12 DDRB_SDQS0 MB_DQS_H[0] MB_DATA[27]
DDRA_SDQS0 G17 J29 DDRA_SDQ27 DDRB_SDQS0# A18 B32 DDRB_SDQ28
11 DDRA_SDQS0 MA_DQS_H[0] MA_DATA[27] 12 DDRB_SDQS0# MB_DQS_L[0] MB_DATA[28]
DDRA_SDQS0# H17 E28 DDRA_SDQ28 DDRB_SDQS1 B24 C31 DDRB_SDQ29
11 DDRA_SDQS0# MA_DQS_L[0] MA_DATA[28] 12 DDRB_SDQS1 MB_DQS_H[1] MB_DATA[29]
DDRA_SDQS1 F22 F27 DDRA_SDQ29 DDRB_SDQS1# A24 E32 DDRB_SDQ30
11 DDRA_SDQS1 MA_DQS_H[1] MA_DATA[29] 12 DDRB_SDQS1# MB_DQS_L[1] MB_DATA[30]
DDRA_SDQS1# G22 H29 DDRA_SDQ30 DDRB_SDQS2 B30 F31 DDRB_SDQ31
11 DDRA_SDQS1# MA_DQS_L[1] MA_DATA[30] 12 DDRB_SDQS2 MB_DQS_H[2] MB_DATA[31]
DDRA_SDQS2 E26 H28 DDRA_SDQ31 DDRB_SDQS2# B29
11 DDRA_SDQS2 MA_DQS_H[2] MA_DATA[31] 12 DDRB_SDQS2# MB_DQS_L[2]
DDRA_SDQS2# F26 DDRB_SDQS3 D32 AK32 DDRB_SDQ32
2 11 DDRA_SDQS2# MA_DQS_L[2] 12 DDRB_SDQS3 MB_DQS_H[3] MB_DATA[32] 2
DDRA_SDQS3 H30 AH29 DDRA_SDQ32 DDRB_SDQS3# D33 AL32 DDRB_SDQ33
11 DDRA_SDQS3 MA_DQS_H[3] MA_DATA[32] 12 DDRB_SDQS3# MB_DQS_L[3] MB_DATA[33]
DDRA_SDQS3# G30 AJ30 DDRA_SDQ33 DDRB_SDQS4 AM32 AP32 DDRB_SDQ34
11 DDRA_SDQS3# MA_DQS_L[3] MA_DATA[33] 12 DDRB_SDQS4 MB_DQS_H[4] MB_DATA[34]
DDRA_SDQS4 AL29 AM28 DDRA_SDQ34 DDRB_SDQS4# AM33 AN31 DDRB_SDQ35
11 DDRA_SDQS4 MA_DQS_H[4] MA_DATA[34] 12 DDRB_SDQS4# MB_DQS_L[4] MB_DATA[35]
DDRA_SDQS4# AL30 AM27 DDRA_SDQ35 DDRB_SDQS5 AN28 AK31 DDRB_SDQ36
11 DDRA_SDQS4# MA_DQS_L[4] MA_DATA[35] 12 DDRB_SDQS5 MB_DQS_H[5] MB_DATA[36]
DDRA_SDQS5 AH25 AH27 DDRA_SDQ36 DDRB_SDQS5# AP29 AK33 DDRB_SDQ37
11 DDRA_SDQS5 MA_DQS_H[5] MA_DATA[36] 12 DDRB_SDQS5# MB_DQS_L[5] MB_DATA[37]
DDRA_SDQS5# AJ25 AH28 DDRA_SDQ37 DDRB_SDQS6 AP23 AN32 DDRB_SDQ38
11 DDRA_SDQS5# MA_DQS_L[5] MA_DATA[37] 12 DDRB_SDQS6 MB_DQS_H[6] MB_DATA[38]
DDRA_SDQS6 AK20 AJ29 DDRA_SDQ38 DDRB_SDQS6# AP24 AP33 DDRB_SDQ39
11 DDRA_SDQS6 MA_DQS_H[6] MA_DATA[38] 12 DDRB_SDQS6# MB_DQS_L[6] MB_DATA[39]
DDRA_SDQS6# AL20 AK27 DDRA_SDQ39 DDRB_SDQS7 AR18
11 DDRA_SDQS6# MA_DQS_L[6] MA_DATA[39] 12 DDRB_SDQS7 MB_DQS_H[7]
DDRA_SDQS7 AK15 DDRB_SDQS7# AP18 AP30 DDRB_SDQ40
11 DDRA_SDQS7 MA_DQS_H[7] 12 DDRB_SDQS7# MB_DQS_L[7] MB_DATA[40]
DDRA_SDQS7# AL15 AK26 DDRA_SDQ40 AR30 DDRB_SDQ41
11 DDRA_SDQS7# MA_DQS_L[7] MA_DATA[40] MB_DATA[41]
AJ26 DDRA_SDQ41 DDRB_CLK0 W32 AP27 DDRB_SDQ42
MA_DATA[41] 12 DDRB_CLK0 MB_CLK_H[0] MB_DATA[42]
DDRA_CLK0 W29 AK23 DDRA_SDQ42 DDRB_CLK0# Y32 AN26 DDRB_SDQ43
11 DDRA_CLK0 MA_CLK_H[0] MA_DATA[42] 12 DDRB_CLK0# MB_CLK_L[0] MB_DATA[43]
DDRA_CLK0# Y30 AJ23 DDRA_SDQ43 DDRB_CLK1 V33 AR32 DDRB_SDQ44
11 DDRA_CLK0# MA_CLK_L[0] MA_DATA[43] 12 DDRB_CLK1 MB_CLK_H[1] MB_DATA[44]
DDRA_CLK1 W26 AM26 DDRA_SDQ44 DDRB_CLK1# V32 AP31 DDRB_SDQ45
11 DDRA_CLK1 MA_CLK_H[1] MA_DATA[44] 12 DDRB_CLK1# MB_CLK_L[1] MB_DATA[45]
DDRA_CLK1# W27 AL26 DDRA_SDQ45 U32 AR28 DDRB_SDQ46
11 DDRA_CLK1# MA_CLK_L[1] MA_DATA[45] MB_CLK_H[2] MB_DATA[46]
U29 AM24 DDRA_SDQ46 V31 AP28 DDRB_SDQ47
V30 MA_CLK_H[2] MA_DATA[46] AL23 DDRA_SDQ47 T33 MB_CLK_L[2] MB_DATA[47]
U26 MA_CLK_L[2] MA_DATA[47] T32 MB_CLK_H[3] AP25 DDRB_SDQ48
U27 MA_CLK_H[3] AK22 DDRA_SDQ48 MB_CLK_L[3] MB_DATA[48] AN24 DDRB_SDQ49
MA_CLK_L[3] MA_DATA[48] AH22 DDRA_SDQ49 DDRB_CKE0 H32 MB_DATA[49] AR22 DDRB_SDQ50
MA_DATA[49] 12 DDRB_CKE0 MB_CKE[0] MB_DATA[50]
DDRA_CKE0 L29 AK19 DDRA_SDQ50 DDRB_CKE1 H33 AP21 DDRB_SDQ51
11 DDRA_CKE0 MA_CKE[0] MA_DATA[50] 12 DDRB_CKE1 MB_CKE[1] MB_DATA[51]
DDRA_CKE1 K30 AH19 DDRA_SDQ51 AP26 DDRB_SDQ52
11 DDRA_CKE1 MA_CKE[1] MA_DATA[51] MB_DATA[52]
AM22 DDRA_SDQ52 DDRB_ODT0 AF31 AR26 DDRB_SDQ53
MA_DATA[52] 12 DDRB_ODT0 MB0_ODT[0] MB_DATA[53]
DDRA_ODT0 AD30 AL22 DDRA_SDQ53 DDRB_ODT1 AH31 AN22 DDRB_SDQ54
11 DDRA_ODT0 MA0_ODT[0] MA_DATA[53] 12 DDRB_ODT1 MB0_ODT[1] MB_DATA[54]
DDRA_ODT1 AG28 AJ20 DDRA_SDQ54 AE32 AP22 DDRB_SDQ55
11 DDRA_ODT1 MA0_ODT[1] MA_DATA[54] MB1_ODT[0] MB_DATA[55]
AE26 AL19 DDRA_SDQ55 AH33
AG29 MA1_ODT[0] MA_DATA[55] MB1_ODT[1] AR20 DDRB_SDQ56
MA1_ODT[1] AK17 DDRA_SDQ56 DDRB_SCS0# AD31 MB_DATA[56] AP19 DDRB_SDQ57
MA_DATA[56] 12 DDRB_SCS0# MB0_CS_L[0] MB_DATA[57]
DDRA_SCS0# AD26 AJ17 DDRA_SDQ57 DDRB_SCS1# AF32 AP16 DDRB_SDQ58
11 DDRA_SCS0# MA0_CS_L[0] MA_DATA[57] 12 DDRB_SCS1# MB0_CS_L[1] MB_DATA[58]
DDRA_SCS1# AE29 AK14 DDRA_SDQ58 AC32 AR16 DDRB_SDQ59
11 DDRA_SCS1# MA0_CS_L[1] MA_DATA[58] MB1_CS_L[0] MB_DATA[59]
AB30 AH14 DDRA_SDQ59 AG32 AN20 DDRB_SDQ60
AF30 MA1_CS_L[0] MA_DATA[59] AM18 DDRA_SDQ60 MB1_CS_L[1] MB_DATA[60] AP20 DDRB_SDQ61
3 MA1_CS_L[1] MA_DATA[60] AL17 DDRA_SDQ61 DDRB_SRAS# AB32 MB_DATA[61] AP17 DDRB_SDQ62 3
MA_DATA[61] 12 DDRB_SRAS# MB_RAS_L MB_DATA[62]
DDRA_SRAS# AB29 AH15 DDRA_SDQ62 DDRB_SCAS# AD32 AN16 DDRB_SDQ63
11 DDRA_SRAS# MA_RAS_L MA_DATA[62] 12 DDRB_SCAS# MB_CAS_L MB_DATA[63]
DDRA_SCAS# AD29 AL14 DDRA_SDQ63 DDRB_SWE# AD33
11 DDRA_SCAS# MA_CAS_L MA_DATA[63] 12 DDRB_SWE# MB_WE_L
DDRA_SWE# AD28
11 DDRA_SWE# MA_WE_L MEM_MB_RST# H31
12 MEM_MB_RST# MB_RESET_L
MEM_MA_RST# J28 MEM_MB_EVENT# Y31
11 MEM_MA_RST# MA_RESET_L 12 MEM_MB_EVENT# MB_EVENT_L
MEM_MA_EVENT# AA26
11 MEM_MA_EVENT# MA_EVENT_L
RICHLAND-A8-SERIES_BGA813
G32
+MEM_VREF M_VREF
1 2 M_ZVDDIO AJ32
+1.35V_VDDQ M_ZVDDIO
RC3 39.2_0402_1%
RICHLAND-A8-SERIES_BGA813 +1.35V_VDDQ
EVENT# pull high
L M_ZVDDIO W/S=8/12 mil, <1000mil 0.75V reference voltage
L +MEM_VREF 15mil
2 Close to JCPU1
RC112
+1.35V_VDDQ 1K_0402_1%
1

+MEM_VREF
2

2
RC113
RC109 1 2 1K_0402_5% MEM_MA_EVENT# 1K_0402_1% CC15
RC110 1 2 1K_0402_5% MEM_MB_EVENT# .1U_0402_16V7K
1
1

4 4

10/4 Eric Del CC45.

11/19 Eric change 4P2R to 8P4R.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 7 of 47
A B C D E
 A B C D E

L Close to APU (JCPU1) Place near APU

UCPU1D DP0_AUXP 2 1
To LVDS
Translator 18 DP0_TXP0_C
CC16 1
CC17 1
2 .1U_0402_16V7K
2 .1U_0402_16V7K
DP0_TXP0
DP0_TXN0
H2
H1 DP0_TXP[0] DP0_AUXP
M5
M6
DP0_AUXP
DP0_AUXN
CC19 1
CC20 1
2 .1U_0402_16V7K
2 .1U_0402_16V7K
DP0_AUXP_C 18 To LVDS Translator DP0_AUXN
RC4
2 1
1.8K_0402_5%
18 DP0_TXN0_C DP0_TXN[0] DP0_AUXN DP0_AUXN_C 18
RC5 1.8K_0402_5%
CC18 1 2 .1U_0402_16V7K DP0_TXP1 H3 L5

DISPLAY PORT 0
18 DP0_TXP1_C DP0_TXP[1] DP1_AUXP
18 DP0_TXN1_C
CC21 1 2 .1U_0402_16V7K DP0_TXN1 H4
DP0_TXN[1] DP1_AUXN
L6 12/19 del CC141/CC142, RC10, RC11
FHD eDP CC26 1 @ 2 .1U_0402_16V7K DP0_TXP2 F4 J5 APU_HDMI_CLK
18 DP0_TXP2_C DP0_TXP[2] DP2_AUXP APU_HDMI_CLK 19
18 DP0_TXN2_C
CC25 1 @ 2 .1U_0402_16V7K DP0_TXN2 F3
DP0_TXN[2] DP2_AUXN
J6 APU_HDMI_DATA
APU_HDMI_DATA 19 To HDMI
CC24 1 @ 2 .1U_0402_16V7K DP0_TXP3 F1 P5
18 DP0_TXP3_C DP0_TXP[3] DP3_AUXP
CC23 1 @ 2 .1U_0402_16V7K DP0_TXN3 F2 P6
1 18 DP0_TXN3_C DP0_TXN[3] DP3_AUXN 1

DISPLAY PORT MISC.

E2 R5
E1 DP1_TXP[0] DP4_AUXP R6
DP1_TXN[0] DP4_AUXN
D4 U5

DISPLAY PORT 1
+1.35V_VDDQ D3 DP1_TXP[1] DP5_AUXP U6
DP1_TXN[1] DP5_AUXN
RP3 D1 M7 DP0_HPD LVDS/eDP
DP1_TXP[2] DP0_HPD DP0_HPD 10
4 5 APU_SIC D2 L7
3 6 APU_SID DP1_TXN[2] DP1_HPD J7 DP2_HPD
DP2_HPD DP2_HPD 19 HDMI
2 7 ALLOW_STOP C1 P7
1 8 ALERT_L C2 DP1_TXP[3] DP3_HPD R7
DP1_TXN[3] DP4_HPD U7
1K_0804_8P4R_5% B2 DP5_HPD
19 APU_HDMI_TXD2+ DP2_TXP[0]
A2 C6 DP_ENBKL DP_ENBKL 10
19 APU_HDMI_TXD2- DP2_TXN[0] DP_BLON D7 DP_ENVDD DP_ENVDD 10 10/3 Eric Add DP_ENVDD control pin.
RC6 2 1 1K_0402_5% B3 DP_DIGON A6 DP_INT_PWM

DISPLAY PORT 2
19 APU_HDMI_TXD1+ DP2_TXP[1] DP_VARY_BL DP_INT_PWM 10
@ To HDMI 19 APU_HDMI_TXD1-
A3
DP2_TXN[1] B6 DP_AUX_ZVSS RC7 1 2 150_0402_1%
Allow_STOP leakage issue DP_AUX_ZVSS
19 APU_HDMI_TXD0+
B4
A4 DP2_TXP[2] AL6 L DP_AUX_ZVSS W/S=8/12 mil, <3000mil
+1.35V_VDDQ 19 APU_HDMI_TXD0- DP2_TXN[2] TEST6 Y23 TC1
B5 TEST9 V23
19 APU_HDMI_TXC+ DP2_TXP[3] TEST10 TC2 10/27 add TP.
1 2 A5 G9 TC3
19 APU_HDMI_TXC- DP2_TXN[3] TEST14
RC9 @ 0_0603_5% F9 TC4
TEST15
4/17 change to 0ohm new symbol 13 APU_CLKP
APU_CLKP AL9
CLKIN_H TEST16
E9 TC5 RP4
100MHz APU_CLKN AK9 G8 TC6 1K_0804_8P4R_5%
13 APU_CLKN CLKIN_L TEST17 F12 APU_TEST18 APU_TEST24 4 5

TEST
TEST18

CLK
RC10 2 1 300_0402_5% APU_RST# 100MHz APU_DISP_CLKP AL7 E12 APU_TEST19 APU_TEST18 3 6
13 APU_DISP_CLKP DISP_CLKIN_H TEST19
NSS APU_DISP_CLKN AK7 F14 APU_TEST20 APU_TEST19 2 7
13 APU_DISP_CLKN DISP_CLKIN_L TEST20
RC11 2 1 300_0402_5% APU_PWRGD G12 APU_TEST24 APU_TEST20 1 8
APU_SVC E5 TEST24 AJ8 TEST25_H RC12 1 2 510_0402_1%
2 46 APU_SVC SVC TEST25_H 2
SVI 2.0 APU_SVD E6 AH8 TEST25_L RC13 1 2 510_0402_1% +1.2VS TEST35 change to PU for
46 APU_SVD SVD TEST25_L
RC14 1 @ 2 1K_0402_5% APU_SVC (0 ohm G14 HDMI can not output
TEST28_H

SER.
APU_SVT D6 H14
RC15 1 @ 2 1K_0402_5% APU_SVD
at Power Side) 46 APU_SVT SVT TEST28_L V25 20110126
TEST30_H TC7
APU_SIC AJ11 Y25 TC8
RC16 1 @ 2 1K_0402_5% APU_SVT APU_SID AH11 SIC TEST30_L AH32 M_TEST RC17 1 @ 2 39.2_0402_1%
SB-TSI (S5 Domain) SID TEST31 +1.35V_VDDQ
Check APU_RST# RC19 1 @ 2 0_0402_5% APU_RST#_APU AK11 TEST32_H
R25
T25
TC9 RC18 1 2 39.2_0402_1%
For ESD request close APU side 13 APU_RST# RESET_L TEST32_L TC10
APU_PWRGD RC20 1 @ 2 0_0402_5% APU_PWRGD_APU AH9 AL5 TEST35 RC21 1 2 300_0402_5% +1.35V_VDDQ
13,46 APU_PWRGD PWROK TEST35 RC22 1 @ 2 300_0402_5%
APU_PROCHOT# AL12 AP10 ALLOW_STOP

CTRL
PROCHOT_L DMAACTIVE_L ALLOW_STOP 13
APU_THERMTRIP# AK5
ALERT_L AR10 THERMTRIP_L T23
ALERT_L TEST4 TC11
4/17 change to 0ohm new symbol TEST5
R23 TC12 TEST35 change to PU for
APU_TDI E11 HDMI can not output
APU_TDO G11 TDI
10/4 Eric Del. 10/25 Eric aremovek H_PROCHOT# . TDO 20110126
APU_TCK H12
APU_TMS F11 TCK L8

JTAG
Internal PU when no use HDT TMS RSVD
APU_TRST# H11 P8
APU_DBRDY E8 TRST_L RSVD AH12
DBRDY RSVD
12/15 change to +1.5V
APU_DBREQ# E7 AJ12 +1.35V_VDDQ
Close to Header

RSVD
DBREQ_L RSVD AK12 RP5
G6 RSVD 1K_0804_8P4R_5%
46 APU_VDD_RUN_FB_L VSS_SENSE
H6 4 5 APU_TRST#
APU_VDDNB_SEN H5 VDDP_SENSE 3 6 APU_TCK
46 APU_VDDNB_SEN VDDNB_SENSE

SENSE
G7 2 7 APU_TMS
APU_VDD_SEN G5 VDDIO_SENSE 1 8 APU_TDI
46 APU_VDD_SEN VDD_SENSE
H7
VDDR_SENSE
10/4 Eric Del.
RICHLAND-A8-SERIES_BGA813
Route as differential with APU_VDD_RUN_FB_L TC14 TC13
RC24 1 2 1K_0402_5% APU_DBREQ#
3 TC13 near APU. 3
12/19 RF request 10/27 300 ohm??

Asserted as an input to +1.35V_VDDQ 1/11 Eric mount RC25 for open drain needed.
CPU TSI interface level shift force processor into 2/29 remove RC42, add EC_THERM for power leakage issue HDT Debug conn 12/19 remove damping 0ohm.
When APU High -> MOS OFF (Vgs < 0.4V ) BSH111, the Vgs is: HTC-active state
APU Low -> MOS ON (Vgs > 1.3V) min = 0.4V
Max = 1.3V 12/15 change to +1.5V
1

1
1K_0402_5%

1K_0402_5%

1 RC25 2 +3VS
10K_0402_5%
RC107

RC108

APU_TCK TC16
EC_THERM 32,39

2
CC22 1 2 0.1U_0402_16V4Z 12/27 Eric Del.
2

APU_TMS

G
TC17
@
+3VS 1 RC27 2 1 RC28 2 APU_PROCHOT# RC29 2 1 0_0402_5%
1 3 APU_TDI TC18
D

S
31.6K_0402_1% 30K_0402_1% QC1 APU_TDO TC19
2N7002K_SOT23-3
APU_TRST# TC26 APU_PWRGD TC20
Vg = 1.607 V +1.35V_VDDQ
EC_THERM# 13,39,46
2
G

Q12 APU_RST# TC21

THERMTRIP shutdown Indicates to the FCH that a thermal trip
APU_SID 3 1 EC_SMB_DA2 temperature: 115 degree has occurred. Its assertion will cause the FCH APU_DBRDY TC22
EC_SMB_DA2 18,30,32,6
1
S

BSH111_SOT23-3
to transition the system to S5 immediately APU_DBREQ# TC23
APU_TEST19 TC24
RC30
2 2

10K_0402_5% APU_TEST18 TC25

2
G

Q16
4 QC4 @ 4
E

APU_SIC 3 1 EC_SMB_CK2 APU_THERMTRIP# 3 1 RC32 2 1 0_0402_5%

EC_SMB_CK2 18,30,32,6 H_THERMTRIP# 15
C
S

BSH111_SOT23-3 MMBT3904_SOT23-3 1 2
MAINPWON 32,41
RC33 @ 0_0402_5%

10/18 Eric change Level shift solution with Pagani AMD.

3/9 add QC5 for +5VS power leakage issue
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 8 of 47
A B C D E
 A B C D E

Power Name Consumption +APU_CORE Decoupling

+1.35V_VDDQ
3/2 Reserve 4 pcs 180pF for EMI DDR noise issue
VDD
+CPU_CORE 60A On power team page
330uF x 4 @ x1
22uF x 10 UCPU1F
VDDNB
+CPU_CORE_NB 37A 0.22uF x2 A17
VSS VSS
Y11

CC166

CC167

CC168

CC169

CC170

CC171

CC172
1 1 1 1 1 1 1 A19 Y12
0.01uF x3 VSS VSS

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J
VDDIO A21
VSS VSS
Y14
+1.5V 3.2A @EMI@ @EMI@ @EMI@ @EMI@ @EMI@ @EMI@ @EMI@
180pF x2 @ x1 A23
A25 VSS VSS
Y15
Y17
2 2 2 2 2 2 2 VSS VSS
VDDP / VDDR A27
VSS VSS
Y19
+1.2VS 5A / 3.5A +APU_CORE_NB Decoupling
A29
A31 VSS VSS
Y20
Y22
VSS VSS
VDDA B1
VSS VSS
AA4
0.75A
1 C3 AA5 1
+2.5VS C4 VSS VSS AB7
330uF x2 VSS VSS
On power team page 22uF x2 @ x2
C33
D5 VSS VSS
AB8
AC1
D9 VSS VSS AC2
10uF x1 D11 VSS VSS AC4
0.22uF x2 D13 VSS VSS AC9
D15 VSS VSS AC11
180pF x3 D17 VSS VSS AC12
D19 VSS VSS AC14
+APU_CORE +APU_CORE D21 VSS VSS AC15
UCPU1E D23 VSS VSS AC17
J12 V17 D25 VSS VSS AC19
J14 VDD VDD V19 D30 VSS VSS AC20
J15 VDD VDD V20 E4 VSS VSS AC22
J17 VDD VDD V22 Decoupling between CPU and DIMMs E27 VSS VSS AC23
J19 VDD VDD W8 E29 VSS VSS AC25
VDD VDD across VDDIO and VSS split VSS VSS
J20 AA8 E30 AE4
J22 VDD VDD AA9 @ @ E33 VSS VSS AF9
VDD VDD @ @ VSS VSS
M11 AA11 +1.35V_VDDQ @ @ @ @ @ @ @ @ @ @EMI@ @EMI@ +1.35V_VDDQ @EMI@ @EMI@ F5 AF11
M12 VDD VDD AA12 F6 VSS VSS AF12
VDD VDD +1.5V / VDDIO Decoupling VSS VSS

CC94

CC95

CC96

CC97

CC98

CC99

CC100

CC101

CC102

CC103

CC104

CC105

CC106

CC107

CC149

CC150

CC151

CC152

CC108

CC109

CC153

CC154

330U_D2_2V_Y

CC148

CC146

CC145

CC147

CC143

CC144

CC110

CC111

CC112

CC113
M14 AA14 1 F7 AF14
M15 VDD VDD AA15 F8 VSS VSS AF15
VDD VDD 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 VSS VSS

CC93
M17 AA17 + F17 AF17
M19 VDD VDD AA19
220uF x1 F20 VSS VSS AF19
VDD VDD 22uF x4 VSS VSS

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

0.22U_0402_10V4Z

180P_0402_50V8J

180P_0402_50V8J
M20 AA20 F23 AF20
M22 VDD VDD AA22 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 F28 VSS VSS AF22
R8 VDD VDD AD9
4.7uF x4 F29 VSS VSS AF23
R9 VDD VDD AD11 0.22uF x6 G1 VSS VSS AF25
R11 VDD VDD AD12 G2 VSS VSS AG1
R12 VDD VDD AD14
180pF x1 @x1 G4 VSS VSS AG2
R14 VDD VDD AD15 G15 VSS VSS AG4
2 R15 VDD VDD AD17 G19 VSS VSS AG9 2
R17 VDD VDD AD19 @EMI@@EMI@ G25 VSS VSS AG11
R19 VDD VDD AD20 G26 VSS VSS AG26
R20 VDD VDD AD22 @ @ @ @ @ @ @EMI@ @EMI@ G27 VSS VSS AH7
R22 VDD VDD AG12
+1.2VS VDDR Decoupling G33 VSS VSS AH17
VDD VDD Close JCPU1.AN14,AP14~15,AR14~15 VSS VSS
CC114

CC115

CC116

CC158

CC156

CC157

CC117

CC118

CC155

CC119

CC120

CC121
U8 AG14 H8 AH20
V9 VDD VDD AG15 H9 VSS VSS AH23
VDD VDD 1 1 1 1 1 1 1 1 1 1 1 1 VSS VSS
V11 AG17 H22 AH26
V12 VDD VDD AG19 10uF x2 H26 VSS VSS AH30
VDD VDD VSS VSS
10U_0603_6.3V6M

10U_0603_6.3V6M

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

.01U_0402_16V7K

.01U_0402_16V7K

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1000P_0402_50V7K

1000P_0402_50V7K

180P_0402_50V8J

180P_0402_50V8J
V14 AG20 12/22 for RF request J4 AJ4
V15 VDD VDD AG22 2 2 2 2 2 2 2 2 2 2 2 2 0.22uF x2 J8 VSS VSS AJ5
VDD VDD 180pF x2 @x2 J9 VSS VSS AJ6
J11 VSS VSS AJ7
A7 B11
0.01uFx2 +APU_CORE_NB J23 VSS VSS AJ9
+APU_CORE_NB VDDNB VDDNB +APU_CORE_NB VSS VSS
A8
VDDNB VDDNB
B12 4.7uFx2 J25
VSS VSS
AJ14
A9 B13 J26 AJ15
A10 VDDNB VDDNB B14 @ @ @ @ J27 VSS VSS AJ19
A11 VDDNB VDDNB B15 J30 VSS VSS AJ22
A12 VDDNB VDDNB C8 K9 VSS VSS AJ27
A13 VDDNB VDDNB C10 @ @ @ @ @
@EMI@ @EMI@ VDDP_CAP@ K11 VSS VSS AJ28
VDDNB VDDNB +1.2VS VSS VSS
A14 C12 VDDP Decoupling K12 AJ33
VDDNB VDDNB +1.2VS VSS VSS
CC124

CC125

CC126

CC127

CC128

CC129

CC130

CC159

CC131

CC132
A15 C14 K14 AK6
VDDNB VDDNB Close JCPU1.AH3~7 VSS VSS

CC122

CC123
B7 D8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 K15 AK8
VDDNB VDDNB VSS VSS

CC133
B8 D10 1 1 C120 C121 C122 C123 K17 AK25
VDDNB VDDNB VSS VSS

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J

15P_0402_50V8J
B9 D12 1 K19 AK28
VDDNB VDDNB 22uF x4 VSS VSS
22U_0805_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

0.22U_0402_10V4Z

0.22U_0402_10V4Z

1000P_0402_50V7K

1000P_0402_50V7K

180P_0402_50V8J

180P_0402_50V8J
B10 D14 K20 AK30
VDDNB VDDNB 2 2 2 2 2 2 2 2 2 2 2 2 2 2 VSS VSS

22U_0805_6.3V6M

10U_0603_6.3V6M
@ + K22 AL1
M9 VDDNB_CAP @ @EMI@
0.22uF x2 2 2 L1 VSS VSS AL2
VDDNB_CAP N9 180pF x2 @x2 L2 VSS VSS AL4

220U_D2_2VY_R15M
VDDNB_CAP 2 VSS VSS
CC134

CC135

CC161

CC160

CC136

L4 AL8
J33 W33 M8 VSS VSS AL11
+1.35V_VDDQ VDDIO VDDIO 1 1 1 1 1 VSS VSS
K23 AA23 M23 AL27
3 K25 VDDIO VDDIO AA25 M25 VSS VSS AL28 3
VDDIO VDDIO VSS VSS
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

180P_0402_50V8J

L28 AA27 220uF x1 N4 AL33

L30 VDDIO VDDIO AA30 2 2 2 2 2 N11 VSS VSS AM5
L33 VDDIO VDDIO AA33 FBMA-L11-201209-221LMA30T_0805 N12 VSS VSS AM7
M27 VDDIO VDDIO AB28 LC1 N14 VSS VSS AM9
N23 VDDIO VDDIO AC30 2 1 @ @ N15 VSS VSS AM11
VDDIO VDDIO +2.5VS +APU_VDDA VSS VSS
N25 AC33 N17 AM15
VDDIO VDDIO VSS VSS
CC137

CC138

CC139

CC140

N30 AD23 N19 AM17

N33 VDDIO VDDIO AD25 N20 VSS VSS AM19
P28 VDDIO VDDIO AD27
1 1 1 1 VDDA Decoupling N22 VSS VSS AM21
VDDIO VDDIO VSS VSS
Power Sequence of APU
R27 AE28 R1 AM23
VDDIO VDDIO VSS VSS
47U_0805_4V6

0.22U_0402_10V4Z

3300P_0402_50V7-K

1000P_0402_50V7K

R30 AE30 Northbridge Power Pins 47uF x1 R2 AM25

R33 VDDIO VDDIO AE33 2 2 2 2 R4 VSS VSS AM29
VDDIO VDDIO for Remote Decoupling VSS VSS
0.22uF x1
U28
U30 VDDIO VDDIO
AG23
AG25 +1.5V T9
T11 VSS VSS
AM30
AN3
U33 VDDIO VDDIO AG27 T12 VSS VSS AN4
W28 VDDIO VDDIO AG30 T14 VSS VSS AN33
VDDIO VDDIO VSS VSS
W30
VDDIO VDDIO
AG33 +1.35V_VDDQ +2.5VS Group A T15
T17 VSS VSS
AP5
AP9
AM12 AN14 T19 VSS VSS AR2
+1.2VS VDDP VDDR +1.2VS VSS VSS
AN12
VDDP VDDR
AP14 VDDR: 3500mA Change 180p to 1000p by AMD T20
VSS VSS
AR5
VDDP: 5000mA AP12
VDDP VDDR
AP15
+1.5VS T22
VSS VSS
AR9
AP13 AR14 U4 AR17
AR12 VDDP VDDR AR15 W1 VSS VSS AR19
AR13 VDDP VDDR W2 VSS VSS AR21
VDDP VSS VSS
VDDP_CAP AA6 +CPU_CORE W4
W5 VSS VSS
AR23
AR25
AA7 VDDP_CAP W6 VSS VSS AR27
VDDP_CAP W7 VSS VSS AR29
TC15 VSS VSS
+APU_VDDA AM13
VDDA Group B Y9
VSS VSS
AR31

VDDA: 750mA
AM14
VDDA +CPU_CORE_NB RICHLAND-A8-SERIES_BGA813
4 4
RICHLAND-A8-SERIES_BGA813
Decoupling Caps.
+1.2VS
Pop / @ 330uF 220uF 47uF 22uF 10uF 4.7uF 0.22uF 0.01uF 3300pF 1nF 180pF
Pumori 2.0 0 19/11 7 5 17 3 1 1/1 13/3 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
Comal 7/2 1 1 19/11 7 4 17 3 1 1/1 14/2 SCHEMATIC, MB A9851
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
P5WS5 7/2 1 1 13 3 8 19 3 1 4 16 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK A

Date: Monday, October 21, 2013 Sheet 9 of 47

A B C D E
 5 4 3 2 1

Panel ENBKL
HPD
+3VS

1
Del reserved NMOS

2
R580
4.7K_0402_5%
R581 D5 @ RB751V-40_SOD323-2

2
D 100K_0402_5% 2 1 D
APU_PCIE_RST# 13,23,31
Translator and eDP HPD

1
From Translator or Conn. D 2
2
EDP_HPD 1 RC35 2 DP0_HPD G Q152 C74
18 EDP_HPD DP0_HPD 8

MMBT3904_SOT23-3
0_0402_5% S 2N7002K_SOT23-3 100P_0402_50V8J

1
Q153 C 1
@ @ESD@

3
1 2 2
8 DP_ENBKL
R582 2.2K_0402_5% B

2
4/17 change to 0ohm new symbol E

3
R583
100K_0402_5%

1
DP_ENBKL R584 1 @ 2 0_0402_5% ENBKL ENBKL 32

Del reserved NMOS

11/13 Eric Add Panel EBBKL circuit.
Verify eDP on DB phase.

+3VS

C eDP Panel ENVDD C

12/06 Del FCH_CRT_HPD Panel ENVDD

1
2
APUEDP@
APUEDP@ R2
R1 4.7K_0402_5%
100K_0402_5%

2
APU_ENVDD 20

1
D
2 APUEDP@
APUEDP@ G Q1
MMBT3904_SOT23-3 S 2N7002K_SOT23-3

1
Q2 C

3
1 2 2
8 DP_ENVDD
R3 2.2K_0402_5% B
APUEDP@ E

3
2
APUEDP@
R4
100K_0402_5%

1
10/3 Eric Add DP_ENVDD control pin.

B B
+3VS
Panel PWM

1
RC36

1
4.7K_0402_5%

2
RC37
47K_0402_5%
APU_INVT_PWM 18

3
Q3B

5 2N7002KDW_SOT363-6

RC38

4
1
2.2K_0402_5% C
1 2 2 Q3A1
8 DP_INT_PWM
1

B
E

3
RC39 MMBT3904_SOT23-3
4.7K_0402_5%
2

A A

Security Classification Compal Secret Data

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
SCHEMATIC, MB A9851
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 10 of 47
5 4 3 2 1
 5 4 3 2 1

+VREF_DQ 15mil
L DDR3 SO-DIMM A
+V_DDR_REFA +1.35V_VDDQ +1.35V_VDDQ

All VREF traces should JDIMM1

have 20 mil trace width +V_DDR_REFA 1 2
3 VREF_DQ VSS1 4 DDRA_SDQ4
VSS2 DQ4

0.1U_0402_16V7K

1000P_0603_50V7K
DDRA_SDQ0 5 6 DDRA_SDQ5
DQ0 DQ5

CD1
1 DDRA_SDQ1 7 8
DQ1 VSS3

1
D D

CD2
DDRA_SDQ[0..63] 9 10 DDRA_SDQS0#
7 DDRA_SDQ[0..63] VSS4 DQS#0 DDRA_SDQS0# 7
DDRA_SDM0 11 12 DDRA_SDQS0
DDRA_SDM[0..7] DM0 DQS0 DDRA_SDQS0 7
7 DDRA_SDM[0..7] 13 14

2
2 DDRA_SDQ2 15 VSS5 VSS6 16 DDRA_SDQ6
DDRA_SMA[0..15] DDRA_SDQ3 17 DQ2 DQ6 18 DDRA_SDQ7
7 DDRA_SMA[0..15] DQ3 DQ7
19 20
DDRA_SDQ8 21 VSS7 VSS8 22 DDRA_SDQ12
DDRA_SDQ9 23 DQ8 DQ12 24 DDRA_SDQ13
25 DQ9 DQ13 26
DDRA_SDQS1# 27 VSS9 VSS10 28 DDRA_SDM1
7 DDRA_SDQS1# DQS#1 DM1
DDRA_SDQS1 29 30 MEM_MA_RST#
7 DDRA_SDQS1 DQS1 RESET# MEM_MA_RST# 7
31 32
DDRA_SDQ10 33 VSS11 VSS12 34 DDRA_SDQ14
DDRA_SDQ11 35 DQ10 DQ14 36 DDRA_SDQ15
37 DQ11 DQ15 38
DDRA_SDQ16 39 VSS13 VSS14 40 DDRA_SDQ20
DDRA_SDQ17 41 DQ16 DQ20 42 DDRA_SDQ21
+1.35V_VDDQ 43 DQ17 DQ21 44
DDRA_SDQS2# 45 VSS15 VSS16 46 DDRA_SDM2
7 DDRA_SDQS2# DQS#2 DM2
DDRA_SDQS2 47 48
7 DDRA_SDQS2 DQS2 VSS17
49 50 DDRA_SDQ22
DDRA_SDQ18 51 VSS18 DQ22 52 DDRA_SDQ23
DQ18 DQ23
2

DDRA_SDQ19 53 54
RD10 +V_DDR_REFA 55 DQ19 VSS19 56 DDRA_SDQ28
DDRA_SDQ24 57 VSS20 DQ28 58 DDRA_SDQ29
1K_0402_1% DQ24 DQ29
DDRA_SDQ25 59 60
61 DQ25 VSS21 62 DDRA_SDQS3#
DDRA_SDQS3# 7
1

DDRA_SDM3 63 VSS22 DQS#3 64 DDRA_SDQS3

DM3 DQS3 DDRA_SDQS3 7
65 66
DDRA_SDQ26 67 VSS23 VSS24 68 DDRA_SDQ30
DDRA_SDQ27 69 DQ26 DQ30 70 DDRA_SDQ31
DQ27 DQ31
2

71 72
RD11 VSS25 VSS26
1K_0402_1%
DDRA_CKE0 73 74 DDRA_CKE1
7 DDRA_CKE0 DDRA_CKE1 7
1

75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDRA_SMA15
C C
DDRA_SBS2# 79 NC1 A15 80 DDRA_SMA14
7 DDRA_SBS2# BA2 A14
81 82
DDRA_SMA12 83 VDD3 VDD4 84 DDRA_SMA11
DDRA_SMA9 85 A12/BC# A11 86 DDRA_SMA7
87 A9 A7 88
DDRA_SMA8 89 VDD5 VDD6 90 DDRA_SMA6
DDRA_SMA5 91 A8 A6 92 DDRA_SMA4
93 A5 A4 94
DDRA_SMA3 95 VDD7 VDD8 96 DDRA_SMA2
DDRA_SMA1 97 A3 A2 98 DDRA_SMA0
99 A1 A0 100
VDD9 VDD10
7 DDRA_CLK0
DDRA_CLK0 101
CK0 CK1
102 DDRA_CLK1
DDRA_CLK1 7 +VREF_CB 15mil +1.35V_VDDQ
Layout Note: 7 DDRA_CLK0#
DDRA_CLK0# 103
105 CK0# CK1#
104
106
DDRA_CLK1#
DDRA_CLK1# 7
Place near JDIMM1.203 & JDIMM1.204 DDRA_SMA10 107 VDD11 VDD12 108 DDRA_SBS1#
DDRA_SBS1# 7
DDRA_SBS0# 109 A10/AP BA1 110 DDRA_SRAS#
7 DDRA_SBS0# BA0 RAS# DDRA_SRAS# 7
111 112
VDD13 VDD14

2
DDRA_SWE# 113 114 DDRA_SCS0#
7 DDRA_SWE# WE# S0# DDRA_SCS0# 7
DDRA_SCAS# 115 116 DDRA_ODT0 RD12
+0.675VS 7 DDRA_SCAS# CAS# ODT0 DDRA_ODT0 7
117 118 1K_0402_1%
DDRA_SMA13 119 VDD15 VDD16 120 DDRA_ODT1 +VREF_CA
A13 ODT1 DDRA_ODT1 7
DDRA_SCS1# 121 122

1
7 DDRA_SCS1# 123 S1# NC2 124
@ @ @ 125 VDD17 VDD18 126
NCTEST VREF_CA
CD3

1U_0402_6.3V6K

CD4

1U_0402_6.3V6K

CD5

CD6

CD7

10U_0603_6.3V6M

CD8

10U_0603_6.3V6M

CD9

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

127 128
VSS27 VSS28

0.1U_0402_16V7K
1 1 1 1 1 1 1 DDRA_SDQ32 129 130 DDRA_SDQ36
DQ32 DQ36

2
DDRA_SDQ33 131 132 DDRA_SDQ37
DQ33 DQ37

CD10

1000P_0603_50V7K
133 134 1 RD13
VSS29 VSS30

1
DDRA_SDQS4# 135 136 DDRA_SDM4 1K_0402_1%
2 2 2 2 2 2 2 7 DDRA_SDQS4# DQS#4 DM4

CD11
DDRA_SDQS4 137 138
7 DDRA_SDQS4 DQS4 VSS31
139 140 DDRA_SDQ38

1
DDRA_SDQ34 141 VSS32 DQ38 142 DDRA_SDQ39 2
DDRA_SDQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRA_SDQ44
DDRA_SDQ40 147 VSS34 DQ44 148 DDRA_SDQ45
DDRA_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRA_SDQS5#
B VSS36 DQS#5 DDRA_SDQS5# 7 B
DDRA_SDM5 153 154 DDRA_SDQS5
DM5 DQS5 DDRA_SDQS5 7
155 156
DDRA_SDQ42 157 VSS37 VSS38 158 DDRA_SDQ46
DDRA_SDQ43 159 DQ42 DQ46 160 DDRA_SDQ47
161 DQ43 DQ47 162
DDRA_SDQ48 163 VSS39 VSS40 164 DDRA_SDQ52
DQ48 DQ52
Layout Note: DDRA_SDQ49 165
167 DQ49 DQ53
166
168
DDRA_SDQ53

Place near JDIMM1 7 DDRA_SDQS6#

DDRA_SDQS6# 169 VSS41 VSS42 170 DDRA_SDM6
DDRA_SDQS6 171 DQS#6 DM6 172
Layout Note: Place these 4 Caps near Command 7 DDRA_SDQS6
173 DQS6 VSS43 174 DDRA_SDQ54
and Control signals of DIMMA DDRA_SDQ50 175 VSS44 DQ54 176 DDRA_SDQ55
DDRA_SDQ51 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDRA_SDQ60
+1.35V_VDDQ DDRA_SDQ56 181 VSS46 DQ60 182 DDRA_SDQ61
DDRA_SDQ57 183 DQ56 DQ61 184
@ @ @ 185 DQ57 VSS47 186 DDRA_SDQS7#
VSS48 DQS#7 DDRA_SDQS7# 7
DDRA_SDM7 187 188 DDRA_SDQS7
DM7 DQS7 DDRA_SDQS7 7
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1 189 190
VSS49 VSS50
CD12

CD13

CD14

CD15

CD16

CD17

CD18

CD19

CD20

CD21

1 1 1 1 1 1 1 1 1 1 @ DDRA_SDQ58 191 192 DDRA_SDQ62

+ CD22 DDRA_SDQ59 193 DQ58 DQ62 194 DDRA_SDQ63
47U 6.3V M B1 ESR70M 195 DQ59 DQ63 196
RD5 1 2 10K_0402_5% 197 VSS51 VSS52 198 MEM_MA_EVENT#
2 2 2 2 2 2 2 2 2 2 2 SA0 EVENT# MEM_MA_EVENT# 7
199 200
+3VS VDDSPD SDA FCH_SDATA0 12,15
2.2U_0603_6.3V6K

0.1U_0402_16V7K

201 202
SA1 SCL FCH_SCLK0 12,15
CD24

1 1 203 204 +0.675VS

VTT1 VTT2
2
CD23

@
RD6 205 206
@ G1 G2
0_0402_5%
2 2 LCN_DAN06-K4406-0102
1

DDR3 SO-DIMM A CONN@

3/2 Reserve 4 pcs 180pF for EMI DDR noise issue

A +1.35V_VDDQ +1.35V_VDDQ
DIMM_A REV H:4mm A

@ @ @ @
<Address: 00>
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
CD26

CD27

CD28

CD25

CD57

CD58

CD59

CD60

1 1 1 1 1 1 1 1
180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

@ @ @ @
2 2 2 2 2 2 2 2
4019NK
Security Classification Compal Secret Data
Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
LA-8661P
Date: Monday, October 21, 2013 Sheet 11 of 47
5 4 3 2 1
 5 4 3 2 1

DDR3 SO-DIMM B
L +VREF_DQ 15mil

All VREF traces should +V_DDR_REFB +1.35V_VDDQ +1.35V_VDDQ

have 20 mil trace width
JDIMM2
+V_DDR_REFB 1 2
3 VREF_DQ VSS1 4 DDRB_SDQ4
VSS2 DQ4

0.1U_0402_16V7K
DDRB_SDQ0 5 6 DDRB_SDQ5
DQ0 DQ5

CD50

1000P_0603_50V7K
1 DDRB_SDQ1 7 8
DQ1 VSS3

1
DDRB_SDQ[0..63] 9 10 DDRB_SDQS0#
7 DDRB_SDQ[0..63] VSS4 DQS#0 DDRB_SDQS0# 7

CD29
DDRB_SDM0 11 12 DDRB_SDQS0
DDRB_SDM[0..7] DM0 DQS0 DDRB_SDQS0 7
13 14
7 DDRB_SDM[0..7]

2
2 DDRB_SDQ2 15 VSS5 VSS6 16 DDRB_SDQ6
D DDRB_SMA[0..15] DDRB_SDQ3 17 DQ2 DQ6 18 DDRB_SDQ7 D
7 DDRB_SMA[0..15] DQ3 DQ7
19 20
DDRB_SDQ8 21 VSS7 VSS8 22 DDRB_SDQ12
DDRB_SDQ9 23 DQ8 DQ12 24 DDRB_SDQ13
25 DQ9 DQ13 26
DDRB_SDQS1# 27 VSS9 VSS10 28 DDRB_SDM1
7 DDRB_SDQS1# DQS#1 DM1
DDRB_SDQS1 29 30 MEM_MB_RST#
7 DDRB_SDQS1 DQS1 RESET# MEM_MB_RST# 7
31 32
10/03 change to +V_DDR_REFB DDRB_SDQ10 33 VSS11
DQ10
VSS12
DQ14
34 DDRB_SDQ14
DDRB_SDQ11 35 36 DDRB_SDQ15
37 DQ11 DQ15 38
DDRB_SDQ16 39 VSS13 VSS14 40 DDRB_SDQ20
DDRB_SDQ17 41 DQ16 DQ20 42 DDRB_SDQ21
43 DQ17 DQ21 44
+1.35V_VDDQ DDRB_SDQS2# 45 VSS15 VSS16 46 DDRB_SDM2
7 DDRB_SDQS2# DQS#2 DM2
DDRB_SDQS2 47 48
7 DDRB_SDQS2 DQS2 VSS17
49 50 DDRB_SDQ22
DDRB_SDQ18 51 VSS18 DQ22 52 DDRB_SDQ23
DDRB_SDQ19 53 DQ18 DQ23 54
DQ19 VSS19
2

55 56 DDRB_SDQ28
RD14 +V_DDR_REFB DDRB_SDQ24 57 VSS20 DQ28 58 DDRB_SDQ29
DDRB_SDQ25 59 DQ24 DQ29 60
1K_0402_1% DQ25 VSS21
61 62 DDRB_SDQS3#
VSS22 DQS#3 DDRB_SDQS3# 7
DDRB_SDM3 63 64 DDRB_SDQS3
DDRB_SDQS3 7
1

65 DM3 DQS3 66
DDRB_SDQ26 67 VSS23 VSS24 68 DDRB_SDQ30
DDRB_SDQ27 69 DQ26 DQ30 70 DDRB_SDQ31
71 DQ27 DQ31 72
VSS25 VSS26
2

RD15
1K_0402_1%
DDRB_CKE0 73 74 DDRB_CKE1
7 DDRB_CKE0 CKE0 CKE1 DDRB_CKE1 7
75 76
1

77 VDD1 VDD2 78 DDRB_SMA15

DDRB_SBS2# 79 NC1 A15 80 DDRB_SMA14
7 DDRB_SBS2# BA2 A14
81 82
DDRB_SMA12 83 VDD3 VDD4 84 DDRB_SMA11
DDRB_SMA9 85 A12/BC# A11 86 DDRB_SMA7
C C
87 A9 A7 88
DDRB_SMA8 89 VDD5 VDD6 90 DDRB_SMA6
DDRB_SMA5 91 A8 A6 92 DDRB_SMA4
93 A5 A4 94
DDRB_SMA3 95 VDD7 VDD8 96 DDRB_SMA2
DDRB_SMA1 97 A3 A2 98 DDRB_SMA0
99 A1 A0 100
VDD9 VDD10
Layout Note: 7 DDRB_CLK0
DDRB_CLK0 101
CK0 CK1
102 DDRB_CLK1
DDRB_CLK1 7 +1.35V_VDDQ
Place near JDIMM1.203 & JDIMM1.204 7 DDRB_CLK0#
DDRB_CLK0# 103
105 CK0# CK1#
104
106
DDRB_CLK1#
DDRB_CLK1# 7
L +VREF_CB 15mil
DDRB_SMA10 107 VDD11 VDD12 108 DDRB_SBS1#
A10/AP BA1 DDRB_SBS1# 7
DDRB_SBS0# 109 110 DDRB_SRAS#
7 DDRB_SBS0# BA0 RAS# DDRB_SRAS# 7
111 112
VDD13 VDD14

2
DDRB_SWE# 113 114 DDRB_SCS0#
+0.675VS 7 DDRB_SWE# WE# S0# DDRB_SCS0# 7
DDRB_SCAS# 115 116 DDRB_ODT0 RD16
7 DDRB_SCAS# CAS# ODT0 DDRB_ODT0 7
117 118 1K_0402_1%
DDRB_SMA13 119 VDD15 VDD16 120 DDRB_ODT1 +VREF_CB
A13 ODT1 DDRB_ODT1 7
DDRB_SCS1# 121 122
@

1
7 DDRB_SCS1# S1# NC2
@ @ 123
VDD17 VDD18
124 15mil
CD41

1U_0402_6.3V6K

CD51

1U_0402_6.3V6K

CD54

CD48

CD53

10U_0603_6.3V6M

CD52

10U_0603_6.3V6M

CD49

10U_0603_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K

125 126
127 NCTEST VREF_CA 128
1 1 1 1 1 1 1 VSS27 VSS28

0.1U_0402_16V7K
DDRB_SDQ32 129 130 DDRB_SDQ36
DQ32 DQ36

2
DDRB_SDQ33 131 132 DDRB_SDQ37
DQ33 DQ37

CD55

1000P_0603_50V7K
133 134 1 RD17
VSS29 VSS30

1
2 2 2 2 2 2 2 DDRB_SDQS4# 135 136 DDRB_SDM4
7 DDRB_SDQS4# DQS#4 DM4 1K_0402_1%

CD30
DDRB_SDQS4 137 138
7 DDRB_SDQS4 DQS4 VSS31
139 140 DDRB_SDQ38

1
DDRB_SDQ34 141 VSS32 DQ38 142 DDRB_SDQ39 2
DDRB_SDQ35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDRB_SDQ44
DDRB_SDQ40 147 VSS34 DQ44 148 DDRB_SDQ45
DDRB_SDQ41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDRB_SDQS5#
VSS36 DQS#5 DDRB_SDQS5# 7
DDRB_SDM5 153 154 DDRB_SDQS5
DM5 DQS5 DDRB_SDQS5 7
155 156
DDRB_SDQ42 157 VSS37 VSS38 158 DDRB_SDQ46
DDRB_SDQ43 159 DQ42 DQ46 160 DDRB_SDQ47
B
161 DQ43 DQ47 162 B
VSS39 VSS40
Layout Note: DDRB_SDQ48
DDRB_SDQ49
163
165 DQ48 DQ52
164
166
DDRB_SDQ52
DDRB_SDQ53
Place near JDIMM1 167 DQ49 DQ53 168
DDRB_SDQS6# 169 VSS41 VSS42 170 DDRB_SDM6
Layout Note: Place these 4 Caps near Command 7 DDRB_SDQS6#
DDRB_SDQS6 171 DQS#6 DM6 172
and Control signals of DIMMA 7 DDRB_SDQS6 DQS6 VSS43
173 174 DDRB_SDQ54
DDRB_SDQ50 175 VSS44 DQ54 176 DDRB_SDQ55
DDRB_SDQ51 177 DQ50 DQ55 178
+1.35V_VDDQ 179 DQ51 VSS45 180 DDRB_SDQ60
DDRB_SDQ56 181 VSS46 DQ60 182 DDRB_SDQ61
@ @ @ DDRB_SDQ57 183 DQ56 DQ61 184
185 DQ57 VSS47 186 DDRB_SDQS7#
VSS48 DQS#7 DDRB_SDQS7# 7
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

1 DDRB_SDM7 187 188 DDRB_SDQS7

DM7 DQS7 DDRB_SDQS7 7
CD37

CD46

CD45

CD40

CD42

CD56

CD44

CD43

CD47

CD39

1 1 1 1 1 1 1 1 1 1 @ 189 190
+ CD36 DDRB_SDQ58 191 VSS49 VSS50 192 DDRB_SDQ62
47U 6.3V M B1 ESR70M +3VS DDRB_SDQ59 193 DQ58 DQ62 194 DDRB_SDQ63
195 DQ59 DQ63 196
2 2 2 2 2 2 2 2 2 2 2 RD7 1 2 10K_0402_5% 197 VSS51 VSS52 198 MEM_MB_EVENT#
SA0 EVENT# MEM_MB_EVENT# 7
199 200
+3VS VDDSPD SDA FCH_SDATA0 11,15
2.2U_0603_6.3V6K

0.1U_0402_16V7K

2 1 201 202
SA1 SCL FCH_SCLK0 11,15
CD38

1 @1 203 204 +0.675VS

VTT1 VTT2
CD31

@ RD9
0_0402_5% 205 206
G1 G2
2 2 LCN_DAN06-K4406-0102

DDR3 SO-DIMM B CONN@

+1.35V_VDDQ
+1.35V_VDDQ

01/15 update DDR address 10 to 01

DIMM_B REV H:8mm
Standard
@ @ @ @
0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

CD61

CD62

CD63

CD64

1 1 1 1 for common design

CD33

CD34

CD35

CD32

A 1 1 1 1 <Address: 01> A
180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

180P_0402_50V8J

@ @ @ @ 2 2 2 2
2 2 2 2

SI# 8/16 Reserve 4 pcs 0.1uF for EMI noise issue 3/2 Reserve 4 pcs 180pF for EMI DDR noise issue
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
Size Document Number Rev
10/05 change to PH. AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 12 of 47
5 4 3 2 1
 A B C D E

UH1A +3VALW
CH18 1 2 150P_0402_50V8J For PCIE device reset on FS1
HUDSON-2
APU_PCIE_RST#_C AE2 AF3 RF@
(GFX,GLAN,WLAN,LVDS Travis)
PCI Host Bus Reset (To EC) PCIE_RST# PCICLK0
RH1 1 2 33_0402_5% AD5 AF1 2 1

PCI CLKS
25,32,36 PLT_RST# A_RST# PCICLK1/GPO36 PCI_CLK1 15,16

5
AF5 33_0402_5% RF10 10/4 Eric Del.
CH1 1 2 .1U_0402_16V7K UMI_MTX_FRX_P0 AE30 PCICLK2/GPO37 AG2 2 RF@ 1 @ 2

P
6 UMI_MTX_C_FRX_P0 UMI_TX0P PCICLK3/GPO38 PCI_CLK3 16 B
CH2 1 2 .1U_0402_16V7K UMI_MTX_FRX_N0 AE32 AF6 2
33_0402_5% RF111 APU_PCIE_RST#_C RH2 1 2 33_0402_5% 4
6 UMI_MTX_C_FRX_N0 UMI_TX0N PCICLK4/14M_OSC/GPO39 PCI_CLK4 16 Y APU_PCIE_RST# 10,23,31
CH3 1 2 .1U_0402_16V7K UMI_MTX_FRX_P1 AD33 33_0402_5% RF12 1
6 UMI_MTX_C_FRX_P1 UMI_TX1P A

G
CH4 1 2 .1U_0402_16V7K UMI_MTX_FRX_N1 AD31 AB5 RF@ UH2
6 UMI_MTX_C_FRX_N1 UMI_TX1N PCIRST#
CH5 1 2 .1U_0402_16V7K UMI_MTX_FRX_P2 AD28 2 2 2 RH3 NC7SZ08P5X_NL_SC70-5
2
6 UMI_MTX_C_FRX_P2

3
CH6 1 2 .1U_0402_16V7K UMI_MTX_FRX_N2 AD29 UMI_TX2P RF14 RF15 @ 8.2K_0402_5%
6 UMI_MTX_C_FRX_N2 UMI_TX2N
CH7 1 2 .1U_0402_16V7K UMI_MTX_FRX_P3 AC30 AJ3 @RF@ 680P_0402_50V7K C75
6 UMI_MTX_C_FRX_P3 UMI_TX3P AD0/GPIO0
CH8 1 2 .1U_0402_16V7K UMI_MTX_FRX_N3 AC32 AL5 680P_0402_50V7K @RF@ @ 100P_0402_50V8J
6 UMI_MTX_C_FRX_N3

1
UMI_TX3N AD1/GPIO1 AG4 1 1 1 1
1 AD2/GPIO2 ESD@ 1
UMI_FTX_C_MRX_P0 AB33 AL6
6 UMI_FTX_C_MRX_P0 UMI_RX0P AD3/GPIO3
UMI_FTX_C_MRX_N0 AB31 AH3

PCI EXPRESS INTERFACES

6 UMI_FTX_C_MRX_N0 UMI_RX0N AD4/GPIO4
UMI_FTX_C_MRX_P1 AB28 AJ5 RH4 1 @ 2 0_0402_5%
6 UMI_FTX_C_MRX_P1 UMI_RX1P AD5/GPIO5
UMI_FTX_C_MRX_N1 AB29 AL1
6 UMI_FTX_C_MRX_N1 UMI_RX1N AD6/GPIO6
UMI_FTX_C_MRX_P2 Y33 AN5
6 UMI_FTX_C_MRX_P2 UMI_RX2P AD7/GPIO7
6 UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_N2
UMI_FTX_C_MRX_P3
Y31
Y28 UMI_RX2N AD8/GPIO8
AN6
AJ1 RF16
02/02 change +3VALW to +3VS for power rail leakage
6 UMI_FTX_C_MRX_P3 UMI_RX3P AD9/GPIO9
UMI_FTX_C_MRX_N3 Y29 AL8 @RF@
6 UMI_FTX_C_MRX_N3 UMI_RX3N AD10/GPIO10 AL3 680P_0402_50V7K
RH5 1 2 590_0402_1% PCIE_CALRP AF29 AD11/GPIO11 AM7 +3VS
RH6 1 2 2K_0402_1% PCIE_CALRN AF31 PCIE_CALRP AD12/GPIO12 AJ6
+PCIE_VDDR_FCH PCIE_CALRN AD13/GPIO13 AK7
V33 AD14/GPIO14 AN8
V31 GPP_TX0P AD15/GPIO15 AG9
GPP_TX0N AD16/GPIO16

2
2.2K_0402_5%

2.2K_0402_5%
W30 AM11
L PCIE_CALRP R=50ohm, 4mil,<1000mil
GPP_TX1P AD17/GPIO17

RH126

RH127
W32 AJ10 Delete GPU
PCIE_CALRN R=50ohm, 4mil,<1000mi
AB26
AB27
GPP_TX1N
GPP_TX2P
AD18/GPIO18
AD19/GPIO19
AL12
AK11
1202 Calvin
Touch@
@ Board ID
AA24 GPP_TX2N AD20/GPIO20 AN12
FCH_GPIO30 FCH_GPIO31

1
GPP_TX3P AD21/GPIO21
Del GPP PCI-E AA23
GPP_TX3N AD22/GPIO22
AG12
AE12
FCH_GPIO30
FCH_GPIO31
AD23/GPIO23 PCI_AD23 16
AA27 AC12
ABO connect to USB3.0 PHY. AA26
W27
GPP_RX0P
GPP_RX0N
AD24/GPIO24
AD25/GPIO25
AE13
AF13
PCI_AD24
PCI_AD25
16
16
PX4 0 0

PCI INTERFACE
GPP_RX1P AD26/GPIO26 PCI_AD26 16
V27 AH13
GPP_RX1N AD27/GPIO27 PCI_AD27 16 Reserve 0 1

1
V26 AH14 TH1
VGA_PWRGD_R Change to GPIO51
W26 GPP_RX2P AD28/GPIO28 AD15 RH8 @
GPP_RX2N AD29/GPIO29 HDDHALT_LED# 25
W24 AC15 FCH_GPIO30 @ 100K_0402_5%
W23 GPP_RX3P
GPP_RX3N
AD30/GPIO30
AD31/GPIO31
AE16 FCH_GPIO31 Board ID DIS 1 0
AN3 RH7

2
CBE0# AJ8 100K_0402_5%
CBE1# UMA 1 1
2
20mil RH9 1 2 2K_0402_1% CLK_CALRN F27 CBE2#
AN10
AD12 2
+1.1VS_CKVDD CLK_CALRN CBE3# AG10
FRAME# AK9
DEVSEL# AL10
G30 IRDY# AF10
G28 PCIE_RCLKP TRDY# AE10
SS For "EXT" CLK mode, input to PCIE, PCIE_RCLKN PAR
APU_DISP_CLKP R26 STOP#
AH1
AM9
Del USB3.0_CLKREQ# PH.
8 APU_DISP_CLKP DISP_CLKP PERR# +RTCBATT
APU DISP APU_DISP_CLKN T26 AH8
8 APU_DISP_CLKN DISP_CLKN SERR# GPIO0 32
AG15
REQ0#
NSS H33
H31 DISP2_CLKP REQ1#/GPIO40
AG13
AF15 ESD@
1
CH101
20mils
DISP2_CLKN REQ2#/CLK_REQ8#/GPIO41 AM17 CRCLK_REQ# RH10 1 2 8.2K_0402_5% JRTC1 @
REQ3#/CLK_REQ5#/GPIO42 +3VS
APU_CLKP T24 AD16 0.1U_0402_16V4Z 1
8 APU_CLKP APU_CLKP GNT0# 2 1
APU APU_CLKN T23 AD13 2
8 APU_CLKN APU_CLKN GNT1#/GPO44 2
AD21
J30 GNT2#/SD_LED/GPO45 AK17 3
Delete GPU SLT_GFX_CLKP GNT3#/CLK_REQ7#/GPIO46 TH2 GND
VGA 1202 Calvin K29 AD19 R5 2 @ 1 PM_CLKRUN# PM_CLKRUN# 32 For EMI Requirement Close to U25 4
SLT_GFX_CLKN CLKRUN# AH9 0_0402_5% GND
LOCK#
H27
H28 GPP_CLK0P AF18
11/08 Reserved BIOS setting ACES_50271-0020N-001
GPP_CLK0N INTE#/GPIO32 AE18
CLK_PCIE_CR J27 INTF#/GPIO33 AC16
25 CLK_PCIE_CR GPP_CLK1P INTG#/GPIO34
12/25 Eric Del TP_INT#
card Reader CLK_PCIE_CR# K26 AD18
25 CLK_PCIE_CR# GPP_CLK1N INTH#/GPIO35 ACCEL_INT# 36
RF@
CLK_PCIE_MINI1 F33 CH9 1 2 15P_0402_50V8J
CLOCK GENERATOR

23 CLK_PCIE_MINI1 GPP_CLK2P
Wireless LAN CLK_PCIE_MINI1# F31 RH11 33_0402_5%
23 CLK_PCIE_MINI1# GPP_CLK2N B25 LPC_CLK0_EC_R 1 2 LPC_CLK0_EC
SS CLK_PCIE_LAN E33 LPCCLK0 RF@
LPC_CLK0_EC 16,32
APU_PG/APU_RST#/LDT_STP# : OD pin
24 CLK_PCIE_LAN GPP_CLK3P
Ethernet LAN CLK_PCIE_LAN# E31 D25 LPC_CLK1 DMA_ACTIVE# : IN/OD, 0.8V threshold
24 CLK_PCIE_LAN# GPP_CLK3N LPCCLK1 LPC_CLK1 16
D27 LPC_AD0 PROCHOT# : IN, 0.8V threshold
LAD0 LPC_AD0 23,32,36
M23 C28 LPC_AD1 LDT_STP : No use, NC
3 GPP_CLK4P LAD1 LPC_AD1 23,32,36 3
M24 A26 LPC_AD2 LPC_AD2 23,32,36 DMA active. The FCH drives the DMA_ACTIVE# to
GPP_CLK4N LAD2 A29 LPC_AD3
LPC

LAD3 LPC_AD3 23,32,36 APU to notify DMA activity. This will cause the APU
M27 A31 LPC_FRAME#
GPP_CLK5P LFRAME# LPC_FRAME# 23,32,36 to reestablish the UMI link quicker.
M26 B27
GPP_CLK5N LDRQ0#
Del MIN2,Card reader, USB 3.0 IC N25 LDRQ1#/CLK_REQ6#/GPIO49
AE27
AE19 SERIRQ
Del USB3.0_CLKREQ#
GPP_CLK6P SERIRQ/GPIO48 SERIRQ 32,36
N26
GPP_CLK6N
R23 10/4 Eric Del.
R24 GPP_CLK7P G25 ALLOW_STOP
L 25M_X1 and 25M_X1_R=50ohm, 4mil
GPP_CLK7N DMA_ACTIVE#
PROCHOT#
E28 EC_THERM_R# 1 @ 2
ALLOW_STOP 8
EC_THERM# 39,46,8
N27 E26 APU_PWRGD RH12 0_0402_5% for ESD Close FCH Side
25M_X2=50ohm, 4mil R27 GPP_CLK8P APU_PG G26
APU_PWRGD 46,8
APU

GPP_CLK8N LDT_STP# F26 APU_RST#

APU_RST# APU_RST# 8
CH10 2 1 10P_0402_50V8J +RTCBATT
J26
14M_25M_48M_OSC

1
TH3 H7
S5_CORE_EN F1 RTC_CLK_R 1 2 RH14
RTCCLK RTC_CLK 16,32
2

F3 RH13 22_0402_5% 1K_0402_5%

INTRUDER_ALERT#
25M_X1 C31 E6 RTCVCC_R RTC_CLK_R=50ohm, 4mil
GND

IN

25M_X1 VDDBT_RTC_G
S5 PLUS

L RTC_CLK=50ohm, 4mil

2
RH16 G2 32K_X1
32K_X1
1M_0402_5% W>=15mils
GND

OUT

25M_X2 C33
X1 25M_X2
W>=15mils +RTCVCC D1
25MHZ_10PF_X1E000311000900 G4 32K_X2 W>=15mils 2
4

32K_X2 1 2 1
RH17 510_0402_5% 3
+3VLP

0.1U_0402_16V4Z
2 1 1 1
CH11 10P_0402_50V8J BOLTON-M2_FCBGA656 CH12 CH13 1 BAV70W_SOT323-3
32K_X1 0.1U_0402_16V4Z 1U_0402_6.3V6K CH14 Update to +3VLP
2 2
4 1 2 32K_X2
2 L D23 close to U25 (FCH) 4
12/27 Eric Del J1 jumper.
RH130 20M_0402_5%
C1205,C1206
Change for G3 YC1
L 32K_X1=50ohm, 4mil,<1500mil
RTC timing issue
1 2
32K_X2=50ohm, 4mil,<1500mil 01/15 change R860 to Jump for Clear CMOS
2 32.768KHZ Q13FC1350000500
<improve amplitude> 2 Security Classification Compal Secret Data Compal Electronics, Inc.
CH15 CH16 2012/11/07 2012/11/07 Title
Issued Date Deciphered Date
1
22P_0402_50V8J
1
22P_0402_50V8J
10/22 Eric modify 32.768 footprint. THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Close to BOLTON-M2 DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 13 of 47
A B C D E
 A B C D E

+3VALW

UH1B
4MB SPI ROM 0.1U_0402_16V4Z
2
CH17
1

HUDSON-2 & Non-share ROM. CF15 39P_0402_50V8J

SATA_STX_DRX_P0 AK19 AL14 1 2
22 SATA_STX_DRX_P0 SATA_TX0P SD_CLK/SCLK_2/GPIO73
SATA_STX_DRX_N0 AM19 AN14 UH3 SA00003K810 @RF@
22 SATA_STX_DRX_N0 SATA_TX0N SD_CMD/SLOAD_2/GPIO74
HDD1 SATA_DTX_SRX_N0 AL20 SD_CD/GPIO75
AJ12
AH12
FCH_SPI_CS1#
FCH_SPI_MISO
1
2 CS# VCC
8
7 FCH_SPI_HOLD#
22 SATA_DTX_SRX_N0 SATA_RX0N SD_WP/GPIO76 SO/SIO1 HOLD#

SD CARD
SATA_DTX_SRX_P0 AN20 AK13 FCH_SPI_WP# 3 6 FCH_SPI_CLK_ROM
22 SATA_DTX_SRX_P0 SATA_RX0P SD_DATA0/SDATI_2/GPIO77 WP# SCLK
AM13 4 5 FCH_SPI_MOSI
AN22 SD_DATA1/SDATO_2/GPIO78 AH15 GND SI/SIO0
AL22 SATA_TX1P SD_DATA2/GPIO79 AJ14 MX25L3206EM2I-12G_SO8
SATA_TX1N SD_DATA3/GPIO80
AH20 AC4
1 AJ20 SATA_RX1N GBE_COL AD3 1
SATA_RX1P GBE_CRS AD9 +3VALW
AJ22 GBE_MDCK W10 10K_0804_8P4R_5%
AH22 SATA_TX2P GBE_MDIO AB8 RP12
SATA_TX2N GBE_RXCLK Check CS# PU R 1kor10k and pop/nopop
10/03 Eric del mSATA by customer GBE_RXD3
AH7 GBE_PHY_INTR 4 5
AM23 AF7 SCL v1.20 : If an SPI ROM is shared between FCH_SPI_HOLD# 3 6
AK23 SATA_RX2N GBE_RXD2 AE7 FCH_SPI_WP# 2 7
SATA_RX2P GBE_RXD1 the FCH and the Embedded Controller
AD7 a 10-K pull-up resistor to +3.3V_S5 is installed. FCH_SPI_CS1# 1 8
AH24 GBE_RXD0 AG8
AJ24 SATA_TX3P GBE_RXCTL/RXDV AD1
SATA_TX3N GBE_RXERR AB7

GBE LAN
AN24 GBE_TXCLK AF9
AL24 SATA_RX3N GBE_TXD3 AG6 GBE_COL / GBE_CRS / GBE_MDIO FCH_SPI_CS1#
SATA_RX3P GBE_TXD2 FCH_SPI_CS1# 32
AE8 GBE_RXERR / Left unconnected. FCH_SPI_MISO
FCH_SPI_MISO 32
AL26 GBE_TXD1 AD8 FCH_SPI_CLK
SATA_TX4P GBE_TXD0 FCH SCL V1.20 19-35 FCH_SPI_CLK 32
AN26 AB9 FCH_SPI_MOSI
SATA_TX4N GBE_TXCTL/TXEN FCH_SPI_MOSI 32
AC2

SERIAL ATA
AJ26 GBE_PHY_PD AA7
AH26 SATA_RX4N GBE_PHY_RST# W9 GBE_PHY_INTR
SATA_RX4P GBE_PHY_INTR
10/9 Eric change RH20 form 0 to 33(EMI).
AN29 RH58 33_0402_5%
AL28 SATA_TX5P V6 FCH_SPI_MISO 1 2 FCH_SPI_CLK_ROM
SATA_TX5N SPI_DI/GPIO164 V5 FCH_SPI_MOSI
SPI_DO/GPIO163

SPI ROM
AK27 V3 FCH_SPI_CLK_R 1 2 FCH_SPI_CLK
AM27 SATA_RX5N SPI_CLK/GPIO162 T6 FCH_SPI_CS1#
SATA_RX5P SPI_CS1#/GPIO165 V1 FCH_SPI_WP# RH20 33_0402_5%
ROM_RST#/SPI_WP#/GPIO161 2
AL29 RF17
AN31 NC6 EMI@ 680P_0402_50V7K
NC7 L30 @RF@ GBE_PHY_INTR
VGA_RED 1
AL31 Pulled-up to +3.3V_S5 with a 10-KΩ 5% resistor.
AL33 NC8
NC9 FCH SCL v1.20 #19-85
L32
2 AH33 VGA_GREEN 2
AH31 NC10 Add for EMI 201011291330
NC11 M29
AJ33 VGA_BLUE Removed RGMII/MII support and updated termination

VGA DAC
NC12
L SATA_CALRP=35ohm,<1000mil AJ31
NC13 M28
requirements for GBE_COL, GBE_CRS, GBE_RXERR
and GBE_MDIO when RGMII/MII interface is not used.
SATA_CALRN=35ohm,<1000mi VGA_HSYNC/GPO68 N30 10/4 Eric Del. FCH DGv1.20 / SCL v1.20
VGA_VSYNC/GPO69
M33
1K_0402_1% 2 1 RH21 SATA_CALRP AF28 VGA_DDC_SDA/GPO70 N32
SATA_CALRP VGA_DDC_SCL/GPO71

+AVDD_SATA 931_0402_1%2 1 RH22 SATA_CALRN AF27

SATA_CALRN K31 1 2
FCH Schematics Check List V1.20 VGA_DAC_RSET RH23 715_0402_1%
SATA_LED# AD22
25 SATA_LED# SATA_ACT#/GPIO67 V28
RH24 1 2 10K_0402_5% AUX_VGA_CH_P V29
+3VS AUX_VGA_CH_N
AF21

VGA MAINLINK
SATA_X1 U28
@ AUXCAL
T31
ML_VGA_L0P
AG21 ML_VGA_L0N
T33
T29
12/19 remove RH29, RH31 for HW request
SATA_X2 ML_VGA_L1P T28
ML_VGA_L1N R32
ML_VGA_L2P R30
ML_VGA_L2N P29
ML_VGA_L3P P28
ML_VGA_L3N

10/17 Eric add GPIO of 56,58,54. ML_VGA_HPD/GPIO229

C29

3 3

33 TOUCH_PAD_PWREN#
TOUCH_PAD_PWREN# AH16
AM15 FANOUT0/GPIO52 VIN0/GPIO175
N2 N2 Check?
FANOUT1/GPIO53
Confirm BT_ON# or BT_ON 23 BT_ON
BT_ON AJ16
FANOUT2/GPIO54
HW MONITOR
VIN1/GPIO176
M3 M3

Del W_DISABLE#_2 31 LANCB_DET#_PCH

WL_OFF#
AK15
AN16 FANIN0/GPIO56 VIN2/SDATI_1/GPIO177
L2 L2
10K_0804_8P4R_5%
23 WL_OFF# FANIN1/GPIO57
LAN_PWR_EN AL16 N4 N4 RP14
31 LAN_PWR_EN FANIN2/GPIO58 VIN3/SDATO_1/GPIO178
10/17 Eric modify BT_ON to pull low. N2 4 5
P1 N4 3 6
K6 K6 VIN4/SLOAD_1/GPIO179 2 7
TEMPIN0/GPIO171 P3 1 8
VIN5/SCLK_1/GPIO180
K5 K5 M1 RH25 1 2 10K_0402_5%
10K_0804_8P4R_5% TEMPIN1/GPIO172 VIN6/GBE_STAT3/GPIO181 @ Enabled integrated pull-down/up and left unconnected.
RP13 M5 M5
4 5 L2 K3 K3 VIN7/GBE_LED3/GPIO182
3 6 K6 TEMPIN2/GPIO173
10K_0804_8P4R_5% 2 7 K5 AG16
RP16 1 8 K3 M6 M6 NC1 AH10
4 5 LAN_PWR_EN TEMPIN3/TALERT#/GPIO174 NC2 A28
3 6 BT_ON NC3 G27
2 7 LANCB_DET#_PCH NC4 L4
1 8TOUCH_PAD_PWREN# NC5 10K_0804_8P4R_5%
+3VS
RP15
4 5
BOLTON-M2_FCBGA656 3 6 M6
2 7 M3
M5 1 8

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 14 of 47
A B C D E
 A B C D E

UH1D

HUDSON-2
FCH_PCIE_RST# IS FOR PCIE AB6 G8 TH5

USB MISC
TH4 PCIE_RST2#/PCI_PME#/GEVENT4# USBCLK/14M_25M_48M_OSC
EC_LID_OUT# R2
DEVICES ON Hudson-M2/M3 32 EC_LID_OUT#
W7 RI#/GEVENT22# B9 USB_RCOMP RH26 1 2 11.8K_0402_1%
SLP_S3# T3 SPI_CS3#/GBE_STAT1/GEVENT21# USB_RCOMP
32 SLP_S3# SLP_S3#
SLP_S5# W2 H1
32 SLP_S5# SLP_S5# USB_FSD1P/GPIO186
PBTN_OUT# J4 H3 Hudson-M2/M3
32 PBTN_OUT# PWR_BTN# USB_FSD1N
FCH_PWRGD N7 OHCI CTL
32 FCH_PWRGD PWR_GOOD

USB 1.1
H6 DEV 20, Fn 5

ACPI / WAKE UP EVENTS

TEST0 T9 USB_FSD0P/GPIO185 H5
TEST0 USB_FSD0N <Disable CTL>
TEST1 T10
TEST2 V9 TEST1/TMS H10
TEST2 USB_HSD13P G10
1
EC_GA20 AE22 USB_HSD13N 1
32 EC_GA20 GA20IN/GEVENT0#
02/22 Add SUS_STAT# USB_HSD12P
K10 Hudson-M2 Hudson-M3
EC_KBRST# AG19 J12 EHCI CTL xHCI CTL
32 EC_KBRST# KBRST#/GEVENT1# USB_HSD12N
EC_SCI# R9 DEV 22, Fn 2 DEV 16, Fn 1
THERMTRIP:
Check with BIOS 32 EC_SCI#
EC_SMI# C26 LPC_PME#/GEVENT3# G12 USB20_P11 <Disable CTL of M2> xHCI CTL
32 EC_SMI# LPC_SMI#/GEVENT23# USB_HSD11P USB20_P11 26
Need level shift from +3VALW to +1.5V 36 SUS_STAT#
SUS_STAT# T5
LPC_PD#/GEVENT5# USB_HSD11N
F12 USB20_N11
USB20_N11 26 USB 2.0 port(Left-2) DEV 16, Fn 0
SYS_RESET# U4
Note: Ensure FCH internal pull-up resistor FCH_PCIE_WAKE# K1 SYS_RESET#/GEVENT19# K12 USB20_P10
23,24 FCH_PCIE_WAKE# WAKE#/GEVENT8# USB_HSD10P USB20_P10 27
to +3.3V S5 is disabled to prevent leakage V7
IR_RX1/GEVENT20# USB_HSD10N
K13 USB20_N10
USB20_N10 27 USB 2.0 port(Left-1)/ Charger
when APU is powered down. H_THERMTRIP# R10
8 H_THERMTRIP# THRMTRIP#/SMBALERT#/GEVENT2#
WD_PWRGD AF19 B11
WD_PWRGD USB_HSD9P
EC_RSMRST# U2 USB_HSD9N
D11 Del USB port 9 Hudson-M2/M3
32 EC_RSMRST# RSMRST# EHCI CTL
E10 USB20_P8 DEV 19, Fn 2
USB_HSD8P USB20_P8 23
SM bus 0-->S0 PWR domain Del MINI2_CLKREQ# AG24
CLK_REQ4#/SATA_IS0#/GPIO64 USB_HSD8N
F10 USB20_N8
USB20_N8 23 Mini1-WLAN
LAN_CLKREQ# AE24
SM bus 1-->S5 PWR domain 24 LAN_CLKREQ#
AE26 CLK_REQ3#/SATA_IS1#/GPIO63 C10
SMARTVOLT1/SATA_IS2#/GPIO50 USB_HSD7P
SATA_ODD_PRSNT_R_N AF22 A10 Del USB port 7

USB 2.0
AH17 CLK_REQ0#/SATA_IS3#/GPIO60 USB_HSD7N
FCH GEVENT (S5 domain) SATA_IS4#/FANOUT3/GPIO55
with isolation circuit to avoid leakage PC_BEEP use. AG18
SATA_IS5#/FANIN3/GPIO59 USB_HSD6P
H9
28 FCH_SPKR
FCH_SPKR AF24
SPKR/GPIO66 USB_HSD6N
G9 01/30 Eric del WWAM for USB 6.
H_THERMTRIP# FCH_SCLK0 AD26

GPIO
11,12 FCH_SCLK0 SCL0/GPIO43
FCH_SDATA0 AD25 A8 USB20_P5
11,12 FCH_SDATA0 SDA0/GPIO47 USB_HSD5P USB20_P5 20
20 Camera
FCH_SCLK1 T7 C8 USB20_N5
18,33 FCH_SCLK1 SCL1/GPIO227 USB_HSD5N USB20_N5
2 FCH_SDATA1 R7
18,33 FCH_SDATA1 SDA1/GPIO228
MINI1_CLKREQ# AG25 F8 USB20_P4
23 MINI1_CLKREQ# CLK_REQ2#/FANIN4/GPIO62 USB_HSD4P USB20_P4 20
20 Touch
C72 CR_CLKREQ# AG22 E8 USB20_N4 Hudson-M2/M3
25 CR_CLKREQ# CLK_REQ1#/FANOUT4/GPIO61 USB_HSD4N USB20_N4
100P_0402_50V8J J2 EHCI CTL
1 AG26 IR_LED#/LLB#/GPIO184 C6
ESD@ SMARTVOLT2/SHUTDOWN#/GPIO51 USB_HSD3P DEV 18, Fn 2
V8 A6 <Support Wakeup>
WWAN_OFF# W8 DDR3_RST#/GEVENT7#/VGA_PD USB_HSD3N
Y6 GBE_LED0/GPIO183 C5
V10 SPI_HOLD#/GBE_LED1/GEVENT9# USB_HSD2P A5
AA8 GBE_LED2/GEVENT10# USB_HSD2N
GBE_STAT0/GEVENT11#
10/18 Eric Add SATA_ODD/PCH_AUDIO control pin. AF25
CLK_REQG#/GPIO65/OSCIN/IDLEEXIT# USB_HSD1P
C1
Del ODD_DA# USB_HSD1N
C3

2
RH27 Del SIMB output SMIB M7
BLINK/USB_OC7#/GEVENT18# USB_HSD0P
E1 USB20_P0
USB20_P0 24 2
R8
USB_OC6#/IR_TX1/GEVENT6# USB_HSD0N
E3 USB20_N0
USB20_N0 24 USB 2.0 / To IO Board. 10/29 change from 2 to 1.
2 1CARD_DET_FCH T1

USB OC
+3VALW USB_OC5#/IR_TX0/GEVENT17#
TH6
P6
F5 USB_OC4#/IR_RX0/GEVENT16# USBSS_CALRP
C16
A16
USBSS_CALRP
USBSS_CALRN
RH55
RH56
1
1
2 1K_0402_1%
2 1K_0402_1% L USBSS_CALRP=35ohm,<1000mil
10K_0402_5% CARD_DET_FCH P5 USB_OC3#/AC_PRES/TDO/GEVENT15# USBSS_CALRN +FCH_VDD_11_SSUSB_S
USBSS_CALRN=35ohm,<1000mi
@ USB_OC1# J7 USB_OC2#/TCK/GEVENT14# A14
27,31 USB_OC1# USB_OC1#/TDI/GEVENT13# USB_SS_TX3P
USB_OC0# T8 C14
26 USB_OC0# USB_OC0#/SPI_TPM_CS#/TRST#/GEVENT12# USB_SS_TX3N
Hudson-M3
C12 xHCI CTL
USB_SS_RX3P A12
USB_SS_RX3N DEV 16, Fn 1
xHCI CTL
Confirm CR det or not. HDA_BITCLK
HDA_SDOUT
AB3
AB1 AZ_BITCLK USB_SS_TX2P
D15
B15
DEV 16, Fn 0
+3VS HDA_SDIN0 AA2 AZ_SDOUT USB_SS_TX2N

HD AUDIO
28 HDA_SDIN0 AZ_SDIN0/GPIO167
33ohm termination HDA_SDIN1 Y5 E14

USB 3.0
1 2 WWAN_OFF# HDA_SDIN2 Y3 AZ_SDIN1/GPIO168 USB_SS_RX2P F14
resistor at CODEC side AZ_SDIN2/GPIO169 USB_SS_RX2N
RH57 10K_0402_5% RP17 HDA_SDIN3 Y1
+3VALW 4 5 HDA_RST# HDA_SYNC AD6 AZ_SDIN3/GPIO170 F15 USB3_TX1_P
28 HDA_RST_AUDIO# AZ_SYNC USB_SS_TX1P USB3_TX1_P 26
3 6 HDA_SYNC HDA_RST# AE4 G15 USB3_TX1_N
28 HDA_SYNC_AUDIO AZ_RST# USB_SS_TX1N USB3_TX1_N 26
2 7 +3VS
13,16 PCI_CLK1
100K_0804_8P4R_5%
28 HDA_SDOUT_AUDIO
1 8 HDA_SDOUT
Change GPIO fellow Pumori USB_SS_RX1P
H13
G13
USB3_RX1_P
USB3_RX1_N
USB3_RX1_P 26 USB 3.0 port(Left-2)
USB_SS_RX1N USB3_RX1_N 26
RP18 33_0804_8P4R_5%
4 5 TH8 K19 J16 USB3_TX0_P
PS2_DAT/SDA4/GPIO187 USB_SS_TX0P USB3_TX0_P 26
3 6 Del FCH_GPIO187 TH9 J19
PS2_CLK/CEC/SCL4/GPIO188 USB_SS_TX0N
H16 USB3_TX0_N
USB3_TX0_N 26
USB_OC1# 2
1
7
8USB_OC0#
33_0402_5%
RH28 1 2HDA_BITCLK
J21
SPI_CS2#/GBE_STAT2/GPIO166 J15 USB3_RX0_P
USB 3.0 port(Left-1)
28 HDA_BITCLK_AUDIO USB_SS_RX0P USB3_RX0_P 26
2 EMI@ K15 USB3_RX0_N
USB_SS_RX0N USB3_RX0_N 26
10/5 Eric modify for EMI requirement RH65 close to PCH
D21 RP19
PS2KB_DAT/GPIO189
12/20 Del DDR3L_EN 1
RF@
RF9
TH7 C20
D23 PS2KB_CLK/GPIO190 SCL2/GPIO193
H19
G19
H19
G19
G22
G21
4
3
5
6
+3VS +3VALW 15P_0402_50V8J C22 PS2M_DAT/GPIO191 EMBEDDED CTRL SDA2/GPIO194 G22 G22 H19 2 7
10K_0804_8P4R_5% PS2M_CLK/GPIO192 SCL3_LV/GPIO195 G21 G21 G19 1 8
RP20 SDA3_LV/GPIO196 E22
1 @ 2 EC_LID_OUT# 4 5 FCH_PCIE_WAKE# EC_PWM0/EC_TIMER0/GPIO197 H22 10K_0804_8P4R_5%
RH29 100K_0402_5% 3 6 H_THERMTRIP# TH11 F21 EC_PWM1/EC_TIMER1/GPIO198 J22 EC_PWM2
3 KSO_0/GPIO209 EC_PWM2/EC_TIMER2/WOL_EN/GPIO199 EC_PWM2 16 3
2 7 CR_CLKREQ# TH10 E20 H21
1 @ 2 SYS_RESET# 1 8 WD_PWRGD TH13 F20 KSO_1/GPIO210 EC_PWM3/EC_TIMER3/GPIO200
RH30 10K_0402_5% TH12 A22 KSO_2/GPIO211 K21
1 @ 2 SMIB TH15 E18 KSO_3/GPIO212 KSI_0/GPIO201 K22
KSO_4/GPIO213 KSI_1/GPIO202 For PCIE device reset on FS1
RH31 10K_0402_5% TH14 A20 F22
+3VS +3VALW TH17 J18 KSO_5/GPIO214 KSI_2/GPIO203 F24
(GFX,GLAN,WLAN,LVDS Travis)
2.2K_0804_8P4R_5% TH16 H18 KSO_6/GPIO215 KSI_3/GPIO204 E24
RP21 TH19 G18 KSO_7/GPIO216 KSI_4/GPIO205 B23
4 5 FCH_SCLK1 TH18 B21 KSO_8/GPIO217 KSI_5/GPIO206 C24
3 6 FCH_SDATA1 TH21 K18 KSO_9/GPIO218 KSI_6/GPIO207 F18
For FCH internal debug use KSO_10/GPIO219 KSI_7/GPIO208
2 7 FCH_SDATA0 TH20 D19
1 @ 2 TEST0 1 8 FCH_SCLK0 TH23 A18 KSO_11/GPIO220
RH32 2.2K_0402_5% TH22 C18 KSO_12/GPIO221
1 @ 2 TEST1 TH25 B19 KSO_13/GPIO222
RH33 2.2K_0402_5% +3VS TH24 B17 KSO_14/GPIO223
1 @ 2 TEST2 TH27 A24 KSO_15/GPIO224
RH34 2.2K_0402_5% TH26 D17 KSO_16/GPIO225
KSO_17/GPIO226
@
1 2 SATA_ODD_PRSNT_R_N BOLTON-M2_FCBGA656
RH66 10K_0402_5%
+3VS +3VALW

RH128 2.2K_0402_5% 11/20 Eric add test point from TH8 ~ TH26.
1 2 LAN_CLKREQ#

1 2 MINI1_CLKREQ#

+3VS RH129 2.2K_0402_5%

Del FCH_GPIO187 R57 R55
Del MINI2_CLKREQ# PH.
1 2 LAN_CLKREQ#
RH35 @ 8.2K_0402_5% 12/06 Del VGA_PWRGD
1 @ 2 EC_RSMRST#
RH36 2.2K_0402_5%
1 @ 2 HDA_BITCLK
4 RH37 10K_0402_5% 4
1 @ 2 HDA_SDIN0
RH38 10K_0402_5%
1 @ 2 HDA_SDIN1
RH39 10K_0402_5%
1 @ 2 HDA_SDIN2
RH40 10K_0402_5%
1 @ 2 HDA_SDIN3
RH41 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

10/4 Eric Del. Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 15 of 47
A B C D E
 A B C D E

Change to SPI

STRAP PINS
PCI_CLK1 PCI_CLK3 PCI_CLK4 LPC_CLK0 LPC_CLK1 EC_PWM2 RTC_CLK

1
PULL ALLOW USE NON_FUSION EC CLKGEN LPC ROM S5 PLUS 1

HIGH PCIE GEN2 DEBUG CLOCK MODE ENABLED ENABLED MODE

STRAPS DISABLED
DEFAULT DEFAULT DEFAULT

PULL FORCE IGNORE FUSION EC CLKGEN SPI ROM S5 PLUS

LOW PCIE GEN1 DEBUG CLOCK DISABLED DISABLE MODE
STRAP MODE DEFAULT ENABLED
DEFAULT DEFAULT DEFAULT

+3VS +3VS +3VALW +3VALW

+3VALW
RH42 10K_0402_5%

RH43 10K_0402_5%

RH44 10K_0402_5%

RH45 10K_0402_5%
1

1
RP23
10K_0804_8P4R_5%
@ @ @ @
1 8 LPC_CLK1
2 7 RTC_CLK
2

2
3 6
4 5
13,15 PCI_CLK1

2 13 PCI_CLK3 2

13 PCI_CLK4

13,32 LPC_CLK0_EC

13 LPC_CLK1

15 EC_PWM2

13,32 RTC_CLK
RH46 10K_0402_5%

RH47 10K_0402_5%

RH48 2.2K_0402_5%

RH49 2.2K_0402_5%
Remove VGA_PD
5
6
7
8
1

1
RP24
10K_0804_8P4R_5%
@ @ @
4
3
2
1
2

2
DEBUG STRAPS Remove VGA_PD

FCH HAS 15K INTERNAL PU FOR PCI_AD[27:23]

3 3

PCI_AD27 PCI_AD26 PCI_AD25 PCI_AD24 PCI_AD23

USE PCI DISABLE USE FC USE DEFAULT DISABLE PCI

PULL PLL ILA PLL PCIE STRAPS MEM BOOT
HIGH AUTORUN
DEFAULT DEFAULT DEFAULT DEFAULT DEFAULT

PULL BYPASS ENABLE BYPASS USE EEPROM ENABLE PCI

LOW PCI PLL ILA FC PLL PCIE STRAPS MEM BOOT
AUTORUN

13 PCI_AD27

13 PCI_AD26

13 PCI_AD25

13 PCI_AD24

13 PCI_AD23
RH50 2.2K_0402_5%

RH51 2.2K_0402_5%

RH52 2.2K_0402_5%

RH53 2.2K_0402_5%

RH54 2.2K_0402_5%

4 4
1

@ @ @ @ @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 16 of 47
A B C D E
 A B C D E

+VCC_FCH_R +1.1VS
UH1C 1007mA RH109
131mA 10mils @ @ @ @ 1 @ 2

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z

22U_0805_6.3V6M
RH110 @ @ HUDSON-2
50mils

CH27

CH28

CH29

CH30

CH31

CH32
+3VS 1 @ 2 +VDDIO_33_PCIGP AB17 T14 0_0805_5%
+3VS VDDIO_33_PCIGP_1 VDDCR_11_1

2.2U_0603_6.3V4Z

.1U_0402_16V7K

.1U_0402_16V7K

.1U_0402_16V7K
AB18 T17 1 1 1 1 1 1
VDDIO_33_PCIGP_2 VDDCR_11_2

CH34

CH35

CH36
LH2 0_0603_5% AE9 T20 UH1E

PCI/GPIO I/O
VDDIO_33_PCIGP_3 VDDCR_11_3

CH33
1 @ 2 +VDDPL_3.3V @ 1 1 1 1 AD10 U16
VDDIO_33_PCIGP_4 VDDCR_11_4

2.2U_0603_6.3V4Z
AG7 U18 HUDSON-2

.1U_0402_16V7K
VDDIO_33_PCIGP_5 VDDCR_11_5 2 2 2 2 2 2

CORE S0
CH37

CH38
0_0603_5% AC13 V14 A3 T25
1 AB12 VDDIO_33_PCIGP_6 VDDCR_11_6 V17 A33 VSS VSS T27 1
220 ohm 1 1 2 2 2 2 VDDIO_33_PCIGP_7 VDDCR_11_7 VSS VSS
AB13 V20 B7 U6
AB14 VDDIO_33_PCIGP_8 VDDCR_11_8 Y17 B13 VSS VSS U14
AB16 VDDIO_33_PCIGP_9 VDDCR_11_9 +1.1VS_CKVDD +1.1VS D9 VSS VSS U17
2 2 VDDIO_33_PCIGP_10 VSS VSS
47mA 10milsH24 20mils 340mA RH111 D13
VSS VSS
U20
+VDDPL_3.3V H26 +1.1VS_CKVDD 1 @ 2 E5 U21
VDDPL_33_SYS VDDAN_11_CLK_1 VSS VSS

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
20mA 10milsV22 VDDAN_11_CLK_2
J25 @ @ @ E12
VSS VSS
U30

CH39

CH40

CH41

CH42

CH43
K24 0_0603_5% E16 U32

CLKGEN I/O
VDDPL_33_DAC VDDAN_11_CLK_3 VSS VSS
20mA 10milsU22 VDDAN_11_CLK_4
L22 1 1 1 1 1 E29
VSS VSS
V11
12/19 change to GND M22 F7 V16
VDDPL_33_ML VDDAN_11_CLK_5 VSS VSS
200mA 10milsT22 VDDAN_11_CLK_6
N21 F9
VSS VSS
V18
N22 F11 W4
VDDAN_33_DAC VDDAN_11_CLK_7 2 2 2 2 2 VSS VSS
20mA 10milsL18 VDDAN_11_CLK_8
P22 F13
VSS VSS
W6
+FCH_VDDPL_33_SSUSB_S F16 W25
VDDPL_33_SSUSB_S VSS VSS
VDDPL_33_SSUSB_S M3 only 17mA 10mils D7 F17
VSS VSS
W28
+PCIE_VDDR_FCH +1.1VS
For Hudson3 USB3.0 only +FCH_VDDPL_33_USB_S
VDDPL_33_USB_S 50mils F19
VSS VSS
Y14
43mA 10mils VDDAN_11_PCIE_1
AB24 1088mA RH115 F23
VSS VSS
Y16
For Hudson2, connect to GND +VDDPL_33_PCIE AH29 Y21 +PCIE_VDDR_FCH 1 @ 2 F25 Y18
VDDPL_33_PCIE VDDAN_11_PCIE_2 VSS VSS

PCI EXPRESS

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
93mA 10mils VDDAN_11_PCIE_3
AE25 @ @ @ F29
VSS VSS
AA6

CH47

CH48

CH49

CH50

CH51
LDO_CAP: Internally generated 1.8V +VDDPL_33_SATA AG28 AD24 0_0805_5% G6 AA12
VDDPL_33_SATA VDDAN_11_PCIE_4 AB23 G16 VSS VSS AA13
supply for the RGB outputs VDDAN_11_PCIE_5 1 1 1 1 1 VSS VSS
For A11: Cap = 1nF @ AA22 G32 AA14
+3VALW 1 2 M31 VDDAN_11_PCIE_6 AF26 H12 VSS VSS AA16
LH4
For A12, Cap = DNI CH46 2.2U_0603_6.3V4Z LDO_CAP VDDAN_11_PCIE_7 AG27 H15 VSS VSS AA17
VDDAN_11_PCIE_8 2 2 2 2 2 VSS VSS
1 @ 2+FCH_VDDPL_33_SSUSB_S 7mA 10mils H29 AA25

GROUND
VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

V21 J6 AA28
VDDPL_11_DAC +1.1VS VSS VSS
CH52

CH53

0_0603_5% 226mA 60mils J9

VSS VSS
AA30
220 ohm 1 1 VDDAN_11_SATA_1
AA21 1337mA+AVDD_SATA RH118 J10
VSS VSS
AA32
20mils VDDAN_11_SATA_4
Y20 +AVDD_SATA 1 @ 2 J13
VSS VSS
AB25

1U_0402_6.3V6K

1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

22U_0805_6.3V6M
Y22 AB21 @ @ @ J28 AC6
VDDAN_11_ML_1 VDDAN_11_SATA_2 VSS VSS

MAIN LINK

CH57

CH58

CH59

CH60

CH61
@ V23 AB22 0_0805_5% J32 AC18

SERIAL ATA
2 2 V24 VDDAN_11_ML_2 VDDAN_11_SATA_3 AC22 K7 VSS VSS AC28
VDDAN_11_ML_3 VDDAN_11_SATA_5 1 1 1 1 1 VSS VSS
2
M3 only 12/19 change to GND V25
VDDAN_11_ML_4 VDDAN_11_SATA_6
AC21
AA20
K16
K27 VSS VSS
AD27
AE6
2

VDDAN_11_SATA_7 AA18 K28 VSS VSS AE15

+VDDAN_33_USB VDDAN_11_SATA_8 AB20 2 2 2 2 2 L6 VSS VSS AE21
LH6 VDDAN_11_SATA_9 AC19 L12 VSS VSS AE28
1 @ 2+FCH_VDDPL_33_USB_S AB10 VDDAN_11_SATA_10 +3VALW L13 VSS VSS AF8
VDDIO_33_GBE_S RH119 VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

10mils 59mA L15

VSS VSS
AF12
CH62

CH63

0_0603_5% AB11 N18 +VDDIO_33_S 1 2 L16 AF16

VDDCR_11_GBE_S_1 VDDIO_33_S_1 VSS VSS

GBE LAN

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
220 ohm 1 1 AA11 L19 @ L21 AF33
VDDCR_11_GBE_S_2 VDDIO_33_S_2 VSS VSS

CH64

CH65

CH66
M18 M13 AG30
VDDIO_33_S_3 0_0402_5% VSS VSS

3.3V_S5 I/O
AA9 V12 1 1 1 M16 AG32
AA10 VDDIO_GBE_S_1 VDDIO_33_S_4 V13 @ M21 VSS VSS AH5
2 @2 +3VALW VDDIO_GBE_S_2 VDDIO_33_S_5 Y12 M25 VSS VSS AH11
VDDIO_33_S_6 VSS VSS
LH7 658mA 30mils VDDIO_33_S_7
Y13
2 2 2
N6
VSS VSS
AH18
1 @ 2 +VDDAN_33_USB G7 W11 N11 AH19
VDDAN_33_USB_S_1 VDDIO_33_S_8 VSS VSS
1U_0402_6.3V6K

1U_0402_6.3V6K

10U_0603_6.3V6M

10U_0603_6.3V6M

.1U_0402_16V7K
H8 N13 AH21
+3VS VDDAN_33_USB_S_2 +3VALW VSS VSS
CH67

CH68

CH69

CH70

CH71
0_0603_5% J8 N23 AH23
VDDAN_33_USB_S_3 LH9 VSS VSS
LH8 220 ohm/3A 1 1 1 1 1 K8
VDDAN_33_USB_S_4 10mils 5mA N24
VSS VSS
AH25
1 @ 2+VDDPL_33_PCIE K9 G24 +VDDXL_3.3V 1 2 P12 AH27
VDDAN_33_USB_S_5 VDDXL_33_S VSS VSS
2.2U_0603_6.3V4Z

.1U_0402_16V7K

.1U_0402_16V7K

2.2U_0603_6.3V4Z
M9 @ P18 AJ18
VDDAN_33_USB_S_6 VSS VSS
CH72

CH73

CH74

CH75
0_0603_5% M10 P20 AJ28
2 2 2 2 2 N9 VDDAN_33_USB_S_7 0_0402_5% P21 VSS VSS AJ29
220 ohm 1 1 VDDAN_33_USB_S_8 1 1 VSS VSS
N10 @ P31 AK21
@ @ @ M12 VDDAN_33_USB_S_9 P33 VSS VSS AK25
VDDAN_33_USB_S_10 VSS VSS
2 @2
N12
M11 VDDAN_33_USB_S_11 2 2 Del L30 R4
R11 VSS VSS
AL18
AM21
+1.1VALW VDDAN_33_USB_S_12 R25 VSS VSS AM25
+1.1VALW VSS VSS
LH10 140mA 10mils R28 AN1

USB
VSS VSS
1 @ 2 @ +VDDAN_11_USB_S U12
VDDAN_11_USB_S_1 10mils 187mA RH121 T11
VSS VSS
AN18
2.2U_0603_6.3V4Z

.1U_0402_16V7K

U13 N20 +VDDCR_1.1V 1 @ 2 T16 AN28

+3VS VDDAN_11_USB_S_2 VDDCR_11_S_1 VSS VSS
CH76

CH77

.1U_0402_16V7K

1U_0402_6.3V6K
0_0603_5% M20 @ T18 AN33
VDDCR_11_S_2 VSS VSS

CH78

CH79
LH11 220 ohm 1 1 0_0603_5%
3 1 @ 2+VDDPL_33_SATA N8 T21 3
1 1 SYSON 32,37,42 VSSAN_HWM VSSPL_DAC
2.2U_0603_6.3V4Z

.1U_0402_16V7K

L28
VSSAN_DAC
CH80

CH81

0_0603_5% K25 K33

VSSXL VSSANQ_DAC

2
2 2

G
220 ohm 1 1 @ N28
2 2 QH10 H25 VSSIO_DAC
3 1 AO3416L_SOT23-3 VSSPL_SYS R6
+1.1VALW EFUSE

D
2 @2 +1.1VALW
LH12 197mA 10mils
1 @ 2 +VDDCR_1.1V_USB T12
VDDCR_11_USB_S_1 10mils 70mA LH13
10U_0603_6.3V6M

2.2U_0603_6.3V4Z

.1U_0402_16V7K

.1U_0402_16V7K

T13 J24 +VDDPL_1.1V 1 2 BOLTON-M2_FCBGA656

VDDCR_11_USB_S_2 VDDPL_11_SYS_S
CH100

CH82

CH83

CH84

2.2U_0603_6.3V4Z
0_0603_5% @ MBK1608221YZF_2P

.1U_0402_16V7K
+1.1VS

CH85

CH86
220 ohm 1 1 1 1 Connected to VSS through a dedicated via.
1 1 LH14
1 @ 2
@ @ @ MBK1608221YZF_2P
2 2 2 2
2 2
220 ohm

+3VALW
+FCH_VDD_11_SSUSB_S RH122
20mils 10mils 12mA
RH123 282mA P16
VDDAN_11_SSUSB_S_1 VDDAN_33_HWM_S
M8 +VDDAN_33_HWM 1 2

2.2U_0603_6.3V4Z
1 @ 2 +VDDAN_SSUSB M14 @ AMD reply:

.1U_0402_16V7K
VDDAN_11_SSUSB_S_2
1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

CH87

CH88
N14 VDDAN_33_HWM_S: Please connect
VDDAN_11_SSUSB_S_3 0_0402_5%
CH89

CH90

CH91

For FCH M2 - BOM option 40mils 0_0603_5% P13 1 1 it to +3.3V_S5 directly if HWM is not used.
VDDAN_11_SSUSB_S_4
+FCH_VDD_11_SSUSB_S

VDDAN_11_SSUSB_S / VDDAN_11_SSUSB_S P14 @

1 1 1 VDDAN_11_SSUSB_S_5
Connected to VSS.
USB SS

2 2
Del M2 BOM option. 2 2 2 30mils
N16
N17 VDDCR_11_SSUSB_S_1 +3VS
VDDCR_11_SSUSB_S_2 RH124
@ @ P17
VDDCR_11_SSUSB_S_3 10mils 26mA
M17 AA4 +VDDIO_AZ 1 @ 2
4 VDDCR_11_SSUSB_S_4 VDDIO_AZ_S 0_0402_5% VDDIO_AZ_S should be tied to 4
POWER 1 2 +3.3/1.5V_S5 rail if Wake on Ring
LH5 RH125 424mA CH92 2.2U_0603_6.3V4Z is supported
+1.1VALW 1 @ 2 1 @ 2 +VDDCR_11_SSUSB BOLTON-M2_FCBGA656 1 2
1U_0402_6.3V6K

.1U_0402_16V7K

.1U_0402_16V7K

@ @ @ @ CH93 .1U_0402_16V7K
CH94

4.7U_0603_6.3V6K

CH95

CH96

CH97

M3 @-->SMT 0_0603_5% 0_0603_5%

42 ohm/4A 1 1 1 1
Security Classification Compal Secret Data Compal Electronics, Inc.
2 2 2 2 Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 17 of 47
A B C D E
 5 4 3 2 1

+DVCC33 UT1
+AVCC33
+3VS
RTD2136S

4.7U_0603_6.3V6K

0.1U_0402_16V7K

0.1U_0402_16V7K
RT1 1 LVDS@ 2 4.7K_0402_5% MIIC_SCL +DVCC33
1 1 1
RT2 1 @ 2 4.7K_0402_5% MIIC_SDA 35 LVDS_A_TXCLK+ LVDS@ @ LVDS@
TXOC+ LVDS_A_TXCLK+ 20

CT2

CT3
22 36 LVDS_A_TXCLK-
+DVCC33 PVCC TXOC- LVDS_A_TXCLK- 20

CT1
0_0603_5%
RP33 LT2 1 @ 2 +DVCC33 18 41 LVDS_A_TXOUT0+ 2 2 2
SWR_VDD TXO0+ LVDS_A_TXOUT0+ 20
4 5 LVDS_SCL 0_0603_5% 42 LVDS_A_TXOUT0-
TXO0- LVDS_A_TXOUT0- 20

PWR
3
2
6
7
LVDS_DAT
CIICSCL
LT3 1 @ 2 +AVCC33 5
DP_V33 39 LVDS_A_TXOUT1+
<LVDS panel>
TXO1+ LVDS_A_TXOUT1+ 20
1 8 CIICSDA +SWR_V12 LT1 1 LVDS@ 2 +SW_LX 17
SWR_LX TXO1-
40 LVDS_A_TXOUT1-
LVDS_A_TXOUT1- 20
L close LT2 L
LVDS@
4.7K_0804_8P4R_5% 4.7UH_PG031B-4R7MS_1.1A_20%
RT3 @2 1 15 37 LVDS_A_TXOUT2+
close UT1 Pin5
D SWR_VCCK TXO2+ LVDS_A_TXOUT2+ 20 D
Ming9/19 Change R to R‐Pak 0_0805_5% 38 LVDS_A_TXOUT2-
TXO2- LVDS_A_TXOUT2- 20

10U_0603_6.3V6M

10U_0603_6.3V6M
43 +DVCC33
VCCK

4.7U_0603_6.3V6K
RP34 33

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4 5 EN_PVCC 11 TXO3+ 34
DP_V12 TXO3- 1 1 1 1 1 1 LVDS@

CT6

CT9
3 6 LVDS_PWM LVDS@ @ @ @

CT5

CT7

CT8
2 7 LVDS_BKLTEN_R

CT4
1 8 25 LVDS_B_TXCLK+
100K_0804_8P4R_5% EDP_T_LANE_P0 7 TXEC+ 26 LVDS_B_TXCLK-
LVDS_B_TXCLK+ 20
L 2 2 2 2 2 2

LVDS
LANE0P TXEC- LVDS_B_TXCLK- 20
LVDS@ EDP_T_LANE_N0 8 @
LANE0N 31 LVDS_B_R_TXOUT0+
EDP_T_LANE_P1 9 TXE0+ 32 LVDS_B_R_TXOUT0-
LANE1P TXE0-
EDP_T_LANE_N1 10
LANE1N <LVDS panel> close LT1 close UT1 Pin18 close UT1 Pin22

DP
RT4 1 @ 2 4.7K_0402_5% MIIC_SCL 29 LVDS_B_R_TXOUT1+
RT5 1 LVDS@ 2 4.7K_0402_5% MIIC_SDA EDP_T_AUX 4 TXE1+ 30 LVDS_B_R_TXOUT1-
AUX-CH_P TXE1-
<CPU> EDP_T_AUX# 3
AUX-CH_N 27 LVDS_B_R_TXOUT2+
TXE2+
10 EDP_HPD
1
EDP_HPD
2
2 LVDS@ 1
1K_0402_5%
1
DP_HPD TXE2-
28 LVDS_B_R_TXOUT2- close UT1 Pin43 close UT1 Pin11
LVDS@

10U_0603_6.3V6M
RT7 RT6 23 +SWR_V12
100K_0402_5% TXE3+ 24

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
TXE3-
1 1 1 1

CT11
<CPU> 10 APU_INVT_PWM
APU_INVT_PWM 21
PWMIN
LVDS@ @ @

CT10

CT12

CT13
@ T1 PAD~D 2 46 LVDS_SCL
TESTMODE MIICSCL1 LVDS_SCL 20
2LVDS@ 1 12 45 LVDS_DAT
DP_REXT MIICSDA1 LVDS_DAT 20 2 2 2 2

OTHERS
12K_0402_1%
LVDS_SCL
LVDS_DAT
RT9 1
RT10 1
@
@
2 0_0201_5%
2 0_0201_5%
MIIC_SCL
MIIC_SDA
RT8
PANEL_VCC
20
19
EN_PVCC
LVDS_PWM
EN_PVCC 20 <LVDS panel>
PWMOUT LVDS_PWM 20
MIIC_SCL 48 44 LVDS_BKLTEN_R
MIICSCL0 BL_EN
MIIC_SDA 47
MIICSDA0 L close LT3
C
Ming9/18 change 0ohm to new footprint close UT1 Pin15 C
RT11 1 @ 2 0_0201_5% CIICSCL 13 6
15,33 FCH_SCLK1 CIICSCL1 DP_GND
RT12 1 @ 2 0_0201_5% CIICSDA 14
15,33 FCH_SDATA1 CIICSDA1 16 1 @ 2

GND
GND RT13 0_0402_5%
RT14 1 @ 2 0_0201_5% 49
30,32,6,8 EC_SMB_CK2 PAD
RT15 1 @ 2 0_0201_5%
30,32,6,8 EC_SMB_DA2
@
RT39
Ming 8/30 need connect to EC SMBUS2 LVDS@ RTD2136S-VE-CG_QFN48_6X6
8 DP0_TXN2_C DP0_TXN2_C 4 5 LVDS_A_TXOUT0-
SA000067100 8 DP0_TXP2_C DP0_TXP2_C 3 6 LVDS_A_TXOUT0+
8 DP0_TXN3_C DP0_TXN3_C 2 7 LVDS_A_TXOUT1-
<CPU by PASS LVDS> <to connector> 8 DP0_TXP3_C DP0_TXP3_C 1 8 LVDS_A_TXOUT1+
0_0804_8P4R_5%
SD309000080 eDP@ SD309000080
RT28 eDP@ RT29

8 DP0_TXP0_C DP0_TXP0_C 4 5 EDP_CPU_R_LANE_P0 EDP_CPU_R_LANE_N0 4 5LVDS_B_TXOUT0-

8 DP0_TXN0_C DP0_TXN0_C 3 6 EDP_CPU_R_LANE_N0 EDP_CPU_R_LANE_P0 3 6LVDS_B_TXOUT0+
<CPU> 8 DP0_TXP1_C DP0_TXP1_C
DP0_TXN1_C
2
1
7 EDP_CPU_R_LANE_P1
8 EDP_CPU_R_LANE_N1
EDP_CPU_R_LANE_N1
EDP_CPU_R_LANE_P1
2
1
7LVDS_B_TXOUT1-
8LVDS_B_TXOUT1+
8 DP0_TXN1_C

0_0804_8P4R_5% 0_0804_8P4R_5%
DP0_AUXP_C RT32 1 eDP@ 2 0_0201_5%
EDP_CPU_R_AUX RT33 1 eDP@ 2 0_0201_5% LVDS_B_TXOUT2+
Ming9/20 eDP into translator transfer LVDS  
8 DP0_AUXP_C
<RT2136> 8 DP0_AUXN_C DP0_AUXN_C RT34 1 eDP@ 2 0_0201_5%
EDP_CPU_R_AUX#RT35 1 eDP@ 2 0_0201_5% LVDS_B_TXOUT2- 0_0804_8P4R_5%

<EC CTRL> EDP_HPD RT22 1 eDP@ 2 0_0201_5% EDP_HPD_PANEL

EDP_HPD_PANEL 20
DP0_TXP0_C
DP0_TXN0_C
1
2
8
7
EDP_T_LANE_P0
EDP_T_LANE_N0
APU_INVT_PWM RT23 1 eDP@ 2 0_0201_5% LVDS_PWM DP0_TXP1_C 3 6 EDP_T_LANE_P1
DP0_TXN1_C 4 5 EDP_T_LANE_N1
B B
RT37 1 @ 2 0_0201_5% LVDS@ SD309000080
RT27

+3VS DP0_AUXP_C RT30 1 2 0_0201_5%

LVDS@ EDP_T_AUX
DP0_AUXN_C RT31 1 2 0_0201_5%
LVDS@ EDP_T_AUX#
5

LVDS@ UT2 Ming9/20  LVDS to connector

LVDS_BKLTEN_R 1
P

IN1
BKOFF# 2 O
4 LVDS_BKLTEN
LVDS_BKLTEN 20 <LVDS panel> RT36
LVDS@ SD309000080
32 BKOFF# IN2
G

LVDS_B_R_TXOUT1+ 4 5LVDS_B_TXOUT1+
LVDS_B_TXOUT1+ 20
SN74AHC1G08DCKR_SC70-5 LVDS_B_R_TXOUT1- 3 6LVDS_B_TXOUT1-
LVDS_B_TXOUT1- 20
3

LVDS_B_R_TXOUT0+ 2 7LVDS_B_TXOUT0+
LVDS_B_TXOUT0+ 20
LVDS_B_R_TXOUT0- 1 8LVDS_B_TXOUT0-
LVDS_B_TXOUT0- 20
RT38 1 2 0_0201_5%
eDP@ 0_0804_8P4R_5%

RT25 1
LVDS_B_R_TXOUT2+ 2 0_0201_5% LVDS_B_TXOUT2+
LVDS@
LVDS_B_TXOUT2+ 20
RT26 1
LVDS_B_R_TXOUT2- 2 0_0201_5% LVDS_B_TXOUT2-
LVDS@
LVDS_B_TXOUT2- 20

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 18 of 47
5 4 3 2 1
 5 4 3 2 1

+3VS

APU_HDMI_TXD0+ 0.1U_0402_16V7K 1 2 CG1 PCH_DPB_P0_C

8 APU_HDMI_TXD0+
APU_HDMI_TXD0- 0.1U_0402_16V7K 1 2 CG2 PCH_DPB_N0_C
8 APU_HDMI_TXD0-
APU_HDMI_TXD1+ 0.1U_0402_16V7K 1 2 CG3 PCH_DPB_P1_C
8 APU_HDMI_TXD1+

1
APU_HDMI_TXD1- 0.1U_0402_16V7K 1 2 CG4 PCH_DPB_N1_C RG1 10/29 Eric Add ESD solution on HDMI_HPT
<CPU> 8 APU_HDMI_TXD1-
APU_HDMI_TXD2+ 0.1U_0402_16V7K 1 2 CG5 PCH_DPB_P2_C 1M_0402_5%
8 APU_HDMI_TXD2+
APU_HDMI_TXD2- 0.1U_0402_16V7K 1 2 CG6 PCH_DPB_N2_C
8 APU_HDMI_TXD2-

2
2
APU_HDMI_TXC+ 0.1U_0402_16V7K 1 2 CG7 PCH_DPB_P3_C
8 APU_HDMI_TXC+
D APU_HDMI_TXC- 0.1U_0402_16V7K 1 2 CG8 PCH_DPB_N3_C 1 6 HP_DETECT D
8 APU_HDMI_TXC- 8 DP2_HPD

20K_0402_5%
@1
QG3A

5
6
7
8

5
6
7
8

1
2N7002KDW_SOT363-6 CM1
5V Level RG2
2
220P_0402_50V7K

2N7002KDW_SOT363-6
QG3B

4
3
2
1

4
3
2
1

2
3 4 SC300002800
RP31 RP32 DM13
560_0804_8P4R_5% 560_0804_8P4R_5% HP_DETECT 1 1 109 HP_DETECT

5
+3VS HDMI_SCLK 2 2 98 HDMI_SCLK

1
HDMI_SDATA 4 4 77 HDMI_SDATA
RG3
100K_0402_5% 5 5 66
9/11 remove RG58/RG62 for doublle PU to CPU side 3 3

2
+3VS
8

ESD@ TVWDF1004AD0

4.7K_0402_5%
R23
PCH_DPB_P3_C RG4 1 2 22_0402_5% HDMI_R_CK+
SC300002800 1 2
4 3 DM11
C LM1 4 3 HDMI_R_D2+ 1 1 109 HDMI_R_D2+ C

2
SM070001S00 @EMI@
WCM-2012HS-900T_4P 1 2 HDMI_R_D2- 2 2 98 HDMI_R_D2- QG4A
1 2 1 6 HDMI_SCLK
8 APU_HDMI_CLK
PCH_DPB_N3_C RG5 1 2 22_0402_5% HDMI_R_CK- HDMI_R_CK+ 4 4 77 HDMI_R_CK+
2N7002DWH_SOT363-6
HDMI_R_CK- 5 5 66 HDMI_R_CK- SB00000DH00
+3VS
PCH_DPB_N0_C RG6 1 2 22_0402_5% HDMI_R_D0- 3 3
1 2
1 2 8
LM2 1 2 R26 4.7K_0402_5%

5
SM070001S00 @EMI@ @ESD@ TVWDF1004AD0
WCM-2012HS-900T_4P 4 3
4 3 4 3 HDMI_SDATA
8 APU_HDMI_DATA
PCH_DPB_P0_C RG7 1 2 22_0402_5% HDMI_R_D0+
2N7002DWH_SOT363-6
SC300002800 SB00000DH00 QG4B
PCH_DPB_P1_C RG8 1 2 22_0402_5% HDMI_R_D1+ DM12
HDMI_R_D1- 1 1 109 HDMI_R_D1-
4
4 3
3 5V PULL UP IN CONNECTER SIDE
LM3 HDMI_R_D1+ 2 2 98 HDMI_R_D1+
SM070001S00 @EMI@
WCM-2012HS-900T_4P 1 2 HDMI_R_D0- 4 4 77 HDMI_R_D0-
1 2
PCH_DPB_N1_C RG9 1 2 22_0402_5% HDMI_R_D1- HDMI_R_D0+ 5 5 66 HDMI_R_D0+

3 3
PCH_DPB_P2_C RG10 1 2 22_0402_5% HDMI_R_D2+
B 8 B
4 3
4 3 +HDMI_5V_OUT
HDMI Conn.
LM4 @ESD@ TVWDF1004AD0
SM070001S00 @EMI@
WCM-2012HS-900T_4P 1 2
1 2

2K_0402_1%
1

1
PCH_DPB_N2_C RG11 1 2 22_0402_5% HDMI_R_D2-
R8 R9 JHDMI1
2K_0402_1% HP_DETECT 19
18 HP_DET
+HDMI_5V_OUT +5V
17

2
HDMI_SDATA 16 DDC/CEC_GND
HDMI_SCLK 15 SDA
10/9 Eric Remvoe CM2 ~ CM9 for EMI requirement. 14 SCL
Reserved
W=40mils HDMI_R_CK-
13
12 CEC
FG1 +HDMI_5V_OUT CK-
11
HDMI_R_CK+ 10 CK_shield
3 HDMI_R_D0- 9 CK+
OUT 8 D0-
1 HDMI_R_D0+ 7 D0_shield
+5VS IN D0+
1 HDMI_R_D1- 6
D1-
W=40mils GND
2
HDMI_R_D1+
5
4 D1_shield 20
CG46 HDMI_R_D2- 3 D1+ GND 21
0.1U_0402_16V7K 2 2 D2- GND 22
AP2330W-7_SC59-3 HDMI_R_D2+ 1 D2_shield GND 23
SA00004ZA00 D2+ GND
ACON_HMR2U-AK120C
A A
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 19 of 47
5 4 3 2 1
 5 4 3 2 1

+3VS
UG1
W=60mils W=60mils
W=80mils W=80mils
5
IN OUT
1 +LCDVDD <Panel power>
10/20 Del LG1.
2
GND

0.1U_0402_16V7K
D D
@ LCDVDD T=0.5m~10ms

CG12
RG12 1 @ 2 0_0201_5%
1 4 3 1 1
SS EN CG11 10/4 Eric Del.
CG10
APL3512_SOT23-5 4.7U_0603_6.3V6K
2 2 2
1500P_0402_50V7K SM010014520 3000ma
220ohm@100mhz
10/3 Eric Add APU_ENVDD control pin. DCR 0.04
<CPU CTRL> 10 APU_ENVDD
RG13 1 eDP@ 2 0_0201_5%
SCA00000U10
<ANX3110\ CTRL> 18 EN_PVCC
RG14 1 2 0_0201_5%
LVDS@ YSLC05CH 3P C/A SOT-23

USB20_N5_R 3
1
USB20_P5_R 2

9/26 Eric remove common chock for touch screen portion, DM1
@ESD@ Put CF11 near webcam connector.
ask key part to add in touch IC side. @RF@

SCA00000U10
CF11
39P_0402_50V8J eDP,TS,Camera Conn.
2 1
C C
YSLC05CH 3P C/A SOT-23
@ RG15 1 2 0_0402_5%
USB20_N4_R 3 JLVDS1
LM5 SM070000K00 1 1
+LCDVDD 1
@ESD@ 1 2 USB20_P4_R USB20_P4_R 2 2
DM3 15 USB20_P4 1 2 2
3
EMI@ 18 LVDS_SCL 3
D_MIC_CLK 2 DM2 4
@ESD@ 18 LVDS_DAT 4
1 4 3 USB20_N4_R 5
15 USB20_N4 4 3 5
D_MIC_DATA 3 LVDS_A_TXOUT0- 6
18 LVDS_A_TXOUT0- 6
WCM-2012-900T_4P LVDS_A_TXOUT0+ 7
18 LVDS_A_TXOUT0+ 7
LVDS_A_TXOUT1- 8
YSLC05CH 3P C/A SOT-23 18 LVDS_A_TXOUT1- 8
@ RG16 1 2 0_0402_5% LVDS_A_TXOUT1+ 9
18 LVDS_A_TXOUT1+ 9
SCA00000U10 LVDS_A_TXOUT2+ 10
18 LVDS_A_TXOUT2+ 10
LVDS_A_TXOUT2- 11
18 LVDS_A_TXOUT2- 11
@ RG17 1 2 0_0402_5% <LVDS> 18 LVDS_A_TXCLK+
LVDS_A_TXCLK+
LVDS_A_TXCLK-
12
13 12
18 LVDS_A_TXCLK- 13
LM14 SM070000K00 14
1 2 USB20_P5_R LVDS_B_TXOUT0- 15 14
15 USB20_P5 1 2 <DB>eDP‐‐>Dual LVDS 18
18
LVDS_B_TXOUT0-
LVDS_B_TXOUT0+
LVDS_B_TXOUT0+ 16 15
EMI@ LVDS_B_TXOUT1- 17 16
18 LVDS_B_TXOUT1- 17
4 3 USB20_N5_R LVDS_B_TXOUT1+ 18
15 USB20_N5 4 3 18 LVDS_B_TXOUT1+ 18
LVDS_B_TXOUT2+ 19
18 LVDS_B_TXOUT2+ 19
WCM-2012-900T_4P LVDS_B_TXOUT2- 20
18 LVDS_B_TXOUT2- 20
B LVDS_B_TXCLK+ 21 B
18 LVDS_B_TXCLK+ 21
@ RG18 1 2 0_0402_5% LVDS_B_TXCLK- 22
18 LVDS_B_TXCLK- 22
23
8/30 colay eDP use 18 LVDS_PWM
LVDS_PWM 24 23
LVDS_BKLTEN 25 24
18 LVDS_BKLTEN 25
26
18 EDP_HPD_PANEL 26
10/3 Eric Del power switch of +3VS_CAMERA & +5V_+3V_TOUCH_PNL. 32 TS_STOP# 27
27
<USB Touch panel> USB20_N4_R
USB20_P4_R
28
29 28
29
<Touch panel> +5V_+3V_TOUCH_PNL 30
31 30
+3VS +3VS_CAMERA 31
<Camara and DMIC> +3VS 32
32
USB20_N5_R
USB20_P5_R
33
34 33 Panel +3VS
35 34
1 2 D_MIC_CLK 36 35 41
+5V_+3V_TOUCH_PNL 28 D_MIC_CLK 36 G1
RG101 @ 0_0603_5% D_MIC_DATA 37 42
28 D_MIC_DATA 38 37 G2 43
38 G3
<Camera> B+ 39
40 39 G4
44
45
1 2 40 G5
+3VS_CAMERA
RG102 @ 0_0603_5% STARC_111H40-100000-G4-R

CONN@
A A
9/6 by EMI request modify LVDS pin defined
Security Classification Compal Secret Data Compal Electronics, Inc.
2012/11/07 2012/11/07 Title
Issued Date Deciphered Date
SCHEMATIC, MB A9851
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 20 of 47
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 21 of 47
5 4 3 2 1
 5 4 3 2 1

mSATA Conn.

10/03 Eric Del mSATA by customer

Reserve SATA Redriver

D D

+3VS +3VS_SATA_RE

@ 0_0603_5%
R570 1 2

+3VS_SATA_RE
+3VS_SATA_RE

Change to 0.01U cap. PN

1
1 2

2
R571 @ C124 @
FCH side 10K_0402_5% R63
0.1U_0402_16V4Z
C125
0_0402_5% 0.01U_0402_16V7K

2
U71 2 1
7 6

1
EN VDD 16
C127 1 2 0.01U_0402_16V7K SATA_STX_R1_DRX_P0 1 VDD
14 SATA_STX_DRX_P0 A_INp
14 SATA_STX_DRX_N0 C126 1 2 0.01U_0402_16V7K SATA_STX_R1_DRX_N0 2 10
A_INn NC 20 1 R572 2
C128 1 2 0.01U_0402_16V7K SATA_DTX_R1_SRX_P0 5 REXT
14 SATA_DTX_SRX_P0 C129 1 2 0.01U_0402_16V7K SATA_DTX_R1_SRX_N0 4 B_OUTp 9 A_PRE0 4.99K_0402_1%~D
14 SATA_DTX_SRX_N0 B_OUTn A_PRE0 8 B_PRE0
B_PRE0 @
B_PRE1 17 11/25 add R4610 4.99k -> Parade review
A_PRE1 19 B_PRE1 15 SATA_STX_R_DRX_P0
A_PRE1 A_OUTp 14 SATA_STX_R_DRX_N0
A_OUTn
+3VS_SATA_RE
1 2 18
3 TEST 11 SATA_DTX_R_SRX_P0
Connector side
R573 @ 10K_0402_5% 13 GND B_INp 12 SATA_DTX_R_SRX_N0
21 GND B_INn
EPAD
C C
PS8520CTQFN20GTR2_TQFN20_4X4

+3VS_SATA_RE
11/29 emphasis=1, 1==>R145/R152

2
R574 R575 R576 R577
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5%
@ @ @ @
1

1
Need Vendor check value
B_PRE1 A_PRE1 A_PRE0 B_PRE0

SATA0 (HDD)

02/22 Eric remvoe SATA power 0 ohm to +5VS.

+5VS

100mils @RF@

10U_0805_10V4Z

0.1U_0402_16V4Z
1 1 1

C1

C2

39P_0402_50V8J
B B

CF12
2 2 2

10/4 Eric Del.

02/22 Eric remvoe SATA 0 ohm co-lay.

<DB>Change to 10 Pin. 2.5" HDD Conn.

ACES_87036-1001-CP
12
11 GND
10 GND
+5VS 10
9
8 9
7 8
6 7
SATA_STX_R_DRX_P0 C3 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_P0 5 6
SATA_STX_R_DRX_N0 C4 1 2 0.01U_0402_16V7K SATA_STX_C_DRX_N0 4 5
3 4
SATA_DTX_R_SRX_N0 C5 1 2 0.01U_0402_16V7K SATA_DTX_C_SRX_N0 2 3
SATA_DTX_R_SRX_P0 C6 1 2 0.01U_0402_16V7K SATA_DTX_C_SRX_P0 1 2
1
JHDD2 CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
C A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 22 of 47
5 4 3 2 1
 5 4 3 2 1

+3V_AOAC

12.08 R73 pull high

1
R11 @ WLAN
10K_0402_5%
+3V_AOAC +1.5VS_WLAN
+3V_AOAC

2
D D
R12 @
0_0402_5% JMINI1 CONN@
1 2 1 2
15,24 FCH_PCIE_WAKE# 1 2
3 4
BT_ON 4/17 change to 0ohm new symbol 1 R13 2 BT_ON_L 5 3 4 6
14 BT_ON 5 6
15 MINI1_CLKREQ# @ 0_0402_5% 7 8 LPC_FRAME#
7 8 LPC_FRAME# 13,32,36
9 10 LPC_AD3
9 10 LPC_AD3 13,32,36
11 12 LPC_AD2
13 CLK_PCIE_MINI1# 11 12 LPC_AD2 13,32,36
13 14 LPC_AD1
13 CLK_PCIE_MINI1 13 14 LPC_AD1 13,32,36
15 16 LPC_AD0
15 16 LPC_AD0 13,32,36

APU_PCIE_RST# 17 18
LPC_CLK0_DG 19 17 18 20 WL_OFF#
32,36 LPC_CLK0_DG 19 20 WL_OFF# 14
21 22 APU_PCIE_RST# APU_PCIE_RST# 10,13,31
23 21 22 24 1 2
6 PCIE_DTX_C_FRX_N1 23 24 +3V_AOAC
6 PCIE_DTX_C_FRX_P1 25
27 25 26
26
28
R14
@
0_0603_5% 12/21 for AMD issue workaround
29 27 28 30
31 29 30 32
6 PCIE_FTX_C_DRX_N1 31 32
33 34 R15 0_0402_5% USB20_N8
6 PCIE_FTX_C_DRX_P1 33 34
35 36 USB20_N8_R 1R16 @ 2
0_0402_5% USB20_N8
35 36 USB20_N8 15
37 38 USB20_P8_R 1 @ 2 USB20_P8
37 38 USB20_P8 15

1
39 40
41 39 40 42 R17
4/17 change to 0ohm new symbol 43 41 42 44 MINI1_LED# 300_0402_5%
43 44 MINI1_LED# 32
45 46
R18 0_0402_5% 47 45 46 48

2
47 48

1
C E51TXD_P80DATA1 @ 2 E51TXD_P80DATA2_R 49 50 C
32 E51TXD_P80DATA 49 50
1 2 E51RXD_P80CLK_R 51 52 R20 1 10P_0402_50V8J
32 E51RXD_P80CLK 51 52
@ 53 54 4.7K_0402_5% C7
R19 0_0402_5% G1 G2
1

(9~16mA)

2
LOTES_AAA-PCI-049-P06-A_52P 2
@ R21
+3V_AOAC
100K_0402_5%
2

For Wireless LAN

+3V_AOAC

60mil

1
C8 +1.5VS +1.5VS_WLAN
@
4.7U_0603_6.3V6K R186 0_0603_5%
2 1 2
@1
C70 Mini Card Power Rating
2
4.7U_0603_6.3V6K Power Primary Power (mA) Auxiliary Power (mA)
B B
Peak Normal Normal
+3VS 1000 750
+3V 330 250 250 (wake enable)
+1.5VS 500 375 5 (Not wake enable)
AOAC_PW_ON# 32

+3V_AOAC
2
G

1 3 +3VALW
D

10/17 Eric modify WLAN power solution.

Q11
AO3413L_SOT23-3
R95
0_1206_5%
2 1

@
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. 4019NK
Date: Monday, October 21, 2013 Sheet 23 of 47

5 4 3 2 1
 5 4 3 2 1

D D

+3VS

2
31,32 EC_LAN_ISOLATEB# EC_LAN_ISOLATEB# 2 1 +3VS
RL6 1K_0402_5% RL4
10K_0402_5%

2
@ @
@ RL8 RL9

1
15 LAN_CLKREQ# LAN_CLKREQ# 2 1 LAN_CLKREQ#_R LAN_CLKREQ#_R 31
15K_0402_5%
0_0201_5%

1
10/19 Eric del @ of RL10 for pull high, Del FCH_PCIE_WAKE# net, short RL12.
@
10K_0402_5% 2 1 RL10 +LAN_VDD_3V3

@ RL12 0_0402_5%
31 LANWAKEB LANWAKEB 1 2 EC_PME# 32
C C
@ RL13 0_0402_5%
1 2
FCH_PCIE_WAKE# 15,23

LED
<DB>Change to subboard.

20 Pin FFC
JIO1 CONN@
1
1 2
2 3 CLK_PCIE_LAN 13
3 4 CLK_PCIE_LAN# 13
4 5
5 6 PCIE_FTX_C_DRX_P0 6
6 7 PCIE_FTX_C_DRX_N0 6
7 8
8 9 PCIE_DTX_C_FRX_P0 6
9 10 PCIE_DTX_C_FRX_N0 6
10 11 USB20_N0
11 12 USB20_N0 15
USB20_P0
12 13 USB20_P0 15
13 14
14 15
15 16
16 17
17 18
B 18 19 B
19 20
20 21
GND 22
GND
ACES_51522-02001-001
ACES_51522-02001-001_20P-T
0226 Eric del SIM signals for remove WWAN.

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 24 of 47
5 4 3 2 1
 A B C D E

Card reader conn

9/4 Modify JP10 connector pin defined
JP10
1 2 +3VS_CR +3VS
6 PCIE_FTX_C_DRX_P3 1 2 +3VALW
3 4
6 PCIE_FTX_C_DRX_N3 3 4
5 6 +3VS_CR
6 PCIE_DTX_C_FRX_P3 5 6
7 8 R24
6 PCIE_DTX_C_FRX_N3 7 8
9 10 +3VS 1 @ 2
11 9 10 12
13 CLK_PCIE_CR 11 12 +5VALW
13 14 SATA_LED# 0_0805_5%
13 CLK_PCIE_CR# 13 14 SATA_LED# 14
15 16
17 15 16 18 PWR_LED# HDDHALT_LED# 13
15 CR_CLKREQ# 17 18 PWR_LED# 32,34
1 13,32,36 PLT_RST# CR_RST# 19 20 1
19 20
21 22
10/4 Eric Reserve R212 for card reader power rail.
23 GND GND 24
9/26 Eric Reserve CR_WAKE# pin
25 GND GND 26
GND GND

PANAS_AXK7L20213G

CONN@

<CPU>

2 2

10/4 Eric Del +3VS_CR power rail from power switch

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 25 of 47
A B C D E
 A B C D E

RS1 @ 0_0402_5% USB3.0 need support 2.5A

15 USB3_TX0_N USB3_TX0_N 0.1U_0402_16V7K 2 1 CS1 USB3TXDN0_C 1 2 USB3TXDN0_C_R change USB PWR SW SA00003TV00
low active 9/13 add US2 for another USB30 port
1 2 +5VALW +USB_VCCC
WCM-2012HS-900T_4P 1 2
SM070001S00 EMI@ W=100mils
LM6 4 3 W=100mils US1

0.1U_0402_16V7K
1 8

47U_0805_6.3V6M
4 3 GND VOUT @

1000P_0402_50V7K
2 7
3 VIN VOUT 6
1 1 1 1
USB3_TX0_P 0.1U_0402_16V7K 2 1 CS2 USB3TXDP0_C 1 2 USB3TXDP0_C_R VIN VOUT

CS17
15 USB3_TX0_P 4 5
RS2 @ 0_0402_5% @ EN FLG CS6
1 1
G547I2P81U_MSOP8
2 2
CS3 CS5
RS3 @ 0_0402_5% 0.1U_0402_16V7K
2 2
15 USB3_RX0_N
1 2 USB3RXDN0_C <EC> <DB>Del B Cap.
@ RS4 0_0402_5%
1 2
<CPU> 31,32 USB_ON# 1 2
WCM-2012HS-900T_4P 1 2 RS6 1 @ 2 USB_OC0#
SM070001S00 EMI@ 31 USB32_P0_PWREN_R# RS5 1 @ 2 0_0402_5% USB_OC0# 15
0_0402_5%
LM7 4 3
4 3
9/26 Eric change CS14 form 150uF to 47uF.
1 2 USB3RXDP0_C SCA00000U10
15 USB3_RX0_P DM4
RS7 @ 0_0402_5%
@ESD@ 2 USB20_N0_C
RS8 @ 0_0402_5% 1
1 2 USB20_N0_C 3 USB20_P0_C
27 U2D_DN0
WCM-2012-900T_4P
4 3 YSLC05CH 3P C/A SOT-23 <DB>Update footprint to DC233008M10.
4 3
2
EMI@ USB2.0/USB3.0 port 1 2

1 2
1 2 SC300002800
LM8 SM070000K00 DM5 +USB_VCCB <DB>Change power rail to U18.
1 2 USB20_P0_C USB3TXDP0_C_R 1 1 109 USB3TXDP0_C_R
27 U2D_DP0
RS9 @ 0_0402_5% JUSB1 CONN@
USB3TXDN0_C_R 2 2 98 USB3TXDN0_C_R 1
USB20_N0_C 2 VBUS
RS10 @ 0_0402_5% USB3RXDP0_C 4 4 77 USB3RXDP0_C USB20_P0_C 3 D-
USB3_TX1_P 0.1U_0402_16V7K 2 1 CS7 USB3TXDP1_C 1 2 USB3TXDP1_C_R 4 D+
15 USB3_TX1_P GND
USB3RXDN0_C 5 5 66 USB3RXDN0_C USB3RXDN0_C 5
USB3RXDP0_C 6 SSRX- 10
4 3 3 3 7 SSRX+ GND 11
LM9 4 3 USB3TXDN0_C_R 8 GND GND 12
SM070001S00 EMI@ 8 USB3TXDP0_C_R 9 SSTX- GND 13
WCM-2012HS-900T_4P 1 2 SSTX+ GND
1 2 ESD@ TVWDF1004AD0 SINGA_2UB4008-500101F

15 USB3_TX1_N USB3_TX1_N 0.1U_0402_16V7K 2 1 CS8 USB3TXDN1_C 1 2 USB3TXDN1_C_R

RS11 @ 0_0402_5%
SCA00000U10
DM6
@
RS12 1 2 0_0402_5% USB3RXDP1_C @ESD@ 2 USB20_P1_C
15 USB3_RX1_P
3 1 3
3 USB20_N1_C

USB2.0/USB3.0 port 2
4 3
LM10 4 3
SM070001S00 EMI@ YSLC05CH 3P C/A SOT-23
WCM-2012HS-900T_4P 1 2
1 2 <DB>Change power rail to U18.
DM7 SC300002800
1 2 USB3RXDN1_C USB3RXDN1_C 1 1 109 USB3RXDN1_C +USB_VCCC
15 USB3_RX1_N
RS13 @ 0_0402_5%
USB3RXDP1_C 2 2 98 USB3RXDP1_C JUSB4 CONN@
1
RS14 @ 0_0402_5% USB3TXDN1_C_R 4 4 77 USB3TXDN1_C_R USB20_N1_C 2 VBUS
1 2 USB20_P1_C USB20_P1_C 3 D-
15 USB20_P11 D+
USB3TXDP1_C_R 5 5 66 USB3TXDP1_C_R 4
LM11 SM070000K00 USB3RXDN1_C 5 GND
1 2 3 3 USB3RXDP1_C 6 SSRX- 10
1 2 7 SSRX+ GND 11
EMI@ 8 USB3TXDN1_C_R 8 GND GND 12
4 3 USB3TXDP1_C_R 9 SSTX- GND 13
4 3 ESD@ TVWDF1004AD0 SSTX+ GND
WCM-2012-900T_4P SINGA_2UB4008-500101F
1 2 USB20_N1_C
15 USB20_N11
RS15 @ 0_0402_5%
4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 26 of 47
A B C D E
 5 4 3 2 1

+VL
+2543PWR +USB_VCCB

47U_0805_6.3V6M
R27
<DB>Remove from US1.

1U_0402_6.3V6K
0_0402_5% @
1 1
@

CS18
C10
1
D D

1 2 2 9/13 remove Q26 and component
@ +VL
C12
2
0.1U_0402_16V7K 10/22 Eric change USB_IN_STATUS# power rail from +3VL to +VL.

2
10/4 Eric Del.
R57
+3VL USB 2.0 / USB 3.0 port(Left) U1
1 12 10K_0402_5%
IN OUT
2

R29 @

1
1 2 13 9 USB_IN_STATUS#
R28 15,31 USB_OC1# FAULT# NC USB_IN_STATUS# 32
0_0402_5%
2 11 U2D_DN0
10K_0402_5% 15 USB20_N10 DM_OUT DM_IN U2D_DN0 26
<PCH> 15 USB20_P10
3
DP_OUT DP_IN
10 U2D_DP0
U2D_DP0 26 <DB>Change to port 0
1

<DB>Change to port 10 ILIM_SEL 4 15 2 1

USB_CHARGE_EN# 5 ILIM_SEL ILIM1 16 R30 2 1 19.1K_0402_1%
EN ILIM0 R31 19.1K_0402_1%
USB_CTL1 6
32 USB_CTL1 CTL1
USB_CTL2 7 14
32 USB_CTL2 CTL2 GND +2543PWR
+3VL 1 2 USB_CTL3_R 8 17 SI7326DN-T1-E3_PAK1212-8
CTL3 GPAD +5VALW U10
R32 10K_0402_5% W=80mils
TPS2546RTER_QFN16_3X3 1
C C
2

0.1U_0402_16V7K
R33 W=80mils

1000P_0402_50V7K
R34 @1 @1 3 5
100K_0402_5% 100K_0402_5%

0.1U_0402_16V7K
10U_0603_6.3V
C65

C66
1 @1
1

4
2 2

C68
10mil 10mil

C67
B+ 2 1
R71 2 2
200K_0402_5% 1
@ C69
+VSB 2 1 .1U_0603_25V7K
R73 2
20K_0402_5%

R585 @ 100K_0402_5%
+VL 2 1

2N7002KDW_SOT363-6
6
+VL

QH2A
R578 100K_0402_5%
B B+ 2 1 2 B
1

1 R35 2

1
@ 0_0402_5% R36 @
100K_0402_5%
R579 100K_0402_5%

2N7002KDW_SOT363-6
3
<EC> 32 USB_CHARGE_EN 2 +5VALW 2 1
2

QH2B
1 USB_CHARGE_EN#
5
32,39,41,43 SPOK
1U_0402_6.3V6K

<CPU> 3
1

4
D2 @
C13

CHN202UPT_SC70-3
@ 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 27 of 47
5 4 3 2 1
 5 4 3 2 1

Notes:
Keep PVDD supply and speaker traces routed on the DGND plane. If Sense_A total length is greater than
Keep away from AGND and other analog signals PLACE CLOSE TO U1 PIN 13 6 inches, chagne C12 to 0.1uF
DVDD_IO should match
with HDA Bus level(optional for 3.3V signaling or 1.5V signaling) RB2 +VDDA_CODEC
+DVDD_IO FBMA-L11-201209-221LMA30T_0805 RB1 1 2 2.49K_0402_1% +AVDD_CODEC
+3VS Place AVDD ,PVDD,and DVDD capacitor close to Codec 2 1
RB1 Bead Max I=3000mA RB3 1 2 20K_0402_1% HP_DET#
+5VS HP_DET# 31
1 @ 2 +3VS_DVDD +3VS
RB4 0_0603_5% RB5 +AVDD_CODEC @ RB37 SENSE_A CB1 1 2 1000P_0402_50V7K
BLM18BD601SN1D_0603 RB7 2 1 1 @ 2
1 2 0_0805_5%

0.1U_0402_16V7K
D 0_0805_5% D
1 2 10K_0402_1%

1U_0402_6.3V6K

0.1U_0402_16V7K
1 1 1 RB3 Bead Max I=200mA SENSE_B RB8 +AVDD_CODEC

1U_0402_6.3V6K
1 1 PVDD

CB2

CB3
1 CB4

CB6

CB7
10U_0603_6.3V CB8 1 2 1000P_0402_50V7K If Sense_B is un-used, then pull high
2 2 2 UB1

10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K
CB5
0.1U_0402_16V7K 1 27 2 2
1 1 1 PLACE CLOSE TO U1 PIN 14 @ Sense_B to AVDD by 10Kohm resistor
2 DVDD_CORE AVDD1 38
AVDD2

CB11

CB9

CB10
3 45
DVDD_IO PVDD1 39 2 2 2
PVDD2
9 13 SENSE_A
DVDD SENSE_A 14 SENSE_B
SENSE_B SPKL+
2 1 CM10 @ 28 CB12 1 2 1U_0603_10V6K SPKL-
HP0_PORTA_L
33P_0402_50V8J
HP0_PORTA_R
29
23
MIC_EXTR
VREFOUT_EXT_MIC
MIC_EXTR 31 Ext MIC MUTE_LED 33 SPKR+
SPKR-
VREFOUT_A VREFOUT_EXT_MIC
15 HDA_BITCLK_AUDIO HDA_BITCLK_AUDIO 6
HDA_BITCLK 31 HP_OUT_L
HP1_PORTB_L HP_OUT_L 30

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
15 HDA_SDOUT_AUDIO HDA_SDOUT_AUDIO 5
HDA_SDO HP1_PORTB_R
32 HP_OUT_R
HP_OUT_R 30 HP Jack RB9 1 1 1 1
15 HDA_SYNC_AUDIO HDA_SYNC_AUDIO 10 19 270_0402_1%
HDA_SYNC PORTC_L

CB13

CB14

CB15

CB16
20
HDA_SDIN0 2 1 SDIN_CODEC 8 PORTC_R 24
15 HDA_SDIN0

2
33_0402_5% RB10 HDA_SDI VREFOUT_C/GPIO4 2 2 2 2
15 HDA_RST_AUDIO# HDA_RST_AUDIO# 11 15
HDA_RST# PORTE_L

6
16
EAPD DB1 1 2 EAPD_L 2 1 PORTE_R QB1A
32 EAPD EAPD_AMP 29

1
CH751H-40PT_SOD323-2 DB2
PORTF_L
17 11/06 Beads close to UB1. 2N7002DWH_SOT363-6

3.3_0402_5%

3.3_0402_5%

3.3_0402_5%

3.3_0402_5%
RB11

RB12

RB13

RB14
CH751H-40PT_SOD323-2 18 MUTE_LED_L 2
47 PORTF_R
100_0402_5% RB15 LM12 FBMA-L10-160808-301LMT_2P EAPD 40 EMI@ LM151 2 BLM18HE601SN1D
SPKL+ 31

1
C
D_MIC_CLK 2 1D_MIC_CLK_L 1 2 D_MIC_CLK_L_C 2 SPK_PORTD_+L 41 EMI@ LM161 2 BLM18HE601SN1D C
20 D_MIC_CLK SPKL- 31

2
4 DMIC_CLK/GPIO1 SPK_PORTD_-L

2
20 D_MIC_DATA D_MIC_DATA D_MIC_DATA_C Internal SPKR
DMIC0/GPIO2 44 EMI@ LM171 2 BLM18HE601SN1D
SPK_PORTD_+R SPKR+ 31 10K_0402_5%
48 43 EMI@ LM181 2 BLM18HE601SN1D
SPDIFOUT0/GPIO3 SPK_PORTD_-R SPKR- 31 RB16
9/17 add RF solution MUTE_LED_L 46
DMIC1/GPIO0/SPDIFOUT1 25
CF13 SUB_OUT 29

1
MONO_OUT
@RF@1 2 D_MIC_CLK 36 12 MONO_INR 1 2 MONO_IN
CAP+ PCBEEP CB17 0.1U_0402_16V7K
2
10P_0402_50V8J CB18 21
CF14 VREFFILT
@RF@ 4.7U_0603_6.3V6K 22
1 2 D_MIC_DATA 1 35 CAP2 34
CAP- V- Place need close UB3
Place C208 close to Codec 37
VREG(+2.5V)

10U_0603_6.3V6M
10P_0402_50V8J 7

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
DVSS

0.1U_0402_16V7K
2 2 1 1

CB22
42 26
PVSS AVSS1

CB19

CB20

CB21
30
49 AVSS2 33
PAD AVSS3 1 1 2 2
92HD91B2X5NLGXWCX8_QFN48_7X7

change PN(SA000059J10) for Place C209,C210,CA87,CA89 close to Codec Audio power

+3VS_DVDD 92HD91B2X5NLGXWCX8
10/17 Eric Del +5VALW to +5VS_AUDIO.
1

B RB18 B
10K_0402_5%

Audio power
2

CB27 RB20
MONO_IN_C 1 2 1 2 MONO_IN
EAPD_L
100K_0402_5%
0.1U_0402_16V7K
1

D
1
15 FCH_SPKR FCH_SPKR 2 QB3
G 2N7002H_SOT23-3 CB28
S 0.01U_0402_16V7K +5VS +VDDA_CODEC
SB Beep
3

2
UB2
W=40Mil 5
VOUT
9/18 add reserve CB28, CB29 1
VIN
@EMI@ CB29 1 2 0.1U_0402_25V6
and stuff CB25,CB22,CB21 0.1uF RB43 10K_0402_5%
1 2 3 BYPASS
4

1 2 0.1U_0402_25V6 EN

0.1U_0402_16V7K
@EMI@ CB30
2 1 2
EMI@ CB31 1 2 0.1U_0402_25V6 GND
1

CB33
HPA01091DBVR _SOT23-5 CB34
EMI@ CB35 1 2 0.1U_0402_25V6 +3VS_DVDD +5V_SUBAMP +AVDD_CODEC CB32 10U_0805_10V6K
0.1U_0402_16V7K 2 1
EMI@ CB36 1 2 0.1U_0402_25V6 2

RB22 1 @ 2
EAPD_L 4 5
A A
0_0805_5% EAPD_AMP# 3 6
29 EAPD_AMP#
MONO_IN_C 2 7 Check HP LDO PN
MONO_IN 1 8

10/9 Eric Add EMI@ solution for CB31, CB35 & CB36 form EMI requirement. RP22
10K_0804_8P4R_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 28 of 47

5 4 3 2 1
 Subwoofer AMP TPA2011 = HPA01086YFFR
DB> TPA2012 Change to TPA2011
+5V_SUBAMP

+5VS 2
CB37

LB1 10U_0603_6.3V6M
1 2 1
BLM18PG181SN1D_2P
UB3
LB3~LB6 Bead Max I=550mA
EMI@
CB38 1 2 SUB+ 2 1 A1 C3 SUBWOOFER+_R1 LB7 1 2 MBK1608221_0603 SUBWOOFER+ SUBWOOFER+ 31
0.033U_0603_16V7 RB23 47K_0402_1% IN+ OUT+

CA1 1 2 SUB- 2 1 C1 EMI@

28 SUB_OUT 0.033U_0603_16V7 RB24 47K_0402_1% IN- A3 SUBWOOFER-_R1 LB8 1 2 MBK1608221_0603 SUBWOOFER-
OUT- SUBWOOFER- 31
B2
PVDD

1
CB54 CB55
B3
B1 PGND 680P_0603_50V7K 680P_0603_50V7K

2
VDD EMI@ EMI@

EAPD_AMP C2 A2
28 EAPD_AMP EN GND

TPA2011D1YFFR_DSBGA9

0.1U_0402_16V4Z

1U_0402_6.3V4Z
2 1

CB41

CB42
1 2

Add circuitry for de-pop

+5V_SUBAMP

6
QB6A
28 EAPD_AMP#
RP36 2N7002DWH_SOT363-6
8 1 2
7 2
6

6 3

1
QB4A 5 4
2N7002DWH_SOT363-6
EAPD_AMP 2 SUB+

3
100K_0804_8P4R_5%
QB6B
1

2N7002DWH_SOT363-6
5

4
SUB-

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 29 of 47
 A B C D E

Headphone AMP TPA6130A2 = HPA00929

DB> HPA01196 Change to HPA00929

1
Headphone amplifier HP_5V

10/22 Eric change +5VS_Audio back to +5VS.
1

HP_5V

10K_0402_1%
+5VS
RB42
LB4 1 2

FBM-11-160808-601-T_0603

CB43 1U_0402_6.3V6K UB4

HP_OUT_R1 2 1 @ 2 5 12
28 HP_OUT_R RIGHTINM VDD_12
LB5 0_0603_5% 4
RIGHTINP
CB44 1U_0402_6.3V6K 11 HP_R RB31 1 2 30_0402_1% HP_OUT_R_1 31
HP_OUT_L1 2 1 @ 2 1 HPRIGHT 14 HP_L RB32 1 2 30_0402_1%
28 HP_OUT_L LEFTINM HPLEFT HP_OUT_L_1 31
2 2 LB6 0_0603_5% 2
LEFTINP
CB45 CB46 3
@ 6 GND_3 9
1U_0402_6.3V6K 1U_0402_6.3V6K SD# GND_9
1 1 EC_SMB_DA2 1 RB33 2 PCH_SMB_DA1_AMP7 10
0_0402_5% SDA GND_10 13
@ GND_13 19
EC_SMB_CK2 1 RB34 2 PCH_SMB_CK1_AMP8 GND_19
2 SCL 2
0_0402_5% 20 15
VDD_20 CPVSS_15 16
CPVSS_16
18 17
CPP CPN
21
GND
+3VS

CB49

CB50

CB51
0.1U_0402_25V6

1U_0402_6.3V6K
HP_5V HPA00929

1U_0402_6.3V6K

0.1U_0402_25V6
2.2U_0402_6.3V6M
1 1 1 2 1
CB47 CB48
2 2 2 1 2
CB52 1U_0402_6.3V6K
4.7K_0402_5%

4.7K_0402_5%
1 2
2

2
RB38

RB39
2

QB5A
1

EC_SMB_CK2 1 6 PCH_SMB_CK1_AMP
18,32,6,8 EC_SMB_CK2
3 2N7002DWH_SOT363-6 3
5

EC_SMB_DA2 4 3 PCH_SMB_DA1_AMP
18,32,6,8 EC_SMB_DA2
2N7002DWH_SOT363-6
QB5B

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
SCHEMATIC, MB A9851
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 30 of 47
A B C D E
 5 4 3 2 1

Ext. Mic Front Speaker Connector 1

SPK conn
RB36
VREFOUT_EXT_MIC 1 2
2.2K_0402_5%
JSPKL1

1U_0402_6.3V6K
1
SPKL+ 1
28 SPKL+ 1

CB53
SPKL- 2
D 28 SPKL- 2 D
2 3
4 GND
GND
ACES_50271-0020N-001
CONN@

2
28 MIC_EXTR MIC_EXTR
DM8 SCA00002900
L03ESDL5V0CC3-2

@ESD@
USB3.0 need support 2.5A

1
change USB PWR SW SA00003TV00
+5VALW
low active +USB_AS
W=100mils
W=100mils US2

1000P_0402_50V7K
1 8
GND VOUT
1000P_0402_50V7K

2 7
3 VIN VOUT 6 @ @
VIN VOUT
Headphone and Mic conn
4 5 1 1
C EN FLG C
@ 1 1
G547I2P81U_MSOP8 CS9 CS10
CS11 CS12 0.1U_0402_16V7K
2 2
0.1U_0402_16V7K
2 2
<DB>Del B Cap. 30 Pin FFC +USB_AS
<DB>Change power rail to US1.
<EC> 1
@
2
RS16 1 @
0_0402_5%
2 USB_OC1# USB_OC1# 15,27 ACES_51522-03001-P01
26,32 USB_ON#
<CPU> RS17
RS18 1 @ 2
0_0402_5%
0_0402_5%
32
31 GND 30 29
30
26 USB32_P0_PWREN_R# GND 29 28
28 27
27 26
26 25 LANCB_DET#
25 24 LANCB_DET#_PCH 14
SUBWOOFER+
24 23 SUBWOOFER+
23 22 SUBWOOFER+ 29
SUBWOOFER-
22 21 SUBWOOFER-
21 20 SUBWOOFER- 29
SPKR+
20 19 SPKR+ 28
SPKR-
19 18 SPKR- 28
18 17
17 16 +3VALW
16 15
B LANWAKEB 24 B
15 14
11/06 EMI Cap close to JIO2. 14 13 WOL_EN 32
13 12 LAN_PWR_EN 14
12 11 LAN_CLKREQ#_R 24
SPKR+
11 10 APU_PCIE_RST# 10,13,23
SPKR- EC_LAN_ISOLATEB# 24,32
10 9
9 8 +SIM_PWR
8 7
CS14 220P_0402_50V7K

CS15 220P_0402_50V7K

7 6
1

6 5
@EMI@

@EMI@

HP_OUT_R_1 1 2
5 4 HP_OUT_R_1 30
2

4 3 HP_OUT_L_1 CF20
3 2 HP_OUT_L_1 30
HP_DET# CF19 1U_0603_10V6K
2 1 HP_DET# 28 2 1
MIC_EXTR
1 1 2 @RF@ RF@
JIO2 CONN@ CS13 0.1U_0402_16V7K

4.7U_0603_6.3V6K
@EMI@

A
10/30 RF add, near JIO1 connector. A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 31 of 47
5 4 3 2 1
 5 4 3 2 1

<DB0>
+3VALW_EC
+3VALW LK1 +3VALW_EC +3VS_TOUCH_PAD
RK2 @ FBMA-L11-160808-800LMT_0603 RK30 4.7K_0402_5%

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
1 2 +3VALW_EC 1 2+EC_VCCA TP_CLK 1 2

2
CK1

CK2

CK3

CK4
1 1 1 1 1 TP_DATA 1 2
0_0603_5% RK3
CK7 100K_0402_5% RK31 4.7K_0402_5%
+3VL +3VS

ECAGND
@ @ 0.1U_0402_16V7K
2 2 2 2 2
<DB>Add RK57 @

1
1 2 BKOFF# RK5 1 2 10K_0402_5%
BOARD_ID @
RK4 0_0603_5%
+3V_EC_VDD <DB>KBC 9012 +3VL

2
0_0402_5%
D 2 @ 1 +3VL RK33 RK10 @ D
33K_0402_1% 100K_0402_5%
RK9 2 1
Ming9/3 change to 8.2KK for DB phase board ID Ming9/3 change Board ID to 8.2K for CS DB phase

1
M12
K12

B11
EC_ACIN 1 @ 2

K7
DB SI PV MV

J7

J4
J6
UK1 ACIN 37,39,40
RK15 0_0402_5%
<DB>Del HDMI_PWR_PD 2

VCC
VCC
VCC
VCC
VCC
VCC

AVCC
Board ID 0 K ohm
12K ohm 15K ohm 20K ohm <DB> add DGPU_GC6_EN on Pin M2 Board ID control
Rk13 Ming8/28 remove DGPU_GC6_EN for UMA only CK12

Project ID 56k ohm EC_GA20 M2 M9

Ming 8/30  remove MINI1_LED# 1
100P_0402_50V8J
56k ohm 56k ohm 56k ohm 15 EC_GA20 GA20/GPIO00 INVT_PWM/PWM0/GPIO0F
RK11 15
EC_KBRST#
EC_KBRST# L2
KBRST#/GPIO01 BEEP#/PWM1/GPIO10
M8 MINI1_LED# MINI1_LED# 23
13,36 SERIRQ SERIRQ M3
SERIRQ# FANPWM0/GPIO12
M10 KBL_OFF# KBL_OFF# 33 MINI1_LED# NonCS only
LPC_FRAME# K4 N10 FAN_PWM
13,23,36 LPC_FRAME# LFRAME# ACOFF/FANPWM1/GPIO13 FAN_PWM 34
LPC_AD3 N3
13,23,36 LPC_AD3 LAD3
LPC_AD2 M4 PWM Output CK8 2 1 100P_0402_50V8J ECAGND
13,23,36 LPC_AD2 LAD2
+3VALW_EC RK11 2 1 330K_0402_5% EC_RST# LPC_AD1 K5 B13
13,23,36 LPC_AD1 LAD1 BATT_TEMP/AD0/GPI38 EC_LID_OUT# 15
LPC_AD0 N4 A13 BOARD_ID
1 2
13,23,36 LPC_AD0
2 R38 1 22_0402_5% LAD0 LPC & MISC BATT_OVP/AD1/GPI39 B12 ADP_I
23,36 LPC_CLK0_DG ADP_I/AD2/GPI3A ADP_I 39,40
CK9 0.1U_0402_16V7K LPC_CLK0_EC N5 AD Input A12 ADP_ID Ming 9/3 add ADP_ID for power
13,16 LPC_CLK0_EC PCICLK AD3/GPI3B ADP_ID 39
13,25,36 PLT_RST# PLT_RST# M5 E7
EC_RST# K13 PCIRST#/GPIO05 AD4/GPI42 D7 2 @ 1
ECRST# SELIO2#/AD5/GPI43 +3VALW_EC
15 EC_SCI# EC_SCI# N6
SCI#/GPIO0E
<DB>Add PM_CLKRUN# and RK59 13 PM_CLKRUN# 1 @ 2 PM_CLKRUN#_R M6
CLKRUN#/GPIO1D
RK34 10K_0402_5% Ming9/18 change 0ohm to new footprint
10/24 Eric modify SMBUS1 power rail to +3VALW_EC. RK12 0_0402_5%
DAC_BRIG/DA0/GPO3C
B10 <PWR>
Ming9/18 change 0ohm to new footprint A9
+3VALW EN_DFAN1/DA1/GPO3D
33 KSI[0..7]
KSI0 D9
DA Output IREF/DA2/GPO3E
A10
B9
<HW>
KSI1 E12 KSI0/GPIO30 DA3/GPO3F Ming 9/4  add WWAN_OFF# to GPIO3D
8 1 EC_SMB_DA1 KSI2 E13 KSI1/GPIO31 Ming 9/3  remove LANCB_DET#_EC and RK55
KSI2/GPIO32 Ming 9/3  remove TP_ON_OFF_LED#
7 2 EC_SMB_CK1 KSI3 D12
KSI3/GPIO33 PSCLK1/GPIO4A
D6 Eric 9/25  Add WWAN_OFF# to GPIO3D Add LANCB_DET#_EC
+3VS 6 3 EC_SMB_CK2 KSI4 D13 E6 USB_ON#
C
5 4 EC_SMB_DA2 KSI5 C12 KSI4/GPIO34 PSDAT1/GPIO4B E5 WLAN_OFF_LED USB_ON# 26,31 C
KSI5/GPIO35 PSCLK2/GPIO4C WLAN_OFF_LED# 35
KSI6 C13 PS2 Interface D5 EAPD EAPD 28
KSI6/GPIO36 PSDAT2/GPIO4D
RPH21
33 KSO[0..17]
KSI7 D10
KSI7/GPIO37 TP_CLK/PSCLK3/GPIO4E
A5 TP_CLK
TP_CLK 33 EAPD:NonCS only
+3VALW_EC 4.7K_0804_8P4R_5% KSO0 J13 B5 TP_DATA
KSO0/GPIO20 TP_DATA/PSDAT3/GPIO4F TP_DATA 33
KSO1 J12 Ming 8/30  remove EAPD
2 1 EC_PME# KSO2 H12 KSO1/GPIO21
KSO3 H13 KSO2/GPIO22 B1 EC_PME#
KSO3/GPIO23 SDICS#/GPXIOA00 EC_PME# 24
RK37 10K_0402_5% KSO4 H10 A1 WOL_EN
KSO4/GPIO24 SDICLK/GPXIOA01 WOL_EN 31
KSO5 H9 C1 VLDT_EN
Ming9/13  remove EC_SMI# for EC request KSO5/GPIO25 Int. K/B SDIDO/GPXIOA02 VLDT_EN 37,44
KSO6 G9
KSO6/GPIO26 Matrix SDIDI/GPXIOD00
C2 VCIN0_PH VCIN0_PH 39 <DB>Del EC SPI ROM
KSO7 G10
KSO7/GPIO27 SPI Device Interface <DB>Del EC SPI signal
KSO8
KSO9
G13
G12 KSO8/GPIO28 J2 FCH_SPI_MOSI
EC suggest does not use as GPIO <DB> add VGA_THRMTRIP# on Pin J2
KSO9/GPIO29 MOSI FCH_SPI_MOSI 14
KSO10
KSO11
F13
F12 KSO10/GPIO2A MISO
K2
M1
FCH_SPI_MISO
FCH_SPI_CLK
FCH_SPI_MISO 14 <DB> add FB_CLAMP_TGL_REQ# on Pin K2
10/15 Eric remove SUSACK#. KSO11/GPIO2B SPI Flash ROM SPICLK/GPIO58 FCH_SPI_CLK 14
KSO12
KSO13
F10
F9 KSO12/GPIO2C SPICS#
N2 FCH_SPI_CS1#
FCH_SPI_CS1# 14 <DB> add DGPU_HOLD_RST# on Pin M1
KSO13/GPIO2D
KSO14
KSO15
E10
E9 KSO14/GPIO2E B6
<DB> add GPU_THERMAL_DET# on Pin N2
KSO15/GPIO2F CIR_RX/GPIO40
Ming9/13 add KSO16/ KSO17 for KB request KSO16
KSO17
E8
D8 KSO16/GPIO48 CIR_RLC_TX/GPIO41
B7
B4
VGATE VGATE 46 Ming8/28 remove GPU GPIO for UMA only
KSO17/GPIO49 FSTCHG/SELIO#/GPIO50 AOAC_PW_ON# 23
A4 Ming 9/13  remove PM_BATLOW#
BATT_CHGI_LED#/GPIO52 BAT_CHG_LED 39
B3 CAP_LOCK#
CAPS_LED#/GPIO53 CAP_LOCK# 33
36,39,40 EC_SMB_CK1
EC_SMB_CK1 A8
SCL0/GPIO44 GPIO BATT_LOW_LED#/GPIO54
A3 PWR_LED#
PWR_LED# 25,34 10/16 Eric change vgate from pin97 to pin 74.
EC_SMB_DA1 A7 A2
36,39,40 EC_SMB_DA1 SDA0/GPIO45 SUSP_LED#/GPIO55 WLAN_ON_LED# 35
18,30,6,8 EC_SMB_CK2
RK17 1 @ 2 0_0402_5% EC_SMB_CK2_R B8
SCL1/GPIO46 SM Bus SYSON/GPIO56
B2 SYSON
SYSON 17,37,42 10/18 Eric Add AOAC_PW_ON.
18,30,6,8 EC_SMB_DA2
RK18 1 @ 2 0_0402_5% EC_SMB_DA2_R A6
SDA1/GPIO47 VR_ON/XCLK32K/GPIO57
H5
EC_LAN_ISOLATEB# 24,31 Add EC_LAN_ISOLATEB#
@ N1 POK_FIX POK_FIX 43
RK19 1 2 10K_0402_5% EC_SCI# AC_IN/GPIO59
+3VS Ming9/18 change 0ohm to new footprint
15 SLP_S3# SLP_S3# J5 D4 EC_RSMRST#
PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 EC_RSMRST# 15
15 SLP_S5# SLP_S5# N9 D1
EC_SMI# L13 PM_SLP_S5#/GPIO07 EC_LID_OUT#/GPXIOA04 D2 VCIN1_PH
B 15 EC_SMI# VCIN1_PH 39 B
K6 EC_SMI#/GPIO08 EC_ON/GPXIOA05 E2 EC_THERM
27 USB_CHARGE_EN LID_SW#/GPIO0A EC_SWI#/GPXIOA06 EC_THERM 39,8
SPOK N7 E4 MAINPWON MAINPWON 41,8
27,39,41,43 SPOK SUSP#/GPIO0B ICH_PWROK/GPXIOA07
2/22 Eric Add SPOK to EC N7. AC_LED# M7 GPO E1 BKOFF# BKOFF# 18
39 AC_LED# PBTN_OUT#/GPIO0C BKOFF#/GPXIOA08
N8 GPIO F4 PBTN_OUT# PBTN_OUT# 15
EC_PME#/GPIO0D WL_OFF#/GPXIOA09
20 TS_STOP# K8
EC_THERM#/GPIO11 GPXIOA10
F2 VR_ON
VR_ON 46 10/3 Eric Del ENBKL control pin.
FAN_SPEED1 M11 F1 ENBKL
34 FAN_SPEED1 FAN_SPEED1/FANFB0/GPIO14 GPXIOA11 ENBKL 10
Add PROC_DETECT# N11
FANFB1/GPIO15 10/16 Eric Change VR_ON to 108.
E51TXD_P80DATA K10
23 E51TXD_P80DATA EC_TX/GPIO16
Ming9/3 remove PROC_DETECT# E51RXD_P80CLK K9 F5 EC_ACIN
23 E51RXD_P80CLK EC_RX/GPIO17 PM_SLP_S4#/GPXIOD01
@ 2 R70 1 0_0402_5%N12 G1 EC_ON
change PM_SLP_SUS# to GPIO15 15 FCH_PWRGD
USB_CTL1 M13 ON_OFF/GPIO18 ENBKL/GPXIOD02 G5 ON/OFF#
EC_ON 41
27 USB_CTL1 PWR_LED#/GPIO19 GPXIOD03 ON/OFF# 34,35
USB_CTL2 L12 GPI H1 LID_SW# LID_SW# 34,35
27 USB_CTL2 NUMLED#/GPIO1A GPXIOD04 G4 SUSP#
GPXIOD05 SUSP# 37,42,45
GPXIOD06
H4
H2
NMI_DBG# <DB>Pin117 NC-->NMI_DBG#
J1 GPXIOD07
27 USB_IN_STATUS# XCLKI +3VALW_EC
<DB>Remove @ 32.768KHz 'XTAL 13,16 RTC_CLK @ RK21 1
0_0402_5%
2 EC_XCLK0 K1
XCLKO V18R
L1 +V18R
1
1

AGND

FCH_PWRGD CK10
GND
GND
GND
GND
GND

6 THERMAL_ALERT# RK32 1 2 0_0402_5% RK22 LID_SW# RK23 2 1 47K_0402_5%

@ 100K_0402_5% 4.7U_0603_6.3V6K
10/4 Eric Del. KB9012BF-A4_LFBGA128 2
2
J8
J9
N13
J10
G2

A11

@ 20mil <DB>RK56 10K-->100K RK24

2

C73 SA000054810 100K_0402_5%

100P_0402_50V8J EC_ON 2 1
1 LK2
ESD@
ECAGND 2 1
RK25 FBMA-L11-160808-800LMT_0603
100K_0402_5%
2 1 PLT_RST# +3VALW_EC

1 2 VR_ON 2
1

A A
<DB>Remove JFW1 RK20 10K_0402_5%
C71 RK28
ECAGND
ECAGND 39
<DB>RK50 10K-->100K 1
100P_0402_50V8J 10K_0402_5%
ESD@
2

NMI_DBG# 1 2 GPIO0
10/4 Eric Del.
DK2
GPIO0 13 Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
CH751H-40PT_SOD323-2
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 32 of 47
5 4 3 2 1
 TOUCH_PAD_PWREN# 14
Keyboard conn

1
R39 32 KSI[0..7]
1K_0402_5% KSI7
@ KSI6
KSI5 JKB1 CONN@

2
+3VS_TOUCH_PAD C27 1 2 0.01U_0402_16V7K KSI4 KSI1 1
KSI3 KSI7 2 1
2

2
@ KSI2 KSI6 3
3

G
@ KSI1 KSO9 4
1 3 KSI0 KSI4 5 4
+3VALW 32 KSO[0..17] 5

S
KSO17 KSI5 6
Q6 KSO16 KSO0 7 6
KSO15 KSI2 8 7
AO3413L_SOT23-3 8
KSO14 KSI3 9
@ 0_0603_5% KSO13 KSO5 10 9
R569 1 2 KSO12 KSO1 11 10
KSO11 KSI0 12 11
KSO10 KSO2 13 12
KSO9 KSO4 14 13
KSO8 KSO7 15 14
+3VS_TOUCH_PAD KSO7 KSO8 16 15
KSO6 KSO6 17 16
17
10/29 Del all KB caps. KSO5 KSO3 18
18
KSO4 KSO12 19
KSO3 KSO13 20 19
+3VS_TOUCH_PAD KSO2 KSO14 21 20
21

2
KSO1 KSO11 22
R452 R453 KSO0 KSO10 23 22
2.2K_0402_5% KSO15 24 23
2.2K_0402_5% 24
KSO16 25
KSO17 26 25

1
26
2

2N7002DWH_SOT363-6 35 WL_WHIT WL_WHIT 27 33

WLAN_AMBER 28 27 GND 34
35 WLAN_AMBER 28 GND
6 1 FCH_SDATA1_TP 28 MUTE_LED MUTE_LED 29
15,18 FCH_SDATA1 29
EMI reserve +5VS 30
Q151A R40 1 2 360_0402_5% 31 30
32 CAP_LOCK# 31
R454 1 2 0_0201_5% +5VS 32
32
@
ACES_51503-03241-001
5

Touch pad conn

3 4 FCH_SCLK1_TP
15,18 FCH_SCLK1

Keyboard backlight Conn

2N7002DWH_SOT363-6
Q151B 0_0201_5%
R455 1 2

<DB>Check footprint and Touch PAD spec +5VS +5VALW

1
+3VS_TOUCH_PAD
R41
Q7 100K_0402_5%
0.1U_0402_16V7K 2 1 C41

3
+5VS_KBL S

2
@ 2
G KBL_OFF# 32
JP14 D

1
JTP1 1
1 1 2 AO3413L_SOT23-3
2 1 5 2 3
NonCS 32
32
TP_DATA
TP_CLK
3 2 6 G1 3 4
4 3 G2 4
FCH_SCLK1_TP 5 4 7 ACES_50504-0040N-001
CS FCH_SDATA1_TP 6 5 G1 8 CONN@
6 G2
ACES_51524-0060N-001

CONN@
3

DM9
YSLC05CH 3P C/A SOT-23
SCA00000U10
@ESD@
1

10/11 Eric del DM10 from ESD requirement.

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 33 of 47
 A B C D E

+5VS +3VS

1
R43 R44 FAN conn
47K_0402_5% 10K_0402_5%
@
1 1

2
40mil 1
JFAN1
5
+5VS 1 GND
FAN_SPEED1 2 6
32 FAN_SPEED1 2 GND
@1 @1 FAN_PWM 3
32 FAN_PWM 4 3
C43 C44 4
1
10U_0603_6.3V6M 0.1U_0402_16V7K C45 ACES_50271-0040N-001
2 2 1000P_0402_50V7K CONN@
@
2

2 2

+3VL

Lid Switch (Hall Effect Sensor)

2

+3VALW_EC
R45
3 100K_0402_5% 3

Powert Button Connector

1

ON/OFF#

1
SA00003GI00 @
R46
JPWR1 U2 47K_0402_5%
+5VALW 1 APX9132ATI-TRL_SOT23-3
2 1

2
25,32 PWR_LED# ON/OFF# 3 2 5 2 3 LID_SW#

GND
32,35 ON/OFF# 3 G1 VDD VOUT LID_SW# 32,35
4 6
4 G2
ACES_50504-00401-001 1 1

1
CONN@ @ C47
C46 10P_0402_50V8J
0.1U_0402_16V7K
2 2
<DB>Change to subboard. @

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
SCHEMATIC, MB A9851
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 34 of 47
A B C D E
 5 4 3 2 1

Reset IC
<DB> RST1# connect to ENM
@ R47 @
0_0402_5% U3

41 VL_ENABLE 1 2KBC_HANGUP_RESET# 1 6
RST1# TEST
D 2 5 D
GND DSR
32,34 ON/OFF# ON/OFF# 1 2 3 4 LID_SW# LID_SW# 32,34
D3 CH751H-40PT_SOD323-2 SR0# VCC

0.1U_0402_16V7K
C48
FT7521_MO_252 1
U4
1 6
RST1# TEST 2 +5VALW +5VALW
2 5
GND DSR
3 4 @
SR0# VCC

SOT23-6
Jacky 4/30 Co-lay Reset IC

1
Amber White
R48 R49
360_0402_5% 360_0402_5%

2
C C
WLAN_AMBER WL_WHIT
33 WLAN_AMBER WL_WHIT 33

2N7002KDW_SOT363-6

2N7002KDW_SOT363-6
6

3
H1 H2 H3 H4

Q9A

Q9B
H_3P3 H_3P3 H_3P3 H_3P3
2 5
32 WLAN_OFF_LED# WLAN_ON_LED# 32
HOLEA HOLEA HOLEA HOLEA
CPU

4
@ @ @ @
1

PAD1
MB_SUP_BRK_25X5

HOLEA
B
H7 H8 ZZZ1
PCB B

H_3P3 H_3P3 @
1

HOLEA HOLEA
Card reader
@ @ LA-9851P
1

DA6000Y8000

H13 H5 H6 H16 H10

H_2P8 H_2P8 H_2P8 H_2P8 H_2P8
FD1 FD2 FD3 FD4
HOLEA HOLEA HOLEA HOLEA HOLEA

@ @ @ @
1

1
@ @ @ @ @
1

FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80 FIDUCIAL_C40M80

A H15 H9 H11 H12 A

H_3P0X2P5 H_2P8 H_3P3 H_3P3

HOLEA HOLEA HOLEA HOLEA

WWAN
Security Classification Compal Secret Data Compal Electronics, Inc.
WLAN Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title
@ @ @ @
SCHEMATIC, MB A9851
1

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 35 of 47
5 4 3 2 1
 5 4 3 2 1

ACCELEROMETER
Sensor hub ‐‐>G‐sensor
D D
D4
Check ACCEL_INT# wiht BIOS
+3VALW ACCEL_INT#_R 1 2
ACCEL_INT# 13
CH751H-40PT_SOD323-2
U5
1 9 +3VALW
Vdd_IO INT2 11
EC_SMB_CK1 4 INT1 14
32,39,40 EC_SMB_CK1 SCL/SPC VDD
EC_SMB_DA1 6
32,39,40 EC_SMB_DA1 SDA/SDI/SDO
7 5
2 1 8 SDO/SA0 GND 12
+3VALW CS GND
R51 10K_0402_5% 10 @
RES 13
RES 1 1
2 15 C49
+3VS +3VALW 3 NC RES 16 C50
+3VS NC RES 0.1U_0402_16V7K 10U_0603_6.3V6M
2 2
HP3DC2

1
R509 R510
R508 9656@ 0_0402_5% 0_0402_5%

1
0_0402_5% 9656@ 9635@
0.1U_0402_16V4Z

2
C C
1
C342
1
C343
1
C344 L Must be placed in the center of the system.
1
TPM@ TPM@ TPM@ 0.1U_0402_16V4Z 2 C130 +3VS SMBUS ID:29H
2 2 2
0.1U_0402_16V4Z 0.1U_0402_16V4Z
24
19
10

1
U69 @ 2
TPM@ R503
VSB
VDD
VDD
VDD

4.7K_0402_5%
9635@
LPC_AD0 26 28 LPC_PD#_TPM
13,23,32 LPC_AD0

2
LPC_AD1 23 LAD0 LPCPD# 9 BADD
13,23,32 LPC_AD1 LAD1 TESTB1/BADD
LPC_AD2 20 8
13,23,32 LPC_AD2 LAD2 TEST1

1
LPC_AD3 17 R504
13,23,32 LPC_AD3 LAD3 14 TPM_XTALO
XTALO

1
13 TPM_XTALI R502 @
TPM XTALI PAD 4.7K_0402_5%
T44
LPC_CLK0_DG 21 SLB 9635 TT 1.1 @ 9635@
23,32 LPC_CLK0_DG

2
LPC_FRAME# 22 LCLK 2 4.7K_0402_5%
13,23,32 LPC_FRAME# LFRAME# GPIO2
PLT_RST# 16 6
13,25,32 PLT_RST#

2
SERIRQ 27 LRESET# GPIO
13,32 SERIRQ SERIRQ @
PM_CLKRUN# 15 T45
1 2 7 CLKRUN# 1 PAD
+3VS PP NC
1

B R449 3 B
R507 @ 4.7K_0402_5% NC 12
GND
GND
GND
GND

0_0402_5% NC
1

9635@
R450 S IC SLB9635TT1.2 TSSOP 28P TPM
2

4
11
18
25

@ 0_0402_5%
2

+3VS
9635@ 18P_0402_50V8J
TPM_XTALI C346 1 2
Y8
1

9635@
R506 R451 4 3
4.7K_0402_5% 9635@ OSC NC
9635@ 1 2
OSC NC
2

@
LPC_PD#_TPM R505 2 1 0_0402_5% SUS_STAT# TPM_XTALO C347 132.768K
2 12.5PF Q13MC1462001700
SUS_STAT# 15
10M_0402_5%9635@
18P_0402_50V8J

9656@
A PLT_RST# R511 2 1 0_0402_5% BADD A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
B A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 36 of 47
5 4 3 2 1
 A B C D E

+1.1VALW TO +1.1VS (1.1A)

+1.1VALW +1.1VS
U6
3/6 Co-lay 3VS/5VS low switch circuit AO4430L_SO8
8 1

1U_0402_6.3V6K
C53
7 2

2
10U_0603_6.3V6M
C51
6 3 1 1
Each 250pF on CAP_MOS1 (2) will make 1 5 @
R55
Slew Rate(uS/V) increase of 100uS/V C64 470_0603_5%

4
4.7U_0603_6.3V6K 2 2

6 1
2

1 1

2 VLDT_EN#
B+ 1 2 1.1VS_GATE
+5VS_IN R56 Q10A

1
3
47K_0402_5% DMN66D0LDW-7_SOT363-6

300K_0402_5%
R58
1

1
+5VS

10U_0603_6.3V6M
VLDT_EN# 5 C54
1 Q10B .1U_0603_25V7K
2

C55
DMN66D0LDW-7_SOT363-6

2
+3VALW +5VALW
2
U7
1 14
VIN1 VOUT1

1
2 13 D
+5VALW VIN1 VOUT1 ACIN 2 U8
32,39,40 ACIN
SUSP# 3 12 C56 1 2 100P_0402_50V8J G 2N7002H_SOT23-3
ON1 CT1
S

3
4 11
VBIAS GND
SUSP# 5 10 C57 1 2 680P_0402_50V7K
ON2 CT2
6 9
7 VIN2 VOUT2 8 +3VS_IN
VIN2 VOUT2
15
GPAD
+3VS
TPS22966DPUR_SON14_2X3~D
1 +1.5VTO +1.5V_PCIE

10U_0603_6.3V6M
C58
2 2

10/17 Eric Del +1.5V to +1.5V_PCIE.

+5VALW

RPH22
SUSP 8 1
SYSON# 7 2
3 SUSP# 6 3 3
SYSON 5 4

100K_0804_8P4R_5%

+0.675VS
+2.5VS +1.2VS +1.35V_VDDQ

2
R182
+VL 22_0603_5% R183 R184 R185
SUSP 470_0603_5% 470_0603_5% 470_0603_5%

2
2

SYSON#

3 1

6 1

3 1
3

R65
6

6
100K_0402_5%

SUSP# 5 DMN66D0LDW-7_SOT363-6
32,42,45 SUSP#
1

VLDT_EN# SYSON 2 DMN66D0LDW-7_SOT363-6 2 SUSP 5 SUSP 2 SUSP 5 SYSON#

17,32,42 SYSON
Q13B
4
1

D Q13A Q14A Q14B Q15A Q15B

1

4
32,44 VLDT_EN 2 U9 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6 DMN66D0LDW-7_SOT363-6
4 G 2N7002H_SOT23-3 4
1

S
3

R68
10K_0402_5%
2

C63 @ Security Classification Compal Secret Data Compal Electronics, Inc.

SYSON 1 2 2012/11/07 2012/11/07 Title
100P_0402_50V8J
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-8041P
Date: Monday, October 21, 2013 Sheet 37 of 47
A B C D E
 5 4 3 2 1

Version ChangeList ( P. I . R. List ) Page1

Request
I tem Page# Title Date I ssueDescription Version
Owner
1 23 Del short pad of R22 1/7 For Port80 issue 0.2

2 32 Change RK33 from 0 ohm to 12k ohm. 1/7 For SI phase board ID requirement 0.2

3 27 Add R578 1/7 For USB charger port requirement 0.2

4 13 Add CH101 1/7 For ESD requirement 0.2

D D
5 23 Del R76, Q150, R370 and C73 1/7 For EC control directly 0.2

6 15 Change RF9 from 680pF to 15pF 1/7 For FIX EA issue 0.2

7 13 Add CH18 1/7 For FIX PLT_RST# noise 0.2

8 32 Del RK35 1/7 For EMI no requirement 0.2

9 26 Add RK37 1/7 For support WOL in DC S5 mode 0.2

10 41 Change jump net name +3VLP to +3VL 1/7 For connection between PWR and HW 0.2

11 41 Change net name VL to +VL 1/7 For connection between PWR and HW 0.2

12 44 Change net name SUSP# to VLDT_EN for 1.2V EN 1/7 For connection between PWR and HW 0.2

13 39 Reserve PC9, PC10, PC13, PR13, PR14, PR16, PR18, PQ2, PQ4 1/7 For charger IC +VSB circuit 0.2

14 40 Change net name +3VALW to +3VL 1/7 For correct cell selection in S5 0.2

15 40 Change PR111 from 0 ohm to 2.2 ohm. 1/7 For EMI request 0.2

16 40 Mount PC110, PC108, PR113, PC120 1/7 For EMI request 0.2

17 40 Add PC136 0805 10uF 1/7 For EMI request 0.2

18 39 Reserve PR29, PR31, PR32, PR33 1/7 For AC LED circuit 0.2

19 39 Reserve PQ6, PU4A, PU4B, PD8, PR19, PR20, PR21, PR22, PC22, PC23 1/7 For One Shot circuit 0.2

20 39 Reserve PR23 1/7 For Hysteresis resistor 0.2

21 39 Change net name H_PROCHOT#_EC to EC_THERM 1/7 For correction 0.2

C C
22 41 Change PR302 from 30k ohm to 30.9k ohm 1/7 For USB port load issue 0.2

SI2 SI2 SI2 SI2

1 21 Remove WWAN portion. 1/30 For HP requirement. 0.4

2 32 Change RK33 to 20K ohm from 15Kohm. 1/30 For EC requirement. 0.4

3 45 Change PWM IC from ISL62771 to ISL6277A 1/30 For Power +APU_CORE_NB two pahse requirement. 0.4

Add one more phase for CORE NB and Use

4 45 Dual-N MOSFET for each phase. 1/30 For Power requirement. 0.4

PV PV

1 32 Change RK33 from 20k ohm to 27k ohm. 3/03 For PV phase board ID requirement 0.5

2 36 Reserve TPM circuit 3/03 For HP requirement. 0.5

3 22 Remove R60, R61, R62 and R63. 3/03 Remove SATA co-lay. 0.5

4 43 Add PR1106. 3/03 For EC Fix code requirement. 0.5

5 22 Remove R69. 3/03 Remove +5V_HDD 0hm. 0.5

6 46 Modify +CPU_CORE_NB to two phase soluiton. 3/03 For PWR requirement. 0.5

7 32 Add C71, C73. 3/03 For ESD requirement. 0.5

8 15 Add C72. 3/03 For ESD requirement. 0.5

9 15 Reserve C74. 3/03 For ESD requirement. 0.5

B B
10 13 Add C75. 3/03 For ESD requirement. 0.5

11 24 Move Lan chip to sub board. 3/03 For HW requirement. 0.5

12 41 Reserve PR318 3/03 For EMI requirement. 0.5

MV MV

1 40 Add PC137 4/09 For PWR requirement. 1.0

change PR151, PR318, PR412, PR1106, PR1203, PRG4,

2 PRG8, PRG10. PRG22, PRG23, PRG28, PRZ9, PRZ12, For PWR requirement. 1.0
4/11
PRZ28, PRZ33, PRZ44 from 0 ohm to short pad

A A

Security Classification Compal Secret Data

Issued Date 2011/06/29 Deciphered Date 2011/06/29 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
Size Document Number Rev
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
D A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 38 of 47
5 4 3 2 1
 5 4 3 2 1

+3VLP +3VLP

10K_0402_5%
1
@ PQ5

3
@ PR27
TP0610K-T1-GE3_SOT23-3

2
EMI@ PL3 2
KC FBMA-L11-160808-301LMA20T 32 AC_LED#
1 2 +3VLP
PJP1 change to DC03000AF00 ADPIN VIN
EMI@ PL2

10K_0402_5%
PR33

1
KC FBMA-L11-160808-301LMA20T 0_0402_5%

@ PR26
1 2 AC_LED# 1 2 ACIN_LED
D @ PJP1 D
EMI@ PL1

100K_0402_5%
ACES_59012-0080N-002 @

1
2 1 KC FBMA-L11-160808-301LMA20T @ PR25 PU2

2
2 1

PR31
1 2 2K_0402_5% 1

P
B

1
4 3 ACIN_LED 1 2 4
4 3 PC1 EMI@ PC2 EMI@ PC3 EMI@ PC4 EMI@ O 2
A

G
6 5 ADP_SIGNAL 100P_0402_50V8J 1000P_0402_50V7K 100P_0402_50V8J 1000P_0402_50V7K

2
6 5 74LVC1G02GW_SOT353-5

3
Charge_LED 8 7 ACIN_LED
8 7

5
@ PU3 BAT_CHG_LED 32

VCC
PR30 1
10K_0402_5% Charge_LED 4 IN1 PR32
ADP_SIGNAL 1 2 OUT 2 2K_0402_5%
ADP_ID 32

GND
IN2
2

3
BAT_CHG_LED 1 2 Charge_LED

1000P_0402_50V7K
100P_0402_50V8J
1

1
MC74VHC1G08DFT2G_SC70-5

3
1

1
10K_0402_5%

100K_0402_5%
GLZ3.6B_LL34-2
PR28

PC15

PC27

PR29
PD7
PD4 ESD@ PD1 ESD@
L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3
1

2
2

2
@

2
C C
ADP_I 32,40
+3VALW_EC

10K_0402_5%

1
PR12
PR15
5.9K_0402_1%
BATT++ BATT+

2
EMI@ PL4
VCIN0_PH 32 VCIN1_PH 32

.1U_0402_16V7K

0.1U_0402_16V7K
@ PJPB1 HCB2012KF-121T50_0805

1
ACES_50278-01401-001 1 2

1
@ PC11

@ PC14
16
GND 15 BATT++ EMI@ PL5 BATT+ PH1 PR17 @ PR23
GND 14 HCB2012KF-121T50_0805 100K_0402_1%_NCP15WF104F03RC 10K_0402_1% 10K_0402_1%

2
14 13
1

1 2

2
13 12 PC7 EMI@ PC8 EMI@
12 11 1000P_0402_50V7K 0.01U_0402_25V7K EC_THERM 32,8
2

11 10
10 9 ECAGND 32
9 8
8 7
7 6
6 5
5 4
4 3
3 2 PR10
2 1 100_0402_5% +5VS
1 1 2
B EC_SMB_DA1 32,36,40 B

PR11

8
100_0402_5%
1 2 3

P
EC_SMB_CK1 32,36,40 + +3VALW
1
O 2
-

G
@ PU4A

1
LM393DR_SO8

4
@ PR19
13,46,8 EC_THERM# 47K_0402_1% @ PR21
10K_0402_1%
@ PU4B

2
8
@ PC22 LM393DR_SO8

1
D 0.022U_0402_16V7K 5

P
@ PQ2 2N7002KW_SOT323-3 2 2 1 7 +
O

1
LL4148_LL34-2
@ PQ6 G 6
TP0610K-T1-GE3 1P SOT23-3 -

1
100P_0402_50V8J
S

1
@ PR20

4
100K_0402_1%

@ PD8

@ PC23
B+ 3 1 @ PR22
+VSB

2
1.5M_0402_5%

2
100K_0402_1%

0.22U_1206_25V7K

2
1

2
1

1
@ PR13

+5VALW
PC9

@ PC10
0.1U_0603_25V7K
2

@
2

2
2

@ PR16
@ PR14 22K_0402_1%
ACIN 32,37,40
100K_0402_1% 1 2
1

A D A
2 @ PQ4
27,32,41,43 SPOK
G 2N7002KW_SOT323-3
S
3
1

@ PC13
.1U_0402_16V7K
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 39 of 47
5 4 3 2 1
 5 4 3 2 1

1
D
2 PQ101
G 2N7002KW_SOT323-3
S

3
PR101 PR102
1M_0402_5% 3M_0402_5%
1 2 1 2
D D

BATT+ BAT_B+
VIN P1 P2 P3
PR103
PQ102 PQ103 EMI@ PL103
0.01_1206_1%
TPCA8057-H_PPAK56-8-5 MDV1526URH_PDFN33-8-5 1UH_PCMB042T-1R0MS_4.5A_20% PQ104
1 1 1 4 1 2 AO4407AL_SO8

2200P_0402_50V7K
2 2 8 1

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
68P_0402_50V8J

0.1U_0402_25V6
5 3 3 5 2 3 7 2
VIN B+ 6 3

1
PC137

@RF@ PC107

EMI@ PC110

EMI@ PC108

PC105

PC106

EMI@ PC136
5
4

4
1

1 4
PC101 PC102 PC109

3
2200P_0402_50V7K 0.1U_0402_25V6 0.1U_0402_25V6
2

1 2
PD104 PR106
BAT54CW_SOT323-3 4.12K_0603_1%

0.1U_0402_25V6

0.1U_0402_25V6

CHGR_BATDRV 2
1
1

1
PC111

PC112
PC113
0.047U_0402_25V7K

2
1

1 2

2.2_0402_1%
1

5
PR107 PR108

10_1206_1%
1

PR110
4.12K_0603_1% 4.12K_0603_1%

PR109
2

PR111

1
C CHGR_DH 1 2 4 C

2
PD102
2.2_0402_5% B+

CHGR_BST
1 2 PQ105

CHGR_DH
RB751V-40_SOD323-2

CHGR_LX
SIS412DN-T1-GE3_POWERPAK8-5
PC114 PC115 PL102 PR112

3
2
1
1U_0603_25V6K 1 2 3.3UH_PCMB063T-3R3MS_6.5A_20% 0.01_1206_1%
CHGR_LX 1 2 1 4
1U_0603_25V6K

1
2 3

20

19

18

17

16

RB751V-40_SOD323-2
PR113 EMI@

BTST
VCC

PHASE

HIDRV

REGN
21

10U_0805_25V6K

10U_0805_25V6K
4.7_1206_5%
PAD

1
1CHGR_SNB 2

1
PD103

PC118

PC119
CHGR_ACN 1 15 CHGR_DL 4
ACN LODRV
PU101 PQ106

2
CHGR_ACP 2 BQ24715RGRR_QFN20_3P5x3P5 14 AON7702A_DFN8-5

2
ACP GND

3
2
1
CHGR_CMSRC 3 13 CHGR_SRP
CMSRC SRP PC120 EMI@
680P_0402_50V7K

2
CHGR_ACDRV 4 12 CHGR_SRN
PR116 ACDRV SRN
10K_0402_1% PR114
1 2 CHGR_ACOK 5 11 CHGR_BATDRV 0_0603_5%
+3VL ACOK ACDET /BATDRV 1 2 CSOP1
@ PR118

CELL
IOUT

SDA

SCL

1
0_0402_5%
32,37,39 ACIN 1 2 PC123
0.1U_0603_25V7K
6

10

2
B 1 2 CSON1 B
PR115
CHGR_ACDET

0_0603_5%

0.1U_0402_25V6
CHGR_CELL
CHGR_IOUT

0.1U_0402_25V6
CHGR_SDA

CHGR_SCL

1
PC116

PC117
PR119
VIN 10K_0402_1%

2
1 2
+3VL
@ PR123
1

0_0402_5%
1 2
EC_SMB_CK1 32,36,39
PR124
270K_0402_1% @ PR122
0_0402_5%
2

1 2
EC_SMB_DA1 32,36,39
1
1

@ PR125
1

0_0402_5%
PC125 PR126
.047U_0402_16V7K 42.2K_0402_1%
2

1 2

ADP_I 32,39
2

PC126
100P_0402_50V8J
B+
2

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K

2200P_0402_50V7K
68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J
0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6

0.1U_0402_25V6
1

1
@RF@ PC134

@RF@ PC135

@RF@ PC133

@RF@ PC122

@RF@ PC124

@RF@ PC121

@RF@ PC128

@RF@ PC129

@RF@ PC127

@RF@ PC131

@RF@ PC132

@RF@ PC130
2

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
Size
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 40 of 47
5 4 3 2 1
 A B C D E

PR301 PR302
13.3K_0402_1% 30.9K_0402_1%
1 2 2 1
+3VALWP

107K_0402_1%

68K_0402_1%

118K_0402_1%
RT8243A_B+
PR303 PR304
RT8243A_B+ 20K_0402_1% 20K_0402_1%

2
1 2 1 1 2 1
PL301 EMI@

2200P_0402_50V7K

10U_0805_25V6K
HCB2012KF-121T50_0805
+5VALW

68P_0402_50V8J

0.1U_0402_25V6
1 2 FB2=1.98V FB1=2V
B+

PR305

PR307

PR306
ENTRIP2 1

ENTRIP1 1

1
2200P_0402_50V7K

@RF@ PC318

@RF@ PC319

@RF@ PC320

PC304
1
10U_0805_25V6K
68P_0402_50V8J

0.1U_0402_25V6
PR317 FB=1.98V(Min) FB=1.98V(Min)

2
1

1
@RF@ PC316

@RF@ PC317

@RF@ PC302

PC303

SIS412DN-T1-GE3_POWERPAK8-5
100K_0402_1% 2.006V(Typ) 2.006V(Typ)
PQ301 2.03V(Max) 2.03V(Max)

5
SIS412DN-T1-GE3_POWERPAK8-5
2

1
27,32,39,43 SPOK

TON
FB2

ENTRIP2

ENTRIP1

FB1
21
4 6 PAD 4
PGOOD

PQ303
PC305 PR308 20
.1U_0603_25V7K 2.2_0603_5% BYP1 PR309 PC306
1 2 1 2 BST_3V 7 2.2_0603_5% .1U_0603_25V7K
@ PR318 BOOT2 19 BST_5V 1 2 1 2

1
2
3

3
2
1
0_0402_5% PU301 BOOT1
1 2 8 RT8243AZQW_WQFN20_3X3
PL303 UGATE2 18 UG_5V
3.3UH_PCMB063T-3R3MS_6.5A_20% UGATE1 PL302
1 2 LX_3V 9 2.2UH_PCMB063T-2R2MS_8A_20%
+3VALWP PHASE2
PHASE1
17 LX_5V 1 2 +5VALWP
1

4.7_1206_5%

1
@EMI@ PR310

LG_3V 10
LGATE2

5
16 LG_5V

ENLDO
LGATE1

LDO5

LDO3
PR311 @EMI@

AON7702A_DFN8-5
ENM
VIN
1 4.7_1206_5%
2

2
2 + PC307 4 Typ: 150mA 2

11

12

13

14

15
680P_0402_50V7K

PQ304
150U_B2_6.3VM_R35M 4 + PC308
PQ302 150U_D2_6.3VY_R15M
+3VLP
1

1
2
@EMI@ PC309

.1U_0603_25V7K
AON7702A_DFN8-5 RT8243A_B+
PC312 @EMI@ 2
1
2
3

ENM
680P_0402_50V7K
2

3
2
1

2
1

1
PC310
PC311
4.7U_0805_10V6K

2
PR312
499K_0402_1% Typ: 225mA
1 2
B+ +VL

1
150K_0402_1%

1U_0603_10V6K
VL_ENABLE

1
35 VL_ENABLE

PC313
PC314

PR313
4.7U_0805_10V6K

2
2
PR314 @ PJ302 @PJP301
2.2K_0402_5% 1 2 1 2
1 2 +3VALWP 1 2 +3VALW +3VLP 1 2 +3VL
32 EC_ON JUMP_43X118 JUMP_43X79
@ PR315
3 0_0402_5% @ PJ303 3
1 2 1 2
32,8 MAINPWON +5VALWP 1 2 +5VALW
JUMP_43X118

ENM
402K_0402_1%

4.7U_0603_6.3V6K
1

For EC use +3VALW,

1
@ PR316

PC315

mark "@" if use +3VLP

2

@
2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 4019NK A
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Monday, October 21, 2013 Sheet 41 of 47
A B C D E
 5 4 3 2 1

PL401 EMI@
HCB2012KF-121T50_0805 PC402 PR401
B+ 1 2 B+_DDR 0.22U_0402_10V6K 2.2_0402_1%
1 2 BST_DDR-1 1 2

2200P_0402_50V7K
68P_0402_50V8J

10U_0805_25V6K
0.1U_0402_25V6

4.7U_0805_25V6-K
1

1
@RF@ PC418

@RF@ PC420

@RF@ PC419

PC405

PC406
D +1.35V_VDDQ D

2
+0.675VSP

VIN_DDRT
BST_DDR

VIN_DDR
DH_DDR
LX_DDR

10U_0805_6.3V6K

10U_0805_6.3V6K
1

1
PC407

PC408
4

16

17

18

19

20

2
PQ401 PU401
SIS412DN-T1-GE3_POWERPAK8-5

PHASE

UGATE

BOOT

VTT
VLDOIN
21

1
2
3
PAD
PL402 DL_DDR 15 1
2.2UH_PCMB063T-2R2MS_8A_20% LGATE VTTGND
1 2
+1.35V_VDDQP 14
PGND VTTSNS
2 VTTSNS_DDRT
1

5
PR403
13.3K_0402_1%
PR404 @EMI@ 1 2 CS_DDR 13 3
4.7_1206_5% CS RT8207MZQW_WQFN20_3X3 GND
1
2

4 VDDP_DDR 12 4 VTTREF_DDRT
+ PC409 PQ402 PR405 +5VALW VDDP VTTREF
1SNB_DDR

330U_2.5V_M AON7702A_DFN8-5 5.1_0603_5%

1 2 VDD_DDR 11 5 VDDQ_DDR +1.35V_VDDQP
2 +5VALW VDD VDDQ

PGOOD
1
2
3

1
C C

TON
PC411 PC412 PC413

FB
S5

S3
PC410 @EMI@ 1U_0603_10V6K 1U_0603_10V6K 0.033U_0402_16V7K

2
680P_0603_50V7K
2

10

6
FB=0.75V

TON_DDR

FB_DDR
S5_DDR

S3_DDR
PR406
8.06K_0402_1%
1 2 +1.35V_VDDQP
PR407
887K_0402_1% @ PC414
B+_DDR 1 2 100P_0402_50V8J
1 2

1
PR413
30K_0402_5%
1 2 PR411
17,32,37 SYSON
10K_0402_1%

2
@ PR412
0_0402_5%
1 2
32,37,45 SUSP#

1
B @ PC416 @ PC417 B
0.1U_0402_10V7K 0.1U_0402_10V7K

2
@ PJP401
2 1
+1.35V_VDDQP 2 1 +1.35V_VDDQ
JUMP_43X118

@ PJP402
2 1
+0.675VSP 2 1
+0.675VS
JUMP_43X39

A A

Security Classification Compal Secret Data

Title
Compal Electronics, Inc.
Issued Date 2012/11/07 Deciphered Date 2012/11/07
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Custom
4019NK A

Date: Monday, October 21, 2013 Sheet 42 of 47

5 4 3 2 1
 5 4 3 2 1

D D

PU1101
SY8809DFC_DFN8_2X2
+1.1VALWP +1.1VALW
4 5 PL1102
GND GND 1UH_PCMB063T-1R0MS_12A_20% @ PJ1101
1.1valwp
EMI@ PL1101
HCB1608KF-121T30_0603
3
LX LX
6 1.1V_LX 1 2 1
1 2
2 Peak Current 5.2A
+5VALW

1
1 2 1.1V_IN 2
IN PG
7 JUMP_43X118 current limited 6.0A
PR1103 @EMI@
(4A,240mils ,Via NO.= 8)

22U_0805_6.3V6M

22U_0805_6.3V6M
1 8 1.1V_FB
EN FB 4.7_0805_5%
1.1V_EN
1

1
PC1107

PC1101

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1

1
1SNUB_+1.1V
2

PC1109

PC1108

PC1104

PC1105
2

2
@ PR1101
0_0402_5%
1 2
27,32,39,41 SPOK
PC1103 @EMI@
680P_0603_50V7K

2
1

@ PR1106
1

0_0402_5%
1 2 @ PR1102 @ PC1102
32 POK_FIX

1
100K_0402_1% 0.1U_0402_10V7K
2

1
2

C PR1104 PC1106 C
84.5K_0402_1% 330P_0402_50V7K

2
FB=0.6V

2
1
PR1105
100K_0402_1%

2
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK A

Date: Monday, October 21, 2013 Sheet 43 of 47

5 4 3 2 1
 5 4 3 2 1

EMI@ PL1201
HCB1608KF-121T30_0603
+1.2VSP_B+ 2 1
B+

2200P_0402_50V7K
68P_0402_50V8J

0.1U_0402_25V6
4.7U_0805_25V6-K

4.7U_0805_25V6-K
1

1
PC1201

PC1202

@RF@ PC1210

@RF@ PC1211

@RF@ PC1204
2

2
5
D D

PR1201 PC1205 4
2.2_0603_5% .1U_0603_25V7K
1 2 1 2 PQ1201
SIS412DN-T1-GE3_POWERPAK8-5
PU1201

3
2
1
PR1202 1 10 BST_+1.2V
110K_0402_1% PGOOD VBST
@ PR1203 1 2 TRIP_+1.2V 2 9 UG_+1.2V PL1202
0_0402_5% TRIP DRVH 1UH_PCMB063T-1R0MS_12A_20%
1 2 EN_+1.2V 3 8 SW_+1.2V 1 2
32,37 VLDT_EN EN SW
+1.2VSP
0.1U_0402_16V7K

1
47K_0402_1%

FB_+1.2V 4 7
VFB V5IN
+5VALW
1

@ PR1204

@ PC1206
1

RF_+1.2V 5 6 LG_+1.2V PR1205 @EMI@

TST DRVL

5
4.7_1206_5% 1

330U_2.5V_M
11
2

SNB_+1.2V 2
TP

1
+

PC1208
PC1207

AON7702A_DFN8-5
2

TPS51212DSCR_SON10_3X3 1U_0603_6.3V6M

2
PR1206
2

PQ1202
470K_0402_1% 4
2

1
3
2
1
PC1209 @EMI@
1000P_0603_50V7K

2
C C

@ PJ1201
JUMP_43X118
PR1207 +1.2VSP 1 2 +1.2VS
1 2
FB=0.7V
7.15K_0402_1%
2 1
1

PR1208
10K_0402_1%
2

B B

PU2501
APL5508-25DC-TRL_SOT89-3
+3VS @ PJ2501
2 3 +2.5VSP JUMP_43X39
IN OUT +2.5VSP 1 2 +2.5VS
1 2

1
GND
1

1
1
(0.75A,40mils ,Via NO.=22)
PC2501 PC2502 @ PR2501
1U_0603_10V6K 4.7U_0805_6.3V6K 10K_1206_5%
2

2
A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK A

Date: Monday, October 21, 2013 Sheet 44 of 47

5 4 3 2 1
 5 4 3 2 1

D D

+3VS Note:Iload(max)=3A
PU151

4 5 PL151
PGND NC 2.2UH_PCMB042T-2R2MS_3A_20%
3 6 1 2
IN LX +1.5VSP
22U_0805_6.3V6M

22U_0805_6.3V6M

22P_0402_50V8J
2 7
PG EN
C C
1

1
PC151

PC152

PC157
1 8

22U_0805_6.3V6M

22U_0805_6.3V6M
PR154
FB SGND 9 30.1K_0402_1%
PGND
2

1
PC155

PC156
SY8003DFC_DFN8_2X2
FB=0.6V

2
1
1

4.7_1206_5%
PR155

@EMI@ PR153
20K_0402_1%
@ PR151

2
0_0402_5%

2
1 2 +1.5VS_EN
32,37,42 SUSP#
1

@ PJP151
1

680P_0402_50V7K
@ PR152 2 1
@ PC153 22K_0402_5% +1.5VSP 2 1
+1.5VS

1
0.1U_0402_16V7K JUMP_43X39
2

@EMI@ PC154
2

B
2 B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 45 of 47
5 4 3 2 1
 5 4 3 2 1

CPU_B+

@ PRG22 PCG17

2200P_0402_50V7K

68P_0402_50V8J
0_0603_5% 0.22U_0603_25V7K

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
PCG1 PRG1 1 2 2 1
330P_0402_50V7K 2K_0402_1%

1
PCG18

PCG15

@RF@ PCZ40

@RF@ PCZ41

@RF@ PCZ39
2 1 2 1
1 2 UGATE_NB2-1
PRG2 PRG3 PCG2 +5VALW @ PRG28

2
2.94K_0402_1% 137K_0402_1% 390P_0402_50V7K 0_0402_5% PUZ2 0_0603_5%

4
2 1 2 1 2 1 2 1 1 2 6 1 UGATE_NB2 @ PRG23
VCC UGATE

1U_0603_16V6K

G1

D1

D1

D1
8 APU_VDDNB_SEN

1
PRG4 7 2 BOOT_NB2
FCCM BOOT

PCG19
PRG5 PCG5 PRG7 PCG6 41.2K_0402_1%
10_0402_5% 1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J PWM2_NB 3 8 PHASE_NB2 9 10

2
2 1 2 1 2 1 2 1 PWM PHASE D2/S1 D1 PLG2
+APU_CORE_NB 4 5 LGATE_NB2 PQG2 0.22UH_PCME064T-R22MS_28A_20% +APU_CORE_NB
D
9 GND LGATE FDMS3664S_POWER56-8-7 PRG26 1 2 D

G2

S2

S2

S2
@ PCG8 TP 10K_0402_1%

1
1000P_0402_50V7K ISL6208BCRZ-T_QFN8_2X2 ISEN2_NB 2 1 2 1 ISEN1_NB

5
2

2 1 @EMI@ PRG20
PCG7 4.7_1206_5% PRG21 PRG27
0.1U_0603_50V7K 3.65K_0402_1% 10K_0402_1%
1

VSUMN_NB 2 1 2 1 VSUMP_NB 2 1

1 2
2

@ PRG9 @ PCG9 PRG17

100_0402_1% 220P_0402_50V7K @EMI@ PCG16 1_0402_1%

0.047U_0402_16V7K
PHG1 2 1 680P_0603_50V7K VSUMN_NB 2 1

2
0.15U_0402_10V6K
10K_0402_5%_ERTJ0ER103J
1

PRG11
11K_0402_1%

APU_CORE_NB
2 1

1 360_0402_1%
PCG11

PCG12
PRG14

TDC 22A
2

1
PRG15 CPU_B+ Peak Current 33A
2

2.61K_0402_1% PRG29
121K_0402_1% OCP current 41A
1

2200P_0402_50V7K

68P_0402_50V8J
VSUMP_NB
Load line -4mV/A

10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
2
PCZ38
FSW=450kHz

1
PCG3

PCG4

@RF@ PCZ35

@RF@ PCZ34

@RF@ PCZ33
0.22U_0402_10V6K PWM2_NB
1 2
LGATE_NB1
UGATE_NB1 2 1 UGATE_NB1-1 DCR 0.98mohm +/-5%

ISUMN_NB
ISUMP_NB

COMP_NB
ISEN1_NB

FCCM_NB
VSEN_NB

2
VSUMN_NB PCZ37 @ PRG8

4
FB_NB
0.22U_0402_10V6K 0_0603_5%
1 2 PHASE_NB1

G1

D1

D1

D1
ISEN2_NB
UGATE_NB1

PHASE_NB1 9 10
D2/S1 D1 PLG1

48

47

46

45

44

43

42

41

40

39

38

37
PRZ43 27.4K_0402_1% PUZ1 PQG1 0.22UH_PCME064T-R22MS_28A_20% +APU_CORE_NB
2 1 BOOT_NB12 1 2 1 FDMS3664S_POWER56-8-7D PRG24 1 2

G2

S2

S2

S2
ISUMP_NB
ISEN1_NB

ISUMN_NB

VSEN_NB

FB_NB

COMP_NB

PGOOD_NB

FCCM_NB

PWM2_NB

LGATEX

PHASEX

UGATEX
10K_0402_1%

1
PHG2 CPU_B+ 0_0603_5% PCG10 ISEN1_NB 2 1 2 1 ISEN2_NB

5
470K_0402_5%_TSM0B474J4702RE PRG19 1 36 BOOT_NB1 @ PRG10 0.22U_0603_25V7K @EMI@ PRG12
10.5K_0402_1% ISEN2_NB BOOTX @ PRZ44 4.7_1206_5% PRG13 PRG25
C C
PRG18 1 2 2 1 NTC_NB 2 35 2 1 3.65K_0402_1% 10K_0402_1%
133K_0402_1% NTC_NB VIN VSUMP_NB 2 1

1 2
2 1 IMON_NB 3 34 BOOT2 0_0603_5%
IMON_NB BOOT2

1
LGATE_NB1 PRG16
2 1 4 33 UGATE2 PCZ42 @EMI@ PCG13 1_0402_1%
8 APU_SVC SVC UGATE2
0.22U_0603_25V7K 680P_0603_50V7K VSUMN_NB 2 1

2
PCG14 5 32 PHASE2
13,39,8 EC_THERM# VR_HOT_L PHASE2 +5VALW
1000P_0402_50V7K
6 31 LGATE2 @ PRZ4
8 APU_SVD SVD LGATE2
ISL6277AHRZ-T QFN 48P PWM 0_0402_5%
7 30 VDDP 1 2 CPU_B+ EMI@ PLZ1
+1.35V_VDDQP VDDIO VDDP FBMA-L11-453215800LMA90T_2P
2 1 8 29 VDD 2 1 1 2 B+
8 APU_SVT SVT VDD

2200P_0402_50V7K

68P_0402_50V8J

68U_D2_16VM_R60M

100U_D2_16VM_R50M
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
PCZ1 9 28 PRZ6 1 1
32 VR_ON ENABLE PWM_Y

1U_0603_16V6K

1U_0603_16V6K
1U_0603_16V6K 1_0603_5% PQZ1

1
+ +

PCZ2

PCZ3

@RF@ PCZ6

@RF@ PCZ7

@RF@ PCZ29

PCZ4

PCZ5
10 27 LGATE1 AON7518_DFN8-5
13,8 APU_PWRGD PWROK LGATE1

PCZ8

PCZ9
IMON 11 26 PHASE1

2
1 2 IMON PHASE1 2 2
12 25 UGATE1
NTC UGATE1
NTC

PRZ11 UGATE1 2 1 4
UGATE1-1

PGOOD

BOOT1
ISUMN
ISUMP

COMP
ISEN3

ISEN2

ISEN1

VSEN

133K_0402_1% PHZ1 PRZ18

RTN

FB2

1 2 470K_0402_5%_TSM0B474J4702RE 10.5K_0402_1% @ PRZ9

FB

TP
2 1 2 1 0_0603_5%
PCZ11 PLZ2
13

14

15

16

17

18

19

20

21

22

23

24

49

3
2
1
1000P_0402_50V7K +3VS 0.22UH_PCME064T-R22MS_28A_20%
PRZ42 27.4K_0402_1% PHASE1 PRZ13 1 2
+APU_CORE

1
2 1 +5VALW 10K_0402_1%
ISEN3

COMP
ISUMP
ISEN2

ISEN1

ISUMN

PGOOD

BOOT1

ISEN1 2 1 1 2 ISEN2
FB2

PRZ16
FB

1
100K_0402_5% BOOT1 2 1 2 1
PRZ17 PRZ14
@ PRZ12 PCZ10 PRZ15 @EMI@ 3.65K_0402_1% 10K_0402_1%

2
0_0603_5% 0.22U_0603_25V7K 4.7_1206_5% VSUM+ 2 1
PCZ13 VGATE 32

2
0.22U_0402_10V6K LGATE1 4 PRZ19
1 2 1_0402_1%

1
B B
VSUM- 2 1
PCZ14 PCZ36 PQZ2 PCZ12 @EMI@
0.22U_0402_10V6K 10P_0402_50V8J SIRA10DP-T1GE3_POWERPAKSO-8-5 680P_0603_50V7K

3
2
1

2
VSUM- 1 2 2 1

VSUM+
PCZ15 PRZ22 PCZ16 @ PRZ23 APU_core
1

1000P_0402_50V7K 301_0402_1% 100P_0402_50V8J 32.4K_0402_1%

CPU_B+
TDC 22A
0.15U_0402_10V6K

PRZ21 2 1 2 1 2 1 2 1
2.61K_0402_1% Peak Current 35A
2

330P_0402_50V7K
11K_0402_1%

OCP current 44A

2

2200P_0402_50V7K
PCZ18 PRZ25 PRZ26 PCZ22
1 2

68P_0402_50V8K
10U_0805_25V6K

10U_0805_25V6K

0.1U_0402_25V6
PRZ24

PCZ17

0.047U_0402_16V7K 1.65K_0402_1% 137K_0402_1% 390P_0402_50V7K

Load line -2.1mV/A
PCZ19

2 1 2 1 2 1 PQZ3
PHZ2
1

5
AON7518_DFN8-5
10K_0402_5%_ERTJ0ER103J FSW=450kHz
1

1
PCZ20

PCZ21

@RF@ PCZ32

@RF@ PCZ31

@RF@ PCZ30
PRZ29
2 1 2 1 DCR 0.98mohm +/-5%
2

2
390_0402_1% PRZ27 PCZ23
VSUM- 2 1 2K_0402_1% 680P_0402_50V7K UGATE2 2 1 4
UGATE2-1
1

@ PRZ28
PCZ24 2 1 2 1 0_0603_5%
0.1U_0603_50V7K PRZ32 PLZ3
2

3
2
1
@ PRZ30 @ PCZ25 10_0402_5% 0.22UH_PCME064T-R22MS_28A_20%
100_0402_1% 820P_0402_50V7K 2 1 +APU_CORE PHASE2 PRZ31 1 2
10K_0402_1% +APU_CORE
ISEN2 2 1 1 2 ISEN1

1
APU_VDD_SEN 8 BOOT2 2 1 2 1
@EMI@ PRZ35 PRZ37 PRZ34
@ PRZ33 PCZ26 4.7_1206_5% 3.65K_0402_1% 10K_0402_1%
0_0603_5% 0.22U_0603_25V7K VSUM+ 2 1

2
LGATE2 4 PRZ39
APU_VDD_RUN_FB_L 8 1_0402_1%
2

1
PCZ28 2 1 VSUM- 2 1
0.01U_0402_25V7K PQZ4 @EMI@ PCZ27
A PRZ40 SIRA10DP-T1GE3_POWERPAKSO-8-5 680P_0603_50V7K A
1

3
2
1

2
10_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2012/11/07 Deciphered Date 2012/11/07 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
SCHEMATIC, MB A9851
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
Size Document Number Rev
Custom A
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
4019NK
Date: Monday, October 21, 2013 Sheet 46 of 47
5 4 3 2 1
 A
B
C
D
2 1 2 1 2 1 2 1 2 1

RF@ PCZ128 PCZ118 PCZ113 PCZ107 PCZ101

5
5

2
1
+
68P_0402_50V8J 0.01U_0402_50V7K 0.22U_0402_16V7K 22U_0805_6.3V6M 22U_0805_6.3V6M
PCZ124
330U_D2_2V_Y 2 1 2 1 2 1 2 1 2 1

RF@ PCZ129 PCZ119 PCZ114 PCZ108 PCZ102

+APU_CORE

68P_0402_50V8J 0.01U_0402_50V7K 0.22U_0402_16V7K 22U_0805_6.3V6M 22U_0805_6.3V6M

+APU_CORE
+APU_CORE

2 1 2 1 2 1 2 1 2 1

RF@ PCZ130 PCZ120 @ PCZ115 PCZ109 PCZ103

2
1
+
68P_0402_50V8J 0.01U_0402_50V7K 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M
PCZ126
330U_D2_2V_Y 2 1 2 1 2 1 2 1 2 1

RF@ PCZ131 PCZ121 @ PCZ116 PCZ110 PCZ104

68P_0402_50V8J 180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

Local
2 1 2 1 2 1 2 1

PCZ122 @ PCZ117 @ PCZ111 PCZ105

180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M 22U_0805_6.3V6M

2 1 2 1 2 1

@ PCZ123 @ PCZ112 PCZ106

180P_0402_50V8J 22U_0805_6.3V6M 22U_0805_6.3V6M

4
4

2 1 2 1 2 1

2
1
+
PCG114 PCG109 PCG107 PCG101
330U_D2_2V_Y 0.22U_0402_16V7K 10U_0603_6.3V6M 22U_0805_6.3V6M

2 1 2 1 2 1

2
1
+
PCG115 PCG110 PCG108 PCG102
330U_D2_2V_Y 0.22U_0402_16V7K 22U_0805_6.3V6M 22U_0805_6.3V6M

2 1 2 1 2 1
+APU_CORE_NB
+APU_CORE_NB

PCG111 RF@ PCG116 PCG103

180P_0402_50V8J 68P_0402_50V8J 22U_0805_6.3V6M

2 1 2 1 2 1
+APU_CORE_NB

PCG112 RF@ PCG117 PCG104

Issued Date
180P_0402_50V8J 68P_0402_50V8J 22U_0805_6.3V6M

2 1 2 1 2 1
Local

Security Classification
PCG113 RF@ PCG118 PCG105
180P_0402_50V8J 68P_0402_50V8J 22U_0805_6.3V6M

3
3

2 1 2 1

RF@ PCG119 PCG106

68P_0402_50V8J 22U_0805_6.3V6M

2012/11/07
APU_CORE

APU_CORE_NB
2
2

Compal Secret Data

Deciphered Date
7
10

2
2

330uF/9m 22uF/0805

2
2

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
0.22uF/0402

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
A3
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Size
Title

Date:
1
10uF/0603

Document Number
4019NK
0.01uF/0402

Monday, October 21, 2013

3
2

1
1

Sheet
180pF/0402

47
SCHEMATIC, MB A9851

of
Compal Electronics, Inc.

47
Rev
A
A
B
C
D