Frequency and Period Measurement: Transmitter
Frequency and Period Measurement: Transmitter
ω vt
transmitter l= 2
receiver
t
Frequency Counter Display
Memory
Strobe
Input
Signal Decade
Input counter
Processor
Reset
Gate
Time base
Input N
f =
t
Gate t
Output N pulses
Time Base
Time base
Crystal signal
Frequency
Oscillator
Divider
Circuit (OSC)
•Non-compensated OSC
•Temp. compensated OSC
•Oven-type OSC
Quartz crystal
High Q ~ 10000
ABCD
Logic Diagram of a time “1110” Store
base for a frequency counter
14
Input Signal Processing
Output
(Digital)
Comparator
Input
(Analog)
Amplifier
Vo
Vref
Vo
R2 R3 Vref
V(1)
VTH
R1 VTL
+
Vo V(0)
Vin Vin output
VTL VTH
Period Measurement
1 µs 1 µs
X pulses Y pulses
counted counted
T PW
Digital measurement of time period
Digital measurement of pulse width
T = (X pulses)(1 µs)
PW = Y µs
= X µs
Period Measurement (between pulses)
start
Input Signal S Gate Count
Signal A Proccessor
Counter
Q
stop
Input Signal
CLK Core system
Signal B Proccessor
R S R Q
1 MHz 1 kHz 0 0 Not use
Control circuit 0 1 1
100 kHz 10 kHz 1 0 0
1 1 No change
A (start)
B (stop)
Gate t
CLK
Count
Period Measurement (pulse duration)
Vref
A C
-
start + S S R Q
stop 0 0 No change
0 1 0
Vref D 1 0 1
- B Gate 1 1 Not use
Amp R Q
+
Comparator
start input
stop Control Gate
circuit Counter
A
B
C CLK
D
Period Measurement (pulse period)
V(1)
SET
D
J Q Gate
+
A B
-
Input C K CLR
Q
High-pass
filter Comparator
V(1) = 5 V
A
V(0) = 0 V
+2.5 V
B -2.5 V
V(1) = 5 V
C V(0) = 0 V
V(1) = 5 V
D
V(0) = 0 V
Measurement Error
1) Gating error (± 1 count)
Frequency measurement
5 pulses If fin = 10 Hz, Gate time = 1 s
Display count: 10±1 counts
6 pulses If fin = 1000 Hz, Gate time = 1 s
Display count: 1000±1 counts
Local
Frequency
Source
Adjustment Time
10 20 30 40 50
(weeks)
Ex A frequency counter with an accuracy of ± 1 LSD ± (1×10-6) is employed to measure
frequencies of 100 Hz, 1 MHz, and 100 MHz. Calculate the percentage measurement
error in each case.
At f = 100 Hz
error = ± (1 count ± 100 Hz × 10-6)
= ± (1 count ± 1 × 10-4 count)
≈ ± 1 count
1
% error = ± × 100%
100 Hz
= ± 1%
At f = 1000 Hz
error = ± (1 count ± 1 MHz × 10-6)
= ± (1 count ± 1 count)
= ± 2 count
2
% error = ± × 100%
1 MHz
= ± 2 × 10-4 %
At f = 100 MHz
error = ± (1 count ± 100 MHz × 10-6)
= ± (1 count ± 100 count)
= ± 101 count
101
% error = ± × 100%
100 MHz
= ± 1.01 × 10-4 %
Time base
error
Low frequency
error
Low frequency ± 1 pulse
High frequency
High frequency
error
± X pulse
Measurement Error
3) Trigger Level Error (Noise)
-Use large signal amplitudes and fast rise time
Trigger Trigger
level level
∆T Noisy signal Cleaned signal
UTP
LTP
UTP
LTP
PW PW
Measured PW Measured PW
Frequency mode
Range: DC to 50 MHz
Gate time: Manual 1 ms to 100 s in decade step
Automatic up 1 s gate time
Period mode
Range: 1 µs to 1 s unit in µs
Duration mode
Range: 100 ns to 104 s
Inputs: 2 channels for start signal and 1 channel
for stop signal
Extending the frequency range of a counter
Prescaler (upto 1.5 GHz)
1-10
MHz 10 MHz
10 - 100
MHz ÷10 Frequency
Counter
Heterodyne Technique
frequency Input
selector Signal (f2)
Counter
100 MHz Harmonic Tuned Low Pass
Amp.
Generator Cavity Filter
f1 ± f2 f1 - f2
100 MHz – 5GHz (f1)
Homodyne and Heterodyne technique
sin2π f1 t ½ {cos [2π( f2- f1 )]t +
cos [2π( f2+ f1 )]t}
sin2π f2 t
If f1 = f2; Homodyne
1
1
0.8
Time
0.5
0.6
-0.5 0.2
-1 0.5 1 1.5 2
Amplitude
If f1 ≠ f2; Heterodyne
Time
0.75
0.5
0.5
domain 0.25
-0.5 -0.5
-0.75
-1
Amplitude
Amplitude
Frequency
domain
f f
0 f1 f2 0 f2 - f1 f1 + f2
Automatic Heterodyne Unit
Level
3.0 GHz
Detector
X5
Control
3.5 GHz logic
Heterodyne Technique
Q Q : Time-base Divisor
Gate time, t = fc : Time-base Clk freq.
fc
N : Harmonic number
Input freq., fin = f in′ ± Nf c
Q Q
Displayed freq. = fin = f in′ ± NQ = f in′ t ± NQ
fc fc
Accuracy ∝ t; (NQ is constant)
Computing Counter
Input Input Gate
Signal A
Processing Counter
Count in A
Input freq. =
B Count in B
Counter
Precision Time
Computer Count in A
Clock Base
Input time =
Clk freq.
Period/
Frequency
Display