Design of RISC Processor Using VHDL and

Cadence
Saeid Moslehpour#1, Chandrasekhar Puliroju#2, Akram Abu-aisheh#3
#1,#2#3
Department of Electrical and Computer Engineering, University of Hartford, West Hartford, CT
#1
[email protected]
#2
[email protected]
#[email protected]


programs. It is also important to show that a VHDL model can
Abstract— The project deals about development of a basic be represented in a working PSpice schematic. Each part of a
RISC processor. The processor is designed with basic processor, whether it be an Arithmetic Logic Unit or a simple
architecture consisting of internal modules like clock generator, Program Counter- has a specific set of input and output logic
memory, program counter, instruction register, accumulator,
that can be emulated from PSpice. If the logic is already
arithmetic and logic unit and decoder. This processor is mainly
used for simple general purpose like arithmetic operations and known to the user, then the user does not have to build the part
which can be further developed for general purpose processor by using each individual logic gate. Instead, a circuit designer can
increasing the size of the instruction register. The processor is create a PSpice part that gives the desired logical outputs.
designed in VHDL by using Xilinx 8.1i version. The present Most importantly, this study can help bridge a gap between
project also serves as an application of the knowledge gained those who simulate with VHDL and those who use PSpice.
from past studies of the PSpice program. The study will show
how PSpice can be used to simplify massive complex circuits
designed in VHDL Synthesis. The purpose of the project is to III. METHODOLOGY
explore the designed RISC model piece by piece, examine and The following VHDL synthesis model provided is an
understand the Input/ Output pins, and to show how the VHDL attempt toward a RISC processor. First, a data path module of
synthesis code can be converted to a simplified PSpice model. The the processor will be shown which clearly shows how the
project will also serve as a collection of various research
materials about the pieces of the circuit.
individual modules are going to send the data from one
module to the other and then a screenshot will be shown of the
top-module view to show each piece of the processor from an
I. INTRODUCTION
outside perspective (with view of all modules)
The present project serves as an application of the
knowledge gained from past studies of the PSpice program.
The study will show how PSpice can be used to simplify
massive complex circuits. In other words, the study will
involve the breakdown of a complex circuit designed by a
graduate student at the University of Hartford. The circuit is a
VHDL Synthesis Model of an 8-bit processor. The purpose of
the project is to explore the designed processor model piece by
piece, examine and understand the Input/ Output pins, and to
show how the VHDL synthesis code can be converted to a
simplified PSpice model. The project will also serve as a
collection of various research materials about the pieces of the
circuit. Background information will be given to give the
reader a basic understanding of the parts to support the further
exploration in the project methods. This report is useful for
students who would like to know more about the PSpice
program and how it is useful for many educational purposes.

II.SIGNIFICANCE OF THE PROJECT

The study of VHDL and PSpice is important because
technology students are using computer software to design and
analyze circuits. A better understanding of computers and
computer languages can be gained when exploring these
Figure 1 Data path module of the processor
 During the first case the opcode is given to the ALU and
decoder for decoding and a series of micro operation are
generated. The data operand is loaded on to the data bus and
transferred to the ALU for its respective micro operations as
specified by its opcode. In the second case the address of the
data operand is loaded onto the address bus (As the fetch
signal is low and the multiplexer loads the IR’s address
contents onto the address lines) and a memory read cycle is
initiated. Here the memory location in the main memory
specified by the address lines is read and the data is transferred
onto the data bus and thus given the ALU to undergo the
operations specified by its opcode.
The results of the ALU are stored in the accumulator. Data
operations may be combined with the memory contents and
the accumulator and the result is transferred back to the
accumulator. The function of the NOR gate is that when ever
all inputs are low the output is high and at all other times
remains low. It is attached to tri-state buffer. When the tri-
state buffer is enabled the data from ALU is fed to the
memory thus allowing the data to be stored into the memory.
When disabled the data is given to all and cut off from being
written onto the data bus. Whenever there results a zero in the
ALU a zero flag is set.

A. CLOCK GENERATOR
Figure 2 Screenshot of VHDL synthesis top module

If one is familiar with PSpice, it would not be hard to

recognize the style of the schematic. However this is not a
PSpice model, yet only a graphical representation of the
VHDL synthesis. It may not be clear in the above screen shot,
however the complete processor contains nine separate
modules. These modules include: Program Counter (PC),
Clock Generator, Instruction Register, ALU, Accumulator,
Decoder, IO Buffer, Multiplexer, and Memory. All of these Figure 3 Clock generator
pieces with the appropriate busses form together to create a
processor capable of storing, loading, and performing Clock generator generates clock, clock2, fetch signals. For
arithmetic and logical operations. This processor only contains every negative edge of clock, clock2 is generated and for
one accumulator which means that the two operands in a every positive edge of clock2, fetch signal is generated.
mathematical operation will not be loaded simultaneously. Clock2 is generated from clock and fetch is generated from
The accumulator acts as a simple buffer to hold a value so that clock2. They are used as the inputs to the decoder which
the next operand can be loaded. controls the operation of the processor. It generated reset pulse
To read an instruction, the contents of Program counter are which must be active low. The reset should allow the rest of
transferred to the address lines. This is done when the fetch the signals to go high on falling edge of clock2 when fetch is
signal is high and the address multiplexers chooses the low.
contents of the Program counter to be loaded on to the address
bus. As soon as the contents of the program counter are
loaded onto the address bus a memory read cycle is initiated B. INSTRUCTION REGISTER
and the instruction is read from the location pointed out by the
address lines and the micro instruction code is placed onto the
data bus. The program counter is incremented to point to the
next micro instruction in the memory location of the control
memory. The data bus transfers the micro instruction to the
Instruction Register. The instruction register has two fields, in
the different formats namely,
1. Opcode, data operand.
2. Opcode, Address of data operand.
 The memory should be 8-bit wide, 32-bit location deep.
Each instruction retrieved from the memory will have its
upper 3 bits as the opcode and lower 5-bits as the address.
Memory has mem_rd, mem_wr and address as inputs and data
as output. If mem_rd is high, it reads the data of memory to
the data register, if mem_wr is high, data is written to the
memory.

Figure 4 Instruction Register

E. ARITHMETIC AND LOGIC UNIT

In instruction register instructions are fetched from and stored.

It performs the action always at positive edge of clock. It has 3
instructions clock, reset, load_ir, and data as inputs and
opsode and address as outputs. If load_ir and reset both are
high, data in instruction register splits into upper 3 bits as
opcode and lower 5 bits as address.

C. ACCUMULATOR

Figure 7 Arithmetic and logic unit

Arithmetic and logic unit (ALU) is a multiplexer, performs

standard arithmetic and logic operations. The operations
Figure 5 Accumulator performed are listed below. ALU operations should be
synchronized to the negative edge of the clock. At each
Accumulator is a register, the result from Arithmetic and negative edge, the ALU should perform the appropriate
logic unit is stored back in the accumulator. It has clock, reset, operation on the incoming data and accumulator, placing the
load_acc and alu_out as inputs and accumulator as output. It is result in alu_out. The 3-bit opcode decodes as follows:
activated only at the positive edge of clock. If load_acc and 000: Pass Accumulator.
reset both are high, data in the accumulator is loaded into 001: Pass Accumulator.
alu_out. 010: Add (data + Accumulator).
011: And (data & Accumulator).
100: Xor (data ^ Accumulator).
D. MEMORY
101: Pass data.
110: Pass Accumulator.
111: Pass Accumulator.

F. MULTIPLEXER

Figure 6 Memory
 A decoder provides the proper sequencing of the system. It
has clock, fetch, clock2, reset, zero instructions and opcode as
inputs and load_ir, load_pc, mem_rd, mem_wr, load_acc as
outputs. The zero bit should be set whenever the accumulator
is zero.
The decoder issues a series of control and timing signals.
Depending on the opcode it decodes after it receives from the
instruction register. The decoder is a simple finite state
machine which consists of states. During the first state it
generates control signal for address setup. The address bus is
setup and the contents of the program counter are transferred
on to the address bus. The instruction fetch is generated in the
Figure 8 Multiplexer second state and the instruction is read from the memory with
the memory read signal and transferred on to the data bus.
The address multiplexer decides one output out of the two When the third state starts the instruction is loaded with the
given inputs. When the fetch signal is high, the address of the ld_ir being high into the instruction register. The opcode is
program counter is transferred on to the address buses and sent to the decoder and the appropriate control and timing
hence instruction is fetched. But if low, the operand address signals are initiated for the execution cycle. This is done in the
specified in the address field of the instruction register is next state in which it remains idle during the decoding of the
transferred onto the address bus and consequently fetched. opcode.
The fetch cycle ends and the program counter is
G. PROGRAM COUNTER incremented with the inc_pc signal. The execution cycle starts
and the address is again setup in the fifth state, but this time
instruction registers address field is loaded onto the address
bus. The operand is fetched in the sixth state with the mem_rd
signal being high and the data id is transferred onto the data
bus and given to the ALU for processing. In the seventh state
the ALU is given its alu_clock amd in synchronization with
the falling edge of the clock the respective operation is
performed. In the last state the decoder issues an ld_acc signal
to store the result into the accumulator.

IV. CONVERTING VHDL TO PSPICE

Figure 9 Program counter

It is a 5-bit general purpose register. The program counter This section will cover how to successfully convert a
points to the next micro instruction to be fetched from the VHDL synthesis model to a working PSpice part. First, the
memory. In case of an unconditional branch the said address is user would have to extract the program to C:\Program Files.
loaded into the program counter for fetching of that This part is important because the program will not work
instruction. Normally, after the fetch cycle is completed the unless it is extracted to the specified directory. It will create a
program counter is incremented and now thus points to the directory in C:\Program Files called VHDL2PSpice. The
next instruction. contents of the folder will show all the necessary files.
The folders created are Capture Symbols, DelphiExamples,
Library, and Source. These folders are necessary for the
H. DECODER program to save the appropriate Capture Model symbols and
library files.
- Now, the user should open the Lattice Synplify program.
Once in the program, click FILE -> NEW -> and start a new
project.
The window shown above should pop-up onto the screen.
- Click Project File and give the project a name.
- NEXT, a project interface screen will show up. Right click
on the project and click add source file.

The option should be in the pop-up menu that appears when

clicking on the project.[8]
Once the VHDL file is added, the user should now be able
Figure 10 Decoder to view the file in the source window by clicking on the source
folder and then the file.
 Export it to the VHDL2PSpice library called “Capture
A window with line numbers shown above should be shown Symbols”. It is ok to copy the files here because the
on the screen. However before synthesis, certain conditions Libpointer.lib file will tell PSpice where these files are saved.
need to be set up by the user in order for the synthesis to
properly work. When the Capture program is opened, the user should be
- Right click on the icon in the project window that appears able to place the symbol onto the schematic. The part should
as a ‘blank screen’. It should be the last item in the project work with PSpice simulation as well.
window. Click on Implementation options. A window should
appear with several tabs and options. The picture above shows the VHDL device successfully
working in PSpice.
Make sure the Technology option is set to LATTICE
MACH, and the part option is set to MACH111. Click the box V. APPLYING THE CONVERSION STEPS TO THE PROCESSOR
in the Device Mapping Options window that says “Disable I/O MODEL
insertion.” The next objective will be to successfully synthesize and
NEXT, go to the implementation tab and click the Write convert the code of each VHDL model to a PSpice library and
Mapped VHDL Net list check box. object file.
The following files will be converted in this project:
After this is done, the program is ready to synthesize.
Click the RUN button back on the project menu. On the right These files are named pul (which I used the first three
window, several files will be generated. letters of the creators name) followed by a word that
represents the part. This makes it easier to follow.
We are interested in the gate level VHDL file. This is the
file with the extension VHM on the right list. Example
Double click on the VHM file to view its contents. Once
there, the file should be saved. Click File-> SAVE AS and The first file we will synthesize will be the ALU file. The
save the file in C:\ProgramFiles\Vhdl2PSpice\Source. file is called pulalu.vhd. This file can be saved anywhere on
- Once the file is saved, the user can now exit the Synplify the computer, as the VHDL2PSpice program will not need
program as it is no longer needed for the conversion. this. The file that the VHDL2PSpice will use will be the
NOW, in C:\ProgramFiles\Vhdl2PSpice directory, run the synthesized version.
Vhdl2PSpice.exe utility.
A window will pop-up on screen with a button labeled By following the steps, the first file is synthesized. As can
“Convert Vhdl 2 PSpice” be seen on the right window, the file PULALU.VHM has been
Enter the name of the VHDL file that was saved into the created. This is the file that will be saved to C:\program
SOURCE directory. There is no need to type the extension, files\vhdl2PSpice. Now the synthesis program is finished and
just the name of the file. it is time to run the VHDL2PSpice program to create a library
After OK is clicked, the user should enter the name of the file.
top level entity (in this example the device is called
COUNTER). Click OK again and almost immediately, the This window shows that we are ready to enter our filename.
conversion will take place. The user should see a success After entering the name of the part, a message box will appear
window appear. and tell the user that the conversion was successful. Note: The
NOW, the program has created output files that can be used Entity name must match the entity title located in the VHDL
in PSpice. Go to the LIBRARY folder in VHDL2PSpice to file, it cannot be a made up label. It should be remembered
view the converted files. The file that the user should look for that the library file generated will say copy_filename_lib. In
will be the same name, however with the word “copy” starting this case, the filename in the LIBRARY folder is named
off the filename. The extension of the file is .LIB. “copypulalu.lib”. Now, the file is ready to be opened with
There is also a file called LIBPOINTER.LIB, which is a PSpice Model Editor. This program will allow the library file
library file that tells PSpice where to look for the created parts. to be exported to the Capture Library. Once in the model
NEXT-> The user should open the PSpice Model Editor editor, the copypulalu.lib file should contain one part named
program and open the created library file that was converted. “alu”. When exporting to Capture Part Library, the .olb file
It should still be found in the VHDL2PSpice library directory. should be exported to the Capture Symbols folder that is a part
Click on the part name to see the structural representation of of the VHDL2PSpice folder. When placing a part, the library
the VHDL code that was converted. will be located in the same capturesymbols directory. This is
the .olb file and not the .lib file.
The next part is very important. Click FILE and click
Export to Capture Part Library. The library file is already
created, however the program will not know how to display A. CONVERTED ALU
the part unless it is properly exported.
 U 1 These parts and their descriptions are shown as follows:
1 1 6
2 A C LK A C O U T 4 1 7
3 M D A T7 A C O U T 3 1 8 B. CONVERTED CLOCK GENERATOR:
4 M D A T6 A C O U T 2 1 9
5 M D A T5 A C O U T 1 2 0
6 M D A T4 A C O U T 0 2 1 U 2
7 M D A T3 A L O U T 7 2 2 1 4
8 M D A T2 A L O U T 6 2 3 2 R STR E Q C LK2 5
9 M D A T1 A L O U T 5 2 4 C LK FC H
M D A T0 A L O U T 4 3 6
1 0
O P C D 2 A L O U T 3
2 5 C LK1 R ST
1 1 2 6
1 2 O P C D 1 A L O U T 2 2 7
O P C D 0 A L O U T 1 C LKG EN
1 3 2 8
1 4 A C O U T 7A L O U T 0 2 9 Figure 13 Clock Generator, [10]
1 5 A C O U T 6 Z R
A C O U T 5
RSTREQ: (input)Reset pin. Clears clock on high signal.
A LU Inactive on low signal
CLK, CLK1, CLK2: Clock generators necessary for
Figure 11 Converted ALU, [10] processing cycles.
RST: (output) Sends high signal for other components to be
This is the converted ALU. The device, just like the VHDL reset
model has all of the input/output pins. The only difference is FCH: (output) used as interface with program counter.
the orientation of the 8-bit input/outputs. This circuit can be C. CONVERTED PROGRAM COUNTER:
simplified further by placing it into a hierarchal block and U3
sending a bus line that covers all 8 bits. This device has an
1 8
ACLK pin, which means that the opcode is read and the ALU 2 P C LK A D IR 0 9
performs at the RISING edge of the clock. 3 R S T A D P C 4 1 0
4 LD P C A D P C 3 1 1
PINS WHEN WHEN DE- 5 A D IR 4 A D P C 2 1 2
ASSERTED ASSERTED 6 A D IR 3 A D P C 1 1 3
ACLK Clock trigger Clock trigger 7 A D IR 2 A D P C 0
MDAT 7- 8 bit data code 8 bit data code A D IR 1
0 ( 1 or 0 ( 1 or 0 PRGCNT
depends on depends on Figure 14 Program Counter, [10]
data word) data word)
OPCD 2- 3-bit opcode (same) PCLK: Clock signal is sent to this input pin to allow the PC to
0 that determines count upward.
the operation RST: This line resets the program counter with a high signal
the ALU must LDPC: When set to high signal, the program counter sets the
perform PC with the value at ADPC 4:0
ADIR 4:0: The value of PC that is passed to the instruction
ACOUT 8-bit data register.
7-0 coming from ADPC4:0: The value that is returned to the PC.
accumulator to
serve as an
operand. D. CONVERTED INSTRUCTION REGISTER
ALOUT The 8-bit result
output from the
ALU

ZR (zero ALU result is ALU result is

bit) 00000000 anything other
than ZERO

Figure 12 ALU assertion chart, [10]

The remaining parts of the processor will be implemented

using the same steps as the ALU since it is known that the
program works successfully.
 U4 U6
1 11 1 8
C LK M D A T0 2 C LK1 L D IR 9
2 12 C LK2 LD AC
3 RST A D IR 4 13 3 10
L D IR A D IR 3 4 FCH MRD 11
4 14 RST MW R
M D A T7 A D IR 2 5 12
5 15 6 OPCD2 LD PC 13
6 M D A T6 A D IR 1 16 OPCD1 PC LK
M D A T5 A D IR 0 7 14
7 17 OPCD0 AC LK
8 M D A T4 OPCD2 18
9 M D A T3 OPCD1 19
DECODER
M D A T2 OPCD0 Figure 17 Instruction Decoder, [10]
10
M D A T1
The decoder contains pins that enable the respective control
INSREG lines.

Figure 15 Instruction Register, [10]

G. CONVERTED IO BUFFER
CLK: The clock pin is necessary for the device works with a
rising clock edge. U 7
1 1 1
RST: On a rising clock edge, the Instruction register becomes 2 M R D AL O U T0 1 2
reset 3 F C H M D A T7 1 3
LDIR: Load Instruction Register. High signal allows the signal 4 C LK2 M D A T6 1 4
5 A LO U T7 M D A T5 1 5
from the PC to be input into ADIR4:0 A LO U T6 M D A T4
OPCD: This is the three bit operation code used for operations 6 1 6
7 A LO U T5 M D A T3 1 7
of the ALU. 8 A LO U T4 M D A T2 1 8
9 A LO U T3 M D A T1 1 9
10 A LO U T2 M D A T0
E. CONVERTED ACCUMULATOR A LO U T1

IO B U F F E R
U5
Figure 18 Input/ Output Buffer, [10]
1 11
2 C LK ALO U T0 12
3 RST ACO U T7 13 MRD: Memory Read, allows the data held in the buffer to be
4 LD AC ACO U T6 14 passed out of MDAT 7:0.
5 ALO U T7 ACO U T5 15 FCH: Allows the device to be written to with the 8-bit data
6 ALO U T6 ACO U T4 16 word of ALOUT 7:0
7 ALO U T5 ACO U T3 17 CLK2: Clock signal that runs the part (rising clock edge)
8 ALO U T4 ACO U T2 18
ALO U T3 ACO U T1 H. CONVERTED MULTIPLEXER
9 19
10 ALO U T2 ACO U T0
ALO U T1 U8
1 9
ACCUMULATOR 2 A D PC 4 A D IR 1 1 0
Figure 16 Accumulator, [10] 3 A D PC 3 A D IR 0 1 1
4 A D PC 2 F C H 1 2
CLK: clock pin runs the accumulator, since in theory the 5 A D PC 1 A D M EM 4 1 3
6 A D PC 0 A D M EM 3 1 4
accumulator is made up of latches.
7 A D IR 4 A D M EM 2 1 5
RST: Resets the accumulator to an ‘empty state’ A D IR 3 A D M EM 1
LDAC: When this pin is asserted the accumulator is loaded 8 1 6
A D IR 2 A D M EM 0
with the value that flows through ALOUT (input pins)
ALOUT: This 8-bit set of pins is the data passed from the MUX
ALU Figure 19 Multiplexer, [10]
ACOUT: This 8-bit set of output pins sends a value to the ADPC 4:0: PC address to be sent to memory and Instruction
ALU for operation. register.
F. CONVERTED DECODER
I. CONVERTED MEMORY
 U9
1 16
2 MRD ED AT6 17
3 MW R ED AT5 18
4 EW R ED AT4 19
5 RST ED AT3 20
6 MAD4 ED AT2 21
7 MAD3 ED AT1 22
8 MAD2 ED AT0 23
9 MAD1 MD AT7 24
10 MAD0 MD AT6 25
11 EAD4 MD AT5 26
12 EAD3 MD AT4 27
EAD2 MD AT3 Figure 22 Output I
13 28
14 EAD1 MD AT2 29
15 EAD0 MD AT1 30
E D A T7 MD AT0
MEMORY
Figure 20 Memory, [10]

J. MODULES INTEGRATED TOGETHER IN PSpice

M D [7 -0]

IR [4 -0 ] U 4
U 1 P [4-0 ] U 2 1 16 A C 4
1 8 1 4 U 11 M D 7 2 A C L K AC O U T 4 17 A C 3
2 P C LK A D IR 0 9 P 4 2 R S TR EQ C LK 2 5 A L[7 -0] 1 11 M D 6 3 M D A T7 AC O U T 3 18 A C 2
3 R ST A D PC 4 10 P 3 3 C LK F C H 6 2 C LK A LO U T0 12 A C 7 M D 5 4 M D A T6 AC O U T 2 19 A C 1
IR 4 4 LD P C A D P C 3 11 P 2 C LK 1 R S T 3 R ST A C O U T7 13 A C 6 M D 4 5 M D A T5 AC O U T 1 20 A C 0
IR 3 5 A D IR 4 A D P C 2 12 P 1 A L7 4 LD A C A C O U T6 14 A C 5 M D 3 6 M D A T4 AC O U T 0 21 A L7
IR 2 A D IR 3 A D P C 1 P 0 C LK G EN A L6 A LO U T7 A C O U T5 A C 4 M D 2 M D A T3 A L O U T 7 A L6
6 13 5 15 7 22
IR 1 7 A D IR 2 A D P C 0 A L5 6 A LO U T6 A C O U T4 16 A C 3 O C [2 -0 ] M D 1 8 M D A T2 A L O U T 6 23 A L5
A D IR 1 A L4 7 A LO U T5 A C O U T3 17 A C 2 M D 0 9 M D A T1 A L O U T 5 24 A L4
IR 0 A L3 8 A LO U T4 A C O U T2 18 A C 1 O C 2 10 M D A T0 A L O U T 4 25 A L3
P RO G R A M C O U N T E R A L2 9 A LO U T3 A C O U T1 19 A C 0 O C 1 11 O P C D 2 A L O U T 3 26 A L2
A L1 10 A LO U T2 A C O U T0 O C 0 12 O P C D 1 A L O U T 2 27 A L1
A LO U T1 13 O P C D 0 A L O U T 1 28 A L0
A C [7 -0] 14 A C O U T7 A L O U T 0 29 O U T
A L0 A C C U M U LATO R A C O U T6 Z R
15
A C O U T5

AL U
O F F TIM E = 5u S D S T M 1 A C 5
O N T IM E = 5 u S A C 6
C LK
D E LA Y = 0 A C 7
S TA R T V AL = 0
O P P VAL = 1

D S TM 4
S 1 R ST
0s 0

Figure 22 Output II
R E P E A T 1 T IM E S
+ 4 u s IN C R B Y 1
E N D R E PE AT

RESULTS FROM PSpice

U 10
1 1 6 E D A T6
A M [4 -0] 2 M R D E D A T6 1 7 E D A T5
D S TM 5 M W R E D A T5
S 1 E WR 3 1 8 E D A T4
4 E W R E D A T4 1 9 E D A T3
0s 1 A M 4 5 R ST E D A T3 2 0 E D A T2
R E P E AT 1 T IM E S A M 3 6 M AD 4 E D A T2 2 1 E D A T1
+ 1 0 u s IN C R B Y 1 A M 2 7 M AD 3 E D A T1 2 2 E D A T0
E N D R E P EA T A M 1 8 M AD 2 E D A T0 2 3 M D 7
A M 0 9 M AD 1 M D A T7 2 4 M D 6
E AD 4 10 M AD 0 M D A T6 2 5 M D 5
E AD 3 11 E AD 4 M D A T5 2 6 M D 4
E AD 2 12 E AD 3 M D A T4 2 7 M D 3
E AD 1 13 E AD 2 M D A T3 2 8 M D 2
E AD 0 14 E AD 1 M D A T2 2 9 M D 1
15 E AD 0 M D A T1 3 0 M D 0
E D A T7 M D A T0

M EM O R Y

E D A T7

D S TM 2 E AD [4 - 0 ]
S 8
0 s 000 000 00
R E P E A T 2 4 T IM E S
+ 2 u s IN C R b y 0 0 0 0 0 0 0 1
E N D R EP EA T

D STM 3 E D AT[7 - 0 ]
S 8
0s 0000 000 0
R E P E A T 2 4 T IM E S
+ 2u s IN C R by 0 00 00 00 1
E N D R E PE AT
U 6
1 1 1
2 M R D A LO U T0 1 2 M D 7
3 F C H M D A T7 1 3 M D 6
A L7 4 C LK 2 M D A T6 1 4 M D 5
A L6 5 A LO U T7 M D A T5 1 5 M D 4
A L5 6 A LO U T6 M D A T4 1 6 M D 3
A L4 7 A LO U T5 M D A T3 1 7 M D 2
A L3 8 A LO U T4 M D A T2 1 8 M D 1
A L2 9 A LO U T3 M D A T1 1 9 M D 0
A L1 10 A LO U T2 M D A T0
A LO U T1

A L0 IO B U F F ER

U 7
1 11
2 C LK M D A T0 12 IR 4
3 R S T A D IR 4 13 IR 3
M D 7 4 LD IR A D IR 3 14 IR 2
M D 6 5 M D AT7 A D IR 2 15 IR 1
M D 5 6 M D AT6 A D IR 1 16 IR 0
M D 4 7 M D AT5 A D IR 0 17 O C 2
M D 3 8 M D AT4 O P C D 2 18 O C 1
M D 2 9 M D AT3 O P C D 1 19 O C 0
M D 1 10 M D AT2 O P C D 0
M D AT1
M D 0 IN S R E G

U 8
1 8
2 C LK 1 LD IR 9
3 C LK 2 LD A C 1 0
4 F C H M R D 1 1
O C 2 5 R S T M W R 1 2
O C 1 6 O P C D 2 LD P C 1 3
O C 0 7 O P C D 1 PC L K 1 4
O P C D 0 AC L K

D EC O D E R

U 9
P4 1 9 IR 1
P3 2 A D PC 4 A D IR 1 1 0 IR 0
P2 3 A D PC 3 A D IR 0 1 1
P1 4 A D PC 2 F C H 1 2 AM 4
P0 5 A D PC 1 A D M EM 4 1 3 AM 3
6 A D PC 0 A D M EM 3 1 4 AM 2
7 A D IR 4 A D M EM 2 1 5 AM 1
8 A D IR 3 A D M EM 1 1 6 AM 0
A D IR 2 A D M EM 0
IR 2
IR 3 M U X
IR 4

Figure 23 Output III

Figure 21 Modules integrated in PSpice

VI. RESULTS

RESULTS FROM VHDL:

 with the VHDL program. VHDL parts can successfully be
converted to PSpice and can be displayed and simulated in a
schematic. The fully functional code helped to complete the
processor and it has been assembled and simulated. It is
possible to connect all of the modules just as the VHDL top
module. The knowledge has been gained on how to convert
the VHDL modules to PSpice. However the VHDL
programmer must be sure that the code is fully functional.
There is no software known as of yet that will convert PSpice
to VHDL.

REFERENCES
[1] mackido.com – What is Risc. Retrieved November 2006
http://www.mackido.com/Hardware/WhatIsRISC.html
Figure 21 Output IV [2] Risc Architecture. Retrieved: November 2006
http://www.geocities.com/SiliconValley/Chip/5014/arch.html
VII. CONCLUSION [3]aallison.com – Brief History of RISC. Retrieved:
November 2006
The first problem to note was that halfway through the
http://www.aallison.com/history.htm
components; the synthesis program gave “warnings” yet still
[4] VHDL and Verilog. Retrieved November 2006
synthesized the files. These warnings only existed with the IO
http://course.wilkes.edu/Engineer1/
BUFFER, MULTIPLEXER, and MEMORY. The program
[5] IEEE.ORG – Vhdl Synthesis model. Retrieved November
stated that there were illegal statements/declarations.
2006
However, the parts of the project that were successfully
http://www.ewh.ieee.org/soc/es/Nov1997/01/INDEX.HTM
synthesized proved to work with the CAPTURE program just
[6] RCore54 Processor. Retrieved: November 2006
fine. Another problem lies in the program’s disregard to the
http://www.ht-lab.com/freecores/risc/risc.html
synthesis errors. When a part is created from the synthesis file,
[7] PSpice (Copyright © 1985 - 2004 Cadence Design
the running part will crash the software. This error was not
Systems, Inc)
fixed, as it wasn’t a PSpice software error, or an error with the
-PSpice Online Manual Retrieved: September 2006 (As
VHDL2PSpice program. The problem existed in the VHDL
shown in Appendices)
errors. It is not known whether the errors are small or large, or
(Copyright © 1985 - 2004 Cadence Design Systems, Inc)
whether or not the parts are complete. However, the project
[8] Sreeram Rajagopalan – Mixed Level and Mixed Signal
goal has still been met. VHDL parts can successfully be
Simulation using PSpice A/D and VHDL
converted to PSpice and can be displayed and simulated in a
VHDL2PSpice Utility.
schematic. Given fully functional code, a complete processor
VHDLPSpice_CDNLive_Sreeram.pdf
would have been assembled and simulated. It is possible to
[9] Chandrasekhar Puliroju –VHDL synthesis models used in
connect all of the modules just as the VHDL top module,
this study.
however without working code; there is no reason to attempt
[10] Christopher L Spivey , “Creating PSpice Parts with
to simulate the modules. Also, the RISC design provided
VHDL Models.” EL 482: Senior Project Report, Fall 2006.
contained no set of pre-programmed code or language. The
model seemed to only be an empty shell of what a RISC
processor looks like from an outside perspective. The project
can be deemed a failure in terms of building a fully functional
processor, however the bridge between PSpice and VHDL has
been met. The knowledge has been gained on how to convert
the VHDL modules to PSpice. However the VHDL
programmer must be sure that the code is fully functional.
There is no software known as of yet that will convert PSpice
to VHDL.

The first problem to note was that halfway through the

components; the synthesis program gave “warnings” yet still
synthesized the files. These warnings only existed with the IO
BUFFER, MULTIPLEXER, and MEMORY. The program
stated that there were illegal statements/declarations.
However, the parts of the project that were successfully
synthesized proved to work with the CAPTURE program just
fine. Another problem lies in the program’s disregard to the
synthesis errors. When a part is created from the synthesis file,
the running part will crash the software. This error was fixed
