Microcontroller Based Design
Dr Mohsin Tiwana
Interrupts
2
Basics
Single Microcontroller can serve many devices
There are 2 ways of doing it
1. Polling
2. Interrupt
3
Polling
Microcontroller continuously monitors the status of a
given device
When condition is met, it performs service and then
moves on to monitor the next device
JNB TF0,$
4
Interrupt
An event that informs microcontroller that a device needs
service / attention
Whenever a device needs attention, it sends an interrupt
to microcontroller
5
Polling Vs Interrupt
A phone with a ringer and a phone without a ringer
Polling (Phone without a ringer): means that you pick up
the phone regularly to see if someone is on the other end
Interrupt (Phone with a ringer): means you can do what
you want and the phone will ring to interrupt you when
someone is on the other end
6
Polling Vs Interrupt
Polling
Microcontroller can serve many devices
Time wasted in waiting for certain conditions
While waiting, no other task can be performed
Interrupt
Microcontroller can serve many devices
Time not wasted in waiting for certain conditions
Microcontroller can perform others tasks and anytime a device
can interrupt it
7
Interrupts in 8051
6 Interrupts
1. Reset
2. Timer 0 overflow
3. Timer 1 overflow
4. Reception / Transmission of serial character
5. External Event 0
6. External Event 1
8
Interrupt SFRs
9
Interrupt SFRs
IE
Interrupt Enable
Bit Addressable
IP
Interrupt Priority
Bit addressable
10
Interrupt SFRs
Interrupt Enable – IE
11
Interrupt SFRs
Interrupt Enable – IE
Set EA (Global Interrupt Enable - Bit 7) high to enable any
interrupt
Set the bit of required interrupt in IE to enable it
12
Interrupt SFRs
Interrupt Priority – IP
2 Levels of interrupt in 8051
0 (Low priority)
1 (High priority)
Priorities of 5 interrupts can be set
All interrupts except Reset
13
Interrupt SFRs
Interrupt Priority – IP
14
Interrupt SFRs
Interrupt Priority – IP
Nothing can interrupt a high priority interrupt – not even
another high priority interrupt
A high priority interrupt may interrupt low priority
interrupt
A low priority interrupt may only occur if no other
interrupt is already being executed
If 2 interrupts occur at same time, interrupt of higher
priority will execute first
If both interrupts have same priority, Polling Sequence
(Next Slide) will determine which interrupt will be
executed first
15
Polling Sequence
External 0 interrupt
Timer 0 Interrupt
External 1 Interrupt
Timer 1 Interrupt
Serial Interrupt
16
IVT
Interrupt Vector Table
For every interrupt, there is a fixed location in memory
that holds address of its ISR
ISR is Interrupt Service Routine
When an interrupt is generated, its ISR is automatically
executed
The group of memory locations that hold the addresses of
ISRs is called Interrupt Vector Table (IVT)
IVT is located in ROM
17
IVT of 8051
18
Interrupt Flags
Timer Control – TCON SFR
19
Interrupt Flags
Timer Control – TCON SFR
20
Interrupt Flags
Serial Control – SCON SFR
21
Interrupt Flags - Summary
22
Clearing Interrupt Flags
Interrupt flags cleared automatically, except
Serial Interrupt.
Serial Interrupt flags are to be manually reset
23
What Happens when an Interrupt Occurs?
Execution of current instruction is completed
PC is saved on stack, low byte first
Interrupts of same and lower priorities are blocked
It jumps to memory location called IVT that keeps
addresses of ISRs
PC is loaded with address of ISR
ISR is executed until “RETI” is reached
24
What happens when an interrupt ends?
RETI ends the execution of ISR
RETI clears the interrupt flags
Except Serial
Serial Flags are to be manually reset
2 Bytes from STACK are Popped and loaded in PC
Program resumes from where it left before interrupt
25
Important Consideration
Take care of registers
ISR may change value of useful registers and flags
A
B
PSW
Carry
Auxiliary Carry
May be saved using STACK
26
Short Interrupt Routine
ORG 00h
JMP MAIN
ORG 00Bh ; Timer 0 ISR
CPL P1.0
RETI
ORG 30h
MAIN:
.
.
END
27
Long Interrupt Routine
ORG 00h
JMP MAIN
ORG 00Bh ; Timer 0 ISR
JMP TOISR
ORG 30h
MAIN:
.
.
JMP MAIN
TOISR: .
.
RETI
END
28
Timer Interrupt
29
Timer Interrupt
Generate 10 Khz Square Wave using Timer 0 Interrupt
Using
Polling
Interrupt
30
Timer – Polling
Generate 10 Khz Square Wave using Timer 0 Without Interrupt
ORG 00h
MOV TMOD,#02h
MOV TH0,# – 50
MOV TL0, # –50
SETB TR0
AGAIN:
JNB TF0,$
CLR TF0
CPL P1^0
JMP AGAIN
END
31
Timer – Interrupt
Generate 10 Khz Square Wave using Timer 0 Interrupt
ORG 00h
JMP MAIN
ORG 00Bh ; Timer 0 ISR
CPL P1^0
RETI
ORG 30h
MAIN:
MOV TMOD,#02h
MOV TH0,# – 50
MOV TL0, # –50
SETB TR0
MOV IE, #82h
SJMP $
END
32
External Interrupts
33
External Interrupts
Two External Interrupts
INT0
INT1
Pins
P3.2
P3.3
Two activation levels
Level Triggered
Edge Triggered
IF IT0 or IT1 (in TCON) is set, it will make INT0 or INT1
Edge Triggered. Else they will be level triggered
Default mode is level trigger
34
External Interrupts
TCON SFR
35
External Interrupts
Level Triggered
Default mode
Interrupt Pins (P3.2 and P3.3) are normally High
LOW level signal triggers the interrupt
LOW level input must be removed before end of ISR,
otherwise interrupted will be generated again
36
External Interrupts
Edge Triggered
By making IT0 and IT1, external interrupts will be edge
triggered
External source must be high for at least 1 machine cycle, and
then Low for at least 1 machine cycle
For another interrupt to be recognized, pin must go back to a
logic high state and then brought back
During execution of ISR, external interrupt pin is ignored, no
matter how many times it makes High-to-Low transitions
37
