SECTION 3

ADDRESSING MODES
Addressing modes determine how the CPU accesses memory locations to be operat-
ed upon. This section discusses the various modes and how they are used.

3.1 Mode Summary

Addressing modes are an implicit part of CPU12 instructions. APPENDIX A IN-
STRUCTION REFERENCE shows the modes used by each instruction. All CPU12
addressing modes are shown in Table 3-1.

Table 3-1 M68HC12 Addressing Mode Summary

Addressing Mode Source Format Abbreviation Description
INST
Inherent (no externally supplied INH Operands (if any) are in CPU registers
operands)
INST # Operand is included in instruction stream
Immediate or IMM
INST # 8- or 16-bit size implied by context

Operand is the lower 8-bits of an address

Direct INST DIR
in the range $0000 – $00FF
Extended INST EXT Operand is a 16-bit address
INST
An 8-bit or 16-bit relative offset from the current
Relative or REL
pc is supplied in the instruction
INST
Indexed
INST , IDX 5-bit signed constant offset from x, y, sp, or pc
(5-bit offset)
Indexed
INST ,– IDX Auto pre-decrement x, y, or sp by 1 ~ 8
(pre-decrement)
Indexed
INST ,+ IDX Auto pre-increment x, y, or sp by 1 ~ 8
(pre-increment)
Indexed
INST , – IDX Auto post-decrement x, y, or sp by 1 ~ 8
(post-decrement)
Indexed
INST , + IDX Auto post-increment x, y, or sp by 1 ~ 8
(post-increment)
Indexed Indexed with 8-bit (A or B) or 16-bit (D)
INST , IDX
(accumulator offset) accumulator offset from x, y, sp, or pc
Indexed 9-bit signed constant offset from x, y, sp, or pc
INST , IDX1
(9-bit offset) (lower 8-bits of offset in one extension byte)
Indexed 16-bit constant offset from x, y, sp, or pc
INST , IDX2
(16-bit offset) (16-bit offset in two extension bytes)
Pointer to operand is found at...
Indexed-Indirect
INST [ , ] [IDX2] 16-bit constant offset from x, y, sp, or pc
(16-bit offset)
(16-bit offset in two extension bytes)
Indexed-Indirect
Pointer to operand is found at...
(D accumulator INST [D, ] [D,IDX]
x, y, sp, or pc plus the value in D
offset)

CPU12 ADDRESSING MODES MOTOROLA

REFERENCE MANUAL 3-1
 The CPU12 uses all M68HC11 modes as well as new forms of indexed addressing.
Differences between M68HC11 and M68HC12 indexed modes are described in 3.8 In-
dexed Addressing Modes. Instructions that use more than one mode are discussed
in 3.9 Instructions Using Multiple Modes.

3.2 Effective Address

Each addressing mode except inherent mode generates a 16-bit effective address
which is used during the memory reference portion of the instruction. Effective address
computations do not require extra execution cycles.

3.3 Inherent Addressing Mode

Instructions that use this addressing mode either have no operands or all operands
are in internal CPU registers. In either case, the CPU does not need to access any
memory locations to complete the instruction.

Examples:

3.4 Immediate Addressing Mode

Operands for immediate mode instructions are included in the instruction stream, and
are fetched into the instruction queue one 16-bit word at a time during normal program
fetch cycles. Since program data is read into the instruction queue several cycles be-
fore it is needed, when an immediate addressing mode operand is called for by an in-
struction, it is already present in the instruction queue.
The pound symbol (#) is used to indicate an immediate addressing mode operand.
One very common programming error is to accidentally omit the # symbol. This causes
the assembler to misinterpret the following expression as an address rather than ex-
plicitly provided data. For example LDAA #$55 means to load the immediate value $55
into the A accumulator, while LDAA $55 means to load the value from address $0055
into the A accumulator. Without the # symbol the instruction is erroneously interpreted
as a direct addressing mode instruction.
Examples:

These are common examples of 8-bit and 16-bit immediate addressing mode. The
size of the immediate operand is implied by the instruction context. In the third exam-
ple, the instruction implies a 16-bit immediate value but only an 8-bit value is supplied.
In this case the assembler will generate the 16-bit value $0067 because the CPU ex-
pects a 16-bit value in the instruction stream.

MOTOROLA ADDRESSING MODES CPU12

3-2 REFERENCE MANUAL
 In this example, extended addressing mode is used to access the operand FOO,
immediate addressing mode is used to access the mask value $03, and relative ad-
dressing mode is used to identify the destination address of a branch in case the
branch-taken conditions are met. BRSET is listed as an extended mode instruction
even though immediate and relative modes are also used.

3.5 Direct Addressing Mode

This addressing mode is sometimes called zero-page addressing because it is used
to access operands in the address range $0000 through $00FF. Since these address-
es always begin with $00, only the eight low-order bits of the address need to be in-
cluded in the instruction, which saves program space and execution time. A system
can be optimized by placing the most commonly accessed data in this area of memory.
The eight low-order bits of the operand address are supplied with the instruction and
the eight high-order bits of the address are assumed to be zero.
Examples:

This is a very basic example of direct addressing. The value $55 is taken to be the
low-order half of an address in the range $0000 through $00FF. The high order half of
the address is assumed to be zero. During execution of this instruction, the CPU com-
bines the value $55 from the instruction with the assumed value of $00 to form the ad-
dress $0055, which is then used to access the data to be loaded into accumulator A.

In this example, the value $20 is combined with the assumed value of $00 to form the
address $0020. Since the LDX instruction requires a 16-bit value, a 16-bit word of data
is read from addresses $0020 and $0021. After execution of this instruction, the X in-
dex register will have the value from address $0020 in its high-order half and the value
from address $0021 in its low-order half.

3.6 Extended Addressing Mode

In this addressing mode, the full 16-bit address of the memory location to be operated
on is provided in the instruction. This addressing mode can be used to access any lo-
cation in the 64-Kbyte memory map.

Example:

This is a very basic example of extended addressing. The value from address $F03B
is loaded into the A accumulator.

CPU12 ADDRESSING MODES MOTOROLA

REFERENCE MANUAL 3-3
3.7 Relative Addressing Mode
The relative addressing mode is used only by branch instructions. Short and long con-
ditional branch instructions use relative addressing mode exclusively, but branching
versions of bit manipulation instructions (BRSET and BRCLR) use multiple addressing
modes, including relative mode. Refer to 3.9 Instructions Using Multiple Modes for
more information.
Short branch instructions consist of an 8-bit opcode and a signed 8-bit offset contained
in the byte that follows the opcode. Long branch instructions consist of an 8-bit pre-
byte, an 8-bit opcode and a signed 16-bit offset contained in the two bytes that follow
the opcode.
Each conditional branch instruction tests certain status bits in the condition code reg-
ister. If the bits are in a specified state, the offset is added to the address of the next
memory location after the offset to form an effective address, and execution continues
at that address; if the bits are not in the specified state, execution continues with the
instruction immediately following the branch instruction.

Bit-condition branches test whether bits in a memory byte are in a specific state. Var-
ious addressing modes can be used to access the memory location. An 8-bit mask op-
erand is used to test the bits. If each bit in memory that corresponds to a one in the
mask is either set (BRSET) or clear (BRCLR), an 8-bit offset is added to the address
of the next memory location after the offset to form an effective address, and execution
continues at that address; if all the bits in memory that correspond to a one in the mask
are not in the specified state, execution continues with the instruction immediately fol-
lowing the branch instruction.
Both 8-bit and 16-bit offsets are signed two’s complement numbers to support branch-
ing upward and downward in memory. The numeric range of short branch offset val-
ues is $80 (–128) to $7F (127). The numeric range of long branch offset values is
$8000 (–32768) to $7FFF (32767). If the offset is zero, the CPU executes the instruc-
tion immediately following the branch instruction, regardless of the test involved.
Since the offset is at the end of a branch instruction, using a negative offset value can
cause the PC to point to the opcode and initiate a loop. For instance, a branch always
(BRA) instruction consists of two bytes, so using an offset of $FE sets up an infinite
loop; the same is true of a long branch always (LBRA) instruction with an offset of
$FFFC.
An offset that points to the opcode can cause a bit-condition branch to repeat execu-
tion until the specified bit condition is satisfied. Since bit condition branches can con-
sist of four, five, or six bytes depending on the addressing mode used to access the
byte in memory, the offset value that sets up a loop can vary. For instance, using an
offset of $FC with a BRCLR that accesses memory using an 8-bit indexed postbyte
sets up a loop that executes until all the bits in the specified memory byte that corre-
spond to ones in the mask byte are cleared.

MOTOROLA ADDRESSING MODES CPU12

3-4 REFERENCE MANUAL
3.8 Indexed Addressing Modes
The CPU12 uses redefined versions of M68HC11 indexed modes that reduce execu-
tion time and eliminate code size penalties for using the Y index register. In most
cases, CPU12 code size for indexed operations is the same or is smaller than that for
the M68HC11. Execution time is shorter in all cases. Execution time improvements are
due to both a reduced number of cycles for all indexed instructions and to faster sys-
tem clock speed.
The indexed addressing scheme uses a postbyte plus 0, 1, or 2 extension bytes after
the instruction opcode. The postbyte and extensions do the following tasks:

1. Specify which index register is used.

2. Determine whether a value in an accumulator is used as an offset.
3. Enable automatic pre or post increment or decrement.
4. Specify size of increment or decrement.
5. Specify use of 5-, 9-, or 16-bit signed offsets.
This approach eliminates the differences between X and Y register use while dramat-
ically enhancing the indexed addressing capabilities.

Major advantages of the CPU12 indexed addressing scheme are:

•The stack pointer can be used as an index register in all indexed operations.
•The program counter can be used as an index register in all but autoincrement
and autodecrement modes.
• A, B, or D accumulators can be used for accumulator offsets.
• Automatic pre- or post-increment or pre- or post-decrement by –8 to +8
• A choice of 5-, 9-, or 16-bit signed constant offsets.
• Use of two new indexed-indirect modes.
— Indexed-indirect mode with 16-bit offset
— Indexed-indirect mode with accumulator D offset
Table 3-2 is a summary of indexed addressing mode capabilities and a description of
postbyte encoding. The postbyte is noted as xb in instruction descriptions. Detailed
descriptions of the indexed addressing mode variations follow the table.

All indexed addressing modes use a 16-bit CPU register and additional information to
create an effective address. In most cases the effective address specifies the memory
location affected by the operation. In some variations of indexed addressing, the ef-
fective address specifies the location of a value that points to the memory location af-
fected by the operation.

Indexed addressing mode instructions use a postbyte to specify X, Y, SP, or PC as the

base index register and to further classify the way the effective address is formed. A
special group of instructions (LEAS, LEAX, and LEAY) cause this calculated effective
address to be loaded into an index register for further calculations.

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REFERENCE MANUAL 3-5
 Table 3-2 Summary of Indexed Operations
Postbyte Source Code Comments
Code (xb) Syntax rr; 00 = X, 01 = Y, 10 = SP, 11 = PC

5-bit constant offset n = –16 to +15

r can specify X, Y, SP, or PC

Constant offset (9- or 16-bit signed)

z- 0 = 9-bit with sign in LSB of postbyte(s) -256 < n < 255
1 = 16-bit 0 < n < 65,535
if z = s = 1, 16-bit offset indexed-indirect (see below)
r can specify X, Y, SP, or PC
16-bit offset indexed-indirect
rr can specify X, Y, SP, or PC 0 < n < 65,535
Auto pre-decrement/increment or Auto post-decrement/increment;
p = pre-(0) or post-(1), n = –8 to –1, +1 to +8
r can specify X, Y, or SP (PC not a valid choice)
+8 = 0111
…
+1 = 0000
-1 = 1111
…
-8 = 1000
Accumulator offset (unsigned 8-bit or 16-bit)
aa- 00 = A
01 = B
10 = D (16-bit)
11 = see accumulator D offset indexed-indirect
r can specify X, Y, SP, or PC
Accumulator D offset indexed-indirect
r can specify X, Y, SP, or PC

3.8.1 5-Bit Constant Offset Indexed Addressing

This indexed addressing mode uses a 5-bit signed offset which is included in the in-
struction postbyte. This short offset is added to the base index register (X, Y, SP, or
PC) to form the effective address of the memory location that will be affected by the
instruction. This gives a range of –16 through +15 from the value in the base index reg-
ister. Although other indexed addressing modes allow 9- or 16-bit offsets, those
modes also require additional extension bytes in the instruction for this extra informa-
tion. The majority of indexed instructions in real programs use offsets that fit in the
shortest 5-bit form of indexed addressing.

Examples:

For these examples, assume X has a value of $1000 and Y has a value of $2000 be-
fore execution. The 5-bit constant offset mode does not change the value in the index
register, so X will still be $1000 and Y will still be $2000 after execution of these in-
structions. In the first example, A will be loaded with the value from address $1000. In
the second example, the value from the B accumulator will be stored at address $1FF8
($2000 – $8).

MOTOROLA ADDRESSING MODES CPU12

3-6 REFERENCE MANUAL
3.8.2 9-Bit Constant Offset Indexed Addressing
This indexed addressing mode uses a 9-bit signed offset which is added to the base
index register (X, Y, SP, or PC) to form the effective address of the memory location
affected by the instruction. This gives a range of –256 through +255 from the value in
the base index register. The most significant bit (sign bit) of the offset is included in the
instruction postbyte and the remaining eight bits are provided as an extension byte af-
ter the instruction postbyte in the instruction flow.
Examples:

For these examples assume X is $1000 and Y is $2000 before execution of these in-
structions. (These instructions do not alter the index registers so they will still be $1000
and $2000 respectively after the instructions.) The first instruction will load A with the
value from address $10FF and the second instruction will load B with the value from
address $1FEC.

This variation of the indexed addressing mode in the CPU12 is similar to the M68HC11
indexed addressing mode, but is functionally enhanced. The M68HC11 CPU provides
for unsigned 8-bit constant offset indexing from X or Y, and use of Y requires an extra
instruction byte and thus, an extra execution cycle. The 9-bit signed offset used in the
CPU12 covers the same range of positive offsets as the M68HC11, and adds negative
offset capability. The CPU12 can use X, Y, SP or PC as the base index register.

3.8.3 16-Bit Constant Offset Indexed Addressing

This indexed addressing mode uses a 16-bit offset which is added to the base index
register (X, Y, SP, or PC) to form the effective address of the memory location affected
by the instruction. This allows access to any address in the 64-Kbyte address space.
Since the address bus and the offset are both 16 bits, it does not matter whether the
offset value is considered to be a signed or an unsigned value ($FFFF may be thought
of as +65,535 or as –1). The 16-bit offset is provided as two extension bytes after the
instruction postbyte in the instruction flow.

3.8.4 16-Bit Constant Indirect Indexed Addressing

This indexed addressing mode adds a 16-bit instruction-supplied offset to the base in-
dex register to form the address of a memory location that contains a pointer to the
memory location affected by the instruction. The instruction itself does not point to the
address of the memory location to be acted upon, but rather to the location of a pointer
to the address to be acted on. The square brackets distinguish this addressing mode
from 16-bit constant offset indexing.
Example:

CPU12 ADDRESSING MODES MOTOROLA

REFERENCE MANUAL 3-7
 In this example, X holds the base address of a table of pointers. Assume that X has
an initial value of $1000, and that the value $2000 is stored at addresses $100A and
$100B. The instruction first adds the value 10 to the value in X to form the address
$100A. Next, an address pointer ($2000) is fetched from memory at $100A. Then, the
value stored in location $2000 is read and loaded into the A accumulator.

3.8.5 Auto Pre/Post Decrement/Increment Indexed Addressing

This indexed addressing mode provides four ways to automatically change the value
in a base index register as a part of instruction execution. The index register can be
incremented or decremented by an integer value either before or after indexing takes
place. The base index register may be X, Y, or SP (auto-modify modes would not
make sense on PC).
Pre decrement and pre increment versions of the addressing mode adjust the value of
the index register before accessing the memory location affected by the instruction —
the index register retains the changed value after the instruction executes. Post-dec-
rement and post-increment versions of the addressing mode use the initial value in the
index register to access the memory location affected by the instruction, then change
the value of the index register.
The CPU12 allows the index register to be incremented or decremented by any integer
value in the ranges –8 through –1, or 1 through 8. The value need not be related to the
size of the operand for the current instruction. These instructions can be used to incor-
porate an index adjustment into an existing instruction rather than using an additional
instruction and increasing execution time. This addressing mode is also used to per-
form operations on a series of data structures in memory.

When an LEAS, LEAX, or LEAY instruction is executed using this addressing mode,
and the operation modifies the index register that is being loaded, the final value in the
register is the value that would have been used to access a memory operand (premod-
ification is seen in the result but postmodification is not).

Examples:

For a “last-used” type of stack like the CPU12 stack, these four examples are equiva-
lent to common push and pull instructions. For a “next-available” stack like the
M68HC11 stack, PSHA is equivalent to STAA 1,SP– and PULA is equivalent to LDAA
1,+SP. However, in the M68HC11, 16-bit operations like PSHX and PULX require mul-
tiple instructions to decrement the SP by one, then store X, then decrement SP by one
again.

MOTOROLA ADDRESSING MODES CPU12

3-8 REFERENCE MANUAL
 In the STAA 1,–SP example, the stack pointer is pre-decremented by one and then A
is stored to the address contained in the stack pointer. Similarly the LDX 2,SP+ first
loads X from the address in the stack pointer, then post-increments SP by two.

Example:

This example demonstrates how to work with data structures larger than bytes and
words. With this instruction in a program loop, it is possible to move words of data from
a list having one word per entry into a second table that has four bytes per table ele-
ment. In this example the source pointer is updated after the data is read from memory
(post-increment) while the destination pointer is updated before it is used to access
memory (pre-increment).

3.8.6 Accumulator Offset Indexed Addressing

In this indexed addressing mode, the effective address is the sum of the values in the
base index register and an unsigned offset in one of the accumulators. The value in
the index register itself is not changed. The index register can be X, Y, SP, or PC and
the accumulator can be either of the 8-bit accumulators (A or B) or the 16-bit D accu-
mulator.

Example:

This instruction internally adds B to X to form the address from which A will be loaded.
B and X are not changed by this instruction. This example is similar to the following
two-instruction combination in an M68HC11.

However, this two-instruction sequence alters the index register. If this sequence was
part of a loop where B changed on each pass, the index register would have to be re-
loaded with the reference value on each loop pass. The use of LDAA B,X is more ef-
ficient in the CPU12.

3.8.7 Accumulator D Indirect Indexed Addressing

This indexed addressing mode adds the value in the D accumulator to the value in the
base index register to form the address of a memory location that contains a pointer
to the memory location affected by the instruction. The instruction operand does not
point to the address of the memory location to be acted upon, but rather to the location
of a pointer to the address to be acted upon. The square brackets distinguish this ad-
dressing mode from D accumulator offset indexing.
Example:

CPU12 ADDRESSING MODES MOTOROLA

REFERENCE MANUAL 3-9
 This example is a computed GOTO. The values beginning at GO1 are addresses of
potential destinations of the jump instruction. At the time the JMP [D,PC] instruction is
executed, PC points to the address GO1, and D holds one of the values $0000, $0002,
or $0004 (determined by the program some time before the JMP).
Assume that the value in D is $0002. The JMP instruction adds the values in D and
PC to form the address of GO2. Next the CPU reads the address PLACE2 from mem-
ory at GO2 and jumps to PLACE2. The locations of PLACE1 through PLACE3 were
known at the time of program assembly but the destination of the JMP depends upon
the value in D computed during program execution.

3.9 Instructions Using Multiple Modes

Several CPU12 instructions use more than one addressing mode in the course of ex-
ecution.

3.9.1 Move Instructions

Move instructions use separate addressing modes to access the source and destina-
tion of a move. There are move variations for most combinations of immediate, ex-
tended, and indexed addressing modes.
The only combinations of addressing modes that are not allowed are those with an im-
mediate mode destination (the operand of an immediate mode instruction is data, not
an address). For indexed moves, the reference index register may be X, Y, SP, or PC.
Move instructions do not support indirect modes, or 9- or 16-bit offset modes requiring
extra extension bytes. There are special considerations when using PC-relative ad-
dressing with move instructions.

PC-relative addressing uses the address of the location immediately following the last
byte of object code for the current instruction as a reference point. The CPU12 normal-
ly corrects for queue offset and for instruction alignment so that queue operation is
transparent to the user. However, move instructions pose three special problems:
1. Some moves use an indexed source and an indexed destination.
2. Some moves have object code that is too long to fit in the queue all at one time,
so the PC value changes during execution.
3. All moves do not have the indexed postbyte as the last byte of object code.
These cases are not handled by automatic queue pointer maintenance, but it is still
possible to use PC-relative indexing with move instructions by providing for PC offsets
in source code.
Table 3-3 shows PC offsets from the location immediately following the current in-
struction by addressing mode.

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3-10 REFERENCE MANUAL
 Table 3-3 PC Offsets for Move Instructions
MOVE Instruction Addressing Modes Offset Value
IMM IDX 1
EXT IDX 2
MOVB IDX EXT –2
– 1 for 1st Operand
IDX IDX
+ 1 for 2nd Operand
IMM IDX 2
EXT IDX 2
MOVW IDX EXT –2
– 1 for 1st Operand
IDX IDX
1 for 2nd Operand

Example:

Moves a byte of data from $2000 to $1009

The expected location of the PC = $1005. The offset = +2.

(1005 + 2 (for 2,PC) + 2 (for correction) = 1009)

$18 is the page pre-byte, 09 is the MOVB opcode for ext-idx, C2 is the indexed post-
byte for 2,PC (without correction).
The Motorola MCUasm assembler produces corrected object code for PC-relative
moves (18 09 C0 20 00 for the example shown). Note that, instead of assembling the
2,PC as C2, the correction has been applied to make it C0. Check whether an assem-
bler makes the correction before using PC-relative moves.

3.9.2 Bit Manipulation Instructions

Bit manipulation instructions use either a combination of two or a combination of three
addressing modes.

The BCLR and BSET instructions use an 8-bit mask to determine which bits in a mem-
ory byte are to be changed. The mask must be supplied with the instruction as an im-
mediate mode value. The memory location to be modified can be specified by means
of direct, extended, or indexed addressing modes.

The BRCLR and BRSET instructions use an 8-bit mask to test the states of bits in a
memory byte. The mask is supplied with the instruction as an immediate mode value.
The memory location to be tested is specified by means of direct, extended, or indexed
addressing modes. Relative addressing mode is used to determine the branch ad-
dress. A signed 8-bit offset must be supplied with the instruction.

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REFERENCE MANUAL 3-11
3.10 Addressing More than 64 Kbytes
Some M68HC12 devices incorporate hardware that supports addressing a larger
memory space than the standard 64 Kbytes. The expanded memory system uses fast
on-chip logic to implement a transparent bank-switching scheme.

Increased code efficiency is the greatest advantage of using a switching scheme in-
stead of a large linear address space. In systems with large linear address spaces, in-
structions require more bits of information to address a memory location, and CPU
overhead is greater. Other advantages include the ability to change the size of system
memory and the ability to use various types of external memory.

However, the add-on bank switching schemes used in other microcontrollers have
known weaknesses. These include the cost of external glue logic, increased program-
ming overhead to change banks, and the need to disable interrupts while banks are
switched.
The M68HC12 system requires no external glue logic. Bank switching overhead is re-
duced by implementing control logic in the MCU. Interrupts do not need to be disabled
during switching because switching tasks are incorporated in special instructions that
greatly simplify program access to extended memory.

MCUs with expanded memory treat the 16 Kbytes of memory space from $8000 to
$BFFF as a program memory window. Expanded-memory devices also have an 8-bit
program page register (PPAGE), which allows up to 256 16-Kbyte program memory
pages to be switched into and out of the program memory window. This provides for
up to 4 Megabytes of paged program memory.

The CPU12 instruction set includes CALL and RTC (return from call) instructions,
which greatly simplify the use of expanded memory space. These instructions also ex-
ecute correctly on devices that do not have expanded-memory addressing capability,
thus providing for portable code.

The CALL instruction is similar to the JSR instruction. When CALL is executed, the
current value in PPAGE is pushed onto the stack with a return address, and a new in-
struction-supplied value is written to PPAGE. This value selects the page the called
subroutine resides upon, and can be considered to be part of the effective address.
For all addressing mode variations except indexed indirect modes, the new page value
is provided by an immediate operand in the instruction. For indexed indirect variations
of CALL, a pointer specifies memory locations where the new page value and the ad-
dress of the called subroutine are stored. Use of indirect addressing for both the page
value and the address within the page frees the program from keeping track of explicit
values for either address.

The RTC instruction restores the saved program page value and the return address
from the stack. This causes execution to resume at the next instruction after the orig-
inal CALL instruction.

Refer to SECTION 10 MEMORY EXPANSION for a detailed discussion of memory ex-

pansion.

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