International Journal of Science and Research (IJSR)

ISSN (Online): 2319-7064

Index Copernicus Value (2013): 6.14 | Impact Factor (2014): 5.611

Design and Implementation of Content Addressable

Memory (CAM) Architecture
Megha Gupta1, Vipin Kumar Gupta2
1
M.Tech. Student, Department of Electronics and Communication Engineering, Suresh Gyan Vihar University, Jagatpura, Jaipur, India
2
Assistant Professor, Department of Electronics and Communication Engineering, Suresh Gyan Vihar University, Jagatpura, Jaipur, India

Abstract: Content addressable memory (CAM) is a storage memory with an extra comparison circuitry. It is also called as associative
memory, which can be accessed by its own contents instead of addresses in a single clock cycle. Due to access of CAM in a parallel
fashion, it has a high speed but consumes very high power. Also, an extra circuitry makes consumption of power higher. In this paper,
a CAM architecture based on parity bit is proposed, which will reduce power consumption and increases its performance compared to
traditional CAM architecture and other existing designs. Comparison of performance parameters of parity bit based PB-CAM with
other existing architectures is presented here and Tanner EDA Tool under 130nm CMOS technology is used for implementation,
simulation, and power and delay are estimated for performance evaluation of CAM architectures.

Keywords: CAM, PB-CAM, Associative memory, Parity Bit, MLSA.

1. Introduction 2. Content Addressable Memory

Most memory devices store and retrieve data by accessing its Content addressable memory (CAM) is a storage memory in
specific memory locations. But content addressable memory which it can be accessed by using its contents instead of
(CAM) is a type of memory in which it can be accessed by using memory locations [6]. When CAM receives the input
using its contents instead of using memory locations. As a data word to search it against table of data words stored in
result, the time required to find an item stored in memory can the CAM memory, it returns the address at which the search
be reduced. Hence, content addressable memory (CAM) is data word is stored.
one such memory that is fast and intuitive.
2.1 CAM Cell
The fast operation of CAM comes at the cost of increased
power consumption and area. The fast operation of CAM is Content Addressable Memory is a storage device that stores
due to the parallel searching operation of contents with all the data in its memory cell like usual memory. But additionally it
stored contents in the memory in a single clock cycle. That is, also has a comparison circuitry which is used to compare
CAM simultaneously searches the input word with all the search data with the data contents stored in its memory
contents stored in the memory. But, this results in the high simultaneously. This comparison circuitry in the CAM cell
power dissipation in the CAM. Hence, due to parallel occupies extra area than usual memory cell. Hence there is
searching operation in CAM, power consumption is always a more power dissipation but high speed due to parallel
major concern while designing CAM. searching operation.

There are various types of applications in which high speed Hence, a basic CAM cell has two functions [1]:
of operation is required. CAMs can be used in these types of 1) Bit Storage like usual memory RAM. So this bit storage
applications. But, the main application of CAM is that it is uses simple SRAM cell which contains two cross-coupled
used in high speed network routers for packet classification inverters forming positive feedback working as a D-latch.
and packet forwarding. As CAM applications grow, there is a 2) Bit Comparison which is equivalent to XNOR logic
demand of large CAM sizes which worsens the problem of operation. It is unique in CAM.
power. So the main challenge is to reduce power
consumption in large capacity CAMs without sacrificing its So, it has three modes of operation: read, write and compare.
speed [6].
2.2 Design Concept of CAM
In this paper, a CAM architecture is proposed in which parity
bit is used. This proposed CAM architecture consumes less
power and increase the searching speed than the basic CAM.
The rest of the paper is organized as follows. Section 2 gives
a brief about CAM. Section 3 explains the literature survey
done. In Section 4, a parity bit based PBCAM is proposed.
Simulation and comparison of results are presented in
Section 5. This paper is concluded in Section 6.

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 International Journal of Science and Research (IJSR)
ISSN (Online): 2319-7064
Index Copernicus Value (2013): 6.14 | Impact Factor (2014): 5.611
gets reduced. The power savings of the pipelined MLs is a
result of activating only a small portion of the matchline
segments. In [5], a new approach for PBCAM known as a
Block-XOR approach was proposed to improve the
efficiency of low power precomputation-based CAM (PB-
CAM) proposed in [8]. In this paper, a Block-XOR
parameter extractor for low power PB-CAM was proposed.
This paper presented theoretical and practical proofs to
verify that this proposed Block-XOR PB-CAM can
effectively achieve greater power reduction by reducing the
number of comparison operations in the second part of the
comparison process. This implies that this approach is more
flexible and adaptive for general designs. In addition, the
proposed Block-XOR PB-CAM can compute parameter bits
in parallel with only three XOR gate delays for any input bit
Figure 1: Conceptual View Diagram of CAM length (constant delay of search operation).

The conceptual view diagram of CAM is shown in Figure1. It 4. Proposed Work

shows that CAM contains m data words in which data is
stored. The search word is the n bit input data which is In this proposed approach, parity bit is introduced as
broadcasted onto the search lines to compare it with the table parameter for comparison operations. The parity bit
of stored words simultaneously [6]. There is a matchline generator is a parameter extractor here that will be used for
associated with each stored word which indicates whether the generating parity bit value. The advantage of using parity as a
search data is matched with the stored data or not. If the parameter is that parameter memory is highly reduced in
search data is matched with stored data, it is a match case comparison with existing PBCAM as only one bit i.e. k=1 is
otherwise mismatch case. These matchlines are fed to an required for storing parameter corresponding to each stored
encoder. This encoder generates the binary location word whatever may be the length of input data bits. Hence,
corresponding to matchline which indicates the match case. If the number of comparison operations in pre-computation is
there are more than one matchline that indicates the match highly reduced and hence the power consumption of
case then the priority encoder can be used to generate the parameter memory. So, overall power consumption of the
matched memory location. The priority encoder gives the CAM is reduced. Compared with existing PBCAM, the
matching address location corresponding to highest priority proposed architecture has improvement in complexity and
matchline. area but in comparison with traditional PBCAM, it has little
area overhead. The searching speed is also increased due to
3. Literature Review reduction in complexity and reduction in parameter
comparison operations. By using parity bits, delay for each
In [9], a technique was proposed to reduce power search operation is reduced. Hence, it boosts the search speed
consumption of matchlines in content addressable memories of parallel CAM.
(CAMs) called selective precharge technique. In selective
precharge technique, the matchline is divided into two 4.1 Parity Bit
segments. Firstly, the searching operation is performed in the
first segment in which first few bits of a word i.e. a small The number of bits having logic value „1‟ in a given binary
subset of CAM cells are searched. If there is a matching of data is counted. If number of bits in the binary data is odd,
data in the first segment only then searching of remaining bits then the parity bit value is „1‟ and if the number of one‟s in a
in the second segment will be activated. In [8], an binary data is even, then the parity bit value is „0‟.
architecture was proposed having low-power, low-cost, and
high-reliability features called as fully parallel
precomputation-based content addressable memory (PB-
CAM). This design is based on a precomputation skill that
saves power consumption of the CAM by reducing number
of comparisons in the second part of the comparison process.
In this design, one’s count approach is used for
precomputation. Hence, a one‟s count parameter extractor
was designed using a chain of full adders but it increases
delay as data bit length increases. In [7], a technique was
proposed to reduce power consumption of matchlines in
content addressable memories (CAMs) called pipelining
technique. In this technique, the search operation is pipelined
by breaking the match-lines into many segments. Since most
stored words do not match in their first segments, the search
operation is aborted for subsequent segments. Hence, power
Figure 2: Logic Circuit of Parity Bit Parameter Extractor.
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 International Journal of Science and Research (IJSR)
ISSN (Online): 2319-7064
Index Copernicus Value (2013): 6.14 | Impact Factor (2014): 5.611
4.2 Proposed PBCAM Architecture

Figure 3: Parity based PBCAM Architecture

Like existing PBCAM, in this design also, first the parity bit Table 1: Result Comparisons
is extracted using parity bit generator and comparisons of One’s Count Block-XOR Conventional Proposed
extracted parity bit is made with that of stored parity bits. Parameters
PBCAM [3] PBCAM [3] CAM PBCAM
Then, according to the results of parity bit comparisons,
Technology 0.35 µm 0.35 µm 0.13 µm 0.13 µm
comparisons in data memory takes place. Comparisons in Power (mW) 266.84 146.48 61.02 33.24
data memory will be made only with those stored data words Delay (ns) 25 15 2.18 1.18
whose corresponding parity bit will be matched with that of
input word‟s parity bit.
6. Conclusion
5. Simulation Results A parity based pre-computation based content addressable
memory (PB-CAM) has been proposed in which parity bit is
The proposed design is implemented and simulated using used as a parameter. In the traditional CAM, a large number
Tanner Tool under 130nm process environment. Figure 4 of comparisons are there for accessing the CAM. So, there is
shows the simulation waveform of proposed design and a large amount of power consumption. By proposed design,
Table 1 compares power and delay of various CAM the number of comparisons in the data memory has been
architectures. reduced for accessing the CAM than the traditional CAM by
little area overhead. Therefore, the proposed design
significantly saves power and provides high performance
than the traditional CAM. Moreover, parameter memory
required for storing parameters and hence parameter memory
comparisons have been reduced than existing PBCAMs. So,
parameter comparison power and parameter memory area are
also reduced than existing PBCAMs (One‟s Count and
Block-XOR), making it efficient to implement and use
practically. The proposed design has been implemented using
Tanner EDA Tool under 130nm technology. Simulation
results are showing that our proposed design achieves less
power and high performance with 33.24mW and 1.18ns
respectively than the traditional CAM with 61.02mW and
2.18ns. In the future, we can reduce more power as compared
to that of proposed design. Work can also be done on
reducing the area of CAM.
Figure 4: Simulation Waveform of Proposed Parity Bit
based PBCAM. References

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 International Journal of Science and Research (IJSR)
ISSN (Online): 2319-7064
Index Copernicus Value (2013): 6.14 | Impact Factor (2014): 5.611
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