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Advanced Digital System Design

Part 1

Kuruvilla Varghese
DESE
Indian Institute of Science

Kuruvilla Varghese

Synchronous Sequential Circuit 2

• Structure
• Design
• Timing analysis
• Xilinx STA

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 Synchronous Counter 3

• Mod 6 Counter (0, 1, 2, 3, 4, 5, 0, …)

NS
Next D Truth Table
State PS
CK Q Preset state Next state
Logic AR
Q2 Q1 Q0 D2 D1 D0

Clock 000 001

Reset 001 010
… …
Di = ℱi (Q2, Q1, Q0)
NS = ℱ (PS) 101 000

Mod 6 Counter (0, 5, 3, 2, 1, 4, 0, …) ?

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Output Waveform 4

CLK
tco

PS 0 1 ? 2 3

Three tco’s, for Q2, Q1, and Q0, Worst case is taken

Q2 Q1 Q0 Q2 Q1 Q0
0 0 1 0 0 1
Q1 < Q0 Q1 > Q0
0 1 1 0 0 0
0 1 0 0 1 0

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 Detailed and Next Level 5

NS D
Next
PS
State
CK Q
Logic AR

Clock
Reset

Incrementer
Cascade of Half- Adders
D Q D Q D Q Q
Q2 Q1 0

CK CK CK =
AR AR AR = ⊕
CLK
RST
= ⊕ · ·⋯ ·
Maximum Possible Paths: 9, Total Paths: 6

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Mod - 6 Counter with UP-DN/ 6

UP-DN/ Next NS D
State PS
CK Q
Logic AR

Clock
Reset

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 Mod - 6 Counter with input UP-DN/ 7

Inputs Preset state Next state Di = ℱi (Q2, Q1, Q0, UP-DN/)

UP-DN/ Q2 Q1 Q0 D2 D1 D0 NS = ℱ (PS, Inputs)
0 000 101
0 001 000 • Inputs
• Count-by-2
… … … • Reset
0 101 100 • Skip-3
1 000 001 • Load, din 2:0
1 001 010
• Synchronous Inputs
… … … • Transferred to output on Clock
1 101 000 • Goes to the Input (D) of FF

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Asynchronous 8

• Can we remove the Flip Flops and use buffers instead ?

NS
Next D
PS Q2 Q1 Q0
State Q
CK 0 0 1
Logic
AR
0 1 1
CLK
0 1 0
RST

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 Asynchronous 9

• Can we remove the Flip Flops and use buffers instead ?

• Yes
• Unbalanced Path delays
• Races
• Difficult to design / control
• Fast

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Meeting Setup and Hold Time 10

Next NS D
State PS
CK Q
Logic AR
Min Clock period (Max frequency)
Clock Tclk(min) > [tco + tcomb + ts]maxpath
Reset
fmax < 1 / Tclk(min)
CLK tco tcomb slack = Tclk(min) – [tco + tcomb + ts]maxpath
PS
th ts th
Avoid Hold time violation
NS (For each path i)
Tclk tco(min)i + tcomb(min)i > th(max)i
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 Max Frequency / Hold time Violation 11

• Earlier we gave seen the basic timing parameter of combinational

circuit, i.e. tpd
• Similarly basic timing parameters of flip-flops are ts, th and tco/tcq, all
the other timing relations/parameters of digital circuits are built on
these.
• For Sequential circuits, the basic timing relations are conditions for
meeting the setup time and the hold time.
• Meeting the setup time defines the minimum clock period / maximum
frequency

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Max Frequency / Hold time Violation 12

• Our analysis assumes that the clock reaches all the flip flops at the
same instant (i.e. there is no clock skew). We will analyze the case
with clock skews later.
• For Minimum time period, we are considering the delay of the slowest
path from flip-flop to flip-flop. Our expression shows the delay of the
longest path.
• For hold time violation we are considering lowest delay of each path
from flip-flop to flip-flop.

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 Max Frequency / Hold time Violation 13

• Minimum clock period is derived considering the register to register

path. When an active clock edge arrives at the source register, data
appear at the input of destination register after the register and
combinational delay. For proper registering this data must arrive at
the destination register before the setup time. This decides the
minimum clock frequency. For minimum clock period we consider
the maximum delay path.
• Similarly, when an active clock edge arrives at the source register, it
takes into consideration the minimum delay for the new data to
appear at the input of destination register. This decides the
conditions for hold time violation. Each path must be analyzed for
hold time violation.
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Max Frequency / Hold time Violation 14

• When a minimum clock period condition is violated, this can be met

by increasing the clock period.
• When there is a hold time violation you need to increase the
combinational delay.
• Since, in a flip flop the tco is greater than th, hold time violation with
our default assumption of no clock skew can not happen.
• But, this can happen when there are clock skews, and could be most
probable where combinational delays are less or zero like in simple
shift registers.

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 Number of Paths 15

• In the case of Mod-6 counter there are 3 flip-flops. Total number of

register to register paths are 9.
• i.e. From each Qi to each Dj for i, j: 0,1,2
• In general, timing of any register to register path follows the same
pattern, it need not be synchronous counter.
• e.g. Source register holding some data which goes to combinational
circuit for some computation, and the output (result) from
combinational circuit is registered in a destination register.
Synchronous counter’s data paths also are of this type.

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Register to Register Path 16

D Q D Q
Comb
CK CK

CLK

Tclk(min) = [tco + tcomb + ts]maxpath + slack

tco(min)i + tcomb(min)i > th(max)i (For each path i)

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 Static Timing Analysis (STA) 17

• Timing simulation: simulates the real time operation of the circuit,

with timing models of blocks for the specified test vectors
• Time consuming for exhaustive simulation
• Static Timing Analysis, analyzes various path delay from Block and
wire delays
• Can make mistake as it is not aware of the real time behavior of the
circuit
• A path that is never used in circuit operation may be reported (False
paths)
• Registers which are not enabled every clock cycle may be reported
(Multi-cycle paths)

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STA 18

• Timing Analysis is done at the fast and slow corners (e.g.

Supply voltage, temperature etc.)

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 STA: Register to Register Path 19

Input port Register to Register Path Output Port

Setup / Hold Clock to setup Clock to out

Input D Q D Q Output
Comb
CK CK

CLK

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Static Timing Analysis 20

• Clock Period: (Setup between Clocks), decided by the maximum

delay path between two registers clocked by the same clock
• Maximum delay path is called critical path delay
• Timing analysis is done against a specified clock constraint (required
clock period)
• The difference between the clock period constraint and the critical
path delay is the slack, which must be positive.

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 Xilinx Vivado: Setup Area (Max Delay Analysis) 21

• Vivado: The Setup area of the Design Timing Summary

section displays all checks related to max delay (max path)
analysis: setup, recovery, and data check.
• Worst Negative Slack (WNS): This value corresponds to the
worst slack of all the timing paths for max delay analysis. It
can be positive or negative.

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Setup Area (Max Delay Analysis) 22

• Total Negative Slack (TNS): The sum of all WNS violations, when
considering only the worst violation of each timing path endpoint. Its
value is:
– 0 ns, when all timing constraints are met for max delay analysis.
– Negative when there are some violations.
• Number of Failing Endpoints: The total number of endpoints with a
violation (WNS < 0 ns).
• Total Number of Endpoints: The total number of endpoints analyzed.

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 Vivado: Timing Report 23

• TNS (Total Negative Slack): The sum of the setup/recovery violations

for each endpoint in the entire design or for a particular clock domain.
The worst setup/recovery slack is the WNS (Worst Negative Slack).
• THS (Total Hold Slack): The sum of the hold/removal violations for
each endpoint in the entire design or for a particular clock domain.
The worst hold/removal slack is the WHS (Worst Hold Slack).

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Vivado: Timing Report 24

• TPWS (Total Pulse Width Slack): The sum of the violations for each
clock pin in the entire design or a particular clock domain for the
following checks:
– minimum low pulse width
– minimum high pulse width
– minimum period
– maximum period
– maximum skew (between two clock pins of a same leaf cell)

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 Vivado: Timing Report 25

• WPWS (Worst Pulse Width Slack): The worst slack for all
pulse width, period, or skew checks on any given clock pin.
• The Total Slack (TNS, THS or TPWS) only reflects the
violations in the design. When all timing checks are met, the
Total Slack is null.

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Vivado: Timing Constraints 26

• Implementation – Open implemented Design – Constraints

Wizard (Detects what is missing)
• Implementation – Open implemented Design – Edit Timing
Constraints

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 Vivado: Timing Report 27

• Implementation – Open implemented Design – Report Timing

Summary – Options – Tick Report Data Sheet – OK
• Timing Summary
– WNS should be positive
– Min Clock Period = Clock Constraint – WNS
• Data sheet
– Setup Between Clocks (Min Clock Period)
– Input Port Setup/Hold
– Output Port: Clock to Out

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STA: Input Delay 28

• Tool is able to analyze the delay of any path from an input pin to input
of any register, which naturally should be less than the clock period
constraint.
• What is more important is to account for the input delay external to
the FPGA device
• E.g. if the input signal originate from another device on the board
clocked by the same clock, then the clock to output delay of that
device and the wire delay to FPGA has to be accommodated, this is
specified as input delay.

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 STA: Input Delay 29

FPGA Device

Input Input port Output Port Output

delay Setup / Hold Register to Register Path Clock to out delay

D Q D Q D Q D Q
Comb
Input Output
CK CK CK CK

CLK

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STA: Input Delay 30

• Tool takes into consideration the clock skew between clock input of
FPGA and FPGA Register clock.
• If you use the timing constraint wizard of the Vivado tool, it analyzes
the missing constraints and prompts you to specify the input delay in
terms of clock to output delay, wire (trace) delay etc. (min and max
values)

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 STA: Output Delay 31

• Tool is able to analyze the delay of any path from the output of any
register to an output pin, which naturally should be less than the clock
period constraint
• What is more important is to account for delay external to the FPGA
device
• E.g. if the output signal goes to another device on board clocked by
the same clock, then wire delay to that device and the setup time of
the device FF has to be accommodated, this is specified as output
delay

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STA: Output Delay 32

FPGA Device

Input Input port Output Port Output

delay Setup / Hold Register to Register Path Clock to out delay

D Q D Q D Q D Q
Comb
Input Output
CK CK CK CK

CLK

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 STA: Output Delay 33

• Tool takes in to consideration the clock skew between clock input of

FPGA and FPGA Register clock.
• If you use the constraint wizard of the Vivado tool, it analyzes the
missing constraints and prompts you to specify the output delay in
terms of wire (trace) delay, setup time etc. (min and max values)

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Combinational Delay 34

FPGA Device
D Q D Q
comb
Input Output
Delay Delay

Virtual Clock Period

• Combinational delay is specified as the period of a virtual clock

• Period includes Input and Output Delays

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 Combinational Delay 35

• If there is a purely combinational circuit between an input and output

port, delay constraint is captured by period of a virtual clock.
• This analysis also accounts for input delay and output delay external
to FPGA and can be specified.
• Real constraint applied for delay between input and output pin is the
clock period minus the sum of input and output delays (min and max)

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Setup, Hold Times with skew 36

2 ns 1 ns
ts th

D’ D CLK
2 ns D Q 2 ns

CLK
D
CK ts’ 4 ns

th’ -1 ns

D’

ts’ = ts + td(skew)
th’ = th – td(skew)

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 Setup, Hold Times with skew 37

• Most often, setup and hold times of flip-flops or registers with respect to a pin or
output of another register need to be analyzed.
• When there is a delay t in the path to D input, the setup time with respect to new
reference point D' is increased by t and hold time is decreased by t.
• In this case, hold time can take a negative value. A hold time of –t means that at
point D’, the data can be removed or changed t time before the active clock
edge.
• Note: Setup time is defined as time before clock data has to be setup. So, for
setup time positive value is going backward from clock edge, and negative value
means it is forward from clock edge. For hold time reverse case applies.

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Setup, Hold Times with skew 38

2 ns 1 ns

ts th

CLK
3 ns
D D Q

D
CLK ts’
CLK’ 3 ns CK -1 ns
th’ 4 ns

CLK’

ts’ = ts – tc(skew)
th’ = th + tc(skew)
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 Setup, Hold Times with skew 39

• When there is a delay t in the path to CLK input, the setup time with
respect to new reference point CLK’ is decreased by t and hold time is
increased by t.
• In this case, setup time can take a negative value. A setup time of –t
means that at point CLK’, the data can be setup t time after the active
clock edge.

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Setup, Hold Times with skew 40

D’ d(skew) D Q

CLK’ c(skew) CK

ts’ = ts + td(skew) – tc(skew)

th’ = th – td(skew) + tc(skew)

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 STA: Combinational Circuit 41

Port to Port
(Combinational Path)

Input Comb Output

• Port to Port Path: Combinational delay from an input port to output

port including wire, buffer delays etc.

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STA: Sequential Circuit 42

Input Clock Period - WNS Clock to output

Setup (Register to Register Path)

Input D Q D Q Output
Comb
CK CK

CLK

• Register to register path decides the clock frequency. But, if other 2 exceeds
one need to choose the maximum value as the minimum clock period.
• In real life, this is not a great concern many a time we are designing some IPs
which goes inside the chip interfaced to other blocks close by. Even in case
inputs are outputs are brought to external pins, proper placement should take
care of these delays.
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