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Single-Phase Controller With Integrated Driver For VR12.1 Mobile CPU Core Power Supply

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0% found this document useful (0 votes)

65 views47 pages

Single-Phase Controller With Integrated Driver For VR12.1 Mobile CPU Core Power Supply

Uploaded by

Denis Denisov

We take content rights seriously. If you suspect this is your content, claim it here.

Available Formats

Download as PDF, TXT or read online on Scribd

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®

RT8199B

Single-Phase Controller with Integrated Driver for VR12.1

Mobile CPU Core Power Supply
General Description Features
The RT8199B is a VR12.1 compliant CPU power controller  VR12.1 Compatible Power Management States
which includes one voltage rails : a 1 phase synchronous  Switching Frequency up to 1MHz
buck controller, the CORE VR. The RT8199B has zero  Serial VID Interface
load-line function to support zero load-line application. The  Signal Phase PWM Controller
RT8199B adopts G-NAVPTM (Green Native AVP), which is  G-NAVPTM Topology
Richtek's proprietary topology derived from finite DC gain  0.5% DAC Accuracy
compensator with current mode control, making it an easy  Differential Remote Voltage Sensing
to set the PWM controller, meeting all Intel CPU  Built-in ADC for Platform Programming
requirements of AVP (Active Voltage Positioning). Based  System Thermal Compensated AVP
on the G-NAVPTM topology, the RT8199B also features a  Diode Emulation Mode at Light Load Condition
quick response mechanism for optimized AVP performance  Fast transient Response
during load transient. The RT8199B supports mode  VR Ready Indicator
transition function with various operating states. A Serial  Thermal Throttling
VID (SVID) interface is built in the RT8199B to  Current Monitor Output
communicate with Intel VR12.1 compliant CPU. The  Low Quiescent Power at PS3 and PS4
RT8199B supports VID on-the-fly function with three  OVP, UVP, OCP, UVLO, NVP
different slew rates : Fast, Slow and Decay. By utilizing  Address Flip Function
the G-NAVPTM topology, the operating frequency of the  DVID Improvement
RT8199B varies with VID, load and input voltage to further
enhance the efficiency even in CCM. The built-in high Applications
accuracy DAC converts the SVID code ranging from 0.25V  VR12.1 Intel Core Supply
to 1.52V with 5mV per step, as shown in Table 1. The  Notebook CPU Core Supply
RT8199B integrates a high accuracy ADC for platform  AVP Step-Down Converter
setting functions, such as quick response or over current
level. The RT8199B provides VR ready output signals. It
Marking Information
also features complete fault protection functions including
3K= : Product Code
Over Voltage (OV), Under Voltage (UV), Negative Voltage
3K=YM YMDNN : Date Code
(NV), Over Current (OC) and Under Voltage Lockout
DNN
(UVLO). The RT8199B is available in a WQFN-32L 4x4
small foot print package.

Simplified Application Circuit

VIN
RT8199B
To PCH VR_READY
VR_HOT UGATE
VCLK PHASE VCORE
To CPU
VDIO
LGATE
ALERT

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RT8199B
Ordering Information Pin Configurations
RT8199B (TOP VIEW)

VBOOTSEL
Package Type

SETGND
QW : WQFN-32L 4x4 (W-Type)

UGATE
ISENN
ISENP
IMON
Lead Plating System

EN
G : Green (Halogen Free and Pb Free) 32 31 30 29 28 27 26 25
Note : VREF 1 24 DRV_EN
COMP 2 23 PHASE
Richtek products are : FB 3 22 BOOT
VSEN 4
GND
21 PVCC
 RoHS compliant and compatible with the current require- RGND 5 20 LGATE
VCC 6 19 PGND
ments of IPC/JEDEC J-STD-020. SET1 7
33
18 DRV_EN
 Suitable for use in SnPb or Pb-free soldering processes. SET2 8 17 VR_READY
9 10 11 12 13 14 15 16

TSEN
VR_HOT
IBIAS
SET3

TONSET
ALERT
VDIO
VCLK
WQFN-32L 4x4

Functional Pin Description

Pin No. Pin Name Pin Function
Fixed 0.6V Output Reference Voltage. This voltage is only used to offset the
1 VREF output voltage of the IMON pin. Between this pin and GND must be placed a
exact 0.47F decoupling capacitor.
CORE VR Compensation Node. This pin is the output node of the error
2 COMP
amplifier.
CORE VR Feedback Voltage Input. This pin is the negative input node of the
3 FB
error amplifier.
CORE VR Voltage Sense Input. This pin is connected to the terminal of CORE
4 VSEN
VR output voltage.
Return Ground for CORE VR. This pin is the negative node of the differential
5 RGND
remote voltage sensing.
Supply Voltage Input. Connect this pin to GND via a ceramic capacitor larger
than 2.2F. The decoupling capacitor should be placed as close to the
6 VCC
controller as possible. If the ripple of voltage source is large, RC low pass filter
is recommended. (R = 20, C = 2.2F)

7 SET1 1st Platform Setting. Platform can use this to set DVID compensation time,
RSET, DVID compensation width and OCS.
2nd Platform Setting. Platform can use this to set ICCMAX, QRTH and
8 SET2
QRWIDTH.
3rd Platform Setting. Platform can use this to set zero load-line, anti-overshoot,
9 SET3 ADDR, switching frequency range, shrink TON at PS2 and PS3 and ZCD
threshold voltage.
Internal Bias Current Setting. Connecting this pin to GND by a 100k resistor
10 IBIAS can set the internal current. Do not connect this pin to GND by a bypass
capacitor.
11 TSEN Thermal Sense Input of CORE VR.

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RT8199B
Pin No. Pin Name Pin Function
12 VR_HOT Thermal Monitor Output. (Active Low).
13 VDIO VR and CPU Data Transmission Interface.
14 ALERT SVID Alert. (Active Low).
15 VCLK Synchronous Clock from the CPU.
CORE VR On-Time Setting. Connect this pin to input voltage with one resistor.
16 TONSET
By this resistor value, ripple size in PWM-mode can be set.
17 VR_READY VR Ready Indicator of CORE VR.
Internal Driv er Enable Control. These two pins should be floating and be
18, 24 DRV_EN
connected together.
19 PGND Driver Power Ground.
20 LGATE Low-Side Gate Driver Output. This pin drives the Gate of low-side MOSFET.
21 PVCC Driver Power. Connect this pin to GND by a ceramic capacitor 2.2F at least.
22 BOOT Bootstrap Supply for High-Side MOSFET.
Switch Node. This Pin is Return Node of The Core VR high-side driver. Connect
23 PHASE this pin to the high-side MOSFET Source together with the low-side MOSFET
Drain and the inductor.
25 UGATE High-Side Gate Driv er Output. This pin drives the Gate of high-side MOSFET.
26 EN VR Enable Control Input.
27 ISENN Negative Current Sense Input.
28 ISENP Positive Current Sense Input.
Boot Voltage Setting. Connect to a resistor divider between VCC and SETGND
29 VBOOTSEL
pins. By using this pin, BOOT voltage can be set to 0.9V, 1V or 1.1V.
Ground Return for the Platform Setting Pins : SET1, SET2, SET3, VBOOTSEL
30 SETGND
and TSEN. The SETGND pin is connected to ground except at PS3 and PS4.
CPU Core Current Monitor Output. This pin outputs a voltage proportional to the
31 IMON inductor current. Do not connect a bypass capacitor from this pin to GND or the
VREF pin.
32 NC No Internal Connection.
33 Ground. The exposed pad must be soldered to a large PCB and connected to
GND
(Exposed Pad) GND for maximum power dissipation.

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RT8199B
Function Block Diagram

VBOOTSEL

VR_READY

SETGND
VR_HOT
ALERT
TSEN
SET1

SET2

SET3

VSEN
VCLK

VDIO

VCC
EN
IMONI
x4 UVLO
MUX GND
IBIAS
ADC
Loop Control
SVID Interface Configuration Protection Logic
Registers Control Logic

TONSET
From Control Logic TZ <7:0> DVID_TH <2:0>
DIMON <7:0> DVID_WTH <2:0>
ZCD <2:0> OCS <2:0>
RGND DAC EN_0LL RSET <2:0>
EN_ANTI_OVS ICCMAX <7:0> PVCC
QR_TH <2:0>
BOOT
QR_WIDTH <2:0>
ERROR UGATE
Soft-Start & Slew VSET AMP CMP
Rate Control + Offset PWM TON PWM PHASE
Driver
FB - Cancellation + GEN
+ - LGATE
COMP
Current Mirror Current Mirror QR PGND
ISENP + QRWIDTH
DRV_EN
ISENN - + TON
-
RSET

IMONI
+ OC To Protection Logic
OCP_SUM,
-
OCP_SPIKE
VSEN OV/UV/NV

IMON VREF

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RT8199B
Operation
The RT8199B adopts G-NAVPTM (Green Native AVP) which Loop Control Protection Logic
is Richtek's proprietary topology derived from finite DC It controls the power on sequence and the protection
gain of EA amplifier with current mode control, making it behavior.
easy to set the droop to meet all Intel CPU requirements
of AVP (Adaptive Voltage Positioning). Offset Cancellation

The RT8199B adopts the G-NAVPTM controller, which is Cancel the current/voltage ripple issue to get the accurate
one type of current mode constant on-time control with VSEN.
DC offset cancellation. The approach can not only improve
UVLO
DC offset problem for increasing system accuracy but also
Detect the PVCC and VCC voltage and issue POR signal
has fast transient response. When current feedback signal
as they are high enough.
reaches COMP signal, the RT8199B generates an on-
time width to achieve PWM modulation. DAC
Besides, RT8199B also can support zero load-line Generate an analog signal according to the digital code
application. generated by Control Logic.

TON GEN Soft-Start & Slew Rate Control

Generate the PWM signal sequentially according to the Control the Dynamic VID slew rate of VSET according to
phase control signal from the Loop Control Protection the SetVID fast or SetVID slow. And the soft-start slew
Logic. rate is the slow slew rate.

SVID Interface/Configuration Registers/Control

Logic
The interface that receives the SVID signal from CPU and
sends the relative signals to Loop Control Protection Logic
to execute the action by CPU.
The registers save the pin setting data from ADC output.
The Control Logic controls the ADC timing and generates
the digital code of the VID that is relative to VSEN.

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RT8199B
Table 1. VR12.1 VID Code Table
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 0 0 0 0 0 0 1 01 0.250
0 0 0 0 0 0 1 0 02 0.255
0 0 0 0 0 0 1 1 03 0.260
0 0 0 0 0 1 0 0 04 0.265
0 0 0 0 0 1 0 1 05 0.270
0 0 0 0 0 1 1 0 06 0.275
0 0 0 0 0 1 1 1 07 0.280
0 0 0 0 1 0 0 0 08 0.285
0 0 0 0 1 0 0 1 09 0.290
0 0 0 0 1 0 1 0 0A 0.295
0 0 0 0 1 0 1 1 0B 0.300
0 0 0 0 1 1 0 0 0C 0.305
0 0 0 0 1 1 0 1 0D 0.310
0 0 0 0 1 1 1 0 0E 0.315
0 0 0 0 1 1 1 1 0F 0.320
0 0 0 1 0 0 0 0 10 0.325
0 0 0 1 0 0 0 1 11 0.330
0 0 0 1 0 0 1 0 12 0.335
0 0 0 1 0 0 1 1 13 0.340
0 0 0 1 0 1 0 0 14 0.345
0 0 0 1 0 1 0 1 15 0.350
0 0 0 1 0 1 1 0 16 0.355
0 0 0 1 0 1 1 1 17 0.360
0 0 0 1 1 0 0 0 18 0.365
0 0 0 1 1 0 0 1 19 0.370
0 0 0 1 1 0 1 0 1A 0.375
0 0 0 1 1 0 1 1 1B 0.380
0 0 0 1 1 1 0 0 1C 0.385
0 0 0 1 1 1 0 1 1D 0.390
0 0 0 1 1 1 1 0 1E 0.395
0 0 0 1 1 1 1 1 1F 0.400
0 0 1 0 0 0 0 0 20 0.405
0 0 1 0 0 0 0 1 21 0.410
0 0 1 0 0 0 1 0 22 0.415
0 0 1 0 0 0 1 1 23 0.420
0 0 1 0 0 1 0 0 24 0.425
0 0 1 0 0 1 0 1 25 0.430
0 0 1 0 0 1 1 0 26 0.435
0 0 1 0 0 1 1 1 27 0.440
0 0 1 0 1 0 0 0 28 0.445

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RT8199B
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 0 1 0 1 0 0 1 29 0.450
0 0 1 0 1 0 1 0 2A 0.455
0 0 1 0 1 0 1 1 2B 0.460
0 0 1 0 1 1 0 0 2C 0.465
0 0 1 0 1 1 0 1 2D 0.470
0 0 1 0 1 1 1 0 2E 0.475
0 0 1 0 1 1 1 1 2F 0.480
0 0 1 1 0 0 0 0 30 0.485
0 0 1 1 0 0 0 1 31 0.490
0 0 1 1 0 0 1 0 32 0.495
0 0 1 1 0 0 1 1 33 0.500
0 0 1 1 0 1 0 0 34 0.505
0 0 1 1 0 1 0 1 35 0.510
0 0 1 1 0 1 1 0 36 0.515
0 0 1 1 0 1 1 1 37 0.520
0 0 1 1 1 0 0 0 38 0.525
0 0 1 1 1 0 0 1 39 0.530
0 0 1 1 1 0 1 0 3A 0.535
0 0 1 1 1 0 1 1 3B 0.540
0 0 1 1 1 1 0 0 3C 0.545
0 0 1 1 1 1 0 1 3D 0.550
0 0 1 1 1 1 1 0 3E 0.555
0 0 1 1 1 1 1 1 3F 0.560
0 1 0 0 0 0 0 0 40 0.565
0 1 0 0 0 0 0 1 41 0.570
0 1 0 0 0 0 1 0 42 0.575
0 1 0 0 0 0 1 1 43 0.580
0 1 0 0 0 1 0 0 44 0.585
0 1 0 0 0 1 0 1 45 0.590
0 1 0 0 0 1 1 0 46 0.595
0 1 0 0 0 1 1 1 47 0.600
0 1 0 0 1 0 0 0 48 0.605
0 1 0 0 1 0 0 1 49 0.610
0 1 0 0 1 0 1 0 4A 0.615
0 1 0 0 1 0 1 1 4B 0.620
0 1 0 0 1 1 0 0 4C 0.625
0 1 0 0 1 1 0 1 4D 0.630
0 1 0 0 1 1 1 0 4E 0.635
0 1 0 0 1 1 1 1 4F 0.640
0 1 0 1 0 0 0 0 50 0.645
0 1 0 1 0 0 0 1 51 0.650

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RT8199B
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 1 0 1 0 0 1 0 52 0.655
0 1 0 1 0 0 1 1 53 0.660
0 1 0 1 0 1 0 0 54 0.665
0 1 0 1 0 1 0 1 55 0.670
0 1 0 1 0 1 1 0 56 0.675
0 1 0 1 0 1 1 1 57 0.680
0 1 0 1 1 0 0 0 58 0.685
0 1 0 1 1 0 0 1 59 0.690
0 1 0 1 1 0 1 0 5A 0.695
0 1 0 1 1 0 1 1 5B 0.700
0 1 0 1 1 1 0 0 5C 0.705
0 1 0 1 1 1 0 1 5D 0.710
0 1 0 1 1 1 1 0 5E 0.715
0 1 0 1 1 1 1 1 5F 0.720
0 1 1 0 0 0 0 0 60 0.725
0 1 1 0 0 0 0 1 61 0.730
0 1 1 0 0 0 1 0 62 0.735
0 1 1 0 0 0 1 1 63 0.740
0 1 1 0 0 1 0 0 64 0.745
0 1 1 0 0 1 0 1 65 0.750
0 1 1 0 0 1 1 0 66 0.755
0 1 1 0 0 1 1 1 67 0.760
0 1 1 0 1 0 0 0 68 0.765
0 1 1 0 1 0 0 1 69 0.770
0 1 1 0 1 0 1 0 6A 0.775
0 1 1 0 1 0 1 1 6B 0.780
0 1 1 0 1 1 0 0 6C 0.785
0 1 1 0 1 1 0 1 6D 0.790
0 1 1 0 1 1 1 0 6E 0.795
0 1 1 0 1 1 1 1 6F 0.800
0 1 1 1 0 0 0 0 70 0.805
0 1 1 1 0 0 0 1 71 0.810
0 1 1 1 0 0 1 0 72 0.815
0 1 1 1 0 0 1 1 73 0.820
0 1 1 1 0 1 0 0 74 0.825
0 1 1 1 0 1 0 1 75 0.830
0 1 1 1 0 1 1 0 76 0.835
0 1 1 1 0 1 1 1 77 0.840
0 1 1 1 1 0 0 0 78 0.845
0 1 1 1 1 0 0 1 79 0.850
0 1 1 1 1 0 1 0 7A 0.855

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RT8199B
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
0 1 1 1 1 0 1 1 7B 0.860
0 1 1 1 1 1 0 0 7C 0.865
0 1 1 1 1 1 0 1 7D 0.870
0 1 1 1 1 1 1 0 7E 0.875
0 1 1 1 1 1 1 1 7F 0.880
1 0 0 0 0 0 0 0 80 0.885
1 0 0 0 0 0 0 1 81 0.890
1 0 0 0 0 0 1 0 82 0.895
1 0 0 0 0 0 1 1 83 0.900
1 0 0 0 0 1 0 0 84 0.905
1 0 0 0 0 1 0 1 85 0.910
1 0 0 0 0 1 1 0 86 0.915
1 0 0 0 0 1 1 1 87 0.920
1 0 0 0 1 0 0 0 88 0.925
1 0 0 0 1 0 0 1 89 0.930
1 0 0 0 1 0 1 0 8A 0.935
1 0 0 0 1 0 1 1 8B 0.940
1 0 0 0 1 1 0 0 8C 0.945
1 0 0 0 1 1 0 1 8D 0.950
1 0 0 0 1 1 1 0 8E 0.955
1 0 0 0 1 1 1 1 8F 0.960
1 0 0 1 0 0 0 0 90 0.965
1 0 0 1 0 0 0 1 91 0.970
1 0 0 1 0 0 1 0 92 0.975
1 0 0 1 0 0 1 1 93 0.980
1 0 0 1 0 1 0 0 94 0.985
1 0 0 1 0 1 0 1 95 0.990
1 0 0 1 0 1 1 0 96 0.995
1 0 0 1 0 1 1 1 97 1.000
1 0 0 1 1 0 0 0 98 1.005
1 0 0 1 1 0 0 1 99 1.010
1 0 0 1 1 0 1 0 9A 1.015
1 0 0 1 1 0 1 1 9B 1.020
1 0 0 1 1 1 0 0 9C 1.025
1 0 0 1 1 1 0 1 9D 1.030
1 0 0 1 1 1 1 0 9E 1.035
1 0 0 1 1 1 1 1 9F 1.040
1 0 1 0 0 0 0 0 A0 1.045
1 0 1 0 0 0 0 1 A1 1.050
1 0 1 0 0 0 1 0 A2 1.055
1 0 1 0 0 0 1 1 A3 1.060

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RT8199B
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
1 0 1 0 0 1 0 0 A4 1.065
1 0 1 0 0 1 0 1 A5 1.070
1 0 1 0 0 1 1 0 A6 1.075
1 0 1 0 0 1 1 1 A7 1.080
1 0 1 0 1 0 0 0 A8 1.085
1 0 1 0 1 0 0 1 A9 1.090
1 0 1 0 1 0 1 0 AA 1.095
1 0 1 0 1 0 1 1 AB 1.100
1 0 1 0 1 1 0 0 AC 1.105
1 0 1 0 1 1 0 1 AD 1.110
1 0 1 0 1 1 1 0 AE 1.115
1 0 1 0 1 1 1 1 AF 1.120
1 0 1 1 0 0 0 0 B0 1.125
1 0 1 1 0 0 0 1 B1 1.130
1 0 1 1 0 0 1 0 B2 1.135
1 0 1 1 0 0 1 1 B3 1.140
1 0 1 1 0 1 0 0 B4 1.145
1 0 1 1 0 1 0 1 B5 1.150
1 0 1 1 0 1 1 0 B6 1.155
1 0 1 1 0 1 1 1 B7 1.160
1 0 1 1 1 0 0 0 B8 1.165
1 0 1 1 1 0 0 1 B9 1.170
1 0 1 1 1 0 1 0 BA 1.175
1 0 1 1 1 0 1 1 BB 1.180
1 0 1 1 1 1 0 0 BC 1.185
1 0 1 1 1 1 0 1 BD 1.190
1 0 1 1 1 1 1 0 BE 1.195
1 0 1 1 1 1 1 1 BF 1.200
1 1 0 0 0 0 0 0 C0 1.205
1 1 0 0 0 0 0 1 C1 1.210
1 1 0 0 0 0 1 0 C2 1.215
1 1 0 0 0 0 1 1 C3 1.220
1 1 0 0 0 1 0 0 C4 1.225
1 1 0 0 0 1 0 1 C5 1.230
1 1 0 0 0 1 1 0 C6 1.235
1 1 0 0 0 1 1 1 C7 1.240
1 1 0 0 1 0 0 0 C8 1.245
1 1 0 0 1 0 0 1 C9 1.250
1 1 0 0 1 0 1 0 CA 1.255
1 1 0 0 1 0 1 1 CB 1.260
1 1 0 0 1 1 0 0 CC 1.265

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RT8199B
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
1 1 0 0 1 1 0 1 CD 1.270
1 1 0 0 1 1 1 0 CE 1.275
1 1 0 0 1 1 1 1 CF 1.280
1 1 0 1 0 0 0 0 D0 1.285
1 1 0 1 0 0 0 1 D1 1.290
1 1 0 1 0 0 1 0 D2 1.295
1 1 0 1 0 0 1 1 D3 1.300
1 1 0 1 0 1 0 0 D4 1.305
1 1 0 1 0 1 0 1 D5 1.310
1 1 0 1 0 1 1 0 D6 1.315
1 1 0 1 0 1 1 1 D7 1.320
1 1 0 1 1 0 0 0 D8 1.325
1 1 0 1 1 0 0 1 D9 1.330
1 1 0 1 1 0 1 0 DA 1.335
1 1 0 1 1 0 1 1 DB 1.340
1 1 0 1 1 1 0 0 DC 1.345
1 1 0 1 1 1 0 1 DD 1.350
1 1 0 1 1 1 1 0 DE 1.355
1 1 0 1 1 1 1 1 DF 1.360
1 1 1 0 0 0 0 0 E0 1.365
1 1 1 0 0 0 0 1 E1 1.370
1 1 1 0 0 0 1 0 E2 1.375
1 1 1 0 0 0 1 1 E3 1.380
1 1 1 0 0 1 0 0 E4 1.385
1 1 1 0 0 1 0 1 E5 1.390
1 1 1 0 0 1 1 0 E6 1.395
1 1 1 0 0 1 1 1 E7 1.400
1 1 1 0 1 0 0 0 E8 1.405
1 1 1 0 1 0 0 1 E9 1.410
1 1 1 0 1 0 1 0 EA 1.415
1 1 1 0 1 0 1 1 EB 1.420
1 1 1 0 1 1 0 0 EC 1.425
1 1 1 0 1 1 0 1 ED 1.430
1 1 1 0 1 1 1 0 EE 1.435
1 1 1 0 1 1 1 1 EF 1.440
1 1 1 1 0 0 0 0 F0 1.445
1 1 1 1 0 0 0 1 F1 1.450
1 1 1 1 0 0 1 0 F2 1.455
1 1 1 1 0 0 1 1 F3 1.460
1 1 1 1 0 1 0 0 F4 1.465
1 1 1 1 0 1 0 1 F5 1.470

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RT8199B
VID7 VID6 VID5 VID4 VID3 VID2 VID1 VID0 HEX Voltage (V)
1 1 1 1 0 1 1 0 F6 1.475
1 1 1 1 0 1 1 1 F7 1.480
1 1 1 1 1 0 0 0 F8 1.485
1 1 1 1 1 0 0 1 F9 1.490
1 1 1 1 1 0 1 0 FA 1.495
1 1 1 1 1 0 1 1 FB 1.500
1 1 1 1 1 1 0 0 FC 1.505
1 1 1 1 1 1 0 1 FD 1.510
1 1 1 1 1 1 1 0 FE 1.515
1 1 1 1 1 1 1 1 FF 1.520

Table 2. Standard Serial VID Commands

Master Slave
Code Commands Payload Payload Description
Contents Contents
00h not supported N/A N/A N/A
1. Set new target VID code, VR jumps to new VID target
01h SetVID_Fast VID code N/A with controlled default "fast" slew rate 13.2mV/s.
2. Set VR_Settled when VR reaches target VID voltage.
1. Set new target VID code, VR jumps to new VID target
02h SetVID_Slow VID code N/A with controlled default "slow" slew rate 3.3mV/s.
2. Set VR_Settled when VR reaches target VID voltage.
1. Set new target VID code, VR jumps to new VID target, but
does not control the slew rate. The output voltage decays
at a rate proportional to the load current.
03h SetVID_Decay VID code N/A
2. Low-side MOSFET is not allowed to sync current.
3. ACK 11b when target higher than current VOUT voltage.
4. ACK 10b when target lower than current VOUT voltage.
1. Set power state.
2. ACK 11b when not support.
Byte
3. ACK 10b even slave not change configuration.
04h SetPS indicating N/A
4. ACK 11b for still running SetVID command.
power states
5. VR remains in lower state when receiving SetVID
(decay).
Pointer of 1. Set the pointer of the data register.
05h SetRegADR registers in N/A 2. ACK 11b for address outside of support.
data table 3. NAK 01b for SetADR (all call).
New data
1. Write the contents to the data register.
06h SetReg DAT register N/A
2. NAK 01b for SetReg (all call).
content
1. Slave returns the contents of the specified register as the
Specified
payload.
07h GetReg Register
2. ACK 11b for non support address.
Contents
3. NAK 01b for GetReg (all call).
08h to
not supported N/A N/A N/A
1Fh

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RT8199B
Table3. SVID Data and Configuration Register
Index Register Name Description Access Default
00h Vendor ID Vendor ID RO, Vendor 1Eh
01h Product ID Product ID RO, Vendor 76h
02h Product Revision Product Revision RO, Vendor 00h
05h Protocol ID SVID Protocol ID RO, Vendor 06h
Bit mapped register, identifies the SVID VR Capabilities
06h Capability RO, Vendor 81h
and which of the optional telemetry register is supported.
10h Status_1 Data register containing the status of VR. R-M, W-PWM 00h
11h Status_2 Data register containing the status of transmission. R-M, W-PWM 00h
Temperature Data register showing temperature zone that has been
12h R-M, W-PWM 00h
Zone entered.
At PS0 to PS2, IOUT report data from ADC sense IMON
15h IOUT voltage. When power state at PS3, the IOUT report data is R-M, W-PWM 00h
fix to 04h.
1Ch Status_2_lastread The register contains a copy of the status_2. R-M, W-PWM 00h
Data register containing the ICC max the platform
21h ICC Max RO, Platform 7Dh
supports. Binary format in A IE 64h = 100A.
Data register containing the temperature max the platform
22h Temp Max supports. RO, Platform 64h
Binary format in C IE 64h = 100C.
Data register containing the capability of fast slew rate the
24h SR-fast platform can sustain. Binary format in mV/S IE 0Ch = RO 0Ch
12mV/s.
Data register containing the capability of slow slew rate.
25h SR-slow RO 03h
Binary format in mV/S IE 03h = 3mV/S.
Slow Slew Rate The register is programmed by master and set the slow
2Ah RW, Master 02h
Selector slew rate.
2Bh PS4 Exit Latency Data register containing the latency of exiting PS4. RO 77h
2Ch PS3 Exit Latency Data register containing the latency of exiting PS3. RO 3Fh

Enable to Ready Data register containing the latency from Enable assertion
2Dh RO BAh
for SVID to the VR being ready to accept an SVID command.

The register is programmed by master and sets the

30h VOUT Max RW, Master D5h
maximum VID.
31h VID Setting Data register containing currently programmed VID. RW, Master 00h
32h Power State Register containing the current programmed power state. RW, Master 00h
33h Offset Set offset in VID steps. RW, Master 00h
Multi VR Bit mapped data register which configures multiple VRs
34h RW, Master 01h
Configuration behavior on the same bus.
Scratch pad register for temporary storage of the
35h Pointer RW, Master 30h
SetRegADR pointer register.
Notes : W-PWM = Write by PWM Only
RO = Read Only Vendor = Hard Coded by VR Vendor
RW = Read/Write Platform = Programmed by the Master
R-M = Read by Master PWM = Programmed by the VR Control IC

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RT8199B
Absolute Maximum Ratings (Note 1)
 VCC, PVCC to GND ---------------------------------------------------------------------------------------------- −0.3V to 6V
 RGND to GND ------------------------------------------------------------------------------------------------------ −0.3V to 0.3V
 TONSET to GND --------------------------------------------------------------------------------------------------- −0.3V to 7.5V
 BOOT to PHASE -------------------------------------------------------------------------------------------------- −0.3V to 6V
 PHASE to GND
DC --------------------------------------------------------------------------------------------------------------------- −0.3V to 32V
< 20ns --------------------------------------------------------------------------------------------------------------- −8V to 38V
 LGATE to GND
DC --------------------------------------------------------------------------------------------------------------------- (GND − 0.3V) to 6V
< 20ns --------------------------------------------------------------------------------------------------------------- (GND − 5V) to 7.5V
 UGATE to PHASE
DC --------------------------------------------------------------------------------------------------------------------- (GND − 0.3V) to 6V
< 20ns --------------------------------------------------------------------------------------------------------------- (GND − 5V) to 7.5V
 Other Pins ----------------------------------------------------------------------------------------------------------- −0.3V to (VCC + 0.3V)
 Power Dissipation, PD @ TA = 25°C
WQFN-32L 4x4 ---------------------------------------------------------------------------------------------------- 3.59W
 Package Thermal Resistance (Note 2)
WQFN-32L 4x4, θJA ----------------------------------------------------------------------------------------------- 27.8°C/W
WQFN-32L 4x4, θJC ---------------------------------------------------------------------------------------------- 7°C/W
 Junction Temperature --------------------------------------------------------------------------------------------- 150°C
 Lead Temperature (Soldering, 10 sec.) ----------------------------------------------------------------------- 260°C
 Storage Temperature Range ------------------------------------------------------------------------------------ −65°C to 150°C
 ESD Susceptibility (Note 3)
HBM (Human Body Model) -------------------------------------------------------------------------------------- 2kV

Recommended Operating Conditions (Note 4)

 Supply Voltage, PVCC ------------------------------------------------------------------------------------------- 4.5V to 5.5V
 Junction Temperature Range ------------------------------------------------------------------------------------ −40°C to 125°C
 Ambient Temperature Range ------------------------------------------------------------------------------------ −40°C to 85°C

Electrical Characteristics
(VCC = 5V, TA = 25°C, unless otherwise specified)
Parameter Symbol Test Conditions Min Typ Max Unit
Supply Input
Supply Voltage VCC 4.5 5 5.5 V
Supply Current IVCC VEN = H, No switching -- 3.6 -- mA
Supply Current at PS3 IVCC_PS3 VEN = H, No switching -- 1.2 -- mA
Supply Current at PS4 IVCC_PS4 VEN = H, No switching -- -- 200 A
Power Supply Voltage PVCC 4.5 -- 5.5 V
Power Supply Current IPVCC No Switching -- 80 -- A
Shutdown Current ISHDN VEN = 0V -- -- 5 A

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RT8199B
Parameter Symbol Test Conditions Min Typ Max Unit
Reference and DAC
% of
VDAC = 0.8V 1.52V 0.5 0 0.5
VID
DAC Accuracy VFB VDAC = 0.5V 0.795V 8 0 8
mV
VDAC = 0.25V 0.495V 10 0 10
PVCC Power On Reset (POR)
VPOR_r PVCC Rising -- 4.2 4.5
POR Threshold V
VPOR_f PVCC Falling 3.4 3.84 --
POR Hysteresis VPOR_HYS -- 360 -- mV
Slew Rate
SetVID Slow 2.5 3.3 3.6
Dynamic VID Slew Rate SR mV/s
SetVID Fast 12.5 13.2 14.4
EA Amplifier
DC Gain ADC RL = 47k 70 -- -- dB
Gain-Bandwidth
GBW CLOAD = 5pF -- 5 -- MHz
Product
CLOAD = 10pF (Gain = 4, RF = 47k,
Slew Rate SREA 5 -- -- V/s
VOUT = 0.5V to 3V)
Output Voltage Range VCOMP RL = 47k 0.5 -- 3.6 V
Maximum Source/Sink
IOUTEA VCOMP = 2V -- 5 -- mA
Current
Load-Line Current Gain Amplifier
Input Offset Voltage VILOFS VIMON = 1V 5 -- 5 mV
VIMON VVREF = 1V,
Current Gain AILGAIN -- 1/3 -- A/A
VFB = VCOMP = 1V
Current Sensing Amplifier
Input Offset Voltage VOSCS 0.8 -- 0.8 mV
Impedance at Positive
RISENP 1 -- -- M
Input
Current Mirror Gain AMIRROR IIMON / ISENN 0.97 1 1.03 A/A
TON Setting
IRTON = 20 A, VDAC = 1V,
TONSET Pin Voltage VTON 3 -- 1 -- V
SET3 = fSW > 500kHz

IRTON = 20 A, VDAC = 1V,

On-Time Setting TON 3 256 285 314 ns
SET3 = fSW > 500kHz
Input Current Range IRTON VDAC = 1V, SET3 = fSW > 500kHz 2 -- 24 A
IRTON = 20 A, VDAC = 1V,
Minimum Off-time TOFF 3 -- 150 -- ns
SET3 = fSW > 500kHz

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RT8199B
Parameter Symbol Test Conditions Min Typ Max Unit
IBIAS
IBIAS Pin Voltage VIBIAS RIBIAS = 100k 1.95 2 2.05 V
Protections
Under Voltage Lockout VUVLO 4.1 4.3 4.45 V
Threshold VUVLO Falling edge hysteresis -- 200 -- mV
VID VID VID
Over Voltage Protection VID higher than 1.2V
VOV + 300 + 350 + 400 mV
Threshold
VID lower than 1.2V 1500 1550 1600
Under Voltage Protection
VUV Respect to VID voltage 400 350 300 mV
Threshold
Negative Voltage Protection
VNV 100 50 -- mV
Threshold
EN and VR_READY
EN Input Logic-High VIH 0.7 -- --
V
Voltage Logic-Low VIL -- -- 0.3
Leakage Current of EN 1 -- 1 A
VR_READY Delay TVR_READY VSEN = VBoot to VR_READY High 3 5 6 s
VR_READY Pull Low
VPGOOD IVR_READY = 10mA -- -- 0.13 V
Voltage
Serial VID and VR_HOT
VIH Respect to INTEL Spec. with 0.65 -- --
VCLK, VDIO V
VIL 50mV hysteresis -- -- 0.45
Leakage Current of VCLK,
ILEAK_IN 1 -- 1 A
VDIO, ALERT and VR_HOT
IVDIO = 10mA
VDIO, ALERT and VR_HOT
IALERT = 10mA -- -- 0.13 V
Pull Low Voltage
IVR_HOT = 10mA
VREF and VBOOT
VREF Voltage VREF 0.55 0.6 0.65 V
VBOOT Voltage VBOOT VBOOT Voltage set to 1V 0.995 1 1.005 V
ADC
VIMON VIMON_INI = 0.4V -- 255 --
Digital IMON Set VIMON VIMON VIMON_INI = 0.2V -- 128 -- Decimal
VIMON VIMON_INI = 0V -- 0 --
Update Period of IMON TIMON -- 400 -- s
TSEN Threshold for
VTSEN 100C -- 1.887 -- V
Tmp_Zone [7] transition
TSEN Threshold for
VTSEN 97C -- 1.837 -- V
Tmp_Zone [6] transition
TSEN Threshold for
VTSEN 94C -- 1.784 -- V
Tmp_Zone [5] transition

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16
RT8199B
Parameter Symbol Test Conditions Min Typ Max Unit
TSEN Threshold for
VTSEN 91C -- 1.729 -- V
Tmp_Zone [4] transition
TSEN Threshold for
VTSEN 88C -- 1.672 -- V
Tmp_Zone [3] transition
TSEN Threshold for
VTSEN 85C -- 1.612 -- V
Tmp_Zone [2] transition
TSEN Threshold for
VTSEN 82C -- 1.551 -- V
Tmp_Zone [1] transition
TSEN Threshold for
VTSEN 75C -- 1.402 -- V
Tmp_Zone [0] transition
Update Period of TSEN tTSEN -- 50 -- s
CICCMAX1 VICCMAX = 0.7V 58 64 70
Digital Code of ICCMAX CICCMAX2 VICCMAX = 0.8V 122 128 134 Decimal
CICCMAX3 VICCMAX = 1V 248 256 260
Switching Time
UGATE Rise Time tUGATEr 3nF load -- 8 -- ns
UGATE Fall Time tUGATEf 3nF load -- 8 -- ns
LGATE Rise Time tLGATEr 3nF load -- 8 -- ns
LGATE Fall Time tLGATEf 3nF load -- 4 -- ns
UGATE Turn-Off
tPDLU Outputs Unloaded -- 35 -- ns
Propagation Delay
LGATE Turn-Off
tPDLL Outputs Unloaded -- 35 -- ns
Propagation Delay
UGATE Turn-On
tPDHU Outputs Unloaded -- 20 -- ns
Propagation Delay
LGATE Turn-On
tPDHL Outputs Unloaded -- 20 -- ns
Propagation Delay
UGATE/LGATE Tri-State
tPTS Outputs Unloaded -- 35 -- ns
Propagation Delay
Output
UGATE Driver Source
RUGATEsr 100mA Source Current -- 1 -- 
Resistance
UGATE Driver Source
IUGATEsr VUGATE VPHASE = 2.5V -- 2 -- A
Current
UGATE Driver Sink
RUGATEsk 100mA Sink Current -- 1 -- 
Resistance
UGATE Driver Sink Current IUGATEsk VUGATE  VPHASE = 2.5V -- 2 -- A
LGATE Driver Source
RLGATEsr 100mA Source Current -- 1 -- 
Resistance
LGATE Driver Source
ILGATEsr VLGATE = 2.5V -- 2 -- A
Current
LGATE Driver Sink
RLGATEsk 100mA Sink Current -- 0.5 -- 
Resistance
LGATE Driver Sink Current ILGATEsk VLGATE = 2.5V -- 4 -- A

DS8199B-01 September 2015 www.richtek.com

17
RT8199B
Note 1. Stresses beyond those listed “Absolute Maximum Ratings” may cause permanent damage to the device. These are
stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in
the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions may
affect device reliability.
Note 2. θJA is measured at TA = 25°C on a high effective thermal conductivity four-layer test board per JEDEC 51-7. θJC is
measured at the exposed pad of the package.
Note 3. Devices are ESD sensitive. Handling precaution is recommended.
Note 4. The device is not guaranteed to function outside its operating conditions.

www.richtek.com DS8199B-01 September 2015

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DS8199B-01
VCC
R1 R2
20 6 2.2
VCC 5V VCC PVCC 21 5V
C1 RT8199B C2
2.2µF 2.2µF
VCC_SENSE

September 2015
R3 39.63k 9 SET3 VIN
C5 VSS_SENSE
R24 0.1µF
R5 16.0634k 8 SET2 2.2
BOOT 22 C6 R26 R27
R7 81.75k R25 22µF 100 100
7 SET1 Q1
25 0
R9 10k UGATE L1
Typical Application Circuit

29 VBOOTSEL
23 Optional 330nH / 2.95m VCORE_OUT
R11 R12 PHASE
Q2 R29 C10 C7 C8
100k 5.6k 11 270μF/6m
TSEN R28 475 0.47µF 22µFx6 LOAD
LGATE 20 x3
R13 R10 R8 R6 R4
C9

Copyright © 2015 Richtek Technology Corporation. All rights reserved.

RNTC1 6.2k 10k 24.0698k 1.15k 13.92k R30
100k 30 475
SETGND ISENP 28
ß = 4485 R31 680
R14 R15 27
ISENN
1 604k 16 TONSET 0.1µF
VIN VSEN 4 VCC_SENSE
C3 33 (Exposed Pad) C11 C12
0.1µF GND 47pF 390pF
R34
100k 10
VCCIO IBIAS R32 R33
2 68k 10k
COMP VCC_SENSE
C13
R19 R20 R21 R22 R23 3 Optional
FB
75 10k 130 130 150
17 RGND 5
VR_READY VSS_SENSE
12 C14
VR_HOT Optional
1
15 VCLK VREF
R16 C4
To CPU 13 VDIO 8.83k 0.47µF
14 R18
ALERT 31 6.63k RNTC2 R17
26 EN IMON
Enable 47k 5.44k
18, 24 DRV_EN 19
PGND ß = 4050

is a registered trademark of Richtek Technology Corporation.

19
www.richtek.com
RT8199B
RT8199B
Typical Operating Characteristics
CORE VR Power On from EN CORE VR Power Off from EN

V CORE V CORE
(500mV/Div) (500mV/Div)

EN EN
(900mV/Div) (900mV/Div)

VR_READY VR_READY
(800mV/Div) (800mV/Div)
UGATE UGATE
(20V/Div) VIN = 7.4V, No Load, Boot VID 0.9V (20V/Div) VIN = 7.4V, No Load, Boot VID 0.9V

Time (200μs/Div) Time (200μs/Div)

CORE VR OCP CORE VR OVP

V CORE
(1V/Div) V CORE
(700mV/Div)
I LOAD VR_READY
(30A/Div) (2V/Div)
UGATE
VR_READY (20V/Div)
(800mV/Div)
UGATE LGATE
(20V/Div) VIN = 7.4V, Boot VID 0.9V (8V/Div) VIN = 7.4V, Boot VID 0.9V, PS2

Time (200μs/Div) Time (100μs/Div)

CORE VR Dynamic VID Up CORE VR Dynamic VID Down

V CORE V CORE

VCLK VCLK
(1V/Div) (1V/Div)
V CORE V CORE
(300mV/Div) (300mV/Div)

VDIO VDIO
(1V/Div) (1V/Div)
ALERT ALERT
(1V/Div) VIN = 7.4V, VID = 0.7V to 1.15V, Slew Rate = Slow (1V/Div) VIN = 7.4V, VID = 1.15V to 0.7V, Slew Rate = Slow

Time (20μs/Div) Time (20μs/Div)

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RT8199B

CORE VR Dynamic VID Up CORE VR Dynamic VID Down

V CORE V CORE

VCLK VCLK
(1V/Div) (1V/Div)
V CORE V CORE
(300mV/Div) (500mV/Div)

VDIO VDIO
(1V/Div) (1V/Div)
ALERT ALERT
(2V/Div) VIN = 7.4V, VID = 0.7V to 1.15V, Slew Rate = Fast (2V/Div) VIN = 7.4V, VID = 1.15V to 0.7V, Slew Rate = Fast

Time (10μs/Div) Time (10μs/Div)

CORE VR Mode Transient CORE VR Mode Transient

V CORE V CORE
(10mV/Div) (10mV/Div)

VCLK VCLK
(1V/Div) (1V/Div)
UGATE UGATE
(20V/Div) (20V/Div)

LGATE LGATE
(8V/Div) VIN = 7.4V, VID = 0.7V, PS0 to PS2, ILOAD = 1A (8V/Div) VIN = 7.4V, VID = 0.7V, PS2 to PS0, ILOAD = 1A

Time (50μs/Div) Time (50μs/Div)

CORE VR Thermal Monitoring VVIMON

IMON vs.
vs. Load Current
Current
1.2

1.0

TSEN 0.8
VIMON (V)

(1V/Div)
0.6

0.4

VR_HOT 0.2
(500mV/Div) VIN = 12V, TSEN Sweep from 1.7V to 2.1V
0.0
Time (10ms/Div) 0 1 2 3 4 5 6 7 8 9 10 11 12 13
Load Current (A)

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RT8199B
Applications Information
The RT8199B is a single phase synchronous Buck Diode Emulation Mode (DEM)
controller designed to meet Intel VR12.1 compatible CPU As well-known, the dominate power loss is switching
specification with a serial SVID control interface. The related loss during light load, hence VR needs to be
controller uses an ADC to implement all kinds of settings operated in asynchronous mode (or called discontinuous
to save a total number of pins for easily using and conduct mode, DCM) to reduce switching related loss
increasing PCB space utilization. since switching frequency is dependent on loading in the
asynchronous mode. RT8199B can operate in Diode
G-NAVPTM Control Mode
Emulation Mode (DEM) in order to improve light load
The RT8199B adopts the G-NAVPTM controller, which is a efficiency. In DEM operation, the behavior of the low-side
current mode constant on-time control with DC offset MOSFET needs to work like a diode, that is, the low-side
cancellation. The approach can not only improve DC offset MOSFET will be turned on when the DCR network voltage
problem for increasing system accuracy but also provide is higher than the ZCD_TH, i.e. the inductor current follows
fast transient response. For the RT8199B, when current from source to drain of low-side MOSFET. The low-side
feedback signal reaches comp signal to generate an on- MOSFET will be turned off when DCR network is lower
time width to achieve PWM modulation. Figure 1 shows than the ZCD_TH, i.e. reversed current is not allowed.
the basic G-NAVPTM behavior waveforms in Continuous The positive voltage threshold (ZCD threshold) of low-side
Conduct Mode (CCM). MOSFET turn off is set by the SET3 pin in Table 9. Figure
Current feedback signal
2 shows the control behavior in DEM. Figure 3 shows the
G-NAVPTM operation in DEM to illustrate the control
behaviors. When the load decreases, the discharge time
of output capacitors increases during UGATE and LGATE
are turned off. Hence, the switching frequency and
Comp signal
switching losses will be reduced to improve efficiency in
PWM1
light load condition.
PWM2

PWM3 Inductor current

TM
Figure 1 (a). G-NAVP Behavior Waveforms in CCM in
Steady State
Phase node

Current feedback signal

UGATE
Comp signal

LGATE

Figure 2. Diode Emulation Mode (DEM) in Steady State

PWM1

PWM2

PWM3

Figure 1 (b). G-NAVPTM Behavior Waveforms in CCM in

Load Transient

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RT8199B
Inductor
current signal

Output capacitor COMP signal

discharge slope

UGATE

LGATE

(a) Lighter Load Condition in DEM.

Capacitor discharge slope is lower than Figure 3 (b).

Inductor
current signal

Output capacitor COMP signal

discharge slope

UGATE

LGATE

(b) Load Increased Condition in DEM.

Capacitor discharge slope is Higher than Figure 3 (a).

Figure 3. G-NAVPTM Operation in DEM.

Switching Frequency (TON) Setting For SET3 pin fSW > 500kHz
R  C  0.11
RT8199B is one kind of constant on-time control. The TON = TON
VIN  VDAC
 VDAC < 1.2V 
patented CCRCOT (Constant Current Ripple COT)
RTON  C  VDAC / 10.9
technology can generate an adaptive on-time with input TON =
VIN  1.2
 VDAC  1.2V 
voltage and VID code to obtain a constant current ripple.
So that the output voltage ripple can be controlled nearly Where C = 18.2pF. By using the relationship between
like a constant as different input and output voltage change. TON and fSW, the switching frequency fSW is :
Connect a resistor RTON between input voltage terminal  1   VDAC(MAX) 
and TONSET pin to set the on-time width.
fSW(MAX) = 
T    VIN(MAX) 
 ON(MAX)   
In order to meet Intel VR12.1 quiescent power specification Where
at PS3 and PS4, RT8199B provides two different fSW(MAX) is the maximum switching frequency.
coefficients for TON. And these coefficients can be setting
VDAC(MAX) is the maximum VDAC of application.
by SET3 pin, as shown in Tablet 9. So, RT8199B can
pass quiescent power for all range switching frequency at VIN(MAX) is the maximum application input voltage.
PS3 and PS4 under battery mode condition. TON(MAX) is the on-time width.
For SET3 pin fSW ≤ 500kHz, When load increases, on-time keeps constant. The
R  C  0.22
TON = TON
VIN  VDAC
 VDAC < 1.2V  off-time width will be reduced so that loading can load
more power from input terminal to regulate output voltage.
RTON  C  VDAC / 5.45
TON =
VIN  1.2
 VDAC  1.2V  Hence, the loading current increases in case the switching
frequency also increases. Higher switching frequency

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23
RT8199B
operation can reduce power component's size and PCB When inductance and DCRx time constant is equal to RXCX
space, trading off the whole efficiency since switching filter network time constant, a voltage ILX x DCRx will drop
related loss increases, vice versa. on CX to generate inductor current signal. According to
Please note that the actual switching frequency is also the Figure 4, the ISENN is as follows :
I  DCR x
dependent on the losses in the main power stage and the ISENN = Lx
RCSx
driver characteristic. So, in order to get more accuracy
Where LX / DCRx = RXCX is held. The method can get high
switching frequency the form of the switching frequency
efficiency performance, but DCRx value will be drifted by
can be rewrote as below :
VDAC(MAX)  ICC(MAX)  (DCR  RONLS  RLL )
temperature, a NTC resistor should add in the resistor
fSW(MAX) 
VIN(MAX)  ICC(MAX)  (RONLS  RONHS )  (TON  TD  TON,VAR )  ICC(MAX)  RONLS  TD network in the IMON pin to achieve DCR x thermal
Where fSW(MAX) is the maximum switching frequency, compensation.
VDAC(MAX) is the maximum application VID, VIN(MAX) is the
It's noted that, in order to avoid current amplifier being
maximum input voltage, ICC(MAX) is the maximum load
saturated. When (ILx x DCRx) is larger than 140mV, the
current, DCR is the inductor DC resistance, RON-HS is the
current sense method should be adopted method II as
equivalent high-side RDS(ON), RON-LS is the equivalent low-
illustrated in Figure 5. According to Figure 5, the RX is as
side RDS(ON), TD is the driver dead time , RLL is the loadline
follows :
value, TON,VAR is the TON variation value.
Rx = Rx1 // RX2
Above method can keep the constant current ripple,
The resistance accuracy of RCSx is recommended to be
whether VIN and VID are variation. But this method will
1% or higher. And in order to get impedance matching,
generate large power consumption on TONSET pin. In
the RCSx must be placed 680Ω resistor.
order to reduce the power consumption on TONSET pin,
here can connect a resister RTON between VCC and ILx VCORE

TONSET pin to set the on-time width. Lx DCRx

The on-time width equation can be rewritten as below. Rx Cx

ISENN
For SET3 pin fSW ≤ 500kHz, +
ISENP

RCSx
RTON  C  0.22 - ISENN
TON 
VCC  VDAC
 VDAC  1.2V 
R  C  VDAC / 5.45
TON  TON
VCC  1.2
 VDAC  1.2V  Figure 4. Lossless Current Sense Method I

For SET3 pin fSW > 500kHz, ILx VCORE

RTON  C  0.11
TON 
VCC  VDAC
 VDAC  1.2V  Lx DCRx

Rx1 Cx
R  C  VDAC / 10.9
TON  TON
VCC  1.2
 VDAC  1.2V  ISENN
ISENP
+
RCSx Rx2
This method can saving power disspation on TONSET pin - ISENN

but it will loss the constant current ripple merit. So, this
method can be used under VIN is fixed application. Figure 5. Lossless Current Sense Method II

Current Sense
Thermal Compensation for Current Sense
In the RT8199B, the current signal is used for load-line
Thermal Compensation for Current Sense is a patented
setting and OC (Over Current) protection. The inductor
topology, unlike conventional current sense method
current sense method adopts the lossless current sensing
requiring a NTC resistor in per phase current loop for
for allowing high efficiency as illustrated in the Figure 4.

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24
RT8199B
thermal compensation. That is to say, this current sense Load-Line (Droop) Setting
of thermal compensation method can be applied to multi- The G-NAVPTM topology can set load-line (droop) via the
phase condition and it only needs one NTC resistor. So, current loop and the voltage loop, the load-line is a slope
the NTC resistor cost can be saved by using the method. between load current ICC and output voltage VCORE as
Figure 6 and Figure 7 show the current sense method shown in Figure 8. Figure 9 shows the voltage control and
which connecting the resistor network between the IMON current loop. By using both loops, the load-line (droop)
and VREF pins to set a part of current loop gain for load- can easily be set. The load-line set equation is :
line (droop) setting and set accurate over current 1 DCR x
  REQ
protection. AI 3 RCSx
RLL = = (m )
AV R2
The method I current sense network equation is as follows :
DCR x R1
VIMON  VREF =  REQ  ILx The load-line can be set to zero by SET3 pin.
RCSx
VCORE
The method II current sense network equation is as follows :
DCR x R x2
VIMON  VREF =  REQ  ILx 
RCSx R x1 + R x2 Load-line slope = -RLL
RLL x ICC
REQ includes a NTC resistor to compensate DCRx thermal
drifting for high accuracy load-line (droop).
VCORE ICC
IMON ILx
VIMON Lx DCRx Figure 8. Load-Line (Droop)
Rx Cx
RNTC
VCORE
ISENN ISENP R2
REQ +
RCSx Voltage Loop TON Generator
- ISENN -
ILx R1 +
+
-
DCRx Lx
VID 1/3
+
-
Rx

VREF Cx RNTC
ISENP ISENN
+
- IMON VREF
RCS ISENN
Figure 6. Total Current Sense Method I Network REQ

Figure 9. Voltage Loop and Current Loop

VCORE
IMON ILx
VIMON Lx DCRx
Compensator Design
Rx1 Cx1
RNTC The compensator of RT8199B doesn't need a complex
ISENN ISENP
REQ +
Rx2
type II or type III compensator to optimize control loop
- ISENN RCSx
performance. It can adopt a simple type I compensator
(one pole, one zero) in G-NAVPTM topology to achieve
constant output impedance design for Intel VR12.1 ACLL
VREF specification. The one pole one zero compensator is
shown as Figure 10, the transfer function of compensator
should be designed as the following transfer function to
Figure 7. Total Current Sense Method II Network achieve constant output impedance, i.e. Zo(s) = load-line
slope in the entire frequency range :

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25
RT8199B
s Function 2 Function 1 80µA
1+ <5:0> <5:0>
AI   fSW
GCON (s)  
RLL s
1+ ADC
ESR VCC

Where AI is current loop gain, RLL is load-line, fSW is Function 1

Register R1
switching frequency and ωESR is a pole that should be
SET[1:3]
located at 1 / (COUT x ESR). Then, the C1 and C2 should
be designed as follows : Function 2 R2
Register SetGND
1
C1 =
R1   fSW
COUT  ESR Function 2 Function 1 80µA
C2 = <5:0> <5:0>
R2
It is noted that, the values of C1 and C2 may fine tune for ADC
VCC
better experimental performance.
C2 Function 1
Register R1
C1 R2 SET[1:3]

-
R1 Function 2 R2
+ Register
SetGND

VID
Figure 11. Multi-Function Pin Setting Mechanism
Figure 10. Type I Compensator
Connecting a R3 resistor from the SET[1:3] pin to the
Multi-Function Pin Setting Mechanism
middle node of voltage divider can help to fine tune the set
For reducing total pin number of package, the SET[1:3] voltage of Function 2, which does not affect the set voltage
pins adopt the multi-function pin setting mechanism in of Function 1. The Figure 12 shows the setting method
RT8199B. Figure 11 illustrates this operating mechanism. and the set voltage of Function 1 and Function 2 can be
First, external voltage divider is to set the Function 1 and represented as :
then internal current source 80μA is to set the Function R2
VFunction 1 =  VCC
2. The setting voltage of Function 1 and Function 2 can R1 + R2
be represented as follows :  R1 R2 
VFunction 2 = 80 A   R3 + 
R2  R1 + R2 
VFunction 1 =  VCC
R1 + R2
R1 R2 Function 2 Function 1
80µA
VFunction 2 = 80 A  <5:0> <5:0>
R1 + R2
All function setting will be done within 500μs after power ADC
VCC
ready (POR).
Function 1
If VFunction 1 and VFunction 2 are determined, R1 and R2 can Register R1
be calculated as follows : SET[1:3] R3
V V
R1 = CC Function 2 Function 2 R2
80 A  VFunction 1 Register
SetGND
R1 VFunction1
R2 =
VCC  VFunction1
In addition, Richtek provides a Microsoft Excel-based
spreadsheet to help design the SETx resistor network for
RT8199B.
Copyright © 2015 Richtek Technology Corporation. All rights reserved. is a registered trademark of Richtek Technology Corporation.

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RT8199B
Function 2 Function 1 The output voltage signal behavior needs to be detected
<5:0> <5:0> 80µA
so that QR mechanism can be trigged. The output voltage
ADC
signal is via a remote sense line to connect at VSEN pin
VCC that is shown in Figure 14. The QR mechanism needs to
Function 1 set QR width and QR threshold. Both definitions are shown
Register R1
R3
in Figure 13. A proper QR mechanism set can meet different
SET[1:3]
applications. The SET2 pin is a multi-function pin which
Function 2 R2 can set QR threshold, QR width and ICCMAX.
Register SetGND

Figure 12. Multi-Function Pin Setting Mechanism with a Current Mirror

VCC_SENSE
R3 resistor to fine tune the set voltage of function 2 VID +
QR trigger
-
Quick Response (QR) Mechanism RQR VSEN
IMirror
When the transient load step-up becomes quite large, it
is difficult for loop response to meet the energy transfer.
Hence, that output voltage generate undershoot to fail
specification. The RT8199B has Quick Response (QR) Figure 14. Simplified QR Trigger Schematic
mechanism being able to help improve this issue. It adopts
An internal current source 80μA is used in multi-function
a nonlinear control mechanism which can enlarge the on
pin setting mechanism. For example, 25mV QR threshold
time of PWM signal at instantaneous step-up transient
and 1.3 x TON QR width are set according to the Table 4,
load to restrain the output voltage drooping, Figure 13
the set voltage should be between 0.6506V and 0.6725V.
shows the QR behavior.
Please note that a high accuracy resistor is needed for
QR Width
this setting accuracy, <1% error tolerance is
recommended.

VCORE QR Threshold In the Table 4, there are some “No Use” marks at QR
Width section. It means that user should not use it to
avoid the possibility of shift digital code due to tolerance
concern.
PWM

Load

Figure 13. Quick Response Mechanism

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RT8199B
Table 4. SET2 Pin Setting for QR Threshold and QR Width
R1 R2
VQR_SET = 80  A 
R1 R2 QR QR Width
QR_TH QRWIDTH Threshold (%TON)
Min Typical Max unit
<2:0> <2:0>
0.000 10.948 21.896 mV 000 No Use
25.024 35.973 46.921 mV 001 155%
50.049 60.997 71.945 mV 010 133%
75.073 86.022 96.970 mV 011 111%
000 Disable
100.098 111.046 121.994 mV 100 89%
125.122 136.070 147.019 mV 101 67%
150.147 161.095 172.043 mV 110 44%
175.171 186.119 197.067 mV 111 No Use
200.196 211.144 222.092 mV 000 No Use
225.220 236.168 247.116 mV 001 155%
250.244 261.193 272.141 mV 010 133%
275.269 286.217 297.165 mV 011 111%
001 15mV
300.293 311.241 322.190 mV 100 89%
325.318 336.266 347.214 mV 101 67%
350.342 361.290 372.239 mV 110 44%
375.367 386.315 397.263 mV 111 No Use
400.391 411.339 422.287 mV 000 No Use
425.415 436.364 447.312 mV 001 155%
450.440 461.388 472.336 mV 010 133%
475.464 486.413 497.361 mV 011 111%
010 20mV
500.489 511.437 522.385 mV 100 89%
525.513 536.461 547.410 mV 101 67%
550.538 561.486 572.434 mV 110 44%
575.562 586.510 597.458 mV 111 No Use
600.587 611.535 622.483 mV 000 No Use
625.611 636.559 647.507 mV 001 155%
650.635 661.584 672.532 mV 010 133%
675.660 686.608 697.556 mV 011 111%
011 25mV
700.684 711.632 722.581 mV 100 89%
725.709 736.657 747.605 mV 101 67%
750.733 761.681 772.630 mV 110 44%
775.758 786.706 797.654 mV 111 No Use
800.782 811.730 822.678 mV 000 No Use
825.806 836.755 847.703 mV 001 155%
850.831 861.779 872.727 mV 010 133%
875.855 886.804 897.752 mV 011 111%
100 30mV
900.880 911.828 922.776 mV 100 89%
925.904 936.852 947.801 mV 101 67%
950.929 961.877 972.825 mV 110 44%
975.953 986.901 997.849 mV 111 No Use

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RT8199B
R1 R2
VQR_SET = 80  A 
R1  R2 QR QR Width
QR_TH QRWIDTH Threshold (%TON)
Min Typical Max unit
<2:0> <2:0>
1000.978 1011.926 1022.874 mV 000 No Use
1026.002 1036.950 1047.898 mV 001 155%
1051.026 1061.975 1072.923 mV 010 133%
1076.051 1086.999 1097.947 mV 011 111%
101 35mV
1101.075 1112.023 1122.972 mV 100 89%
1126.100 1137.048 1147.996 mV 101 67%
1151.124 1162.072 1173.021 mV 110 44%
1176.149 1187.097 1198.045 mV 111 No Use
1201.173 1212.121 1223.069 mV 000 No Use
1226.197 1237.146 1248.094 mV 001 155%
1251.222 1262.170 1273.118 mV 010 133%
1276.246 1287.195 1298.143 mV 011 111%
110 40mV
1301.271 1312.219 1323.167 mV 100 89%
1326.295 1337.243 1348.192 mV 101 67%
1351.320 1362.268 1373.216 mV 110 44%
1376.344 1387.292 1398.240 mV 111 No Use
1401.369 1412.317 1423.265 mV 000 No Use
1426.393 1437.341 1448.289 mV 001 155%
1451.417 1462.366 1473.314 mV 010 133%
1476.442 1487.390 1498.338 mV 011 111%
111 45mV
1501.466 1512.414 1523.363 mV 100 89%
1526.491 1537.439 1548.387 mV 101 67%
1551.515 1562.463 1573.412 mV 110 44%
1576.540 1587.488 1598.436 mV 111 No Use

Dynamic VID (DVID) Compensation The RT8199B provides a DVID compensation function. A
When VID transition event occurs, a charge current will virtual charge current signal can be established by the
be generated in the loop to cause that DVID performance SET1 pin to cancel the real induced charge current signal
is deteriorated by this induced charge current, the and the virtual charge current signal is defined in Figure
phenomenon is called droop effect. The droop effect is 17. Figure 16 shows the operation of canceling droop
shown in Figure 15. When VID up transition occurs, the effect. A virtual charge current signal is established first
output capacitor will be charged by inductor current. Since and then VID signal plus virtual charge current signal is
current signal is sensed in inductor, an induced charge generated in FB pin. Hence, an induced charge current
current will appear in control loop. The induced charge signal flows to R1 and is cancelled to reduce droop effect.
current will produce a voltage drop in R1 to cause output As mention before, the charge current will be generated
voltage to have a droop effect. Due to this, VID transition when VID transition event occurs. This charge current will
performance will be deteriorated. not only deteriorated DVID performance but also may
damage power switches. Due to this, user should consider
the power rating current of power switches when choosing
the power switches.

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RT8199B
Charge current Table 5 and Table 6 show the DVID_Threshold and
VIN
L DVID_Width settings in SET1 pin, respectively. For
Q1 CO1 CO2 example, 25mV DVID_Threshold and 72μs DVID_Width
Q2
Gate
Driver
are designed (OCP sets as 110% ICCMAX, and RSET
RESR
CPU
sets as 100% Ramp current). The DVID_Threshold is set
Ai by an external voltage divider to set and the DVID_Width
Induced charge C2 Output voltage
current signal is set by an internal current source 80μA by the multi-
R2 C1
CCRCOT function pin setting mechanism. According to the Table 5
COMP - R1
VIN
- and Table 6, the DVID_Threshold set voltage should be
VID tON + EA
+ IDROOP between 1.226V and 1.248V and the DVID_Width set
VID voltage should be between 0.125V and 0.147V. Please
note that a high accuracy resistor is needed for this setting,
VID Transition
<1% error tolerance is recommended.
Figure 15. Droop Effect in VID Transition

Charge current

L
VIN
Q1 CO1 CO2
Q2 Output voltage
Gate
Driver RESR
CPU

Ai C2
Induced charge
current signal C1
R2
CCRCOT
IDROOP
VIN COMP - R1
-
VID tON + EA Virtual Charge Current
+

Slew Rate
+ VID
Control

VID
DVID Event Transition
Virtual Charge
Current SET1
Generator

Figure 16. DVID Compensation

DVID_Width

DVID_Threshold

Figure 17. Definition of Virtual Charge Current Signal

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RT8199B
Table 5. SET1 Pin Setting for DVID_Threshold
R1 R2
VDVID_Threshold = 80  A 
R1  R2 DVID_Threshold OCP = %ICCMAX
DVID_TH OCS
Min Typical Max unit
<2:0> <2:0>
0.000 10.948 21.896 mV 000 No Use
25.024 35.973 46.921 mV 001 110%
50.049 60.997 71.945 mV 010 119%
75.073 86.022 96.970 mV 011 128%
111 85mV
100.098 111.046 121.994 mV 100 138%
125.122 136.070 147.019 mV 101 147%
150.147 161.095 172.043 mV 110 156%
175.171 186.119 197.067 mV 111 No Use
200.196 211.144 222.092 mV 000 No Use
225.220 236.168 247.116 mV 001 110%
250.244 261.193 272.141 mV 010 119%
275.269 286.217 297.165 mV 011 128%
110 75mV
300.293 311.241 322.190 mV 100 138%
325.318 336.266 347.214 mV 101 147%
350.342 361.290 372.239 mV 110 156%
375.367 386.315 397.263 mV 111 No Use
400.391 411.339 422.287 mV 000 No Use
425.415 436.364 447.312 mV 001 110%
450.440 461.388 472.336 mV 010 119%
475.464 486.413 497.361 mV 011 128%
101 65mV
500.489 511.437 522.385 mV 100 138%
525.513 536.461 547.410 mV 101 147%
550.538 561.486 572.434 mV 110 156%
575.562 586.510 597.458 mV 111 No Use
600.587 611.535 622.483 mV 000 No Use
625.611 636.559 647.507 mV 001 110%
650.635 661.584 672.532 mV 010 119%
675.660 686.608 697.556 mV 011 128%
100 55mV
700.684 711.632 722.581 mV 100 138%
725.709 736.657 747.605 mV 101 147%
750.733 761.681 772.630 mV 110 156%
775.758 786.706 797.654 mV 111 No Use
800.782 811.730 822.678 mV 000 No Use
825.806 836.755 847.703 mV 001 110%
850.831 861.779 872.727 mV 010 119%
875.855 886.804 897.752 mV 011 128%
011 45mV
900.880 911.828 922.776 mV 100 138%
925.904 936.852 947.801 mV 101 147%
950.929 961.877 972.825 mV 110 156%
975.953 986.901 997.849 mV 111 No Use

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RT8199B
R1 R2
VDVID_Threshold = 80 A 
R1  R2 DVID_Threshold OCP = %ICCMAX
DVID_TH OCS
Min Typical Max unit
<2:0> <2:0>
1000.978 1011.926 1022.874 mV 000 No Use
1026.002 1036.950 1047.898 mV 001 110%
1051.026 1061.975 1072.923 mV 010 119%
1076.051 1086.999 1097.947 mV 011 128%
010 35mV
1101.075 1112.023 1122.972 mV 100 138%
1126.100 1137.048 1147.996 mV 101 147%
1151.124 1162.072 1173.021 mV 110 156%
1176.149 1187.097 1198.045 mV 111 No Use
1201.173 1212.121 1223.069 mV 000 No Use
1226.197 1237.146 1248.094 mV 001 110%
1251.222 1262.170 1273.118 mV 010 119%
1276.246 1287.195 1298.143 mV 011 128%
001 25mV
1301.271 1312.219 1323.167 mV 100 138%
1326.295 1337.243 1348.192 mV 101 147%
1351.320 1362.268 1373.216 mV 110 156%
1376.344 1387.292 1398.240 mV 111 No Use
1401.369 1412.317 1423.265 mV 000 No Use
1426.393 1437.341 1448.289 mV 001 110%
1451.417 1462.366 1473.314 mV 010 119%
1476.442 1487.390 1498.338 mV 011 128%
000 15mV
1501.466 1512.414 1523.363 mV 100 138%
1526.491 1537.439 1548.387 mV 101 147%
1551.515 1562.463 1573.412 mV 110 156%
1576.540 1587.488 1598.436 mV 111 No Use

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RT8199B
Table 6. SET1 Pin Setting for DVID_Width
R2
VDVID_Width =  5V
R1  R2 RSET % 300kHz DVID_Width
RSET DVID_WTH
Min Typical Max unit
<3:0> <1:0>
0.000 10.948 21.896 mV 00 No Use
25.024 35.973 46.921 mV 01 72s
0000 83%
50.049 60.997 71.945 mV 10 96s
75.073 86.022 96.970 mV 11 No Use
100.098 111.046 121.994 mV 00 No Use
125.122 136.070 147.019 mV 01 72s
0001 100%
150.147 161.095 172.043 mV 10 96s
175.171 186.119 197.067 mV 11 No Use
200.196 211.144 222.092 mV 00 No Use
225.220 236.168 247.116 mV 01 72s
0010 117%
250.244 261.193 272.141 mV 10 96s
275.269 286.217 297.165 mV 11 No Use
300.293 311.241 322.190 mV 00 No Use
325.318 336.266 347.214 mV 01 72s
0011 133%
350.342 361.290 372.239 mV 10 96s
375.367 386.315 397.263 mV 11 No Use
400.391 411.339 422.287 mV 00 No Use
425.415 436.364 447.312 mV 01 72s
0100 150%
450.440 461.388 472.336 mV 10 96s
475.464 486.413 497.361 mV 11 No Use
500.489 511.437 522.385 mV 00 No Use
525.513 536.461 547.410 mV 01 72s
0101 167%
550.538 561.486 572.434 mV 10 96s
575.562 586.510 597.458 mV 11 No Use
600.587 611.535 622.483 mV 00 No Use
625.611 636.559 647.507 mV 01 72s
0110 183%
650.635 661.584 672.532 mV 10 96s
675.660 686.608 697.556 mV 11 No Use
700.684 711.632 722.581 mV 00 No Use
725.709 736.657 747.605 mV 01 72s
0111 200%
750.733 761.681 772.630 mV 10 96s
775.758 786.706 797.654 mV 11 No Use
800.782 811.730 822.678 mV 00 No Use
825.806 836.755 847.703 mV 01 72s
1000 217%
850.831 861.779 872.727 mV 10 96s
875.855 886.804 897.752 mV 11 No Use
900.880 911.828 922.776 mV 00 No Use
925.904 936.852 947.801 mV 01 72s
1001 233%
950.929 961.877 972.825 mV 10 96s
975.953 986.901 997.849 mV 11 No Use

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RT8199B
R2
VDVID_Width =  5V
R1  R2 RSET % 300kHz DVID_Width
RSET DVID_WTH
Min Typical Max unit
<3:0> <1:0>
1000.978 1011.926 1022.874 mV 00 No Use
1026.002 1036.950 1047.898 mV 01 72s
1010 250%
1051.026 1061.975 1072.923 mV 10 96s
1076.051 1086.999 1097.947 mV 11 No Use
1101.075 1112.023 1122.972 mV 00 No Use
1126.100 1137.048 1147.996 mV 01 72s
1011 267%
1151.124 1162.072 1173.021 mV 10 96s
1176.149 1187.097 1198.045 mV 11 No Use
1201.173 1212.121 1223.069 mV 00 No Use
1226.197 1237.146 1248.094 mV 01 72s
1100 283%
1251.222 1262.170 1273.118 mV 10 96s
1276.246 1287.195 1298.143 mV 11 No Use
1301.271 1312.219 1323.167 mV 00 No Use
1326.295 1337.243 1348.192 mV 01 72s
1101 300%
1351.320 1362.268 1373.216 mV 10 96s
1376.344 1387.292 1398.240 mV 11 No Use
1401.369 1412.317 1423.265 mV 00 No Use
1426.393 1437.341 1448.289 mV 01 72s
1110 317%
1451.417 1462.366 1473.314 mV 10 96s
1476.442 1487.390 1498.338 mV 11 No Use
1501.466 1512.414 1523.363 mV 00 No Use
1526.491 1537.439 1548.387 mV 01 72s
1111 333%
1551.515 1562.463 1573.412 mV 10 96s
1576.540 1587.488 1598.436 mV 11 No Use

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RT8199B
Ramp Compensation Current Monitor, IMON
G-NAVPTM topology is one type of ripple based control RT8199B includes a current monitor (IMON) function which
that has fast transient response, no beat frequency issue can be used to detect over current protection and the
in high repetitive load frequency operation and low BOM maximum processor current ICCMAX, and also sets a
cost. But ripple based control usually has no good noise part of current gain in the load-line setting. It produces an
immunity. The RT8199B provides a ramp compensation analog voltage proportional to output current between the
to increase noise immunity and reduce jitter at the IMON and VREF pins.
switching node. Figure 18 shows the ramp compensation. The calculation of current sense method I for IMON − VREF
voltage is shown as below :
Noise Margin w/o ramp compensation DCR x
VIMON  VREF =  REQ  ILx
IMON-VREF RCSx
Where ILx is output current and the definitions of DCRx,
RCS and REQ can refer to Figure 6.
VCOMP

Maximum Processor Current Setting, ICCMAX

The maximum processor current ICCMAX can be set by
w/ ramp compensation
Noise Margin the SET2 pin. ICCMAX register is set by an external voltage
IMON-VREF divider by the multi-function mechanism. The Table 7
shows the ICCMAX setting in SET2 pin. For example,
ICCMAX = 25A, the VICCMAX needs to be set as 0.635V
VCOMP
typically. Additionally, VIMON − VREF needs to be set as
0.4V when ILx = 25A. The ICCMAX alert signal will be
pulled to low level if VIMON − VREF = 0.4V.
Figure 18. Ramp Compensation

For the RT8199B, the ramp compensation also needs to

be considered during mode transition from PS0/1 to PS2.
For achieving smooth mode transition into PS2, a proper
ramp compensation design is necessary. Since the ramp
compensation needs to be proportional to the switching
frequency, in others words, ramp compensation is
dependent on switching frequency. The Table 6 shows
the relationship between switching frequency and ramp
compensation. For example, when designed switching
frequnecy is 400kHz, the RAMP is set as 400kHz  100% .
300kHz

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RT8199B
Table 7. SET2 Pin Setting for ICCMAX
R2
VICCMAX =  5V
R1 R2 ICCMAX Unit
Min Typical Max Unit
0.000 9.384 18.768 mV 0 A
25.024 34.409 43.793 mV 1 A
50.049 59.433 68.817 mV 2 A
75.073 84.457 93.842 mV 3 A
100.098 109.482 118.866 mV 4 A
125.122 134.506 143.891 mV 5 A
150.147 159.531 168.915 mV 6 A
175.171 184.555 193.939 mV 7 A
200.196 209.580 218.964 mV 8 A
225.220 234.604 243.988 mV 9 A
250.244 259.629 269.013 mV 10 A
275.269 284.653 294.037 mV 11 A
300.293 309.677 319.062 mV 12 A
325.318 334.702 344.086 mV 13 A
350.342 359.726 369.110 mV 14 A
375.367 384.751 394.135 mV 15 A
400.391 409.775 419.159 mV 16 A
425.415 434.800 444.184 mV 17 A
450.440 459.824 469.208 mV 18 A
475.464 484.848 494.233 mV 19 A
500.489 509.873 519.257 mV 20 A
525.513 534.897 544.282 mV 21 A
550.538 559.922 569.306 mV 22 A
575.562 584.946 594.330 mV 23 A
600.587 609.971 619.355 mV 24 A
625.611 634.995 644.379 mV 25 A
650.635 660.020 669.404 mV 26 A
675.660 685.044 694.428 mV 27 A
700.684 710.068 719.453 mV 28 A
725.709 735.093 744.477 mV 29 A
750.733 760.117 769.501 mV 30 A

Anti-Overshoot Function
When DVID slew rate increases, loop response is difficult load transient condition. When Anti-overshoot function is
to meet energy transfer so that output voltage generates triggered, the UGATE and LGATE signal will be masked
overshoot to fail specification. The RT8199B has Anti- to reduce the overshoot. The Table 8 shows the Anti-
Overshoot function being able to help improve this issue. Overshoot setting in SET3 pin and this function can be
The VR will turn off low-side MOSFET when output voltage enabled/disabled by SET3 pin under load transient
ramps up to the target VID (ALERT signal be pulled low). condition. Please note that, this function is always enabled
This function also can improve the overshoot during the under DVID condition.

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RT8199B
Zero Load-Line VR Address Setting
The RT8199B adopts G-NAVPTM (Green Native AVP), In VR 12.1 Intel SVID protocol, the data packet will contain
which is Richtek's proprietary topology derived from finite a 4 bit addressing code for future platform flexibility. The
DC gain compensator with current mode control, making RT8199B provides a VR address setting function that can
it an easy to set the PWM controller, meeting all Intel be set by SET3 pin. The VR will react according to the
CPU requirements of AVP (Active Voltage Positioning). SVID command when VR addressing setting bit is the
The RT8199B also can support zero load-line application. same with the CPU addressing code. When VR addressing
This function can be enabled/disabled by SET3 pin, as setting bit and the CPU addressing code are different, the
shown in Table 8. VR will skip the SVID command.
The Table 8 and Table 9 show the VR Address setting in
Shrink TON
SET3 pin. It is noted that VR Address constructs from
In order to reduce ripple at PS2 and PS3. RT8199B support
MSB and LSB. The Table 10 shows the more clearly
shrink on-time function. If this function is enabled, the on-
relation about the real VR Address.
time at PS2 and PS3 will be 65% on-time of PS0. But the
switching frequency will be faster at PS2 and PS3.

Table 8. SET3 Pin Setting for Function 1

R2
VSET3_1   5V VR Address
R1 R2 Anti-Overshoot Zero Load-Line
MSB
Min Typical Max Unit
0.000 10.948 21.896 mV
25.024 35.973 46.921 mV
50.049 60.997 71.945 mV
75.073 86.022 96.970 mV
0
100.098 111.046 121.994 mV
125.122 136.070 147.019 mV
150.147 161.095 172.043 mV
175.171 186.119 197.067 mV
Disable
200.196 211.144 222.092 mV
225.220 236.168 247.116 mV
250.244 261.193 272.141 mV
275.269 286.217 297.165 mV
Disable 1
300.293 311.241 322.190 mV
325.318 336.266 347.214 mV
350.342 361.290 372.239 mV
375.367 386.315 397.263 mV
400.391 411.339 422.287 mV
425.415 436.364 447.312 mV
450.440 461.388 472.336 mV
475.464 486.413 497.361 mV
Enable 0
500.489 511.437 522.385 mV
525.513 536.461 547.410 mV
550.538 561.486 572.434 mV
575.562 586.510 597.458 mV

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RT8199B
R2
VSET3_1   5V VR Address
R1 R2 Anti-Overshoot Zero Load-Line
MSB
Min Typical Max Unit
600.587 611.535 622.483 mV
625.611 636.559 647.507 mV
650.635 661.584 672.532 mV
675.660 686.608 697.556 mV
Disable Enable 1
700.684 711.632 722.581 mV
725.709 736.657 747.605 mV
750.733 761.681 772.630 mV
775.758 786.706 797.654 mV
800.782 811.730 822.678 mV
825.806 836.755 847.703 mV
850.831 861.779 872.727 mV
875.855 886.804 897.752 mV
0
900.880 911.828 922.776 mV
925.904 936.852 947.801 mV
950.929 961.877 972.825 mV
975.953 986.901 997.849 mV
Disable
1000.978 1011.926 1022.874 mV
1026.002 1036.950 1047.898 mV
1051.026 1061.975 1072.923 mV
1076.051 1086.999 1097.947 mV
1
1101.075 1112.023 1122.972 mV
1126.100 1137.048 1147.996 mV
1151.124 1162.072 1173.021 mV
1176.149 1187.097 1198.045 mV
Enable
1201.173 1212.121 1223.069 mV
1226.197 1237.146 1248.094 mV
1251.222 1262.170 1273.118 mV
1276.246 1287.195 1298.143 mV
0
1301.271 1312.219 1323.167 mV
1326.295 1337.243 1348.192 mV
1351.320 1362.268 1373.216 mV
1376.344 1387.292 1398.240 mV
Enable
1401.369 1412.317 1423.265 mV
1426.393 1437.341 1448.289 mV
1451.417 1462.366 1473.314 mV
1476.442 1487.390 1498.338 mV
1
1501.466 1512.414 1523.363 mV
1526.491 1537.439 1548.387 mV
1551.515 1562.463 1573.412 mV
1576.540 1587.488 1598.436 mV

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RT8199B
Table 9. SET3 Pin Setting for Function 2
VR
Switching
Min Typical Max unit Address Shrink T ON ZCD_TH<1:0>
Frequency
LSB

0.000 23.46041 46.921 mV 0.75mV

50.049 73.48485 96.921 mV 1.5mV

Disable
100.098 123.5093 146.921 mV 2.25mV
150.147 173.5337 196.921 mV 3mV
FSW > 500kHz
200.196 223.5582 246.921 mV 0.75mV
250.244 273.5826 296.921 mV 1.5mV
Enable
300.293 323.607 346.921 mV 2.25mV
350.342 373.6315 396.921 mV 3mV
1
400.391 423.6559 446.921 mV 0.75mV
450.440 473.6804 496.921 mV 1.5mV
Disable
500.489 523.7048 546.921 mV 2.25mV
550.538 573.7292 596.921 mV 3mV
FSW ≦ 500kHz
600.587 623.7537 646.921 mV 0.75mV
650.635 673.7781 696.921 mV 1.5mV
Enable
700.684 723.8025 746.921 mV 2.25mV
750.733 773.827 796.921 mV 3mV

800.782 823.8514 846.921 mV 0.75mV

850.831 873.8759 896.921 mV 1.5mV

Disable
900.880 923.9003 946.921 mV 2.25mV
950.929 973.9247 996.921 mV 3mV
FSW > 500kHz
1000.978 1023.949 1046.921 mV 0.75mV
1051.026 1073.974 1096.921 mV 1.5mV
Enable
1101.075 1123.998 1146.921 mV 2.25mV
1151.124 1174.022 1196.921 mV 3mV
0
1201.173 1224.047 1246.921 mV 0.75mV
1251.222 1274.071 1296.921 mV 1.5mV
Disable
1301.271 1324.096 1346.921 mV 2.25mV
1351.320 1374.12 1396.921 mV 3mV
FSW ≦ 500kHz
1401.369 1424.145 1446.921 mV 0.75mV
1451.417 1474.169 1496.921 mV 1.5mV
Enable
1501.466 1524.194 1546.921 mV 2.25mV
1551.515 1574.218 1596.921 mV 3mV

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RT8199B
Table 10. Composing about Real VR Address
VR Address
Real VR Address
MSB/LSB
0 0 0
0 1 1
1 0 4
1 1 5

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RT8199B
Over Current Protection between 0V and −0.05V due to OVP latch and NVP
The RT8199B has dual OCP mechanism. One is named triggering. The NVP function will be active only after OVP
OCP-SUM, the other is called OCP-SPIKE. The over is triggered.
current protection (OCP) forces high-side MOSFET and
Under Voltage Protection
low-side MOSFET off by shutting down internal PWM logic
drivers. RT8199B provides OCP-SUM which is set by SET1 When the VSEN pin voltage is 350mV less than VID, a
pin. The OCP-SUM threshold setting can refer to ICCMAX UVP will be latched. When UVP latched, both the UGATE
current in the Table 7. For example, if ICCMAX is set as and LGATE will be pulled-low. A 3.5μs delay is used in
25A, user can set voltage by using the external voltage UVP detection circuit to prevent false trigger. Besides,
divider in SET1 pin as 1.262V typically if DVID_Threshold the UVP function is masked when dynamic VID transient
= 25mV, then 30A OCP-SUM (120% x ICCMAX) threshold occurs and after dynamic VID transition, UVP is masked
will be set. When output current is higher than the OCP- for 80μs.
SUM threshold, OCP-SUM is latched with a 40μs delay
Under Voltage Lock Out (UVLO)
time to prevent false trigger. Besides, the OCP-SUM
During normal operation, if the voltage at the VCC pin
function is masked when dynamic VID transient occurs
drops below POR threshold 4.1V (min), the VR will trigger
and after dynamic VID transition, OCP-SUM is masked
UVLO. The UVLO protection forces high-side MOSFET
for 80μs. The other one is per phase OCP which should
and low-side MOSFET off by shutting down internal PWM
trip when the output current exceeds quintuple ICCMAX
logic drivers.
during soft-start. When output current is higher than the
per phase OCP threshold, per phase OCP is latched with Power Ready (POR) Detection
a 1μs delay time to prevent false trigger. Please note that,
During start-up, the RT8199B will detect the voltage at
here is no OCP at PS3.
the voltage input pins : VCC, EN and PVCC. When VCC >
Over Output Voltage Protection 4.1V and PVCC > 4V the RT8199B will recognize the
power state of system to be ready (POR = high) and wait
There are two conditions for OVP. One is when VSEN is
for enable command at the EN pin. After POR = high and
higher than 1.2V. The other is when VSEN is smaller than
VEN > 0.7V, the RT8199B will enter start-up sequence. If
1.2V. For VSEN is higher than 1.2V, OVP condition is
the voltage at any voltage pin drops below low threshold
detected when the VSEN pin is 350mV more than VID.
(POR = low), the RT8199B will enter power down
For VSEN is smaller than 1.2V, OVP is occurred when
sequence and all the functions will be disabled. Normally,
VSEN is higher than 1.55V. When OVP condition is
connecting system voltage VTT (1.05V) to the EN pin is
detected, the upper gate voltage UGATE is pulled-low and
recommended.1ms (max) after the chip has been enabled,
lower gate voltage LGATE is pulled-high. OVP is latched
the SVID circuitry will be ready. All the protection latches
with a 0.5us delay time to prevent false trigger.
(OVP, OCP, UVP) will be cleared only by VCC. The
Negative Voltage Protection condition of VEN = low will not clear these latches. Figure
Since the OVP latch continuously turns on low-side 19 and Figure 20 show the POR detection and the timing
MOSFET of the VR, the VR will suffer negative output chart for POR process, respectively.
voltage. When the VSEN detects a voltage below −0.05V 5V
VCC
+
CP

after triggering OVP, the VR will trigger NVP to turn off 4.1V -

low-side MOSFET of the VR while the high-side MOSFET PVCC

PVCC
DRIVER POR

remains off. After triggering NVP, if the output voltage rises

Enable
above 0V, the OVP latch will restart to turn on low-side VTT EN
+
CP
1.05V
MOSFET. Therefore, the output voltage may bounce 0.7V -

Figure 19. POR Detection

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RT8199B
divider elements (R1, R2 and NTC) so that VTSEN = 1.887V
VCC
at 100°C. The resistance accuracy of TSEN network is
PVCC recommended to be 1% or higher.
R2
POR VTSEN = VCC  = 1.887V
R2 + R1//RNTC(100C) 
EN 1ms VDDIO
SVID Invalid Valid Invalid
VR_HOT

VCC
Figure 20. Timing Chart for POR Process

Precise Reference Current Generation, IBIAS R1 NTC

Analog circuits need very precise reference voltage/current TSEN

+
to drive/set these analog devices. The RT8199B provides -
R2
a 2V voltage source at the IBIAS pin, and a 100kΩ resistor 1.887V
SetGND
is required to be connected between IBIAS pin and analog
ground to generate a very precise reference current. Figure 22. VR_HOT Circuit
Through this connection, the RT8199B will generate a VBOOT
20μA current from the IBIAS pin to analog ground, and The RT8199B provides controllable VBOOT function as
this 20μA current will be mirrored inside the RT8199B for shown in Figure 23. The VBOOT voltage can be set by
internal use. The IBIAS pin can only be connected with a the VBOOTSEL pin. Table 11 shows the VBOOT voltage
100kΩ resistor to GND for internal analog circuit use. The setting in VBOOTSEL pin. For example, when VBOOT =
resistance accuracy of this resistor is recommended to 1V, the VBOOTSEL set voltage will be between 1.3V and
be 1% or higher. Figure 21 shows the IBIAS setting circuit. 3.7V. It's noted that, if floating VBOOTSEL pin that the
Current Mirror VBOOT voltage will not be defined.
VCC
2V + 20µA
- R1

VBOOTSEL
IBIAS
100k R2
SetGND

Figure 21. IBIAS Setting Circuit

Figure 23. VBOOTSEL Circuit.

TSEN and VR_HOT Table 11. VBOOTSEL Pin setting for VBOOT
The VR_HOT signal is an open-drain signal which is used R2
VBOOTSEL   5V
for VR thermal protection. When the sensed voltage in R1  R2 VBOOT
TSEN pin is over 1.887V under VCC is exact 5V condition, Min Typical Max Unit
the VR_HOT signal will be pulled-low to notify CPU that 0 0.6 1.2 V 0.9
the thermal protection needs to work. Please note that, 1.3 2.5 3.7 V 1.0
the VR thermal protection is only valid under PS0, PS1 3.8 4.4 5 V 1.1
and PS2 condition. According to Intel VR definition,
VR_HOT signal needs acting if VR power chain Differential Remote Sense Setting
temperature exceeds 100°C. Placing an NTC thermistor The VR provides differential remote-sense inputs to
at the hottest area in the VR power chain and its eliminate the effects of voltage drops along the PC board
connection is shown in Figure 22, to design the voltage traces as signified as Figure 24. CPU internal power routes
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RT8199B
and socket contacts. The CPU contains on-die sense pins, Lx
R x  Cx =
VCC_SENSE and VSS_SENSE. Connecting RGND to VSS_SENSE DCR x
and connect FB to VCC_SENSE with a resistor to build the VCORE
IOUT x RLL
negative input path of the error amplifier. The VDAC and the
precision voltage reference are referred to RGND for
accurate remote sensing. IOUT
CPU VCC_SENSE IOUT

VOUT Expected load transient waveform

FB R1
-
EA
+ COUT Lx
+ R x  Cx <
DCR x
VID
-
VCORE
RGND R2 IOUT x RLL

CPU VSS_SENSE
IOUT
Figure 24. Remote Sensing Circuit
IOUT
Current Loop Design in Details Undershoot created in VCORE
VCORE
ILx
Lx DCRx
Lx
VREF
Rx Cx R x  Cx >
REQ DCR x
VCORE
ISENN ISENP IOUT x RLL
RNTC IMON +
- ISENN 680

0.6V - IOUT
+

2/3
IOUT
- Sluggish droop
COMP + +
Figure 26. All Kind of RXCX Constants

Figure 25. Current Loop Structure For DCLL performance and ICCMAX accuracy, since the
Figure 25 shows the whole current loop structure. The copper wire of inductor has a positive temperature
current loop plays an important role in RT8199B that can coefficient, when temperature goes high in the heavy load
decide ACLL performance (for load-line is required condition then DCR value goes large simultaneously. A
condition), DCLL accuracy and ICCMAX accuracy. For resistor network with NTC thermistor compensation
ACLL performance, the correct compensator design is connecting between IMON pin and REF pin is necessary,
assumed, if RC network time constant matches inductor to compensate the positive temperature coefficient of
time constant LX / DCRX, an expected load transient inductor DCR. The design flow is as follows :
waveform can be designed. If RXCX network time constant Step1 : Given the three system temperature TL, TR and
is larger than inductor time constant LX / DCRX, VCORE TH, at which are compensated.
waveform has a sluggish droop during load transient. If
Step2 : Three equations can be listed as
RXCX network is smaller than inductor time constant 1
DCR (TL )
LX / DCRX, a worst VCORE waveform will sag to create an
680
  iLi  REQ (TL ) = 0.4
undershoot to fail the specification. Figure 26 shows the i=1
1
DCR (TR )
variety of RXCX constant corresponding to the output
waveforms. 680
  iLi  REQ (TR ) = 0.4
i=1

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RT8199B
1 Design Step
DCR (TH )
680
  iLi  REQ (TH ) = 0.4
RT8199B Excel based design tool is available. Users can
i=1
contact your Richtek representative to get the
Where :
spreadsheet. Three main design procedures of RT8199B
(1) The relationship between DCR and temperature is as design, first step is initial settings, second step is loop
follows : design and last step is protection settings. The following
DCR (T) = DCR (25C)  1+ 0.00393 (T - 25) design example is to explain RT8199B design procedure:
(2) REQ(T) is the equivalent resistor of the resistor network VCORE Specification
with a NTC thermistor
Input Voltage 7.4

REQ (T) = RIMON1 + RIMON2 / / RIMON3 + RNTC (T)  No. of Phase 1
And the relationship between NTC and temperature is as VBoot 1
follows : ICCMAX 13
1 1
β(  )
RNTC (T) = RNTC (25C)  e T+273 298 ICC-Dyn 8

β is in the NTC thermistor datasheet. MAX Switching Frequency 800kHz

Step3 : Three equations and three unknowns, RIMON1, The output filter requirements of VRTB specification are
RIMON2 and RIMON3 can be found out unique solution. as follows :
RIMON2  (RNTCTR +RIMON3 ) Output Inductor : 330nH/2.95mΩ
RIMON1 = K TR 
RIMON2 +RNTCTR +RIMON3
Output Bulk Capacitor : 270μF/2V.6mΩ (3pcs)
2 Output Ceramic Capacitor : 22μF/0603 (6pcs max sites
[KR3 +KR3 (RNTCTL +RNTCTR )
RIMON2 =
+RNTCTLRNTCTR ]α TL on top side)
(1) Initial Settings
RIMON3 = -RIMON2 +KR3
 RT8199B initial VBoot voltage is 1V
Where : R2
5 =2.5V, R1 can be selected by user and here
K TH  K TR R1+R2
α TH =
RNTCTH  RNTCTR R1 is equal to 10kΩ so R2 is equal to 10kΩ.
K TL  K TR
α TL =  IBIAS needs to connect a 100kΩ resistor to ground.
RNTCTL  RNTCTR
(2) Loop Design
(α TH / α TL )RNTCTH  RNTCTL
KR3 =
1  (α TH / α TL )  On time setting :

0.4 VIN(MAX) = 7.4V, VDAC(MAX) = 1V, FSW(MAX) = 800kHz, ICC(MAX)

K TL =
GCS(TL)  ICC-MAX = 13A, DCR = 2.95mΩ, RLL = 0Ω, RON-HS = 6mΩ, RON-LS
= 6mΩ, TD = 30ns, TON,VAR = 15ns.
K TR = 0.4
GCS(TR)  ICC-MAX Using the Microsoft Excel-based spreadsheet from
RICHTEK.
K TH = 0.4
GCS(TH)  ICC-MAX The RTON resistance can be calculated after the switching
frequency and the on-time are decided.
(V  VDAC )  TON
RTON  IN  652k
18.2p  0.11
Choosing the nearest on-time setting resistor RTON =
649kΩ
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RT8199B
 Current sensor adopts lossless RC filter to sense current Where RLL is load-line, COUT is total output capacitance
signal in DCR. For getting an expected load transient and dVID/dt is DVID fast slew rate. Here the load-line is
waveform RXCX time constant needs to match LX / DCRX. equal to zero. Thus the DVID compensation isn't work
CX = 0.47μF is set, then under the zero load-line application. So, DVID_TH and
LX DVID_Width can be set to any value. Here DVID_TH
RX   240
0.47μF  DCR X and DVID_Width are chosen as 15mV and 72μs,
But RX = 240Ω will let REQ is too small, so here the current respectively. Next, OCP threshold I is designed as 1.28
sense method 2 should be selected. By using the design x ICCMAX. Last, RAMP = 800kHz / 300kHz = 267%,
tool, Rx1 and Rx2 can be determined, both are equal to 267% is set. By using above information, the two
475Ω. equations can be listed by using multi-function pin
 IMON resistor network design : TL = 25°C, TR = 50°C setting mechanism :
and TH = 100°C are decided, NTC thermistor = 100kΩ 5 R2  1137.3mV
R1 R2
@ 25°C, β = 4050 and ICCMAX = 13A. According to the
sub-section “Current Loop Design in Details”, RIMON1 80μ  R1 R2  1487.6mV
R1 R2
= 6.63kΩ, RIMON2 = 8.83kΩ and RIMON3 = 5.44kΩ can R1 = 81.757kΩ and R2 = 24.065kΩ.
be decided. The REQ (25°C) = 14.187kΩ.
 SET2 resistor network design : The QR mechanism
 Load-line design : If load-line is required, the load-line parameters need to be designed at first. Due to the load
can be determined by below equation and the voltage current step is small and output capacitance is large,
loop AV gain is also decided by the following equation : the QR mechanism isn't necessary. The QR_TH is set
1  DCR  R to disable and QR Width is designed as 1.11 x TON. The
EQ
A V 3 RCS
RLL   (m) ICCMAX is designed as 13A. By using the information,
AI R2
R1 the two equation can be listed by using multi-function
Here the load-line isn't required. The suggestion AV gain pin setting mechanism :
is 5 to 10 for the zero load-line application. R1 = 10kΩ is 5 R2  334.7mV
R1  R2
usually decided and here R2 is chosen to 68kΩ.
80μ  R1 R2  86.02mV
 Typical compensator design can use the following R1  R2
equations to design C1 and C2 values R1 = 16.063kΩ and R2 = 1.1524kΩ.

C1  1  39.7pF  SET3 resistor network design: The zero load-line function

R1  fSW
and anti-overshoot function are decided to enable at first.
C  ESR
C2  OUT  28pF Then, the ZCD threshold is chosen as 0.75mV, shrink
R2
TON is disabled, switching frequency is chosen fSW >
For Intel platform, in order to induce the band width to 500kHz and VR address is usually set to 0. By using
enhance transient performance to meet Intel's criterion, the information, the two equations can be listed by using
the zero location can be designed close to 1/10 of the multi-function pin setting mechanism:
switching frequency or less than the 1/10 of switching 5  R2  1299.7mV
R1  R2
frequency.
80μ  R1 R2  824.24mV
 SET1 resistor network design : First, the DVID R1  R2
compensation parameters need to be decided. The R1 = 39.64kΩ and R2 = 13.92kΩ.
DVID_TH can be calculated as the following equation :
VDVID_TH  RLL  COUT  dVID
dt

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RT8199B
(3) Protection Settings 4.0

Maximum Power Dissipation (W)1

Four-Layer PCB
 OVP/UVP protections: When the VSEN pin voltage is 3.5
350mV higher than VID, the OVP will be latched. When 3.0
the VSEN pin voltage is 350mV lower than VID, the
2.5
UVP will be latched.
2.0
 TSEN and VR_HOT design : Using the following equation
to calculate related resistances for VR_HOT setting. 1.5

VTSEN  VCC  R2  1.887V 1.0

R2  RNTC(100oC) //R1
  0.5

Choosing R1 = 100kΩ and an NTC thermistor RNTC (25°C) 0.0

= 100kΩ and its β = 4485. When temperature is 100°C, 0 25 50 75 100 125

the RNTC(100°C) = 4.85kΩ. Then R2 = 2.8kΩ can be Ambient Temperature (°C)

calculated. Figure 27. Derating Curve of Maximum Power
Dissipation
Thermal Considerations
For continuous operation, do not exceed absolute Layout Considerations
maximum junction temperature. The maximum power
PCB layout is critical to achieve low switching losses and
dissipation depends on the thermal resistance of the IC
stable operation. The switching power stage requires
package, PCB layout, rate of surrounding airflow, and
particular attention. If possible, mount all of the power
difference between junction and ambient temperature. The
components on the top side of the board with their ground
maximum power dissipation can be calculated by the
terminals flushed against one another. Follow these
following formula :
guidelines for the optimum PCB layout :
PD(MAX) = (TJ(MAX) − TA) / θJA
 Keep the high current paths short, especially at the
where TJ(MAX) is the maximum junction temperature, TA is ground terminals.
the ambient temperature, and θJA is the junction to ambient
 Keep the power traces and load connections short. This
thermal resistance.
is essential for high efficiency.
For recommended operating condition specifications, the
 When trade-offs in trace lengths must be made, it's
maximum junction temperature is 125°C. The junction to
preferable to let the inductor charging path be longer
ambient thermal resistance, θJA, is layout dependent. For
than the discharging path.
WQFN-32L 4x4 package, the thermal resistance, θJA, is
27.8°C/W on a standard JEDEC 51-7 four-layer thermal  Place the current sense component close to the
test board. The maximum power dissipation at TA = 25°C controller. ISENP and ISENN connections for current
can be calculated by the following formula : limit and voltage positioning must be made using Kelvin
sense connections to guarantee current sense accuracy.
PD(MAX) = (125°C − 25°C) / (27.8°C/W) = 3.59W for
The PCB trace from the sense nodes should be
WQFN-32L 4x4 package
paralleled back to the controller.
The maximum power dissipation depends on the operating
 Route high speed switching nodes away from sensitive
ambient temperature for fixed T J(MAX) and thermal
analog areas (COMP, FB, ISENP, ISENN, etc...)
resistance, θJA. The derating curve in Figure 27 allows
the designer to see the effect of rising ambient temperature  Connect the exposed pad to the ground plane through
on the maximum power dissipation. low impedance path. Recommend use of at least 5 vias
to connect to ground planes in PCB internal layers.

www.richtek.com DS8199B-01 September 2015

46
RT8199B
Outline Dimension

1 1

2 2

DETAIL A
Pin #1 ID and Tie Bar Mark Options

Note : The configuration of the Pin #1 identifier is optional,

but must be located within the zone indicated.

Dimensions In Millimeters Dimensions In Inches

Symbol
Min. Max. Min. Max.
A 0.700 0.800 0.028 0.031
A1 0.000 0.050 0.000 0.002
A3 0.175 0.250 0.007 0.010
b 0.150 0.250 0.006 0.010
D 3.900 4.100 0.154 0.161
D2 2.650 2.750 0.104 0.108
E 3.900 4.100 0.154 0.161
E2 2.650 2.750 0.104 0.108
e 0.400 0.016
L 0.300 0.400 0.012 0.016

W-Type 32L QFN 4x4 Package

Richtek Technology Corporation

14F, No. 8, Tai Yuen 1st Street, Chupei City
Hsinchu, Taiwan, R.O.C.
Tel: (8863)5526789

Richtek products are sold by description only. Richtek reserves the right to change the circuitry and/or specifications without notice at any time. Customers should
obtain the latest relevant information and data sheets before placing orders and should verify that such information is current and complete. Richtek cannot
assume responsibility for use of any circuitry other than circuitry entirely embodied in a Richtek product. Information furnished by Richtek is believed to be
accurate and reliable. However, no responsibility is assumed by Richtek or its subsidiaries for its use; nor for any infringements of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Richtek or its subsidiaries.
DS8199B-01 September 2015 www.richtek.com
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