Lecture 1

CPU Instruction set

 What is an instruction set
● It is a language such that it can be executed
directly by the CPU hardware
● They are designed so that building the
hardware and compiler for them are easy while:
– maximising performance
– Minimising cost and energy
● In this course we will only focus on the ARM
instruction set.
 What is an assembler
● A program that converts CPU instructions text to
CPU numeric instruction code (or Op-code).
● Why? Because human are clumsy in setting the
correct numeric instruction code values. Text is more
user friendly for producing numeric instruction codes
● ARM classified as Reduced Instruction Set
Computer (RISC)
● Intel’s x86 or AMD’s 64 classified as Complete ISC
(CISC)
 To be RISC or CISC?
● CISC focus on workload efficiency. It has a larger instruction set to
reduce the code size of programs.
– The price: more complex circuitry and consumes more power.
● RISC focus on power efficiency. It has a smaller instruction set and
simpler circuitry.
– The price: code size of programs are bigger and reduce work performance
● RISC dominate in embedded and mobile computing markets where it
favours power efficiency over performance.
●
CISE dominate in high performance computing (HPC) markets (vice
versa to RISC)
● What is the Trend?
– New instruction sets are design somewhere in between.
 Common Op-code classes
● Data handling and memory operations
– Assign literal values to register
– Copy data from memory to register or vice versa
– Read / Write data from other hardware devices
●
Arithmetic and logic operations
– Integer and floating point maths operations
– Bitwise operations
● Control flow operation
– Function calls and Jump instructions
● other operations:
– Concurrency control, thread management, interrupt handling.
 Main features of the ARM
● All instructions are 32 bits long.
● Most instructions execute in a single cycle
● Most instructions can be conditionally executed
● A load/store architecture
– Data processing instructions act only on registers
● Three operand format
● Combined ALU and shifter for high speed bit manipulation
– Specific memory access instructions with powerful auto ‐indexing addressing modes.
● 32 bit and 8 bit data types
– and also 16 bit data types on ARM Architecture v4.
● Flexible multiple register load and store instructions
● Instruction set extension via coprocessors
● Very dense 16‐bit compressed instruction set (Thumb)
 The Register
●
ARM has 37 registers in total, all of which are 32‐bits long.
– 1 dedicated program counter
– 1 dedicated current program status register
– 5 dedicated saved program status registers
– 30 general purpose registers
●
However these are arranged into several banks, with the accessible bank
being governed by the processor mode. Each mode can access
– a particular set of r0‐r12 registers
– a particular r13 (the stack pointer) and r14 (link register)
– r15 (the program counter)
– cpsr (the current program status register)
● And privileged modes can also access
– a particular spsr (saved program status register)
 Processor Modes
● The ARM has six operating modes:
– User (unprivileged mode under which most tasks run)
– FIQ (entered when a high priority (fast) interrupt is raised)
– IRQ (entered when a low priority (normal) interrupt is raised)
– Supervisor (entered on reset and when a Software Interrupt
instruction is executed)
– Abort (used to handle memory access violations)
– Undef (used to handle undefined instructions)
● ARM Architecture Version 4 adds a seventh mode:
– System (privileged mode using the same registers as user mode)
ARM Register Set
The Program Status Register
(CPSR and SPSRs)
Condition Flags
 The Program Counter (R15)
● When the processor is executing in ARM state:
– All instructions are 32 bits in length
– All instructions must be word aligned
– Therefore the PC value is stored in bits [31:2] with bits [1:0] equal to zero
(as instruction cannot be halfword or byte aligned).
●
R14 is used as the subroutine link register (LR) and stores the return
address when Branch with Link operations are performed,
calculated from the PC.
●
Thus to return from a linked branch:
– MOV r15,r14
or
– MOV pc,lr
 Arithmetic Operations
●
Operations are:
– ADD operand1 + operand2; Add
– ADC operand1 + operand2 + carry; Add with carry
– SUB operand1 ‐operand2; Subtract
– SBC operand1 ‐operand2 + carry ‐1 ; Subtract with carry
– RSB operand2 ‐operand1; Reverse subtract
– RSC operand2 ‐operand1 + carry ‐1; Reverse subtract with carry
● Syntax:
– <Operation> Rd, Rn, Operand2
●
Examples
– ADD r0, r1, r2
– SUBGT r3, r3, #1
– RSBLES r4, r5, #5
 Comparisons
● Comparisons
● The only effect of the comparisons is to update the condition flags. Thus no need
to set S bit.
● Operations are:
– CMP operand1 ‐operand2; Compare
– CMN operand1 + operand2; Compare negative
– TST operand1 AND operand2; Test
– TEQ operand1 EOR operand2; Test equivalence
● Syntax:
– <Operation> Rn, Operand2
● Examples:
– CMP r0, r1
– TSTE Qr2, #5
 Logical Operators
● Operations are:
– AND operand1 AND operand2
– EOR operand1 EOR operand2
– ORR operand1 OR operand2
– ORN operand1 NOR operand2
– BIC operand1 AND NOT operand2 [ie bit clear]
● Syntax:
– <Operation>{<cond>}{S} Rd, Rn, Operand2
● Examples:
– AND r0, r1, r2
– BICEQ r2, r3, #7
– EORS r1,r3,r0
 Data Movement

●
Operations are:
– MOV operand2
– MVN NOT operand2
– Note that these make no use of operand1.
●
Syntax:
– <Operation> Rd, Operand2
●
Examples:
– MOV r0, r1
– MOVS r2, #10
– MVNEQ r1,#0