RESEARCH PAPERS

A NOVEL MULTILEVEL INVERTER WITH MINIMUM SWITCHES

By

MANJUNATHA B M * ASHOK KUMAR D V ** VIJAY KUMAR M ***

* Assistant Professor, Department of Electrical and Electronics Engineering, Rajeev Gandhi Memorial
College of Engineering and Technology, Nandyal, Andhra Pradesh, India.
** Professor, Department of Electrical and Electronics Engineering, Rajeev Gandhi Memorial
College of Engineering and Technology, Nandyal, Andhra Pradesh, India.
*** Professor, Department of Electrical and Electronics Engineering, Jawaharlal Nehru Technological
University, Anantapur, Andhra Pradesh, India.

ABSTRACT
This paper presents a unique three phase seven level inverter with reduced number of switches. Multilevel Inverters (MLI)
are used in high power and high voltage applications as they are capable of producing multiple levels in output voltage
with reduced THD. To reduce THD further the number of levels in the output voltage has to be increased, which is directly
associated with the number of switches required. To accomplish this, the conventional MLI experiences complexity in
control, number of required DC sources, size, switching losses and cost of overall system increases. The proposed
topology overcomes aforesaid limitations and compared with the conventional MLI in terms of the number of switches,
DC sources, capacitors, fundamental voltage and THD. The performance is analyzed by using simulation tool.

Keywords: Multilevel Inverter, THD, Reduced Switches, Level Shifted Carriers, Modulating Techniques.

INTRODUCTION carrier based PWM techniques are discussed in section 3,

Based on the circuit configuration the multilevel inverters the simulation results of proposed and conventional
are classified as diode clamped, flying capacitor and seven level inverters are presented in section 4, finally
cascaded [1-3]. Out of which Cascaded Multilevel conclusions are made in last section .
Inverter (CMLI) is having more advantages when 1. Single Phase Converter
compared to diode clamped and flying capacitor in For reducing the number of components, control
terms of the number of switches, control complexity and complexity, cost and size of multilevel inverter used for
voltage balancing [3]. Furthermore clamping diodes and high voltage and high power applications a novel single
flying capacitors are not required for CMLI. With phase five level inverter is explained [5]. The proposed
conventional CMLI the number of levels can be increased single phase seven level inverter is represented in Figure. 2.
by increasing the number of series connected H Bridges.
The circuit configuration of three phase CMLI is
represented in Figure 1.
This paper presents a novel seven level inverter with
reduced number of switches. The numbers of levels are
increased by increasing the number of switches instead of
adding the H bridge.
The rest of the paper is organized as follows, concept of
single phase seven level inverter with reduced number of
switches is explained in section 1, the same idea is
extended for three phase inverter section 2, different
Figure1. Three Phase CMLI Configuration

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The proposed topology is cascaded linkage of following

S1 S2 S3 S4 S5 S6 S7 Output
parts:
Part I: Level generator which generates the positive 1 1 0 0 1 0 0 Vdc

stepped waveform across the inverter

1 1 0 0 0 1 0 2Vdc
Part II: H Bridge, used for polarity reversal.
The Generalized equation to decide number of DC 1 1 0 0 0 0 1 3Vdc
sources, switches required for a proposed MLI is given
below: 0 1 1 0
0 0 0 0
Number of source required Ns= (n-1)/2 (1)
1 0 0 1
Number of switches = n (2)
Where n is the number of levels in output voltage. 0 0 1 1 1 0 0 -Vdc

The proposed seven level inverter requires three dc

0 0 1 1 0 1 0 -2Vdc
sources of equal magnitude and seven switches.
Comparison of different components required for 0 0 1 1 0 0 1 -3Vdc
conventional and proposed MLI's is shown in Table 1.
* 0 = switch turned off, 1 switch turned on
Table 2. Switching Sequence

The proposed seven level inverter is capable of producing

seven levels ±3Vdc, ±2Vdc, ±Vdc and 0 in the output
voltage waveform. The switching sequence t produce
these seven levels in the output voltage is shown in Table 2.
At any instant only three switches will be conducting. Two
switches for polarity reversal and one switch for getting the
desired voltage level in the output waveform. Single
phase Seven level inverter with nine and ten switches is
discussed [6, 7].
2. Proposed Three Phase Seven Level Topology

Figure 2. Single Phase Seven Inverter Circuit Configuration The concept of proposed single phase seven level
inverter can be easily extended to the three phase seven
DCMLI CCMLI CHMLI PMLI

DC (n-1) (n-1) (n-1)/2 (n-1)/2

Sources

Main 6*(n-1) 6*(n-1) 6*(n-1) n

Switch
Clamping 3*(n-1) 0 0 0
Diode *(n-2)

Clamping 0 1.5*(n-1) 0 0
Capacitor *(n-2)

Table 1. Comparison with Conventional MLI Figure 3. Three Phase Seven Level Inverter.

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Figure 6. Phase Opposition Disposition Carriers

Figure 4. Flow Chart of PWM Methods Classification

level inverter. The proposed three phase topology is easy

to control as the number of switches conducting at any
instant is less when compared with conventional
topology. Figure 3, represents the circuit configuration of
proposed three phase seven level inverter.
3. Carrier Based PWM Techniques
The purpose of PWM is to generate the variable voltage
and variable frequency from the fixed DC input. In PWM
techniques two signals are used, i.e., carrier and
Figure 7. Alternate Phase Opposition Disposition carriers
reference signal. When reference is greater than a carrier,
ON pulse is generated and OFF pulse is generated when With space vector method, the number of switching states
the carrier is greater than the reference [8, 9]. is equal to n3 where n represents number of levels. It is
Classification of PWM methods is shown in Figure 4. difficult to identify the sectors, sub sector and switching
sequence. The phase shifted carriers generates a lot of
harmonics in the output voltage. To overcome the intact
drawbacks the level shifted carriers are used.
·Phase Disposition (PD) : All the carrier waveforms are in
phase as shown in Figure 5.
·Phase Opposition Disposition (POD) : All carrier
waveforms above the zero reference are in phase
and 180° out of phase with those below zero. Which is
shown in Figure 6.
·Alternate Phase Disposition (APOD) : The carrier
waveforms are in out of phase with its neighbor carrier
Figure 5. Phase Disposition Carriers

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by 180° and it is shown in Figure7.

4. Simulation Results
Conventional seven level cascaded and proposed
seven level inverters are simulated with level shifted carrier
PD, POD and APOD. These inverters are simulated with the
following parameters,
Input Voltage = 100V,
Switching Frequency = 10000Hz,
Figure 9. THD and Output Voltage with POD
Modulation Index = 1

Figure 10. THD and Output Voltage with APOD

Resistive Load =100 Ω.

Figure 8 to 10 shows the simulation results for THD and the
output line to line voltage for conventional seven level
Figure 8. THD and Output Voltage with PD inverter using PD, POD and APOD PWM techniques

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Type of Type of Fundamental THD

carrier converter Voltage

PD Conventional 262 12.96

Proposed 259.4 11.78

POD Conventional 260.1 14.64

Proposed 259.6 15.49

APOD Conventional 260.1 14.3

7
Figure 11. THD and Output Voltage with PD Proposed 259.7 15.26

Table 3. Comparison of CMLI's and PMLI

respectively.
Figure 11 to 13 shows the THD and the output line to line
voltage simulation results for proposed seven level inverter
using PD, POD and APOD pwm techniques. The
comparison results are shown in Table 3.
Conclusion
This paper presents the new three phase seven level
inverter with reduced number of switches. The proposed
inverter is capable of producing the same fundamental
voltage and THD as that of conventional seven level
cascaded inverter. The proposed circuit reduces the
complexity of control, size and cost of the inverter, as the
number of components used in this circuit is equal to a
Figure 12. THD and Output Voltage with POD number of levels. The same inverter can be extended to n
levels with n switches
References
[1]. Marchesoni. M, (2002). “Diode-clamped multilevel
converters: a practicable way to balance DC-link
voltages” Industrial Electronics, IEEE Transactions, Vol. 49,
No. 4, pp. 752-765.
[2]. Escalante, Miguel F. Jean-Claude Vannier, and Amir
Arzandé.(2002). "Flying capacitor multilevel inverters and
DTC motor drive applications." Industrial Electronics, IEEE
Transactions on , Vol. 49, No. 4 , pp. 809-815.
[3]. Mariusz Malinowski, K. Gopakumar, Jose Rodriguez
and Marcelo A. Perez (2010). “A Survey on Cascade
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[4]. Franquelo. L. G., Rodriguez. J., Leon. S., Kouro. J. I.,
Portillo. R , and Prats. M. A., M.(2008). “The age of
Figure 13. THD and Output Voltage with APOD multilevel converters arrives”, IEEE Ind. Electron. Mag,

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ABOUT THE AUTHORS

B M Manjunatha is currently working as an Assistant Professor in the Department of Electrical and Electronics Engineering in RGM
College of Engineering and Technology, Nandyal, Andhra Pradesh, India. He has graduated from the Visvwsvaraya
Technological University and Post graduated from JNTU and Pursuing Ph.D at JNTU, Anantapur. He has eight years of teaching
experience and one year of Industrial experience. His main areas of research include Power Electronics, Renewable energy
sources, drives and control of special machines.

D.V. Ashok Kumar obtained his UG Degree, PG Degree and Ph.D from J.N.T.U.C.E, Anantapur. Presently, he is dean of
administration in RGMCET, Nandyal. He has published more than 30 research papers in national and international conferences
and journals. He has attended 10 National and international workshops. His areas of interests are Electrical Machines, Power
Systems and Solar Energy. He is a member of IEEE, I.S.T.E, K.D.T.F and SESI.

M. Vijaya Kumar is currently working as Professor in the Department of Electrical and Electronics Engineering, JNTU College of
Engineering, Anantapur, Andhra Pradesh, India. He has graduated from S.V. University, Tirupathi, Andhra Pradesh and obtained
M.Tech degree from Regional Engineering College, Warangal, India. He received a Doctoral degree from Jawaharlal Nehru
Technological University, Hyderabad, India. He has published 88 research papers in national and international conferences and
journals. He received two research awards from the Institution of Engineers (India). His areas of interests include Electrical
Machines, Electrical Drives, Microprocessors and Power Electronics

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