The art of writing predictors

efficiently using UVM

Dolly Mehta, Jeremy Ridgeway

Avago Technologies, Inc.

1
 Agenda
• Goal
• Overview of Predictors
• Advanced Prediction Techniques
– Asynchronous Predictor with multiple comparators
– Multi data stream time consuming Predictor
– Predictor synchronized with design under test
• Conclusions

© Accellera Systems Initiative 2

 Goal
• To make the environment handle any possible data
stream
– Identify the various requirements which are likely to
influence the results
– Determine the architecture of the Predictor which satisfy
the requirements

© Accellera Systems Initiative 3

 Problems
• Find a way to handle the input data stream
– That gets split into different paths in the design

• Find a way to determine the output transaction order

– When multiple input transactions are received at the same time
– When the input transactions are received in parts

• Find a way to handle the input data stream

– That targets different layers in the design

© Accellera Systems Initiative 4

 Solutions
When the input data stream • Asynchronous Predictor with multiple
gets split into different paths in
the design comparators

When multiple input

transactions are received at
the same time • Multi data stream time consuming
When the input transactions Predictor
are received in parts

When the input data stream • Predictor synchronized with design under
targets different layers in the test
design

© Accellera Systems Initiative 5

 Agenda
• Goal
• Overview of Predictors
• Advanced Prediction Techniques
– Asynchronous Predictor with multiple comparators
– Multi data stream time consuming Predictor
– Predictor synchronized with design under test
• Conclusions

© Accellera Systems Initiative 6

 Role of a Scoreboard
• Verify functional correctness

Expected Observed
Input Output Output

PREDICTOR EVALUATOR

SCOREBOARD

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 Role of a Predictor
• Produce the expected output transaction
– Transaction format
– Transaction order
TLM export to Broadcast the expected output
communicate with PREDICTOR transaction through the analysis
the Monitor port to the Evaluator
Transfer
Function

Define the actions to produce the

expected output transaction

© Accellera Systems Initiative 8

 Various Predictor requirements
Input transaction Input transaction
Timing
stream(s) abstraction
• Zero time • Single • Complete
• Time • Multiple • Low
Consuming

Expected Output Expected Output Synchronization

Transaction Format Transaction Order Required
• Same as input • Ordered Stream • No
transaction • Multiple • Within the
• Different Unrelated multiple input
streams streams
• With the DUT
© Accellera Systems Initiative 9
 Agenda
• Goal
• Overview of Predictors
• Advanced Prediction Techniques
– Asynchronous Predictor with multiple comparators
– Multi data stream time consuming Predictor
– Predictor synchronized with design under test
• Conclusions

© Accellera Systems Initiative 10

 Problem #1
• Find a way to handle the input data stream
– That gets split into different paths in the design

© Accellera Systems Initiative 11

 DUT Architecture
• Single input
interface Application
• Three receiver
buffers Output
• Three independent interfaces
hardware DUT
Receiver
interfaces to give Buffer A Buffer B Buffer C
Buffers
the packets to
application
Single input
• Application decides interface
when to read the
packet and from
which buffer

© Accellera Systems Initiative 12

 Verification Challenges
• How to handle the application timing in the
verification environment?

Input Output
transaction transaction
order order

PKT1_typeA PKT2_typeB
PKT2_typeB PKT4_typeB
DUT
PKT3_typeC PKT3_typeC
PKT4_typeB PKT1_typeA

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 Solution to #1 : Asynchronous
Predictor with multiple comparators
• Decouple the prediction technique from application
timing
Broadcast the output
transaction to the
appropriate evaluator
PREDICTOR
EVALUATOR1

Transfer
EVALUATOR2
Function

EVALUATOR3

© Accellera Systems Initiative 14

The Verification Environment

Buffer C
DUT
Buffer B
Buffer A

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The Verification Environment
Input stream

PREDICTOR

Buffer C
Input

DUT
Buffer B
Agent

Buffer A

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 The Verification Environment
Expected output streams Input stream

PREDICTOR

EVALUATOR1

Buffer C
Input

DUT
EVALUATOR2

Buffer B
Agent

Buffer A
EVALUATOR3

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 The Verification Environment
Expected output streams Input stream

PREDICTOR

EVALUATOR1 Output Agent 1

Buffer C
Monitor

Output Agent 2
Input

DUT
EVALUATOR2

Buffer B
Monitor
Agent
Output Agent 3

Buffer A
EVALUATOR3 Monitor

Observed output streams

© Accellera Systems Initiative 18
 Summary: Asynchronous Predictor
with multiple comparators
Input transaction Input transaction
Timing
stream(s) abstraction
• Zero time • Single • Complete

Expected Output Expected Output Synchronization

Transaction Format Transaction Order Required
• Same as input • Multiple • No
transaction Unrelated
streams

© Accellera Systems Initiative 19

 Agenda
• Goal
• Overview of Predictors
• Advanced Prediction Techniques
– Asynchronous Predictor with multiple comparators
– Multi data stream time consuming Predictor
– Predictor synchronized with design under test
• Conclusions

© Accellera Systems Initiative 20

 Problem # 2
• Find a way to determine the output transaction
order
– When multiple input transactions are received at the same
time
– When the input transactions are received in parts

© Accellera Systems Initiative 21

 DUT Architecture
• Three independent
hardware interfaces
on the input side, Application
each accepting a
dedicated
transaction type Input
interfaces
• Possible that one
interface gets stalled Transmit
after receiving a part TRANSMIT QUEUE
queue
of the packet
DUT
• Possible to get the Single
packets on multiple output
interfaces at same interface
time. Performs
Arbitration at start of
packet.

© Accellera Systems Initiative 22

 Verification challenges
• How to handle
– Multiple input transactions at same time
– Blocked transaction(s)
Input Output
transaction order transaction order

PKT1_typeA, PKT1_typeB
PKT1_typeB, PKT2_typeB
PKT1_typeC
DUT PKT1_typeA
PKT2_typeB, PKT1_typeC
PKT2_typeC PKT2_typeC

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 Solution to #2 :Multi data stream time
consuming Predictor
• Synchronize the input streams
• Get the transactions at low level of abstraction
PREDICTOR
Ordered
output
End of YES
Perform Arbitration and pkt
apply Ordering rules seen?
EVALUATOR

NO

Multiple input
WAIT
streams

© Accellera Systems Initiative 24

The Verification Environment

TRANSMIT QUEUE

© Accellera Systems Initiative 25

DUT
The Verification Environment

Input Agent 1
Monitor

Sequencer Driver
PREDICTOR

Input Agent 2

TRANSMIT QUEUE
Monitor

DUT
Sequencer Driver

Input Agent 3
Monitor

Sequencer Driver
Input streams
© Accellera Systems Initiative 26
 The Verification Environment
Expected output

EVALUATOR

Input Agent 1
Monitor

Sequencer Driver
PREDICTOR

Input Agent 2

TRANSMIT QUEUE
Monitor

DUT
Sequencer Driver

Input Agent 3
Monitor

Sequencer Driver
Input streams
© Accellera Systems Initiative 27
 The Verification Environment
Expected output Observed output

EVALUATOR

Input Agent 1
Monitor

Sequencer Driver
PREDICTOR

Input Agent 2

TRANSMIT QUEUE
Monitor
Output

DUT
Sequencer Driver Agent

Input Agent 3
Monitor

Sequencer Driver
Input streams
© Accellera Systems Initiative 28
 Summary: Multi data stream time
consuming Predictor
Input transaction Input transaction
Timing
stream(s) abstraction
• Time • Multiple • Low
Consuming

Expected Output Expected Output Synchronization

Transaction Format Transaction Order Required
• Same as input • Ordered Stream • With in the
transaction multiple input
streams

© Accellera Systems Initiative 29

 Agenda
• Goal
• Overview of Predictors
• Advanced Prediction Techniques
– Asynchronous Predictor with multiple comparators
– Multi data stream time consuming Predictor
– Predictor synchronized with design under test
• Conclusions

© Accellera Systems Initiative 30

 Problem # 3
• Find a way to handle the input data stream
– That targets different layers in the design

© Accellera Systems Initiative 31

 DUT Architecture
• When an erroneous
packet is detected
Application
then the DUT: Interrupt
interface
• Drops the
Registers DUT
packet Receive
data
• Performs
LAYER 3
path
Possibility
Error Logging latency of error
detection
• Indicates the LAYER 2
at various
error to the layers
application LAYER 1
• Transmits the
response to the
packet originator
© Accellera Systems Initiative 32
 Verification challenges
• How to handle the receive data path latency in the
environment?
– To keep the response generation in sync
– To keep the register model in sync
Input Output
transaction transaction
order order

PKT1_ERROR PKT3_ERROR
PKT1_GOOD PKT1_ERROR
DUT
PKT2_ERROR PKT1_GOOD
PKT3_ERROR PKT2_GOOD

© Accellera Systems Initiative 33

Solution to # 3 :Predictor synchronized
with design under test
• First Predictor detects the erroneous transactions
– Does not take any actions for error handling
– Generates the expected interrupts

• Second Predictor performs the error handling

– Gets the synchronized interrupt stream as input
– Produces the expected error response

© Accellera Systems Initiative 34

Solution to # 3 :Error Detector
Expected Observed
Interrupts Interrupts

INTERRUPT
EVALUATOR 1

PREDICTOR
INTERRUPT INTERRUPT
(ERROR
EVALUATOR 2 AGENT
DETECTOR)

INTERRUPT
EVALUATOR 3

© Accellera Systems Initiative 35

 Solution to #3 :Error Handler
Expected Expected
Interrupt stream Error
synced with DUT Response

INTERRUPT
EVALUATOR 1

PREDICTOR
INTERRUPT RESPONSE
(ERROR
EVALUATOR 2 EVALUATOR
HANDLER)

INTERRUPT
EVALUATOR 3

© Accellera Systems Initiative 36

The Verification Environment

LAYER 3

LAYER 2

LAYER 1
DUT
Registers

© Accellera Systems Initiative 37

The Verification Environment
Input data stream

PREDICTOR
(ERROR DETECTOR)

LAYER 3

LAYER 2

LAYER 1
Input

DUT
Agent
Registers

© Accellera Systems Initiative 38

The Verification Environment
Expected Interrupts
Input data stream

PREDICTOR
(ERROR DETECTOR)

INTERRUPT
EVALUATOR 1

LAYER 3

LAYER 2

LAYER 1
Input

DUT
INTERRUPT
EVALUATOR 2
Agent
Registers

INTERRUPT
EVALUATOR 3

© Accellera Systems Initiative 39

The Verification Environment
Expected Interrupts
Input data stream

PREDICTOR
(ERROR DETECTOR)

INTERRUPT
EVALUATOR 1

LAYER 3

LAYER 2

LAYER 1
Interrupt Input

DUT
INTERRUPT
EVALUATOR 2
Agent Agent
Registers

INTERRUPT
EVALUATOR 3

Observed Interrupts
© Accellera Systems Initiative 40
 The Verification Environment
Interrupt PREDICTOR
stream (ERROR HANDLER)
synced
with DUT
PREDICTOR
(ERROR DETECTOR)

INTERRUPT
EVALUATOR 1

LAYER 3

LAYER 2

LAYER 1
Interrupt Input

DUT
INTERRUPT
EVALUATOR 2
Agent Agent
Registers

INTERRUPT
EVALUATOR 3

© Accellera Systems Initiative 41

 The Verification Environment
Expected Response
Interrupt PREDICTOR
stream (ERROR HANDLER)
RESPONSE
EVALUATOR
synced
with DUT
PREDICTOR
(ERROR DETECTOR)

INTERRUPT
EVALUATOR 1

LAYER 3

LAYER 2

LAYER 1
Interrupt Input

DUT
INTERRUPT
EVALUATOR 2
Agent Agent
Registers

INTERRUPT
EVALUATOR 3

© Accellera Systems Initiative 42

 The Verification Environment
Expected Response
Interrupt PREDICTOR
stream (ERROR HANDLER)
RESPONSE
EVALUATOR
synced
with DUT Observed
PREDICTOR
Response
(ERROR DETECTOR) from
output
agent
INTERRUPT
EVALUATOR 1

LAYER 3

LAYER 2

LAYER 1
Interrupt Input

DUT
INTERRUPT
EVALUATOR 2
Agent Agent
Registers

INTERRUPT
EVALUATOR 3

© Accellera Systems Initiative 43

 Summary: Error Detector
Input transaction Input transaction
Timing
stream(s) abstraction
• Zero Time • Single • Complete

Expected Output Expected Output Synchronization

Transaction Format Transaction Order Required
• Different • Multiple • No
unrelated
streams

© Accellera Systems Initiative 44

 Summary: Error Handler
Input transaction Input transaction
Timing
stream(s) abstraction
• Zero Time • Multiple • Complete

Expected Output Expected Output Synchronization

Transaction Format Transaction Order Required
• Different • Single ordered • DUT
stream

© Accellera Systems Initiative 45

 Agenda
• Goal
• Overview of Predictors
• Advanced Prediction Techniques
– Asynchronous Predictor with multiple comparators
– Multi data stream time consuming Predictor
– Predictor synchronized with design under test
• Conclusions

© Accellera Systems Initiative 46

 Results
• Successfully applied these techniques for PCIe
Controller Verification
– Transaction ordering
– Receive data path
– Error Handling

• Have taped out multiple customer programs

© Accellera Systems Initiative 47

 Conclusions
• Predictors are used to compute the expected output response

• Asynchronous predictors with multiple comparators are

required
– when there are unrelated transaction streams

• Multi-data stream time consuming predictors are required

– when the transaction order is important for the application

• Predictors synchronized with design under test are required

– when the expected response generation needs to happen in sync with
the DUT

© Accellera Systems Initiative 48

 Questions

Thank You!

© Accellera Systems Initiative 49