Lecture Notes in Computer Science 11444

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David Hutchison
Lancaster University, Lancaster, UK
Takeo Kanade
Carnegie Mellon University, Pittsburgh, PA, USA
Josef Kittler
University of Surrey, Guildford, UK
Jon M. Kleinberg
Cornell University, Ithaca, NY, USA
Friedemann Mattern
ETH Zurich, Zurich, Switzerland
John C. Mitchell
Stanford University, Stanford, CA, USA
Moni Naor
Weizmann Institute of Science, Rehovot, Israel
C. Pandu Rangan
Indian Institute of Technology Madras, Chennai, India
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TU Dortmund University, Dortmund, Germany
Demetri Terzopoulos
University of California, Los Angeles, CA, USA
Doug Tygar
University of California, Berkeley, CA, USA
More information about this series at http://www.springer.com/series/7407
Christian Hochberger Brent Nelson
• •

Andreas Koch Roger Woods

• •

Pedro Diniz (Eds.)

Applied Reconfigurable
Computing
15th International Symposium, ARC 2019
Darmstadt, Germany, April 9–11, 2019
Proceedings

123
Editors
Christian Hochberger Brent Nelson
Technical University of Darmstadt Brigham Young University
Darmstadt, Germany Provo, UT, USA
Andreas Koch Roger Woods
Technical University of Darmstadt Queen’s University Belfast
Darmstadt, Germany Belfast, UK
Pedro Diniz
INESC-ID
Lisbon, Portugal

ISSN 0302-9743 ISSN 1611-3349 (electronic)

Lecture Notes in Computer Science
ISBN 978-3-030-17226-8 ISBN 978-3-030-17227-5 (eBook)
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 Preface

The 15th International Symposium on Applied Reconfigurable Computing (ARC) was

held in April 2019 at TU Darmstadt in Germany. It is highly appropriate that ARC
came to Darmstadt as TU Darmstadt was the first university worldwide to create a
Chair for Electrical Engineering, awarded to Professor Erasmus Kittler in 1882.
Even closer to ARC’s key focus on reconfigurable computing are two globally
renowned research and high-tech institutions, both located in Darmstadt: The GSI
Helmholtz Centre for Heavy Ion Research is a hotbed of high-energy physics research,
employing a number of accelerators, detectors, lasers, and storage rings for advanced
experiments. Discoveries made at GSI include six new elements, among them Darm-
stadtium (Ds, atomic number 110). Many of the scientific instruments employ recon-
figurable devices such as field-programmable gate arrays (FPGAs), which are the key
subject of ARC, in critical functions.
A similarly keen interest in the use of FPGAs is also prevalent in the European
Space Agency (ESA), which operates its European Space Operations Centre (ESOC) in
Darmstadt. FPGAs are investigated by ESA in Darmstadt both for ground as well as for
space use, e.g., as components for compact CubeSats. In the course of ARC 2019,
excursions to both of these fascinating institutions were part of the symposium’s
program.
The main program of the symposium was formed by 20 full papers and seven poster
presentations. They were selected from over 50 submissions from all around the world.
The selection was driven by a thorough review process with more than 200 reviews in
total, which resulted in a competitive process. Besides these high-quality scientific
papers, one tutorial and an invited talk complemented the program.
We hope that you find the selected papers interesting and useful for your own
research or development!

February 2019 Christian Hochberger

Brent Nelson
Andreas Koch
Roger Woods
Pedro Diniz
 Organization

General Chairs
Andreas Koch TU Darmstadt, Germany
Roger Woods Queen’s University Belfast, UK

Program Chairs
Christian Hochberger TU Darmstadt, Germany
Brent Nelson Brigham Young University, USA

Proceedings Chair
Pedro Diniz INESC-ID, Lisboa, Portugal

Steering Committee
Hideharu Amano Keio University, Japan
Jürgen Becker Universität Karlsruhe (TH), Germany
Mladen Berekovic Universität zu Lübeck, Germany
Koen Bertels Delft University of Technology, The Netherlands
João M. P. Cardoso University of Porto, Portugal
Katherine (Compton) University of Wisconsin-Madison, USA
Morrow
George Constantinides Imperial College of Science, Technology
and Medicine, UK
Pedro Diniz INESC-ID, Lisboa, Portugal
Philip H. W. Leong University of Sydney, Australia
Walid Najjar University of California Riverside, USA
Roger Woods Queen’s University of Belfast, UK

In memory of Stamatis Vassiliadis [1951–2007], ARC 2006–2007

Steering Committee member.

Program Committee
Hideharu Amano Keio University, Japan
Zachary Baker Los Alamos National Laboratory, USA
Juergen Becker Karlsruhe Institute of Technology, Germany
Nikolaos Bellas University of Thessaly, Greece
Mladen Berekovic TU Braunschweig, Germany
Joao Bispo University of Porto, Portugal
viii Organization

Vanderlei Bonato University of São Paulo, Brazil

Christos Bouganis Imperial College London, UK
João Canas Ferreira University of Porto, Portugal
Joao Cardoso University of Porto, Portugal
Luigi Carro Universidade Federal do Rio Grande do Sul, Brazil
Ray Cheung City University of Hong Kong, SAR China
Daniel Chillet CAIRN, IRISA/ENSSAT, France
Steven Derrien Université de Rennes 1, France
Giorgos Dimitrakopoulos Democritus University of Thrace, Greece
Pedro Diniz INESC-ID, Lisboa, Portugal
Antonio Ferrari University of Aveiro, Portugal
Ricardo Ferreira Universidade Federal de Vicosa, Brazil
Apostolos Fournaris Technological Educational Institute of Western Greece,
Greece
Roberto Giorgi University of Siena, Italy
Diana Goehringer TU Dresden, Germany
Marek Gorgon AGH University of Science and Technology, Poland
Frank Hannig Friedrich-Alexander University Erlangen-Nürnberg,
Germany
Jim Harkin University of Ulster, UK
Christian Hochberger TU Darmstadt, Germany
Michael Huebner Brandenburg University of Technology Cottbus,
Germany
Kimon Karras Sunlight.io, Greece
Chrysovalantis Kavousianos University of Ioannina, Greece
Krzysztof Kepa GE Global Research, USA
Georgios Keramidas Technological Educational Institute of Western Greece,
Greece
Andreas Koch TU Darmstadt, Germany
Tomasz Kryjak AGH University of Science and Technology, Poland
Konstantinos Masselos University of the Peloponnese, Greece
Cathal Mccabe Xilinx, Ireland
Antonio Miele Politecnico di Milano, Italy
Takefumi Miyoshi e-trees.Japan, Inc., Japan
Walid Najjar University of California Riverside, USA
Brent Nelson Brigham Young University, USA
Horacio Neto Universidade de Lisboa, Portugal
Dimitris Nikolos University of Patras, Greece
Kyprianos Papadimitriou Neapolis University Pafos and Technical University
of Crete, Greece
Monica Pereira Universidade Federal do Rio Grande do Norte, Brazil
Thilo Pionteck Otto-von-Guericke Universität Magdeburg, Germany
Marco Platzner University of Paderborn, Germany
Mihalis Psarakis University of Piraeus, Greece
Kyle Rupnow Inspirit IoT, USA
Kentaro Sano RIKEN R-CCS, Japan
 Organization ix

Marco Domenico Politecnico di Milano, Italy

Santambrogio
Yukinori Sato Toyohashi University of Technology, Japan
Antonio Carlos Schneider Universidade Federal do Rio Grande do Sul, Brazil
Beck
Yuichiro Shibata Nagasaki University, Japan
Dimitrios Soudris National Technical University of Athens, Greece
Theocharis Theocharides University of Cyprus, Cyprus
George Theodoridis University of Patras, Greece
David Thomas Imperial College, London, UK
Nikolaos Voros Technological Educational Institute of Western Greece,
Greece
Chao Wang University of Science and Technology of China, China
Markus Weinhardt Osnabrück University of Applied Sciences, Germany
Roger Woods Queen’s University Belfast, UK
Yoshiki Yamaguchi University of Tsukuba, Japan

Sponsors

The 2019 Applied Reconfigurable Computing Symposium (ARC 2019) was sponsored
by:
 Contents

Applications

Fault-Tolerant Architecture for On-board Dual-Core Synthetic-Aperture

Radar Imaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Helena Cruz, Rui Policarpo Duarte, and Horácio Neto

Optimizing CNN-Based Hyperspectral Image Classification on FPGAs . . . . . 17

Shuanglong Liu, Ringo S. W. Chu, Xiwei Wang, and Wayne Luk

Supporting Columnar In-memory Formats on FPGA: The Hardware Design

of Fletcher for Apache Arrow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Johan Peltenburg, Jeroen van Straten, Matthijs Brobbel,
H. Peter Hofstee, and Zaid Al-Ars

A Novel Encoder for TDCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

Günter Knittel

A Resource Reduced Application-Specific FPGA Switch . . . . . . . . . . . . . . . 58

Qian Zhao, Yoshimasa Ohnishi, Masahiro Iida, and Takaichi Yoshida

Software-Defined FPGA Accelerator Design for Mobile Deep

Learning Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Panagiotis G. Mousouliotis and Loukas P. Petrou

Partial Reconfiguration and Security

Probabilistic Performance Modelling when Using Partial Reconfiguration

to Accelerate Streaming Applications with Non-deterministic
Task Scheduling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Bruno da Silva, An Braeken, and Abdellah Touhafi

Leveraging the Partial Reconfiguration Capability of FPGAs

for Processor-Based Fail-Operational Systems. . . . . . . . . . . . . . . . . . . . . . . 96
Tobias Dörr, Timo Sandmann, Florian Schade, Falco K. Bapp,
and Jürgen Becker

(ReCo)Fuse Your PRC or Lose Security: Finally Reliable

Reconfiguration-Based Countermeasures on FPGAs . . . . . . . . . . . . . . . . . . 112
Kenneth Schmitz, Buse Ustaoglu, Daniel Große, and Rolf Drechsler
xii Contents

Proof-Carrying Hardware Versus the Stealthy Malicious LUT

Hardware Trojan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
Qazi Arbab Ahmed, Tobias Wiersema, and Marco Platzner

Secure Local Configuration of Intellectual Property Without a Trusted

Third Party. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Nadir Khan, Arthur Silitonga, Brian Pachideh, Sven Nitzsche,
and Jürgen Becker

Image/Video Processing

HiFlipVX: An Open Source High-Level Synthesis FPGA Library

for Image Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Lester Kalms, Ariel Podlubne, and Diana Göhringer

Real-Time FPGA Implementation of Connected Component Labelling

for a 4K Video Stream . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 165
Piotr Ciarach, Marcin Kowalczyk, Dominika Przewlocka,
and Tomasz Kryjak

A Scalable FPGA-Based Architecture for Depth Estimation in SLAM . . . . . . 181

Konstantinos Boikos and Christos-Savvas Bouganis

High-Level Synthesis

Evaluating LULESH Kernels on OpenCL FPGA. . . . . . . . . . . . . . . . . . . . . 199

Zheming Jin and Hal Finkel

The TaPaSCo Open-Source Toolflow for the Automated Composition

of Task-Based Parallel Reconfigurable Computing Systems . . . . . . . . . . . . . 214
Jens Korinth, Jaco Hofmann, Carsten Heinz, and Andreas Koch

Graph-Based Code Restructuring Targeting HLS for FPGAs . . . . . . . . . . . . 230

Afonso Canas Ferreira and João M. P. Cardoso

CGRAs and Vector Processing

UltraSynth: Integration of a CGRA into a Control

Engineering Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 247
Dennis Wolf, Tajas Ruschke, Christian Hochberger, Andreas Engel,
and Andreas Koch

Exploiting Reconfigurable Vector Processing for Energy-Efficient

Computation in 3D-Stacked Memories. . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
João Paulo C. de Lima, Paulo C. Santos, Rafael F. de Moura,
Marco A. Z. Alves, Antonio C. S. Beck, and Luigi Carro
 Contents xiii

Automatic Toolflow for VCGRA Generation to Enable CGRA Evaluation

for Arithmetic Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 277
André Werner, Florian Fricke, Keyvan Shahin, Florian Werner,
and Michael Hübner

Architectures

ReM: A Reconfigurable Multipotent Cell for New Distributed

Reconfigurable Architectures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 295
Ludovica Bozzoli and Luca Sterpone

Update or Invalidate: Influence of Coherence Protocols on Configurable

HW Accelerators. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 305
Johanna Rohde, Lukas Johannes Jung, and Christian Hochberger

Design Frameworks and Methodology

Hybrid Prototyping for Manycore Design and Validation . . . . . . . . . . . . . . . 319

Leonard Masing, Fabian Lesniak, and Jürgen Becker

Evaluation of FPGA Partitioning Schemes for Time and Space Sharing

of Heterogeneous Tasks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 334
Umar Ibrahim Minhas, Roger Woods, and Georgios Karakonstantis

Invited Talk

Third Party CAD Tools for FPGA Design—A Survey

of the Current Landscape . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353
Brent E. Nelson

Convolutional Neural Networks

Filter-Wise Pruning Approach to FPGA Implementation of Fully

Convolutional Network for Semantic Segmentation . . . . . . . . . . . . . . . . . . . 371
Masayuki Shimoda, Youki Sada, and Hiroki Nakahara

Exploring Data Size to Run Convolutional Neural Networks in Low

Density FPGAs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
Ana Gonçalves, Tiago Peres, and Mário Véstias

Faster Convolutional Neural Networks in Low Density FPGAs Using

Block Pruning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 402
Tiago Peres, Ana Gonçalves, and Mário Véstias

Author Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 417