Experiment 7 Concurrent Code
Experiment 7 Concurrent Code
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Experiment 7
Concurrent Code:
Design Example Comparator
Learning Objectives:
1. Some fundamental VHDL concurrent statement will introduced in this experiment, with
special emphasis on those that are synthesizable.
2. To design, synthesize, and simulate the operation of a comparator circuit with VHDL
language.
Equipment and Materials:
full version of Xilinx ISE 9.2i software installed on your laboratory personal computer.
Introduction:
VHDL code can be concurrent (parallel) or sequential. The former will be studied in this
experiment ,while the latter will be seen in next experiments. The concurrent code
statements can only be used outside PROCESSES, FUNCTIONS, or PROCEDURES. They are the
WHEN statement and the GENERATE statement. Besides them, assignments using only
operators (logical, arithmetic, etc) can obviously also be used to create combinational circuits.
Also, a special kind of statement, called BLOCK, can also be employed. In concurrent code the
following can be used:
1- Operators: table below summarize operators that can be used in concurrent code:
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Advanced Digital Electronics Laboratory Exp.7
2- The WHEN statement: There are two kinds of WHEN statements: WHEN/ELSE or
WITH/SELECT/WHEN.
3- The GENERATE statement: Also There are two kinds of GENERATE statement one used
with FOR the other used with IF:
4- The BLOCK statement: There are two kinds of BLOCK statements: Simple and Guarded.
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Advanced Digital Electronics Laboratory Exp.7
Procedures:
1.Write a VHDL concurrent code to construct a circuit capable of comparing two 8-bit vectors, a
and b. A selection pin (sel) should determine whether the comparison is signed (sel = ‘1’) or
unsigned (sel = ‘0’). The circuit must have three outputs, x1, x2, and x3, corresponding to a > b,
a = b, and a < b, respectively.
2.Implement your designed in step 1 using Xilinx ISE 9.2i tools for Spartan 3E FPGA board. Follow
the same steps in previous in Experiments to synthesize and obtain a timing diagram after
simulation to verify correct outputs.
3.In order to unifying the results please use the following test vectors in your simulation test
bench: