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S.no RTL Name Signals Required: Horizontal Microcode

This document discusses horizontal and vertical microcode implementation. It contains a table listing micro-operations and their required control signals. It then groups the control signals and lists the corresponding micro-operations. Finally, it shows how the micro-operations can be encoded into a smaller ROM using vertical instead of horizontal coding.

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Arslan Ali
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© © All Rights Reserved
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Download as DOCX, PDF, TXT or read online on Scribd
46 views

S.no RTL Name Signals Required: Horizontal Microcode

This document discusses horizontal and vertical microcode implementation. It contains a table listing micro-operations and their required control signals. It then groups the control signals and lists the corresponding micro-operations. Finally, it shows how the micro-operations can be encoded into a smaller ROM using vertical instead of horizontal coding.

Uploaded by

Arslan Ali
Copyright
© © All Rights Reserved
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
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Horizontal microcode

Table listing all micro-operations and control signals required.

s.no RTL NAME Signals required


1. MAR ß PC PCMAR Pc2bus,marld,read
2. IR ß M[MAR] MIR Mem2bus,irld
3. PC ß PC + 1 INCPC Pcinc
4. MAR ß IR[11..0] IRMAR Ir2bus,marld
5. MBR ß M[MAR] MMBR Mem2bus, mbrld
6. AC ß MBR MBRAC Mbr2bus,acld
7. MBR ß AC ACMBR Ac2bus,mbrld
8. M[MAR] ß MBR MBRM Mbr2bus, write
9. AC ß AC + MBR ADDAC Aluadd,acld
10. AC ß AC - MBR SUBAC Alusub, acld
11. PC ß MAR MARPC Mar2bus,pcld
12. MAR ß MBR[11..0] MBRMAR Mbr2bus,marld

13.
Horizontal microcode

Signals and corresponding micro-operations.

SIGNAL Needed when following Micro –operation is Control signals equations in terms of Micro-
performed operations bit from control ROM
1. Pc2bus PCMAR Pc2bus = PC2MAR
2. Marld PCMAR, IRMAR, MBRMAR Marld = PC2MAR v IR2MAR v MBR2MAR
3. Read PCMAR Read = PC2MAR
4. Mem2bus MIR,MMBR, Mem2bus = M2IR v M2MBR
5. Irld MIR Irld = M2IR
6. Pcinc INCPC Pcinc = INCPC
7. Ir2bus IRMAR Ir2bus = IR2MAR
8. marld IRMAR, MBRMAR Maeld = IR2MAR v MBR2MAR
9. mbrld MMBR, ACMBR Mbrld = M2MBR v AC2MBR
10. mbr2bus MBRAC, MBRM, MARPC Mbr2bus = MBR2AC v MBR2M v MAR2PC
11. acld MBRAC, ADDAC, SUBAC Acld = MBR2AC v ADD2AC v SUB2AC
12. Ac2bus ACMBR Ac2bus = ACMBR
13. write MBRM Write = MBR2M
14. aluadd ADDAC Aluadd = ADD2AC
15. alusub SUBAC Alusub = SUB2AC
16. Mar2bus MARPC Mar2bus = MAR2PC
17. pcld MARPC Pcld = MAR2PC
Horizontal microcode
PC2 M2 INC IR2 M2 MBR AC2 MBR ADD SUB MAR MBR
MA IR PC MA MBR 2AC MBR 2M 2AC 2AC 2PC 2MA
R R R
opcode Rom selec 1 2 3 4 5
MUX 6 7 8 9 10 11 12 Nxt
addr t Addr
Fetch 0000 0 x 00001
1 0 Address register
Fetch 0000 0 x x 00010
2 1
Fetch 0001 1 x xxxxx
3 0
Load1 0001 0001 0 x 00101
1
Load2 0010 0 x 00000
0
Store1 0010 0010 0 x 00110
1
Store2 0011 0 x 00000
0
Add1 0011 0011 0 x 10000
1
Add2 1000 0 X 00000
0
Subt1 0100 1000 0 x 10010
1
Subt2 1001 0 x 00000
0
Jump1 0101 1001 0 x 00000
1
Addi1 0110 1010 0 x 10101
0
Addi2 1010 0 x 10110
1
Addi3 1011 0 x 10111 This table
0 shows
Addi4 1011 0 X 00000
1
Skip1 1000 1100 0 x 00000
0
halt 0111 1100 0 11001
1
Horizontal microcode
PC2 M2 IR2 M2 MBR AC2 INC MBR ADD SUB MAR MBR
MA IR MA MBR 2AC MBR PC 2M 2AC 2AC 2PC 2MA
ROM
R R R
opcode Rom selec 1 2 4 5 6 7 3 8 9 10 11 12 Nxt values for
addr t Addr Horizontal
Fetch 0000 0 x 00001 coding.
1 0 Next we
Fetch 0000 0 x x 00010 group Bit
2 1 fields for
Fetch 0001 1 x xxxxx
vertical
3 0
Load1 0001 0001 0 x 00101 coding.
1
Group1 nop PC2MAR M2IR IR2MAR M2MBR MBR2AC AC2MBR
Load2 0010 0 x 00000
code 000 001 010 011 100 101 110
0
Group2 nop INCPC MBR2M ADD2AC SUB2AC MAR2PC MBR2MAR
Store1 0010 0010 0 x 00110
code 000 001 010 011 100 101 110
1
Store2 0011 0 x 00000
0
Using this
Add1 0011 0011 0 x 10000
grouping
1
Add2 1000 0 X 00000 we get a
0 smaller
Subt1 0100 1000 0 x 10010 ROM
1 word size.
Subt2 1001 0 x 00000
0
Jump1 0101 1001 0 x 00000
1
Addi1 0110 1010 0 x 10101
0
Addi2 1010 0 x 10110
1
Addi3 1011 0 x 10111
0
Addi4 1011 0 X 00000
1
Skip1 1000 1100 0 x 00000
0
halt 0111 1100 0 11001
1
Horizontal microcode

PC2 M2 IR2 M2 MBR AC2 INC MBR ADD SUB MAR MBR
MA IR MA MBR 2AC MBR PC 2M 2AC 2AC 2PC 2MAR
R R
opcode Rom select 1 2 4 5 6 7 3 8 9 10 11 12 Nxt
addr Addr
Fetch 0000 0 001 X 000 00001
1 0
Fetch 0000 0 010 x 001 x 00010
2 1
Fetch 0001 1 011 x 000 xxxxx
3 0
Load1 0001 0001 0 100 x 000 00101
1
Load2 0010 0 101 x 000 00000
0
Store1 0010 0010 0 110 x 000 00110
1
Store2 0011 0 000 010 x 00000
0
Add1 0011 0011 0 100 x 000 10000
1
Add2 1000 0 000 011 X 00000
0
Subt1 0100 1000 0 100 x 000 10010
1
Subt2 1001 0 000 100 x 00000
0
Jump1 0101 1001 0 000 101 x 00000
1
Addi1 0110 1010 0 100 x 000 10101
0
Addi2 1010 0 000 110 x 10110
1
Addi3 1011 0 100 x 000 10111
Horizontal microcode

0
Addi4 1011 0 000 011 X 00000
1
Skip1 1000 1100 0 000 001 x 00000
0
halt 0111 1100 0 000 000 11001
1
New ROM contents using vertical coding.
Horizontal microcode

Finally the ROM contents :


opcode Rom select Nxt
addr Addr
Fetch 0000 0 001 000 00001
1 0
Fetch 0000 0 010 001 00010
2 1
Fetch 0001 1 011 000 xxxxx
3 0
Load1 0001 0001 0 100 000 00101
1
Load2 0010 0 101 000 00000
0
Store1 0010 0010 0 110 000 00110
1
Store2 0011 0 000 010 00000
0
Add1 0011 0011 0 100 000 10000
1
Add2 1000 0 000 011 00000
0
Subt1 0100 1000 0 100 000 10010
1
Subt2 1001 0 000 100 00000
0
Jump1 0101 1001 0 000 101 00000
1
Addi1 0110 1010 0 100 000 10101
0
Addi2 1010 0 000 110 10110
1
Addi3 1011 0 100 000 10111
0
Addi4 1011 0 000 011 00000
1
Skip1 1000 1100 0 000 001 00000
0
halt 0111 1100 0 000 000 11001
1
Horizontal microcode

Truth table for Mapping Logic

Op- Rom minterms


code address
0000 00000
0001 00011 m1 Op-code to Rom address Mapping function.
0010 00101 m2
0011 00111 m3
0100 10001 m4
0101 10011 m5
0110 10100 m6
0111 11001 m7
1000 11000 m8
Horizontal microcode
Horizontal microcode

Vertical Micro-coding.

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