Characterization and Modeling of Low Frequency Noise and

Dielectric Traps in Scaled MOSFET Devices

Dissertation

Presented in Partial Fulfillment of the Requirements for the Degree

Doctor of Philosophy in the Graduate School of The Ohio State
University

By

Xiaochen Zhang, M.S.

Graduate Program in Electrical and Computer Engineering

The Ohio State University

2013

Dissertation Committee:
Marvin H. White, Advisor
Leonard J. Brillson
Wu Lu
© Copyright by
Xiaochen Zhang

2013
 Abstract

CMOS scaling has pushed the industry toward circuits and systems of better per-

formance, higher density, and lower cost for electronic products through the past

several decades. The high-K materials are introduced into the MOSFET structure

to reduce the gate leakage current, increase the gate capacitance for current drive

and reduce short channel effects. However, the oxide trap density in these materials

is intrinsically higher and that leads to stronger trapping effects. This dissertation

describes the modeling and electrical characterization of nanoscaled high-K and SiON

MOSFET devices, focusing on their trap-related device performances. Research work

on performance characterization of carbon ion implantation in advanced CMOS re-

placement technology is also included pursuing a cost-effective approach for precise

control of vertical dopant profile.

We develop a quantum mechanical treatment of low-frequency noise to extend the

“unified” noise model and includes remote Coulomb scattering and surface roughness

- the latter is a new consideration in the theory. Our experimental work focuses on

scaled NMOS devices with a composite dielectric consisting of a 0.5 nm SiO2 covered

with a high-K, 1.6 nm HfO2 with a metal gate. In the past, Coulomb scattering was

assumed to arise from trapping centers located at the Si-SiO2 interface; however, this

cannot give rise to a 1/f noise spectrum. We model remote Coulomb scattering into

the dielectric film as traps in these films easily lie within a tunneling distance from

ii
the interface. This approach explains the decrease in the remote Coulomb scattering

parameter (α) as a function of gate voltage. In addition, we introduce surface rough-

ness scattering through fluctuations in the normal electric field due to fluctuations in

the free carrier density with a surface scattering parameter (β) proportional to the

SPICE surface roughness parameter θS . Good agreement is obtained between our

model and experimental results for both IDS - VGS and the power spectral density,

SId , characteristics in very strong inversion region where the surface quantization of

the 2D subbands is strong.

Characterization on SiON MOSFET devices are performed including I-V (Current-

Voltage), C-V (Capacitance-Voltage), charge pumping etc. NMOS transistors exhibit

a higher interface trap density (9.7E10 cm−2 eV−1 ) than PMOS (5.8E10 cm−2 eV−1 ).

The mean capture cross sections are comparable in these devcies: 3.3E-17 cm2 and

9.1E-17 cm2 , receptively, for CMOS devices. Different mobility extraction methods

are presented and the results indicate strong surface roughness scattering in these

devices.

The effects of channel carbon ion implantation (Cii) on advanced high-K metal

gate low-power CMOS devices have been studies. Cii improves the device perfor-

mance, especially for NMOS. The improvement comes mainly from an improvement

in electron mobility, where Coulomb scattering is reduced due to retarded boron

diffusion with carbon.

iii
This dissertation is dedicated to my parents Minghua He and Jin Zhang,

for their support, love, and belief in me throughout all these years.

iv
 Acknowledgments

My first homework upon joining our group was to read one of the previous stu-

dents’ dissertation. Now, six years later, I am writing my own. There are a long list

of people I want to thank, without whom this journey would not be as unforgettable

as it is.

First and formost, I would like to express my deepest gratitude to my advisor, Dr.

Marvin H. White, who has been such an inspiring, supportive and considerate mentor

throughout my graduate study. It’s more than a privilege to work with and learn

from him. His never-ceasing passion for research and teaching, profound knowledge

in semiconductor and electronics, generosity to reach out and help other people, and

so many more, have deeply made an impact in my life. I will always remember what

he said when I told him I got my first car and drivers’ license - “Deedee, you are an

independent woman now, you don’t have to depend on anyone.” And I will miss the

wonderful time I had when Dr. White and Mrs. White invited me to dinner.

I would like to thank Prof. Leonard J. Brillson and Prof. Wu Lu for serving on my

committee and providing valuable advices on my research and dissertation. I would

also like to thank Prof. Steven B. Bibyk for serving on my candidacy committee.

Many thanks are owed to my mentors and managers during my internship at

IBM Hopewell Junction site in 2011: Dr. Huiling Shang, Dr. Melanie Sherony, Dr.

Yanxiang Liu, Hiroyuki Onoda, Fumihiko Sato and Manfred Eller. I had a great

v
experience there and I am looking forward to be part of this amazing team soon.

Special thanks to Yanxiang and Huiling for their help on the channel carbon ion

implantation draft.

It is a great pleasure to work with the current and previous members in our group:

Christopher J. Barthol, Dr. Gan Wang, Dr. Yanli Zhang .etc. I have also enjoyed

the company of the fellow students here at OSU and previously at Lehigh University.

Recent working nights with Yuji Wang are quite fun.

Ms. Tricia Toothman and Ms. Stephanie Muldrow deserve a big applause for

their administrative service, which makes the students’ life much easier. It’s such a

blessing to have them staffing in our department. Especially I want to thank Tricia

for her encouragement and assistance during my studies here at OSU.

I am grateful for all my friends who have never stopped encouraging and inspiring

me: Dr. Weilin Li, Lina Zhang, Ming Sheng, Nanxi Bian, Yuting Ding, Yinghui

Duan, Yan Li, Xuan Dai, Xiaodi Hou, my other “JMs”, “FANTUAN” group and

everyone else.

I cannot wait to see my parents, Minghua He and Jin Zhang, again and spend

some time with them, whom I missed for so long. I am so grateful to them for putting

up with me, loving and supporting me all the time. Last, but not least, I want to

thank my boyfriend, Weike Wang, for being the one that “makes me laugh”.

The work presented on channel carbon ion implantation in Chapter 4 was per-

formed during my internship at the IBM Microelectronics Div., Semiconductor Re-

search & Development Center, Hopewell Junction, NY 12533.

I also want to thank the National Science Foundation (NSF) ECCS Division for

the continued support for my research and education.

vi
 Vita

June 24, 1985 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Born - Yangzhou, Jiangsu, China

2007 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . B.E., Electronic Science and Technol-

ogy, Shanghai Jiao Tong University,
Shanghai, China
2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . M.S. Electrical and Computer Engi-
neering (ECE), Lehigh University
2010–2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graduate Fellow, Department of ECE,
The Ohio State University.
2011 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Technology Assurance/Device Engi-
neer Intern, IBM SRDC, Hopewell
Junction, NY
2013–present . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Graduate Research Associate, Depart-
ment of ECE, The Ohio State Univer-
sity
2010 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . NJ Zink Fellow, Lehigh University

2009 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Sherman Fairchild Fellow, Lehigh Uni-

versity

Publications

X. Zhang and M. H. White. A quantum mechanical treatment of low frequency noise

in high-K NMOS transistors with ultra-thin gate dielectrics. Solid-State Electronics,
vol. 78, pp. 131–135, December 2012.

X. Zhang and M. H. White. A quantum mechanical treatment of low frequency noise

in high-K NMOS transistors with ultra-thin gate dielectrics. International Semicon-
ductor Device Research Symposium (ISDRS), University of Maryland, College Park,
MD, December 2011.

vii
X. Zhang, Y. Zhang, and M. H. White. Characterization of traps in scaled NMOS
transistors with ultra-thin high-K dielectrics and metal gate electrodes. ISDRS,
University of Maryland, College Park, MD, December 2009.

X. Zhang, L. S. Liyanage, N. Eichenlaub, and M. H. White. Characterization of

1/f noise in scaled high-K NMOS transistors and SONOS nonvolatile semiconduc-
tor memory (NVSM) devices. ISDRS, University of Maryland, College Park, MD,
December 2009.

G. Wang, J. Goldman, X. Zhang, N. Eichenlaub, L. S. Liyanage, and M. H. White.

Electron mobility in SONOS nonvolatile semiconductor memory (NVSM) devices.
Semidoncutor Interface Specialists Conference (SISC), San Diego, CA, December
2008.

Fields of Study

Major Field: Electrical and Computer Engineering

viii
 Table of Contents

Page

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

Dedication . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

Acknowledgments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

Vita . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xiii

Chapter 1: Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1 1/f Noise in MOSFET . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1.1 Introduction and Review of 1/f Noise Theories . . . . . . . 1
1.1.2 Low Frequency Noise in Scaled CMOS Devices . . . . . . . 9
1.2 CMOS Scaling and Advanced Gate Dielectrics . . . . . . . . . . . . 11
1.2.1 Scaling Principles . . . . . . . . . . . . . . . . . . . . . . . . 11
1.2.2 Technology Improvement to Continue “Shrinking” . . . . . 13
1.2.3 Advanced Dielectrics High-K Materials . . . . . . . . . . . . 16
1.3 Dopant Profile Control in Nanoscaled CMOS Technology . . . . . . 21
1.4 Scope of the Dissertation . . . . . . . . . . . . . . . . . . . . . . . 24

Chapter 2: A Quantum Mechanical Treatment of Low Frequency Noise in

High-K NMOS Transistors with Ultra-thin Gate Dielectrics . . . . . . . . 26

2.1 Theoretical Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.1.1 The Noise Model . . . . . . . . . . . . . . . . . . . . . . . . 27
2.1.2 Band Structure . . . . . . . . . . . . . . . . . . . . . . . . . 31
2.1.3 Remote Coulomb Scattering (α) . . . . . . . . . . . . . . . 42

ix
 2.1.4 Surface Roughness (β) . . . . . . . . . . . . . . . . . . . . . 44
2.2 Experiments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
2.2.1 Experimental Setup and simulation . . . . . . . . . . . . . . 47
2.2.2 Discussions . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

Chapter 3: Characterization of Nanoscaled SiON MOSFET Devices . . . . 56

3.1 Overall Setup and LabVIEW Programming . . . . . . . . . . . . . 57

3.1.1 State Programming in LabVIEW . . . . . . . . . . . . . . . 58
3.2 Capacitance-Voltage (CV) Characteristics . . . . . . . . . . . . . . 59
3.2.1 Gate-to-Channel and Gate-to-Bulk Capacitance . . . . . . . 60
3.2.2 CV Measurement for MOS Devices with Leakage . . . . . . 61
3.3 Current-Voltage (IV) Characteristics . . . . . . . . . . . . . . . . . 64
3.3.1 IV Characteristics and Threshold Voltage Extraction . . . . 64
3.3.2 I-V Characteristics and Mobility . . . . . . . . . . . . . . . 71
3.4 Interface Trap Characterization with Charge Pumping Technique . 77
3.5 1/f Noise Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 87
3.5.1 Measurement Setup . . . . . . . . . . . . . . . . . . . . . . 87

Chapter 4: Channel Carbon Implantation in Advanced Replacement Gate

Technology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4.1 Boron Transient Enhanced Diffusion and Carbon Co-Implantation . 93

4.2 Device Fabrication . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
4.3 Characterization and Results . . . . . . . . . . . . . . . . . . . . . 95
4.3.1 DC performance Ieff-Ioff . . . . . . . . . . . . . . . . . . . . 95
4.3.2 Charge Pumping . . . . . . . . . . . . . . . . . . . . . . . . 97
4.3.3 Effective Mobility . . . . . . . . . . . . . . . . . . . . . . . 98
4.3.4 Threshold Voltage Comparison . . . . . . . . . . . . . . . . 99
4.4 Discussion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

Chapter 5: Conclusions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.1 Summaries of This Work . . . . . . . . . . . . . . . . . . . . . . . . 104

5.2 Recommendations for Future Research . . . . . . . . . . . . . . . . 107

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

Appendix A: Derivation of the Remote Coulomb Scattering Parameter in 1/f

Noise Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117

x
Appendix B: Operation Details of Performing Characterization in Our Lab . 124

B.1 Designing the LabVIEW programs . . . . . . . . . . . . . . . . . . 124

B.1.1 Graphical Programming and User Interface . . . . . . . . . 125
B.2 Device Characterization Setup and Operation . . . . . . . . . . . . 125
B.2.1 Setup and Operation of IV Measurement . . . . . . . . . . . 126
B.2.2 Setup and Operation of Capacitance Voltage (C-V) Measure-
ment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
B.3 Setup and Operation of Leakage and Stress Induced Leakage Current
(SILC) Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . 135
B.4 Setup and Operation of Stress IV Measurement . . . . . . . . . . . 136
B.4.1 Setup and Operation of Charge Pumping Measurement . . . 137
B.4.2 Setup and Operation of Noise Measurement . . . . . . . . . 143

Appendix C: Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

xi
 List of Tables

Table Page

1.1 Scaling principles for CMOS devices. . . . . . . . . . . . . . . . . . . 13

3.1 Extracted parameters from I-V characteristics and VT H analysis. . . . 69

3.2 Extracted parameters from I-V characteristics. . . . . . . . . . . . . . 77

3.3 Extracted parameters from charge pumping measurement with trian-

gular pulses. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

B.1 Front panel control definitions for the ID -VG program. . . . . . . . . . 129

B.2 Front panel control definitions for the ID -VD program. . . . . . . . . . 130

B.3 Front panel control definitions for the CG -VG program. . . . . . . . . 134

B.4 Front panel control definitions for the CPamp program. . . . . . . . . 140

B.5 Front panel control definitions for the CPbase program. . . . . . . . . 143

xii
 List of Figures

Figure Page

1.1 Spectrum of low frequency or “1/f ” noise versus frequency. . . . . . . 2

1.2 MOSFET trapping and detrapping. . . . . . . . . . . . . . . . . . . . 4

1.3 Tunneling and capture-emission processes in NMOSFET. . . . . . . . 5

1.4 Example of random telegraph signal (RTS) noise measured in the drain
current of a MOSFET. . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.5 Schematic illustration of MOSFET constant electric field scaling. . . . 12

1.6 Strain introduction in CMOS for mobility enhancement. . . . . . . . 14

1.7 SOI and multi-gate architectures which reduce source-drain interaction. 16

1.8 Scaling trend of L and EOT. . . . . . . . . . . . . . . . . . . . . . . . 17

1.9 The increase of gate leakage with reduced EOT. . . . . . . . . . . . . 19

1.10 Laterally nonuniform halo doping in nMOSFETs. . . . . . . . . . . . 23

2.1 MOSFET structure showing the infinitesimal segment ∆x of the channel. 28

2.2 Energy band diagram for SiO2 /High-K structure at strong inversion. . 32

2.3 Triangular well code flow chart. . . . . . . . . . . . . . . . . . . . . . 36

2.4 The first three quantized energy levels and quasi-Fermi level versus
surface potential. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

xiii
2.5 Inversion layer carrier density versus surface potential. . . . . . . . . 40

2.6 Inversion layer carrier density composition trend. . . . . . . . . . . . 41

2.7 A model of the rough silicon surface. . . . . . . . . . . . . . . . . . . 44

2.8 Cross-section of the scaled NMOS transistors with 0.5 nm SiO2 /1.6 nm
HfO2 gate dielectric and 10 nm TiN gate electrodes (non-self-aligned). 47

2.9 Comparison of the simulated and experimental IDS versus VGs curve. 48

2.10 Modeled variation of α and β versus carrier density. . . . . . . . . . . 49

2.11 Drain current noise PSD versus gate voltage for high-K, NMOS device
at VDS = 50 mV (W = 100 um, L = 10 um), f = 4 Hz. . . . . . . . . 51

2.12 Comparison of calculated α values with different consideration. . . . . 53

2.13 Comparison of number fluctuation and mobility fluctuation. . . . . . 54

3.1 Basic structure of the ‘state machines’ in a LabVIEW— environment. 59

3.2 Schematic for gate-to-channel capacitance measurement. . . . . . . . 60

3.3 Capacitance-Voltage characteristics for both N and P transistors. . . 62

3.4 Small signal equivalent circuit of MOS capacitors. . . . . . . . . . . . 63

3.5 Dual frequency C-V characteristics of both NMOS and PMOS ad-
vanced SiON devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.6 Transfer characteristics of SiON CMOS Devices. . . . . . . . . . . . . 66

3.7 Linear extrapolation for threshold voltage of a NMOS transistor. . . . 67

3.8 Flowchart for extracting the effective substrate doping concentration

NA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
√ √
3.9 Plot of VT H versus VSB + 2φF − 2φF . . . . . . . . . . . . . . . . . 70

3.10 Plot of the measured conductance mobility versus effective electric field. 73

xiv
3.11 Plots to show the extraction of the carrier mobility, surface roughness
and series resistance from transfer characteristics. . . . . . . . . . . . 75

1
√ √
3.12 Plots of βef f
−RSD (4λn 2φF + VSB + 3VD δ) vs. 4λn 2φF + VSB + 3VD δ. 76

3.13 Basic experimental setup for the charge pumping technique. . . . . . 78

3.14 Base sweep and amplitude sweep methods for the charge pumping tech-
nique. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

3.15 Measurement of amplitude voltage sweep of both NMOS and PMOS. 82

3.16 Measurement of base level sweep of NMOS before gate current correction. 83

3.17 Measurement of base level sweep of NMOS after gate current correction. 84

3.18 Measurement of base level sweep of PMOS after gate current correction. 84
√
3.19 QSS versus frequency used to determine σn σp and Dit . . . . . . . . 86

3.20 Noise measurement system for packaged DUT. . . . . . . . . . . . . . 88

3.21 Schematic of the circuit for package-DUT noise measurement. . . . . 89

3.22 Noise measurement system for on-wafer DUT. . . . . . . . . . . . . . 90

4.1 Process Flow of both the Cii and Control splits. . . . . . . . . . . . . 95

4.2 Comparison of the NMOS Ieff-Ioff. . . . . . . . . . . . . . . . . . . . 96

4.3 Comparison of the interface quality density Nit . . . . . . . . . . . . . 98

4.4 Comparison of the mobility of the NMOS long channel devices. . . . . 99

4.5 Threshold voltage change of the SC devices. . . . . . . . . . . . . . . 101

A.1 Coordinate system for calculating the remote Coulomb scattering pa-
rameter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118

A.2 Coulomb elastic scattering of a plane wave. . . . . . . . . . . . . . . . 120

xv
B.1 Picture of the probe station and measurement setup. . . . . . . . . . 126

B.2 Equipment setup for the I-V measurement. . . . . . . . . . . . . . . . 127

B.3 The IDS -VGS characterization front panel for LabVIEW. . . . . . . . 128

B.4 The IDS -VDS characterization front panel for LabVIEW. . . . . . . . 130

B.5 Equipment setup for the CV measurement. . . . . . . . . . . . . . . . 133

B.6 The CG -VG characterization front panel for LabVIEW. . . . . . . . . 134

B.7 The stress and IV sweep front panel for LabVIEW. . . . . . . . . . . 136

B.8 Equipment setup for the charge pumping. . . . . . . . . . . . . . . . 138

B.9 The variable amplitude charge pumping characterization front panel

for LabVIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 139

B.10 The variable base charge pumping characterization front panel for Lab-
VIEW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

B.11 The noise PSD spectrum versus bias front panel for LAbVIEW. . . . 145

xvi
 Chapter 1: Introduction

1.1 1/f Noise in MOSFET

In solid state devices, noise appears as current or voltage fluctuations, which can

arise from several sources. The inherent noise of electronic devices affects many

aspects of electronic system development, for example, the signal-to-noise ratio sets

the minimum detectable power of a communication system [1]. In addition to the fact

that noise is a performance feature in every generation of electronic devices, noise can

serve as a investigative tool to determine important device parameters. Also, noise can

be employed to predict the reliability of devices and integrated circuits [2]. Generally,

the noise in devices can be classified into several categories: thermal noise, shot noise,

generation-recombination noise, random telegraph signal (RTS) noise, and 1/f (or so

called flicker or low-frequency) noise. In this dissertation, we will focus on the 1/f

noise of scaled high-K MOSFET with both experimental and theoretical studies.

1.1.1 Introduction and Review of 1/f Noise Theories

Low frequency noise is characterized generally by its current or voltage power

spectral density S(f ) (PSD), which is inversely proportional to the measurement

frequency. In circuit designs, the historical method of treating this noise is to refer

1
Figure 1.1: Spectrum of low frequency or “1/f ” noise versus frequency. The y-axis is
usually power spectral density (PSD), the x-axis is frequency. As a common practice,
both axes are in log scale.

the PSD, which appears as a fluctuation in the MOSFET drain current, to a voltage

PSD in series with the gate electrode. The drain current PSD can be converted to

the so-called “input-referred” noise at the gate electrode by dividing the drain PSD
2
by gm where gm is the transconductance of the transistor. For device study itself,

the drain current PSD is often compared and studies directly. If the measured power

spectral density S(f ) has a slope, which is inversely proportional to frequency with

a constant f γ , where γ is approximately 1, then the measured noise is considered as

“1/f ” noise (as shown in Figure 1.1). Surface channel MOSFETs show a large noise

at low frequencies, which make the study of 1/f noise very important [3].

The flicker noise study in semiconductors started even before the development of

the MOSFET [4]. The origin of 1/f noise in MOSFETs has been discussed for nearly

2
half a century [5], and, although there have been attempts to develop a unified 1/f

noise theory, there is still discussions on this subject, especially with the scaling of

MOSFET gate dielectrics MOSFETs.

There are two major theoretical approaches to the origin of low-frequency, or 1/f

noise: 1) the carrier number fluctuation model, which attributes the observed 1/f

noise to fluctuation of the number of inversion-layer carriers caused by the capture

and emission of the carriers into trap centers close to the substrate/dielectric interface

[3, 6–8], and 2) the bulk mobility fluctuation model, which ascribes the 1/f noise in

the inversion layer conductance to fluctuations in the mobility of the free carriers in

the conducting channel of the MOSFET [9].

The number fluctuation model, originally proposed by McWhorter [6], states that

the random trapping and detrapping processes of charges in the oxide traps near the

dielectric-semiconductor interface results in surface potential fluctuations, which in

turn modulates the channel carrier density. As shown in Figure 1.2), when carriers

travel from the source to the drain terminal under the effect of electric field, the traps

lie within the oxide layer can interact with these carriers by capture and emission

mechanisms, and therefore the overall channel conductance fluctuates which leads to

drain current fluctuation.

Sah [10] applied the theory of Shockley-Read-Hall (SRH) trapping to explain the

low frequency noise arising from bulk traps in the p-n junction gate space-charge

region in junction gate field effect transistors (JFETs) and derived the 1/f frequency

dependence of the noise spectrum density, which resulted from traps in this p-n junc-

tion transition region of the JFETs. Sah and Hielscher [7] demonstrated qualitative

and quantitative correlation between the lossy part of the gate impedance, due to

3
 -
-
- - - - - -
n+ n+

Figure 1.2: Cross-section of the MOSFET depicting the trapping and detrapping of
the electroncs in the channel from oxide traps.

recombination with semiconductor interface traps, Dit over the silicon energy band

gap,and the 1/f noise power spectrum.

Christensson et al. [3] analyzed the tunneling of carriers from the MOSFET inver-

sion layer to traps in the gate oxide and showed this process gave rise to a dispersion

of time constants, which added up to yield a 1/f noise spectrum (as depicted in

Figure 1.3). In their analysis, which is based on PMOS transistors, carriers in the

inversion layer can tunnel from the valance band to near interface oxide traps at a

certain distance from the interface and then be captured. When a carrier is emitted

by an oxide trap, it can tunnel back into the channel area and adds up to the de-

vice drive current. For each oxide trap, there is a specific time constant associated,

which depends mainly on the distance from where the trap is located to the interface.

The dispersion of the time constants gives rise to the 1/f noise spectrum. Figure 1.3

includes a schematic picture of such capture and emission processes for the case of

electrons in NMOS devices (processes i and ii).

4
Figure 1.3: Energy diagram of the oxide-semiconductor interface region to explain the
two competing theories concerning the communication of the carriers and the oxide
traps. The black arrows represent the Christensson et al. [3]’s theory: i - tunneling
into or out of a near interface oxide trap and ii - capture/emission processes; the red
dashed arrows represent the Fu and Sah [11]’s theory: a - captured or emitted by an
interface state and b - tunneling into or out of a near interface oxide trap.

5
 Later, Fu and Sah [11] proposed a different model which requires an intermediate

state for the communication between the carriers and the oxide traps. In this model,

the carriers in conduction or valence bands communicate with interface states located

at the interface through the SRH process. The carriers then tunnel into or out of the

oxide traps located at some distance away from the interface elastically. This process

is also shown in Figure 1.3 (processes a and b). In the context of noise analysis,

these two competing theories (Christensson et al. [3] and Fu and Sah [11]) lead to the

dispersion of the time constants in a similar way. The time constants are dominated

by the tunneling time, since the capture/emission time constants are much shorter

than the tunneling time constants [11]. The time constants in Fu and Sah [11]’s

model could be slightly larger than those in Christensson et al. [3]’s model, since

the potential barrier is defined between the interface state and the oxide trap in

[11]; whereas this potential barrier is defined roughly the barrier height between the

semiconductor and the oxide dielectric in [3].

Reimbold [8] developed the number fluctuation theory further, by taking into ac-

count all the capacitive components in a small signal device model. This model is

further supported by the widely observed correlation between the low-frequency noise

and interface trap density. Celik-Butler and Hsiang [12] and Jayaraman and Sodini [13]

presented the employment of 1/f noise measurements to extract the trap density at

and near the interface.

As the area of the MOSFET is scaled below 1 um2 , where there is only one or

two traps detected to participate in the drain current fluctuation at the time of mea-

surement, a phenomenon called random telegraphy noise (RTS) can be observed.

6
Figure 1.4: Example of random telegraph signal (RTS) noise measured in the drain
current of a MOSFET as a function of time [14].

Figure 1.4 includes an examples of the RTS measured in the drain current of a MOS-

FET as a function of time. The times in the high- and low-current states correspond

to carrier capture and emission respectively [14]. Although the title of this publica-

tion by Kirton and Uren [14] says “interface”, later experiments and publications by

the same group of authors states that the traps responsible for RTS noise reside in

the oxide and these traps have a wide range of time constants and are also responsible

for 1/f noise [15].

For each individual trap, its communication with the carriers in the channel will

induce a small amount of current fluctuation. Such fluctuation will generate a RTS

noise versus time, if fed to an oscilloscope type of current monitor. If this fluctuation

due to a single trap is transformed into frequency regime, it will be a Lorentzian

power spectra over the frequency which is flat from DC and roll off as “1/f 2 ” once it

reaches certain turnover frequency [15]. If we consider all the oxide traps lying in the

dielectric layer of a MOSFET, the time constants spread to a wider distribution. The

7
total noise will be the rms sum of all the Lorentzian spectra components with different

amplitude and turnover frequencies. The resulted spectrum will demonstrate “1/f”

behavior.

The mobility fluctuation model, on the other hand, is an empirical model based on

experimental observations. The fluctuation of mobility is proposed to be caused by

acoustic phonon scattering [16]. The mobility fluctuation model, which gives a good

prediction for p-type devices in strong inversion, fails to explain the mobility behavior

in weak inversion [17]. The so-called noise coefficient αH in this model varies from

device to device and lacks strong theoretical definition [5]. However, this so-called

“Hooge parameter” αH is often utilized as a figure of merit for noise performance

comparison.

Since the general measured noise in MOSFETs has a more complicated depen-

dence on the gate bias and oxide thickness than either the number or mobility fluc-

tuation model predicts, Hung et al. [18] proposed a “Unified Model” which correlates

both the number and surface mobility fluctuation theory. In this Unified Model, the

fluctuation in the occupied oxide trap density induces the fluctuation of the free car-

rier density in the inversion layer, as mentioned previously in number fluctuation. At

the same time, this fluctuation in the occupancy of the oxide traps also perturbs the

carrier mobility, due to the scattering effects of the oxide trapped charges on the car-

riers. This model proposes a parameter “α” which represents the correlation between

the oxide traps and the mobility limited by oxide charge scattering. The total drain

current noise PSD is [18]

2
I 2 kB T

1
SID (f ) = D + αµ ρt (Ef n ). (1.1)
λW Lf Nn

8
where ID is the drain current, λ is the attenuation coefficient of the carrier wave

function in the oxide, W and L are the width and the length of the MOSFET, Nn is the

inversion carrier density, µ is the total mobility, and ρt (Ef n ) is the volume trap density

around the quasi-Fermi level Ef n , which is assumed independent of the distance. In

this model, the correlation coefficient α is treated as a fitting parameter. This Unified

Model yielded better results for both n and p type MOSFETs over a wide temperature

and bias range. Later in 2000 Vandamme and Vandamme [19] in a critical review [19]

points out that the screen scattering coefficient in the Unified Model is not a constant

versus the gate voltage since the channel mobility demonstrates dependence on the

inversion carrier density.

1.1.2 Low Frequency Noise in Scaled CMOS Devices

The new materials and structures can have a direct impact on the 1/f noise. The

scaling of the device dimensions also reduce the operating voltages, which in turn

lowers the signal-to-noise ratio. With these changes, the 1/f noise performance of

scaled CMOS devices needs to be carefully evaluated.

The incorporation of high-K dielectrics into MOSFET overcomes the issue of gate

leakage current; however, the process gives rise to other issues such as an observed

increase in the trap density at the silicon interface, which resulted in one or two or-

ders of magnitude increase in the observed 1/f noise than its SiO2 counterpart [20].

Several papers reported increased trap density in high-K MOSFET devices with noise

techniques [21, 22]. In addition to the increase in the magnitude of the interface trap

density, for a multiple dielectric gate stack, the high-K process is more complex, since

traps exist in both the high-K layer and the interfacial layer. The Unified Model,

9
which has been developed for the conventional Si-SiO2 system, does not include the

multi-stack, high-K and interfacial SiO2 structure into the formalism. Therefore, dis-

crepancies are reported when extracting the dielectric trap density from the noise data

with the original Unified Model. Morshed et al. [17] presented a physics-based 1/f

noise model for a multi-layered structure consisting of a high-K gate dielectrics and

the interfacial SiO2 film and this so-called Multi Stack Unified Model (MSUM) has

been reported to eliminate the previously mentioned discrepancies. In this treatment,

the correlation parameter “α” is still treated as a fitting parameter, although the de-
1/2
pendence on the inversion carrier density is considered, by assuming α = (µcoNN )−1

where µco itself is a fitting parameter. 1/f noise is becoming suitable parameters for

evaluating the impact of difference processes conditions on the gate stack quality and

is more and more being used for that purpose [23–25].

In the scaled devices where the vertical electric field is raised, the surface roughness

scattering has become significant in determining the carrier mobility. The fluctuation

of surface roughness scattering should be taken into account into the 1/f noise mod-

eling where the fluctuation in the carrier density perturbs the surface field and leads

to fluctuation in the channel current, i.e., drain current noise.

In addition to 1/f noise, RTS noise has become more important than before. As the

device area keeps decreasing, the number of detected traps is smaller thus make RTS

noise more apparent than devices with larger areas. In modern scaled CMOS devices,

RTS noise is not only a noise phenomenon, but also a major source of variability in

threshold voltages: RTN noise will increase the threshold voltage variation which will

impact the noise margin in SRAM designs [26, 27]. The temporal behavior of RTS

makes it difficult to screen for RTN-affected devices in manufacturing [27].

10
 Despite the research interests and reported study, several aspects are still missing

in the understanding and modeling of 1/f noise study 1) the correlation coefficient

“α” has historically been treated as a fitting parameter; 2) there has been no con-

sideration of the correlation between the surface field fluctuation, due to inversion

carrier density, and the fluctuation in the carrier mobility; 3) the quantization effects

at the semiconductor substrate are neglected. Therefore, it is necessary to develop

a quantum mechanical treatment to take into account of these effects and promote

better understanding of 1/f noise in scaled MOSFET devices.

1.2 CMOS Scaling and Advanced Gate Dielectrics

In the past several decades, the Complementary Metal Oxide Semiconductor

(CMOS) technology evolution has followed the device scaling recommendations of

the International Technology Roadmap for Semiconductors (ITRS) [28]to achieve

high density, high speed and low power dissipation. As a consequence, the feature

size (i.e., ITRS node) and metal oxide semiconductor field effect transistor (MOS-

FET) channel length have been reduced from several microns in the 1970’s to below

20 nm in 2013. Two key features characterize this era of “shrinking”: 1) the focus

on scaling through constant improvements in lithography, guided by certain scaling

principles; 2) the introduction and incorporation of new materials and structures.

1.2.1 Scaling Principles

The most widely followed scaling principles are constant-field scaling [29] and

generalized scaling [30]. In constant-field scaling, the device physical dimensions and

applied voltages are reduced by a factor of α (α > 1) and the substrate doping

concentration is increased by α in order to maintain the constant electric field in

11
 Figure 1.5: Schematic illustration of MOSFET constant electric field scaling [31].

the device and prevent short-channel effects (as depicted in Figure 1.5). Table 1.1

features some featured scaling rules for the constant field scaling. One of the most

important benefits of scaling is the increased circuit density, which was seen in the

early days of integrated circuits as a key to reduce manufacturing costs, but over

the years it has changed the overall blueprint of computing. The incentive for this

scaling principle is that the circuit speed is improved by a factor of α and the power

dissipation is reduced to 1/α together with the constant power density.

However, the requirement of reducing the voltage by the same factor as the device

physical dimensions is too restrictive. The MOS device subthreshold region does not

scale and a reluctance to depart from the standardized voltage levels of the previous

generation meant that the operating voltages were seldom scaled proportional to the

scaling of the device channel length. Thus it was necessary to develop a more general

set of guidelines that allow the electric field to increase. In such “Generalized Scaling”

(also presented in Table 1.1), the physical dimensions are still scaled with the same

12
 MOSFET Constant-Field Scaling Generalized Scaling
Device Parameters α>1 α>β>1
Physical dimensions 1/α 1/α
Substrate doping density α α/β
Operating voltage 1/α β/α
Drain current 1/α β/α
Circuit area 1/α2 1/α2
Capacitance 1/α 1/α
Circuit speed α α (goal)
Power dissipation 1/α2 β 2 /α2
Power density 1 β2
Power-delay product 1/α3 β /α3
2

Table 1.1: Scaling principles for CMOS devices (scaling factors α > β > 1) [29, 30].

factor of α as in constant field scaling; however, the operating voltage is only scaled to

β/α, where this new scaling factor β is smaller than α, but larger than 1. In this way,

the desired design is less restrictive, but the scaling benefits can still be achieved with

the increased circuit density and speed. However, the power density is increased by

a factor of β 2 . It was difficult to achieve high performance and low power dissipation

at the same time with the traditional CMOS technologies.

1.2.2 Technology Improvement to Continue “Shrinking”

As mentioned previously, there have been quite a few technologies introduced into

the MOSFET design to increase scaling, especially in the past ten years. Two key

incentives of these technologies are: 1) to improve the drive current; 2) to reduce

the short channel effects (SCE). Examples of the former are mobility enhancement

through strain and alternative substrate materials. Examples of the latter include: 1)

13
 (a) NMOS: Silicon nitride capping layer (b) PMOS: SiGe selective heteroepitaxy
creates a tensile stress to enhance elec- film creates a compressive stress to en-
tron moblity. hance hole mobility.

Figure 1.6: Strain introduction in CMOS for mobility enhancement [33].

using multi-gate structures such as double gate and FinFET (or tri-gate) structures;

2) using the advanced gate dielectrics such as high-K materials.

Strain enhancement of mobility in silicon has emerged as one of the key elements

in the scaling of CMOS devices since it offers an increased drive current without the

penalty of additional capacitance, although the complexity of fabrication is also raised.

Electron and hole act differently concerning the direction of the applied stress. In

modern CMOS technology, for NMOS, a tensile capping layer of silicon nitride can be

deposited on top of the fully formed transistor, enhancing the electron mobility [32].

For PMOS, compressive strain is implemented in the channel, achieved by etching

silicon and growing heteroepitaxy material (such as SiGe) in the S/D region after

formation of the gate stack, S/D extensions and spacer [33].

In addition to increasing the conduction current when the device is “on”, efforts

have also been paid to reduce the leakage current when the device is “off”. The

14
increase off-current is one of the most serious SCE’s since the gate is losing control

of the channel and there will be no significant distinctions between the two states

thus no switching behavior. Remedies for this increased off-current primarily fo-

cus on eliminating the off-current path between the source and drain. Successful

demonstrations include silicon-on-insulator (SOI) technology, multi-gate structures

etc Figure 1.7. These advanced structures require excellent control of process and of

course cost more than the traditional bulk technology. However, they are the price

that has to be paid to increase scaling.

In SOI, the channel is located in an ultra-thin crystalline silicon layer sitting on

top of a thick oxide, thus, there is no leakage path between the S and D terminals.

Besides reducing the S-to-D leakage current, SOI technology also significantly reduces

junction capacitance and allows the circuits to operate at higher speed or substantially

lower power at the same speed. SOI structure also eliminates latch up in bulk CMOS,

alleviates the short channel effect and soft error immunity. SOI CMOS process can be

readily developed due to the compatibility with established bulk process technology.

The challenges SOI faces are the raised cost and lack of a good stress approach for

mobility improvement.

The Multi-gate devices exhibit a scaling advantage due to better gate control of

the channel charge. With tri-gate [34] or FinFET [35] structures, in which the gate

wraps around the active silicon area, all surfaces, including the side of height and

the top surface of width, contribute to the channel conduction. With the elevated

structure, the FinFET can provide a much wider effective channel width than the

actual width it takes horizontally. More importantly, because the gate has more

control of the channel charge, the off-current path is eliminated between the source

15
Figure 1.7: SOI and multi-gate architectures which reduce source-drain interaction
[36].

and the drain terminal. Therefore, the on/off current ratio can be increased, which

means better switching capability. The improved performance of FinFET for thinner

width (body thickness) is directly related to the better short channel scaling behavior

of the device, which allows lower threshold voltage. The ultimate stage of this multi-

gate structures will be a “surrounding-gate” structure where the channel is more like

a nano-wire wrapped by gate dielectric and gate electrode. The fabrication process of

FinFET is more complicated than the planer counterpart considering step coverage,

gate contact, variability of the fin thickness, interface qualify of the side wall etc.

1.2.3 Advanced Dielectrics High-K Materials

It is important to ensure that it is the gate terminal, rather than drain, that

controls the channel current flow. For this purpose, the gate dielectric layer is scaled

16
Figure 1.8: Scaling trend of the physical length L and effective oxide thickness (EOT)
[28]. The diamond symbols represent the physical gate length, the dot symbols depict
the EOT and the triangular symbols represent the electrical EOT.

together with the channel length to mitigate short-channel effects and improve device

performance.

Figure 1.8 shows the scaling trend of the physical length (Lg ) and the effective ox-

ide thickness (EOT), which is defined as (Kox /Kf )/tf , where tf is the physical thick-

ness of an overlying dielectric of relative dielectric constant Kf and Kox is the relative

dielectric constant of silicon dioxide [28]. In the same figure, the electrical effective ox-

ide thickness (EOTelec ) is also shown, which includes the previously-mentioned EOT,

depletion layer effects in the gate electrode (e.g. polygate depletion) and the finite

extension of the inversion carrier distribution in the silicon substrate [28]. The figure

shows a prediction of the scaling trend in the next 5 years.

17
 In the early years of CMOS scaling (1960-2000), silicon dioxide SiO2 had been the

gate dielectric used by silicon-based integrated circuits (ICs). A primary reason for

this selection had been the excellent quality of the Si-SiO2 system. In this period,

the Si-SiO2 interface was characterized by interfacial trap densities (Dit ) around 1010

cm−2 eV−1 , which provided surface recombination velocities less than 1 nA/cm2 . In

addition, bulk SiO2 trap densities (Not ) were less than 1017 cm−3 eV−1 and did not

affect adversely the stability of device threshold voltages. However, as feature sizes

moved below the 65 nm ITRS node, the corresponding oxide thickness fell below 2

nm and direct tunneling causes a dramatic increase in gate leakage current densities

as a consequence of quantum mechanical tunneling [37] as shown in Figure 1.9.

Clearly, the increase in gate current became intolerable when the increase in

standby power dissipation caused excessive chip heating as power densities approached

and exceeded 100 W/cm2 , which affected device and circuit reliability as well as per-

formance [38]. It was challenging enough to deal with dynamic power dissipation at
2
the gate level (Pd = C · VDD · fc ) where C is the load capacitance, VDD the drain

supply voltage and fc the clock frequency; but now designers were faced with a rising

standby power dissipation at the device level, which was (IGL + IDL ) · VDD where IGL

and IDL are the gate and drain leakage currents, respectively.

This limitation in the vertical scale also rises from the manufacturability point

of view. When the desired oxide film is only a few monolayers thick, the variation

of these films over a 300 mm silicon wafer is of substantial concern. A variation in

thickness of only 1 Å could result in changes in device operating conditions, making it

extremely difficult to maintain the device tolerances. As scaling of the oxide thickness

continues, it is desirable to maintain or increase the reliability of such films. However,

18
Figure 1.9: Measured and calculated oxide tunneling currents vs. gate voltage for
different oxide thickness [37]. As the oxide thickness is scaled thinner, the gate leakage
current increases dramatically.

19
when the oxide thickness goes to nanometer level, it is not easy to guarantee the oxide

quality any longer.

The solution to this dilemma was to increase the physical thickness of the gate

insulator to inhibit the direct tunneling, yet as the same time decrease the electric

thickness of the gate insulator. This was possible through the introduction of new

gate insulators with higher relative dielectric constants. These insulators became

known as high-K dielectrics. The use of high-K materials reduced the gate tunneling

current by orders of magnitude and consequently reduced the static power dissipation

caused by the gate tunneling currents. The requirement and challenges for high-K

gate dielectric in CMOS include: 1) large bandgap and sufficient barrier height to Si;

2) thermodynamic stability on Si; 3) interface quality; 4) film morphology; 5) gate

material compatibility; and 6) charge trapping and reliability.

Compared to SiO2 , high-K gate dielectrics exhibit a substantial flatband voltage

shift due to positive fixed charges in the high-K film with associated charge trapping.

The high fixed charge density, believed to originate from the detailed bonding of the

atoms associated with the dielectric near the dielectric/semiconductor interface [39].

There are also oxygen vacancies which act as carrier traps and high leakage paths in

these high-K materials [39]. These defects pose serious issues for threshold voltage

control and carrier mobility degradation, as well as 1/f noise. An ultra-thin SiO2

film (typically less than 0.5 nm in thickness) is placed between the high-K dielectric

and the silicon surface to ensure a good interface between the semiconductor and

the dielectric layer. For such composite gate dielectric layers, the total EOT (Xef f )

becomes
 
Kox
Xef f = XIL + Xf (1.2)
Kf

20
where XIL is the thickness of the SiO2 interfacial layer, Kox is the dielectric constant

of SiO2 , Kf is the dielectric constant of the high-K material, and Xf is the thickness

of the high-K layer. This SiO2 interfacial layer will increase the total EOT, thus it

should be kept very thin to maintain the scaling benefits. Besides, process improve-

ments, such as post high-K deposition anneals and interfacial layer optimization, is

required to minimize this fixed charge, which will affect the electrical characteristics

and reliability of CMOS devices and their applications.

Based on the above criteria, dielectric materials such as SiON and HfO2 were

implemented successfully (starting with the 45 nm ITRS node) as part of the gate

dielectric, to alleviate the issue of gate leakage current, increase the gate capacitance

for current drive and reduce short channel effects [40].

1.3 Dopant Profile Control in Nanoscaled CMOS Technology

In the very early MOS technology in the 1970’s, the doping profile was constant

in the substrate. For a uniform channel doping, the maximum gate depletion width

at the 2φF condition, s

4ǫS φF
Wdm = (1.3)
qNA

where
kB T NA
φF = ln( ) (1.4)
q ni

is the difference between the Fermi level and the intrinsic potential in the bulk region

for a doping concentration of NA , and kB is the Boltzmann’s constant, q is the electron

charge, ni is the intrinsic carrier density. The depletion charge term of the threshold

voltage,
√
−Qd qNB Wdm 4ǫS qNA φF
= = (1.5)
Cox Cox Cox
21
are coupled through the substrate doping concentration NB , and therefore cannot be

varied independently. In order to control the short-channel effect, the depletion width

should be small enough so that Wdm + tox is smaller than L/2, due to the exponential

factor in the short-channel VT H expression [41]. However, the doping concentration

that satisfies this requirement may not give the desired threshold voltage that satisfies

the on and off-current requirements.

Therefore, for a given Wdm , it is necessary to employ nonuniform doping to adjust

the depletion charge density to obtain the desired Vth . Nonuniform channel doping

gives the device designer some additional flexibility to adjust the profile for meeting

both the SCE and the threshold requirements. Such an optimization is made possible

by the ion implantation technology.

In modern MOS technology, the doping profile designing is focused on two aspects:

1) alleviating the short-channel effects; 2) the threshold voltage adjustment implants.

The former is achieved by halo doping region and ultra-shallow junction, the latter

is achieved by multi-step implants at different energy and dose and annealing steps

which are carefully designed.

In the lateral direction, nonuniform doping is also used in very short-channel

devices. For nMOSFETs, it is achieved by a medium-dose p-type implant carried out

together with the n+ source-drain implant after gate patterning. The p-type doping

peaks near the source and drain ends of the device but dips in the middle because of

blocking of the implant by the gate, as showing in Figure 1.10.

Such a self-aligned, laterally nonuniform channel doping is refereed to as halo or

pocket implants [42]. The short channel effects predict the threshold voltage rolloff

toward the shorter devices within a spread of the channel length. At the longer end of

22
 (a) Long Channel (b) Short Channel

Figure 1.10: Laterally nonuniform halo doping in nMOSFETs [41]. For a given design
length on the mask, there is a spread of the sctual gate lengths on the wafer. The
longer end of the spread is shown in (a), the short in (b). The sketch below each
cross section shows the schematic doping variation along a horizontal cut through the
source and drain regions. In the shorter device, the doping is higher in the middle of
the channel due to the overlap of the p+ pocket spread. This increased doping helps
to reduce short channel effects.

the spread, the two p+ pocket are farther apart than at the shorter end of the spread

of shorter end. This creates a higher doping in the shorter device than in the longer

device. Higher doping means higher threshold voltage. So laterally nonuniform halo

doping establishes a tendency for the threshold voltage to increase toward the shorter

devices, which works to offset the short-channel effect in the opposite direction [41].

For nanoscaled MOSFETs, to reduce the threshold voltage without significantly

increasing the gate depletion width, the vertical doping profile is desired to be a

low-high doping, i.e., the so-called “retrograde” doping [43]. Such a profile is formed

using higher-energy implants that peak below the surface. The net effect of low-

high doping is that the threshold voltage is reduced, but the depletion width has

increased, within reasonable amount. Such design will minimized the deletion width

thus effective prevent punch-through between the source and drain region, and at the

23
same time, avoid to increase the surface field, which will induce surface roughness

scattering. The intermediate surface doping concentration itself will yield better

carrier mobility than the high doping density, due to reduced Coulomb scattering

caused by ionized dopants.

One challenge in controlling a well-defined substrate dopant profile, especially

boron profile in NMOS, is the boron diffusion in silicon, especially during high tem-

perature treatment, such as oxidation, annealing etc. During oxidation, oxidization-

enhanced diffusion due to injection of self-interstitials contributes significantly to

dopant redistribution and makes the desired doping profiles very difficult to real-

ize. This redistribution can be of great concern for boron, the diffusivity of which is

mainly determined by the concentration of self-interstitials [44]. This enhanced diffu-

sion is mainly due to the interstitial sites in the silicon substrate. These sites act like

stepping stones for boron to diffuse through the silicon. The implant damage causes

more sites like this than it is already in there. And this became a serious problem for

scaling MOSFETs.

1.4 Scope of the Dissertation

This dissertation focuses on the trapping effects of nanoscaled CMOS devices with

high-K and high-quality SiON dielectrics. In particular, 1/f noise mechanisms in these

scaled devices are investigated. We have also compared a variety of performances and

physical properties of both N and P type advanced transistors. This dissertation also

includes the device study of channel carbon ion implantation in nanoscaled CMOS

devices fabricated with replacement gate technology.

24
 Chapter 2 presents a quantum mechanical treatment of 1/f noise for nanoscaled

high-K NMOS transistors. This treatment addresses the importance of including the

surface roughness scattering in 1/f noise. Our work also provides a theoretical analysis

to model the remote Coulomb scattering component in 1/f noise. Both theoretical

and experimental work is included and they agree well with each other.

Chapter 3 presents the characterization of advanced SiON CMOS transistors.

Capacitance-Voltage (C-V), Current-Voltage (I-V), charge pumping and stress mea-

surement are employed to study and compare the carrier mobility, interface trap

density, charge trapping properties etc. of the advanced SiON CMOS devices. Com-

prehensive measurement and analysis are performed and included in this chapter to

study the physical properties of these devices.

Chapter 4 introduces the device characterization on channel carbon ion implan-

tation utilized in advanced replacement gate platform. The work included provides a

novel and cost-effective solution to the dopant profile control and threshold voltage

reduction for advanced CMOS development.

Chapter 5 concludes this dissertation and provides suggestions for future work.

In addition, the detailed derivation of the remote Coulomb scattering parame-

ter is included in Appendix A. Appendix B documents the measurement operation

developed in our lab for the employed characterization techniques presented in this

work. The MATLAB®programs coded and utilized for the work in this dissertation

is included in Appendix C for completeness.

25
 Chapter 2: A Quantum Mechanical Treatment of Low
Frequency Noise in High-K NMOS Transistors with
Ultra-thin Gate Dielectrics

According to a so-called Unified Model, the measured 1/f noise in MOSFETs is

a result of the correlation of both number and the mobility fluctuations [18]. The

number fluctuation is modeled in detail, based on capture-emission and tunneling

mechanisms [3, 6]. The correlated mobility fluctuations, on the other hand, have

generally been treated as a fitting parameter in various noise models [18], which is still

the case even in the recently proposed so-called Multi-Stack Unified Model (MSUN)

[17], and this chapter attempts to provide a theoretical treatment for this scattering

parameter which deals with the remote Coulomb scattering of the carriers by the

oxide trapped charges. The Unified 1/f noise model has historically treated mobility

fluctuations as arising only from the trapped charges assuming the above-mentioned

correlation would be sufficient to explain the experimental results. However, the free

carriers, along with the ionized impurities in the space-charge region beneath the

surface, are responsible for the transverse (normal) electrical field that acts on the

free carriers to either attract or repel these carriers from source to drain [45]. The

trapping-detrapping mechanism induces fluctuation of the carriers in the inversion

layer, which in turn, perturbs the effective vertical field acting upon the carriers, which

26
gives rise to fluctuation in surface roughness mobility. As scaling continues beyond

the 22 nm node, the effective oxide thickness of modern MOS devices is easily less

than 1 nm. The vertical electrical field is increased significantly; therefore, the surface

roughness scattering plays a more important role in the total mobility. Because of

the inclusion of high-K materials into the gate composites, modern CMOS devices

demonstrate stronger trapping effects, which make the 1/f noise a more important

consideration in both analog and digital integrated circuits [21].

In order to obtain a comprehensive understating of the noise mechanism in high-

K MOSFETs with ultra-thin dielectrics, we have included the influence of surface

roughness into the 1/f noise theory. We employ a Quantum Mechanical treatment

to obtain an analytical model for the mobility scattering parameters and conduct

experimental characterization to validate the proposed model.

2.1 Theoretical Modeling

2.1.1 The Noise Model

We begin with the idea that the fluctuations in the free carriers density in the

inversion layer and the trapped charge density in the near interface region are cor-

related and responsible for the fluctuations in both the drain current and carrier

mobility in a MOS transistor. Since the drain current, ID , is the product of the free

carrier concentration and carrier mobility, we can express its fluctuations as

δID 1 δ(∆N) 1 δ(µ) 1 δ(µ) δ(∆N)

= δ(∆NT ) + δ(∆NT ) + δ(∆NT ) (2.1)
ID ∆N δ(∆NT ) µ δ(∆NT ) µ δ(∆N) δ(∆NT )

where the last term represents the influence of the free carrier fluctuations on the

mobility - a term not considered by previous researchers [3, 6, 17, 18]. The incremental

quantities ∆N = NW ∆y and ∆NT = NT W ∆y are the number of free carriers and

27
Figure 2.1: MOSFET structure showing the infinitesimal segment ∆x of the channel
[18].

occupied traps in a segment ∆x of the channel (as shown in Figure 2.1). The ratio

R = δ(∆N)/δ(∆NT ) has been called a “coupling coefficient” [8] and is nearly unity

in very strong inversion. In order to proceed in the development of a unified 1/f noise

model, we need to consider the various components of the carrier mobility. In our

model, we believe the mobility can be composed of three major components: µ0 , µc

and µsr , where µc is the mobility limited by remote Coulumb scattering, µsr is the

mobility limited by surface roughness scattering and µ0 is the mobility limited by

other scattering mechanisms [46, 47]. Based on the Matthiessen’s rule,

1 1 1 1
= + +
µ µ0 µc µsr
1
= + αNT + β(2NB + Nn ) (2.2)
µ0
1 2β 1
= + αNT + (QB + Qn )
µ0 e 2

28
where α is the Coulomb scattering coefficient, β is related to surface roughness scat-

tering. The modeling of these two parameters will be introduced later in Section 2.1.3

and Section 2.1.4 respectively. We differentiate Equation (2.2) to obtain

δµ αµ2 δµ βµ2
=− and =− (2.3)
δ(∆NT ) W ∆x δ(∆N) W ∆x

which allows us to write

δID 1
=− [1 + (α + β)N] δ(∆N) (2.4)
ID ∆N

where we have assumed R ≈ 1. We have neglected the fluctuations in depletion

charge caused by fluctuations in the surface potential. The power spectrum density

of the local current fluctuation is

 2
ID
S∆ID (x, f ) = (1 + (α + β)µN) S∆NT (x, f ) (2.5)
∆N

where S∆NT (x, f ) is the power spectral density of the mean square fluctuation in the

number of occupied traps over the area W ∆x. According to the conventional number

fluctuation theory [3], S∆NT (x, f ) is given by

S∆NT (x, f )
Z EC Z W Z Tox
τ (E, x, y, z) (2.6)
= 4NT (E, x, y, z)∆xft (1 − ft ) dzdydE
EV 0 0 1 + ω 2τ (E, x, y, z)2
where NT (E, x, y, z) is the distribution of the traps over the space and energy, τ (E, x, y, z)

is the trapping time constant, ft = [1 + exp(EEF n )/kB T ]−1 the trap occupancy func-

tion, Ef n the quasi Fermi level, ω = 2πf the angular frequency, Tox the total oxide

thickness, and EC − EV the silicon energy gap [18].

If we adopt the same assumptions as in [18]: 1) the oxide traps have a uniform

spatial distribution near the interface, i.e, NT (E, x, y, z) = ρt (E); 2) the probability

of an electron penetrating into the oxide decreases exponentially with the distance

29
from the interface. The second assumption leads to the expression for the trapping

time constant as

τ = τ0 (E) exp(λz) (2.7)

where τ0 (E) is the time constant at the interface and λ is the attenuation coefficient of

the electron wave function in the oxide [3, 11]. The WKB theory for carrier tunneling

predicts that
2p ⋆
λ= 2m (ΦB − EAVE ) (2.8)
~

where m⋆ is the effective mass of the carrier in the gate dielectric, ΦB is the tunneling

barrier height, and EAVE is the average energy of all the carriers.

Since the term ft (1 − ft ) in Equation (2.6) behaves like a delta function around

the quasi-Fermi level, the major contribution to the integral will be from those trap

levels around EF n . Thus ρt (E) can be approximated by ρt (EF n and taken out from

the integral. Replacing ft (1 − ft ) by −kB T dft /dE and carrying out the integration

gives [18]
kB T W ∆x
S∆NT (x, f ) = ρt (Ef n ) . (2.9)
λf

Therefore the total drain current noise power is [18]

Z L
1
SId (f ) = 2 S∆ID (x, f )∆xdx
L 0
2 Z L
 2 (2.10)
kT ID 1
= ρt (EF n ) + (α + β)µ dx.
λf W L2 0 Nn (x)

At very low drain voltages, the carrier density is uniform along the channel, and the

drain PSD can be expressed as

2
I 2 kB T

1
SID (f ) = D + (α + β)µ ρt (EF n ). (2.11)
λW Lf Nn

30
 In the above formula (Equation (2.11)) of our 1/f noise model, the first term (Nn−1 )

inside the square bracket is related to the contribution due to the fluctuations in free

carriers, and the second term represents the correlated fluctuation in mobility.

2.1.2 Band Structure

In the previously derived expression Equation (2.11), there are several things to

be modeled and calculated to obtain the overall noise PSD: Nn , α, β, µ and ρt (EF n ).

One of the first things to do is to setup the sub-band structures, which leads to Nn

and facilitates the modeling of the scattering parameters as well.

There is a classical method to obtain the inversion carrier density by treating the

energy to be continuous at the surface [41]. However, with the continuous scaling of

CMOS devices, quantum mechanical effects within the silicon substrate become non-

negligible, especially at the surface of the substrate where the surface field is high

(as shown in Figure 2.2). These effects lead to significant quantization of the carrier

energy and a redistribution of the carries at the semiconductor and gate dielectric

interface.

The quantum mechanical treatment for the inversion layer carrier density is given

by Stern [49] under the assumptions: 1) the effective mass approximation is valid, so

we can neglect the periodic potential and use the effective masses and the dielectric

constant of the perfect crystal; 2) the envelope wave function vanishes at the surface.

The band bending at a semiconductor surface can be characterized by an electro-

static potential φ(z). Under the assumption that planar dimensions of the MOS tran-

sistor are much greater than the depth of the semiconductor potential well, therefore,

31
Figure 2.2: Energy band diagram for SiO2 /High-K structure at strong inversion [48].
EC and EV are the conduction and valence band of the semiconductor, Ei is the
intrinsic Fermi level, EF is the Fermi level at the bulk, Eg is the semiconductor
energy gap, φ(z) is the electrostatic potential at location z, and φs is the surface
potential which represents the amount of band bending at the interface. E00 , E10 and
E01 represent the lowest three subbands.

32
the vertical field is much greater than the planer electric field, the electrostatic charac-

teristics of 2-D electron gas (2-DEG) are described by the system of one-dimensional

Schrödinger and Poisson equations.

d2 Ψij (z) 2mi3

+ 2 [Eij + qφ(z)] Ψij (z) = 0 (2.12)
dz 2 ~
d2 φ(z) −q
= [NA (z) − ND (z) + n(z) − p(z)] (2.13)
dz 2 ǫs

where q is the electron charge, ~ is the reduced Plank’s constant, ǫs is the semiconduc-

tor permittivity, φ(z) denotes the electrostatic potential along the normal direction -

“z”, Ψij (z) is the normalized wave function representing an electron in the ij th state

corresponding to the discrete energy level Eij , NA (z) and ND (z) are the acceptor

and donor concentration, and n(z) and p(z) are the electron and hole concentration,

respectively. Here ‘i’ is the valley index, i = 0 for the lower valley, and i = 1 for the

higher energy valley. ‘j’ denotes the sub-band index of energy level, starting from 0.

Accurate analysis for the 2D electron gas can be most accurately obtained from

the self-consistent calculation based on Equation (2.12) and Equation (2.13) using

numerical methods. For our purpose, we employed simplified and intermediately

accurate methods to calculate the quantum mechanical effects in the inversion layer

of a silicon substrate [49, 50].

Since the semiconductor band bending at the semiconductor surface region in the

strong inversion state creates a potential well for electrons ,the electron concentration

distribution is calculated as
1 X
X ∞
n(z) = Nij |Ψij (z)|2 (2.14)
i=0 j=0

33
where Nij is the ij th sub-band inversion layer electron concentration, which can be

written as
  
nνi mdi kB T EF n − Eij
Nij = ln 1 + exp (2.15)
π~2 kB T

where nνi is degeneracy number in the i th valley, mdi is the density of state mass in

the i th valley, kB is Boltzman’s constant, T is the absolute temperature, EF n is the

Fermi level (referred to the top the conduction band), which can be expressed as
  
EG NA
EF n = qφs − (ECB − EF ) = qφs − + kB T ln (2.16)
2 ni

where φs is the surface potential, ECB is the conduction band edge at the bulk, EF

is the Fermi level at the bulk, EG is the energy bandgap of the substrate material,

NA is the substrate acceptor doping concentration, ni is the intrinsic electron density.

The conduction band edge at the surface is used as the energy reference point for the

analysis.

We explore the simplified methods to calculate the inversion layer carrier concen-

tration, one is based on the triangular potential well assumption [50] and the other

one is based on the variational approach [49].

Triangular Potential Well Approximation

We start from the triangular well approximation, which replaces the potential φ(z)

in Schrödinger and Poisson equations by FS · z inside the silicon substrate (z < 0)

and by an infinite barrier in the dielectric (z > 0) based on the assumption of a linear

shape of the potential in the semiconductor surface layer. This approximation leads

34
to the Airy function with solutions
( 1/3  )
2mi3 qEs Eij
Ψij = Ai |z| − (2.17)
~2 qEs
 2 1/3   2/3
~ 3 3
Eij = πqEs j + (2.18)
2mi3 2 4

where the surface electric field is

Es = q(NB + Nn )/ǫs (2.19)

NB is the total number of charges per unit area in the depletion layer and Nn is the

total number of charges per unit area in the inversion layer.

X
Nn = Nij (2.20)
ij
p
NB = 2ǫs φd (NA − ND )/q (2.21)

where φd is the effective band bending from the bulk to the surface, apart from the

contribution of the inversion layer itself, and

kB T qNn zav
φd = φS − − . (2.22)
q ǫS

zav is the weighted average separation of inversion charge away from the interface,

which can be calculated as

X
zav = Nij zij /Nn (2.23)
ij

and zij is approximated as 2/3 of the distance where the ij th sub-band energy level

intercepts the linear potential well, i.e.,

2Eij
zij = (2.24)
3qES

Triangular well approximation is easy to solve, if we use the surface field Es as the

unknown variable, the rest of unknowns parameters can be calculated accordingly.

35
 Start

Input Es

Eij

Nij , Nn

zij , zav Bi-section for another Es

φd , NB

New Es′ No

Es′ = Es

Yes
Save Results

End

Figure 2.3: Triangular well code flow chart.

The solving process is fast to converge as well, if certain algorithm is utilized. For the

work presented in this dissertaion, the bi-sectional method is used, with the flow chart

shown in Figure 2.3. The written MATLAB®program attached in Appendix C.

Variational Approach

The triangular-well is a reasonable approximation when there is little or no charge

in the inversion layer, but fails when the charge density per unit area in the inversion

layer is comparable to or exceeds that in the depletion layer [49]. Additionally, during

the later development of the scattering parameter modeling, this approximation is

36
found to over-simplify the field dependence of the charge separation. Due to these

facts, we need to seek another way to construct the sub-band structures. A variational

approach gives a good estimate for the energy of the lowest sub-band, when only one

subband is occupied [49]. This approach also enables us to use the Stern-Howard

wave function. For the lowest subband, the wave function is

1/2
b3i

bi z
Ψ00 (z) = z exp(− ) (2.25)
2 2

where the parameter bi is determined by minimizing the energy of the system and is

given as
1/3
12mi3 q 2
 
11
bi = NB + Nn (2.26)
ǫs ~2 32

if the small perturbation term mentioned in Stern [49] is neglected.

The variational results are as follows.

z00 = z00 + δz00 (2.27)

" #1/3
9ǫs ~2
z00 = 11

(2.28)
4m03 q 2 NB + N
32 n
4NA z00 2
δz00 = 11

(2.29)
9 NB + 32 Nn
E00 = E00 + δE00 (2.30)
 5/3  2 2/3   −1/3
3 q ~ 55 11
E00 = √ Nn + Nn Nn + Nn (2.31)
2 m03 ǫs 96 32
" #
2NA q 2 z00 2

11
δE00 = − Nn + Nn (2.32)
3ǫs NB + 11


N
32 n
96

Approximate energy levels for the excited states can be obtained in the elec-

tric quantum limit by treating the inversion-layer potential and the curvature of the

depletion potential as perturbations. The energy levels for the excited states are

37
approximately given by
2
q 2 EB En zav
2 4Eij,d
Eij = Eij,d − − + qEn zav (2.33)
4Eij,d 15qEB zd
where
1/3  2/3
~2
 
3 3
Eij,d = πqEB j + (2.34)
2mi3 2 4
qNB
EB = (2.35)
q
qNn
En = (2.36)
q
and
s
2ǫs φd
zd = . (2.37)
qNB

The second term in the Equation (2.33) is the approximate lowering of the excited-

state energy by the inversion-layer potential well. The third term gives the approxi-

mate contribution of the depletion-potential curvature to the energy levels. The last

term gives the inversion-layer contribution to the potential energy at the surface.

Unlike the previously mentioned triangular well approximation, where the whole

group of expressions can be setup by solving for the surface field Fs , there is more

than one key unknown variable (NB and Nn , at least) in the variational approach.

Iteration in 2 directions is quite inefficient. Thus, we decided to use the triangular-

well results as a starting point and iterate NB and Nn around that states for a pair

of values which achieve the self-consistency: if we use this pair of NB and Nn to

calculate the subband structures and use these new subband energy levels to obtain

another pair of NB and Nn ; when the newly-obtained NB and Nn roughly agree with

the original NB and Nn , the iteration reaches self-consistency. The implemented code

is also included in Appendix C. The simulation result and comparison are included

in the following paragraphs and figures.

38
Figure 2.4: The first three quantized energy levels (E00 , E10 and E01 ) and quasi-Fermi
level EF n versus surface potential. EF n surpasses E00 at surface potential of around
1.2 V.

Figure 2.4 depicts the first three subbands energy levels E00 , E10 and E01 as

functions of the surface potential φs . E00 is the lowest level, while E10 is slightly

lower than E01 . In this figure, what is also shown in the quasi-Fermi level at the

surface EF n . As the surface potential, φs , increases, all three subband levels increases,

along with the quasi-Fermi level. When the surface potential reaches around 1.2V,

the quasi-Fermi level surpasses the lowest subband E00 . As the surface potential

get larger, the difference between the subband levels, especially between E00 and the

other two levels are increased, indicating a more severe energy band splitting when

the electric field is increased.

39
Figure 2.5: Inversion layer carrier density versus surface potential. Most of the carriers
are located in the lowest subband E00 . As the surface potential get larger, the surface
become more “inverted”.

The carrier density located at each energy level (N00 , N01 and N10 ) versus the

surface potential is shown in Figure 2.5. Most of the carrier are located in the lowest

energy subband E00 . As the surface potential increases and the surface is more

inverted, there are more minority carriers in the channel area. N00 grows the fasted

with the surface potential. A more intuitive representation of such trend is shown

in Figure 2.6, where the composition of the total inversion carrier density is shown.

As the surface electric field increase and the total inversion carrier density get larger,

more and more carriers are located in the lowest subband E00 . Over the range where

the later simulation is conducted, more than 80% of the inversion layer carriers are

located in E00 .

40
Figure 2.6: Inversion layer carrier density composition trend. A larger portion of
carriers are located in the lowest subband E00 as the total carrier density grows.

The quantum mechanical variational approach will be used in our simulation for

the electron transport model and later the noise model. The first three subbands are

considered, as more than 90% of the inversion carrier is located in these bands and

this value increase to more than 98% for inversion carrier densities above 1 × 1012

cm−2 [49, 50].

At this point, we should develop expressions for α and β in Equation (2.11) in

order to see the influence of Coulomb scattering and surface roughness on the PSD.

In our simulation, for surface potentials greater than 1.2 V, we find over 80% of the

inversion carrier charge in the electronic ground state E00 , which lies at an energy level

of about 180 mV above the conduction band edge for devices with ultra thin oxide.

Therefore, for the modeling and calculation of α and β presented in this chapter, we

41
assume the lowest energy level E00 as the averaged energy level of all free carriers lie

in the lowest three 2D sub-band.

2.1.3 Remote Coulomb Scattering (α)

As mentioned previously, the correlated remote Coulomb scattering parameter

has been historically treated as a fitting parameter [17, 18]. The existing theories

showed discrepancies between the models and the experiments, mainly because these

models assume that the traps that scatter the carriers are located right at the interface

[51]. In our work, we have developed a theoretical model that focus on the trap that

located in the oxide that within the tunneling distance from the interface. We have

also included the effects of the charge centroid and the screening effects to explain

the observed gate bias dependency of the remote Coulomb scattering [18].

When the oxide trapped charges located in the dielectric layer, especially in the

high-K layer, can interact with the electrons in the inversion layer by means of tun-

neling and trapping/detrapping processes. At the same time, these trapped charges

affect the carrier mobilty by remote Coulomb scattering. Therefore, when the oc-

cupied trap density fluctuates in the dielectric layer, the remote Coulomb scattering

component fluctuates, which leads the fluctuation in the carrier mobility. An analysis

of remote Coulomb scattering, assuming a spatial distribution of scattering centers

Nf (z) in the overlying dielectric, yields the following expression for a single dielectric

system [52, 53] with the inversion electron lying in the first excited state, E00 (see

Appendix A the detailed derivation in ).

R z0 √
π/2
4α0 dzNf (z)e−4kth z ukin sin ϕ
Z
0
αNT = 2 dϕ (2.38)
π √
6 
0 ukin 1 + 2k3th z̄ ukin sin ϕ 1 + 4kth kB TqQ√n
ǭ ukin sin ϕ

42
where
√
2mt kB T
kth = ;
~
Ekin
ukin = ;
kB T
3
z̄ = ;
b  
EF n −E00
Ekin = kB T ln 1 + e kB T ; (2.39)
  1/3
12qml 11
b= QB + Qn ;
~2 ǫs 32
q 3 mt
α0 = ;
32~ǭ2 kB T
EG
EF n = q(φs − φF ) − .
2

To accommodate the formula in Equation (2.2),

αNT
R z0 √
π/2
4α0 NT dzNf (z)e−4kth z ukin sin ϕ
Z
0
= 2 dϕ (2.40)
πz0 2kth z̄ √

6  qQn
0 ukin 1+ 3 ukin sin ϕ 1 + 4kth kB T ǭ√ukin sin ϕ
, α0 f (z0 , QB , Qn )NT

where
f (z0 , QB , Qn )
√
1 − e−4kth z ukin sin ϕ
Z π/2

1
= dϕ. (2.41)
πz0 kth 0 3/2 √ 6

qQ
2
1 + 2k3th z̄ ukin sin ϕ


ukin 1 + 4kth kB T ǭ√nukin sin ϕ sin ϕ

In Equation (2.41), the second term in the denominator describes the finite extension

of the inversion charge into the semiconductor [52, 53] as portrayed by the charge

centroid, while the third term in the denominator describes the effect of screening

[53] with the inversion charge density Qn . In this analysis, we assumed a constant

sheet density with an effective volume density of Coulomb traps in the insulator,

43
Figure 2.7: A model of the rough silicon surface. ∆ is a measure of the interfacial
displacement and Lc represents the spatial variation in the direction of the channel
[54].

Nf (z) = NT /z0 . In scaled devices with a dual dielectric gate, Equation (2.41) becomes

f (z0 , zf , QB , Qn )
√ √
dϕe−4kth z0 ukin sin ϕ 1 − e−4kth zf ukin sin ϕ
Z π/2

1 (2.42)
= .
πzf kth 0 3/2 √
6  2
ukin 1 + 2k3th z̄ ukin sin ϕ 1 + 4kth kB TqQ√n
ǭ ukin sin ϕ
sin ϕ

where we assumed the Coulomb scattering centers lie in the dielectric of thickness,

zf , overlying the oxide of thickness, z0 , rather than in the oxide itself. In this system,

the EOT is given as

ǫox
zeq = EOT = z0 + zf . (2.43)
ǫf

2.1.4 Surface Roughness (β)

As depicted in Figure 2.7, the interface between the Si substrate and the oxide

layer is not a perfect plane. The interface disorder will impose short-range scattering

on the carriers, which limits the mobility of 2DEG near the Si/SiO2 interface. And

this scattering process has a strong dependency on the electric field at the surface. As

mentioned previously, as the inversion carrier density fluctuates, due to the trapping

effects, the vertical electric field also fluctuates, which in turn perturbs the surface

44
roughness mobility of the carriers. Such mechanism leads to another correlation be-

tween the fluctuation of the occupied traps and the observed 1/f noise in the channel.

The analysis of surface roughness begins with the statistics, which governs the surface

roughness of the Si-SiO2 interface. In a theoretical treatment of interface or surface

roughness, we can assume an autocovariance function in 2D real space of the form

[45]
r n
C(q) = ∆2 e−( Lc ) (2.44)

where ∆ is a measure of the interfacial displacement and Lc represents the spatial

variation in the direction of the channel. If n = 2 we have a Gaussian autoco-

variance function and the case of n = 1 yields an exponential autocovariance func-

tion. The roughness power spectrum is obtained from the 2D Fourier transform of

Equation (2.44)
Z ∞
2 n
S(q) = 2π(∆Lc ) xe−x J0 (qLc x) dx
0
2
− (qL4c )
= π(∆Lc )2 e Gaussian(n = 2) (2.45)
π(∆Lc )2
=h  2 2 i3/2 Exponential(n = 1) (2.46)
1 + q 2Lc

where q = 2k sin θ2 is the magnitude of the scattering vector between initial and final

states. We formulate the relaxation time associated with surface roughness scattering

for both cases as [54]

1 9(∆Lc )2 mt q 2 ESH
2
FG,E (k)
= 3
for Stern-Howard (2.47)
τG,E (k) 2~

where the Stern-Howard electric field FSH is given by

11
QB + 32 Qn
ESH = (2.48)
ǫs

45
with associated energy level E00 given by Stern and Howard [50]. The subscript stand

for Gaussian (G) and Exponential (E) distributions with the functions
Z π k2 L2
c (1−cos θ)
FG (k) = (1 − cos θ)e− 2 dθ (2.49)
0
π
1 − cos θ
Z
FE (k) = dθ (2.50)
0 [1 + k 2 L2c (1 − cos θ)]3/2

In the simulation performed in this work, exponential distribution is chosen because it

is shown to be a better fit to experimental findings as reported by Goodnick et al. [55]

in 1985 and most recently by Chen et al. [56] for ultra-thin gate oxide. If we con-

sider the lowest lying energy level, E00 , and the Stern-Howard variational approach,

with effects of charge centroid, follow the similar variable manipulation included in

Appendix A (step Equation (A.19)), then we can write the following expression for

the surface roughness mobility

1/2
1 9∆2 qmt ESH2
= 1/2 f (ukin, QB , Qn ) (2.51)
µsr 2 Lc (kB T )3/2

where
f (ukin , QB , Qn )
Z π/2
sin2 ϕ (2.52)
=
6 dϕ
2kth z̄ √
h i3/2
3/2
0
ukin k2 1
2 + 2 sin2 ϕ 1+ 3
ukin sin ϕ
th ukin Lc

and with reference to Equation (2.2), using the definitions in Equation (2.39), we find
1/2
qθS 9∆2 q 2 mt ESH 2
β= = f (ukin , QB , Qn ) (2.53)
µ0 Cef f Lc (2kB T )3/2 ǫs Eef f

where we have Cef f = ǫox /EOT and the ratio of the Stern-Howard to the Effective

electric fields. At high inversion charge densities this ratio, ESH /Eef f approaches to

11/16. Equation (2.53) relates the value of β to SPICE’s surface roughness parameter,

θS , assuming negligible series resistances in the device.

46
Figure 2.8: Cross-section of the scaled NMOS transistors with 0.5 nm SiO2 /1.6 nm
HfO2 gate dielectric and 10 nm TiN gate electrodes (non-self-aligned, W = 100 um,
L = 10 um).

2.2 Experiments

2.2.1 Experimental Setup and simulation

The noise is measured on NMOS devices (packaged and probed) with a system

comprised of a low-noise preamplifier and a SR760 FFT Spectrum Analyzer enclosed

in a Faraday cage. Figure 2.8 shows the cross-section of the measured scaled NMOS

devices with a composite dielectric consisting of a 0.5 nm SiO2 covered with a high-K,

1.6 nm HfO2 with a TiN metal gate. Electrical measurements of modeling parameters

from DC device modeling permits the extraction of α and β to correlated with noise

measurements.

47
Figure 2.9: Comparison of the simulated and experimental IDS versus VGs curve.
The solid line represents simulation results, while the diamond symbols represent
experimental results.

The simulation process starts with sub-band construction: first, we employ simple

triangular potential well approximately to obtain a set of trial levels (E00 , E01 and

E10 ), as this approximation [49] converges more easily; second, we modify the trial en-

ergy levels according to the variational method [49] and arrive at self-consistency. The

scattering parameters are calculated using the expressions mentioned in Section 2.1.3

and Section 2.1.4, assuming that all the carriers lie in the lowest sub-band E00 for

simplification. The unknown parameters (∆ and Lc ) are obtained by comparing the

simulated DC characteristics (ID -VGS curve) with measurement results (as shown in

Figure 2.9, ID = VDS / [RS + Rch ] where RS is the series resistance, Rch is the channel
1
resistance which can be approximated by W µqNn /L
).

48
Figure 2.10: Modeled variation of α and β versus carrier density. The solid line
represents α, while the dashed line represents β. The star symbols represent the
sum of α and β. The diamond symbols represent the extracted scattering parameter
reported by [18], while the plus symbols represent the extracted scattering parameter
reported by [17] for comparison with (α + β).

Figure 2.10 depicts the scattering parameters (α and β) as functions of the inver-

sion carrier density Nn . As VGS and Nn increases, both remote Coulomb scattering

(α) and surface roughness scattering (β) parameters decrease (i.e., more scattering

and degraded mobility, as carriers move to the surface). At low Nn , β is smaller

than α. However, β decreases much slower than α, and eventually exceeds α at high

Nn where surface roughness scattering is more significant. The values of α and β

confirm the necessity to take into account the fluctuations in mobility induced by the

variations in the normal electric field.

49
 In the study reported in this dissertation, we have not obtained extracted value

from independent experiments concerning the scattering parameters. However, we

have compared our simulated results with experimental or extracted values reported

by other researchers. The diamond symbols in Figure 2.10 represent the “α” values

reported in [18] obtained from Random Telegraph Signal (RTS) noise measurement.

Note, this “alpha” value is equivalent to the sum of α and β in our model. Since

the gate oxide was much thicker back then and the carrier density is much lower

than our device today, the reported value is expected to be higher than that in our

device, which is the case shown in Figure 2.10. Morshed et al. [17] have extracted
 −1
1/2
the “screened scattering coefficient”, expressed as µcoNn with µco as fitting

parameters, from 1/f noise measurement on poly-HfSiON-SiON-Si MOSFETs with

thin gate dielectrics. Note again that this so-called “screened scattering coefficient”

is equivalent to the sum of α and β in our model. If we use the same expression

and calculate this sum, then good agreement at higher Nn can be achieved with µco

of about 0.4 × 1010 cmV−1 s−1 (plus symbols in Figure 2.10). The difference in the

extracted µco (1.75 ∼ 5.0 × 1010 cmV−1 s−1 as reported in [17]) and discrepancies

at lower Nn can be attributed to the differences in device structures as well as the

assumption we made: all the electrons are located in E00 , which slightly overestimates

the scattering parameters at lower Nn due to the carriers located at E10 and E01 .

The drain noise PSD (SId ) is calculated using Equation (2.11). The bulk trap

density depends on the Fermi energy level according to an exponential bandtail model

as [57]
EC − Ef n
ρt (Ef n ) = ρt0 + ρtc exp(− ). (2.54)
ζ

50
Figure 2.11: Drain current noise PSD versus gate voltage for high-K, NMOS device
at VDS = 50 mV (W = 100 um, L = 10 um), f = 4 Hz. The analytical expression for
SId is given for low VDS as well as the expression for mobility, which involves remote
Coulomb scattering (α) and surface roughness β.

In our simulation, we use 0.18m0 [58] as the effective tunneling mass to calculate the

attenuation coefficient λ, where m0 is the electron mass. With ρt0 , ρtc and ζ equal

to 1019 cm−3 eV−1 , 3 × 1018 cm−3 eV−1 and 0.108 eV respectively, the simulated noise

PSD in plotted in Figure 2.11 compared to the experimental value.

In our calculation, the experiment starts from VGS = 1.0 V, which ensures the

surface is inverted. Meanwhile the applied gate voltage is kept below 1.8 V, so that

the electric field in the ultra-thin dielectric will not be so large as to be near the break-

down region. The model shows good agreement with the experiments over higher VGS

range and slightly overestimates the result at low VGS . This is due to the assumption

to locate all the carriers in E00 when modeling the scattering parameters, similar

51
to the description in the previous paragraph: at higher VGS and Nn , more electrons

are located in the lowest sub-band, which indicates that our model processes more

accurate as the quasi Fermi level is moving up.

2.2.2 Discussions

Note, if we assume the inversion charge lies at the Si-SiO2 interface (z̄ = 0),

neglect screening (Qn = 0), scattering at the interface (Nf (z) = NT δ(0)), and assume

ukin = 2, then we will arrive at

e3 mt
α = α0 = (2.55)
32~ǭ2 kB T

where mt is the effective mass of carriers in a [100] direction and ǭ = (ǫs + ǫox )/2

is the average of the semiconductor and oxide dielectric constants. This expression

has been used previously for the value of α, which has yielded a value 20 times

larger than obtained from experiments [51]. Equation (2.55), besides assuming the

Coulomb scattering centers lie at the interface, neglects the finite distribution of the

carriers into the semiconductor and scattering centers into the overlying gate dielectric

combined with the screening of these scattering centers by the increasing carrier

density in the inversion layer. In addition to these effects, there is a contradiction

in the previous analyses because the complete localization of scattering centers at

the Si-SiO2 interface cannot produce a 1/f noise spectrum, since traps must have a

spatial distribution in time constants as described in [3]. the models expressed in

Equation (2.41) and Equation (2.42), which include the effects of charge centroid and

finite extension provide a theoretical basis for the scattering parameters. As shown in

Figure 2.12, the complete alpha value is compared with the calculated value without

the effects of charge centroid of screening, versus the carrier density in the channel

52
Figure 2.12: Comparison of calculated α values with different consideration. The solid
line represents the complete α with consideration as stated in Section 2.1.3. The dot
symbols represent calculated α without the effects of charge centroid. The trian-
gular symbols represent calculated α without screening. The dashed line represents
α0 , the constant remote Coulomb scattering parameter without the charge centroid,
screening and assuming all the traps located at the Si/SiO2 interface as discussed in
Section 2.2.2.

region. In Figure 2.12, the constant α0 is also plotted as a reference. It can be

seen that the above-mentioned effects are not negligible in modeling, especially for

nanoscaled devices with ultra-thin gate dielectrics.

Although the fluctuations in the carrier density and the carrier mobility are cor-

related, we can still generate some ideas as to the dominating noise mechanism by

comparing the term 1/Nn and the term (α + β) · µ, as indicated Equation (2.11).

Figure 2.13 illustrates such comparison: at high VGS , the contribution of mobility

53
Figure 2.13: Comparison of number fluctuation and mobility fluctuation. The solid
line represents 1/Nn - a quantity related to number fluctuation, while the dashed line
represents “(α + β)µ” - a quantity related to the mobility fluctuation.

fluctuation is about 1/6 smaller than that of number fluctuation; however, the dif-

ference is significant smaller at lower VGS . thus for the studied high-K MOSFET

device, number fluctuation is more important than the mobility fluctuation, espe-

cially at higher gate bias. And yet the latter is indispensable in noise modeling and

understanding, especially at lower gate bias region for devices with ultra-thin gate

dielectric.

Although this chapter presents the simulation based only on NMOS transistors,

this modified unified 1/f noise model can easily be extended to PMOS transistors

as well. The trapping/detrapping and correlated scattering processes in PMOS are

similar to those in NMOS. There two things that need modification for PMOS: 1)

54
band structure; 2) parameters for holes. The 2D hole gas behavior is more complicated

than for electrons. However, if one can find a reasonable approximation of the energy

levels for the holes in the inversion layer in PMOS transistors, plus the careful choice

of parameters for holes, such as effective mass, density of state etc., the rest of the

noise simulation employed in this work can be easily adopted for PMOS.

The model presented in this work can also be applied to materials besides Si. For

each material and device system, with the careful construction of energy band and

subband structures and appropriate choice for physical parameters of the correspond-

ing materials, one can easily employ this modified unified 1/f noise model to model

and predict the 1/f noise behavior of the device under test (DUT).

55
 Chapter 3: Characterization of Nanoscaled SiON MOSFET
Devices

Device characterization includes measuring certain characteristics, predicting as-

sumed behavior, proposing the appropriate setup and conditions, extracting certain

parameters etc. The results from the device characterization can help us understand

the device performance and provide the device parameters that can be used to op-

timize the fabrication process and develop device models. This chapter covers some

of the most important characterization techniques for MOSFET devices: the basic

principles, implemented setups used for this dissertation, data processing procedures

as well as the example measurement from devices of interests. We have implemented

both basic and advanced characterization techniques, such as C-V (Capacitance Volt-

age), I-V (Current Voltage), CP (Charge Pumping) etc, to extract device parameters

including effective oxide thickness (EOT), threshold voltage, carrier mobility, effective

substrate doping, interface trap density etc. Some operation details can be found in

Appendix B for clarification.

In this chapter, the presented characterization techniques and results are mainly

based on high quality CMOS transistors with nanoscaled SiON dielectric layer and

polysilicon gate. The physical EOT for the dielectric layer is 18 Å, with the electrical

EOT at inversion being about 24 Å. Gate oxidation/post-nitridation process has

56
been optimized for both gate leakage and reliability. Different test structures are

fabricated specifically for certain types of characterization. For the measurement

results presented in this chapter, the I-V related characterization is performed on

standard transistor structures where the width is 10 um, and the length is 1um;

whereas the C-V related and charge pumping characterization is performed on gated

capacitors where 50 small 5 um × 5 um are wired together to form a large capacitor,

and between these small capacitor squares lie the pseudo “source and drain” regions

which provide minority carriers and promote inversion.

3.1 Overall Setup and LabVIEW Programming

Generally, the characterization setup is composed of a probe system, peripheral

equipment, software or programs that controls the equipment and processes the data,

as well as a shielding environment.

LabVIEW— programs are created to control the equipment and process measured

data. LabVIEW is a graphical system design software that provides tools, in order

to create and deploy measurement, control systems and integrate hardware [59]. It

can greatly enhance the measurement productivity and capability, as well as reduc-

ing errors that might have been caused by manual operations. Some characterization

techniques, especially those involving multiple pieces of equipment or complicated

equipment control, is almost impossible to be accomplished without certain com-

puter controlling. LabVIEW provides a straight-forward platform to implement the

required controlling. The availability of equipment drivers, manufacturers’ support

and the user-friendly interface make it a powerful tool for constructing experimental

setups.

57
3.1.1 State Programming in LabVIEW

Most of the programs used for this dissertation are based on the ‘state machine’

technique, which is a powerful programming scheme in LabVIEW. For our lab, the

major role played by LabVIEW is to control certain equipment or several equipments

at the same time collaboratively, to perform complex measurements, some of which

are quite difficult or even impossible if done manually. For each measurement, there

is a series of “actions” to be performed, in some cases there is a strict order for these

‘actions’, whereas, in other cases there is no strict sequence for the required ‘action’

and one might need to hop between different phases repetitively, e.g., stress tests.

Previously, most of the programs in our lab are written by sequential programming:

everything is executed one by one for only once according to a definitive order. That

is fine for simple application, however, it is not very efficient for program reuse and it

is difficult to conduct test schemes where the executing sequence is not definite and

therefore lacks flexibility. “State” programming provides flexibility, repeatability of

code and much more.

In the “state” programming, each state represents a particular segment of the

measurement process. As indicated in Figure 3.1, the program is mainly composed of

a ‘while loop’, a case structure, a state shift register, and state functionality code and

transition code inside the case structure. The program will start from an “initial”

state. At every run of the ‘while loop’, the program will first check the concurrent

state and decide which segment to perform. All desired actions are included in the

case structure. After completing the “state functionality code”, the “transition code”

will be executed to determine the next state. This new state is passed to the next

loop by the shift register. Different values can be passed through the program by

58
Figure 3.1: Basic structure of the ‘state machines’ in a LabVIEW— environment [60].

shift registers and local or global variables. This process will run till the “STOP”

Boolean status is “true”.

By implementing the state programming scheme, we have recreated the testing

environment for electrical characterization in our lab. The new LabVIEW programs

are more efficient, flexible and user-friendly than the previous versions. The details

of the usage of our LabVIEW programs can be found in Appendix B.

3.2 Capacitance-Voltage (CV) Characteristics

The Capacitance-Voltage (C-V) measurement is a fundamental characterization

technique for MOS capacitors and transistors. Accurate determination of device ca-

pacitance is critical for the determination of oxide thickness, inversion carrier density,

mobility and interface trap density.

59
 Figure 3.2: Schematic for gate-to-channel capacitance measurement [61].

3.2.1 Gate-to-Channel and Gate-to-Bulk Capacitance

For MOS transistors, since source and drain regions already exit and they can

provide inversion carriers directly, a significant inversion can be observed when the

gate-to-source bias exceeds the threshold voltage. Capacitance measurement on MOS

structures can be performed with several options of connections, according to different

objectives: between gate and the channel, gate and the bulk, or gate and bulk plus

channel together.

Taking the gate-to-channel capacitance as an example, the schematic is shown in

Figure 3.2, where the capacitance is measured between the gate and the source/drain

electrodes with the bulk terminal tied to ground. For a NMOS transistor, at negative

gate voltages, the channel region is accumulated and the overlap capacitance 2Cov

are measured. When the gate voltage surpasses the threshold voltage and the surface

is inverted, the sum Cch + 2Cov is measured.

Similarly, for gate-to-bulk capacitance Cgb , the capacitance is measured between

the gate and the substrate electrode, with the drain/source electrodes tied to ground.

60
At negative gate voltages, for a NMOS transistor, the oxide capacitance Cox is mea-

sured; at inversion region, the depletion capacitance is in series with the oxide capac-

itance and the total capacitance is measured.

Figure 3.3 includes the above-described “split” measured Cgc and Cgb versus Vgs

for both NMOS and PMOS transistors.

3.2.2 CV Measurement for MOS Devices with Leakage

At the ITRS 45 nm technology node and beyond, the gate leakage problem and se-

ries resistance needs to be considered in order to determine the true value of the capac-

itance. A dual frequency C-V measurement has been proposed by Yang and Hu [62],

which allows the frequency-independent device capacitance to be accurately extracted

from an impedance measurement at two different frequencies.

The three-element circuit model of a MOS capacitor with leaky gate oxide is shown

in Figure 3.4(a) C represents the actual frequency-independent device capacitance,

RP represents the effective device resistance due to leakage through the thin oxide,

and RS represents the serious resistance of the substrate and the gate. The measured

capacitance using the parallel circuit model is dependent on frequency for a MOS

capacitor, and the equivalent measurement circuit is shown in Figure 3.4(b). Cm is

the measured capacitance, and Rm is the measured resistance. For the LCR meter,

the selected circuit mode is “parallel” for this kind of “leaky” capacitors, although

one can always convert between “parallel” and “series” circuit modes by calculation.

The impedance of the three-element circuit model at frequency ω is given by

RP (1 − jωCRP )
Z = RS + . (3.1)
1 + ω 2C 2 RP2

61
 (a) NMOS

(b) PMOS

Figure 3.3: Capacitance-Voltage characteristics for both N and P transistors. Mea-

surement is performed at 1 MHz to minimized the influence of interface trap capaci-
tance.

62
 (a) Device model (b) Measurement model

Figure 3.4: Small signal equivalent circuit of MOS capacitors.

The impedance of the parallel circuit model at frequency ω is given by

Dm − j
Zm = 2 )
(3.2)
ωCm(1 + Dm
1
where Dm = ωRm Cm
is the dissipation factor. Equating the imaginary parts of the

measured impedance in Equation (3.2) and the true impedance in Equation (3.1), we

obtain
1 + ω 2C 2 RP2
2
= ω 2 Cm (1 + Dm
2
). (3.3)
CRP
Measuring the capacitance and dissipation at two different frequencies, substituting

into the above expression for each frequency, subtracting, and solving for C, we obtain

f12 Cm1 (1 + Dm1

2
) − f22 Cm2 (1 + Dm2
2
)
C= 2 2
(3.4)
f1 − f2

where Cm1 , Dm1 are the values measured at the frequency f1 and Cm2 , Dm2 are the

values measured at the frequency f2 .

The gate-to-drain Capacitance-Voltage (C-V) measurements are taken at 1 MHz

and 800 KHz for the sample described previously and the result for both NMOS

63
and PMOS are shown in Figure 3.5. Since there isn’t much difference between the

capacitance measured at these two frequencies for either type, the measured data

at 1 MHz only is sufficient for further analysis, for these low gate leakage and low

series resistance devices. The extracted capacitance values at |Vgs |= 1.5 V (strong

inversion) are 1.44E-6 F/cm2 and 1.32E-6 F/cm2 for NMOS and PMOS transistors,

respectively. The corresponding effective oxide thickness can be calculated by

ǫox
EOT = (3.5)
Cef f

which yields value of 2.4 nm and 2.6 nm for N and P MOSFET. The designed physical

oxide layer thickness is around 1.8 nm. The addition to the effective thickness is

attributed to the polysilicon gate depletion due to a finite doping concentration in

the polysilicon gate, as well as the distance of the charge centroid of the free carriers

in the channel region when the surface is under strong inversion.

3.3 Current-Voltage (IV) Characteristics

3.3.1 IV Characteristics and Threshold Voltage Extraction

The threshold voltage Vth is one of the most important device parameters of MOS-

FET. There are several ways to define and extract this parameter. In an industrial

development environment, where a large number of samples are evaluated in a “point-

data” sense, Vth is usually defined as the gate bias that will drive a certain amount

of current through the drain, and this value depends on the operation region (i.e.,

linear or saturation). On the other hand, for research purposes, bench-testing (curve)

data are utilized more often. One way to define and extract this value is the so-called

“linear extrapolation method”. Figure 3.6 shows the transfer characteristics of the

measured SiON CMOS devices at different substrate biases.

64
 (a) NMOS

(b) PMOS

Figure 3.5: Dual frequency C-V characteristics of both NMOS and PMOS advanced
SiON devices. Measurement are taken at 1 MHz and 800 KHz.

65
 (a) NMOS

(b) PMOS

Figure 3.6: Drain current (ID ) and transconductance gm as a function of gate to

source voltage VGS at different substrate biases VSB . A linear extrapolation at the
point of tangency gives the device threshold voltage. The measurements are taken
with a small drain bias, typically VDS = 50 mV for NMOS and -50 mV for PMOS)
.

66
 Figure 3.7: Linear extrapolation for threshold voltage of a NMOS transistor.

According to the linear extrapolation method, we first find the gate bias where

the transconductance gm reaches the maximum. At the same bias level on the current

curve (IDS −VGS ), we draw a tangent line and look for the intercept with the VGS axis.

This intercept value gives the threshold voltage of this device at the corresponding

substrate bias level. As shown in Figure 3.7, with an increase of the substrate to

source bias difference (VSB1 < VSB2 < VSB3 ), the threshold voltage shifts in a more

positive direction (VT H1 < VT H2 < VT H3 . This can be explained by the general model

of the MOS threshold voltage in Equation (3.7), and we can use this feature to extract

the effective substrate doping density of the device. At strong inversion, Vth for an

67
NMOS transistor can be expressed

p
VT H = VF B + 2φF + λn 2φF + VSB (3.6)
p p
= VT H0 + λn ( VSB + 2φF − 2φF ) (3.7)

where
p
VT H0 = VF B + 2φF + λn 2φF (3.8)

is the threshold voltage at zero substrate bias;

√
2ǫS qNA
λn = (3.9)
Cef f

is the body effect parameter. The Fermi potential φF is given as

 
kB T NA
φF = ln (3.10)
q ni

which is the potential difference between the Fermi level and the intrinsic energy level

in the semiconductor bulk. VF B is the flatband voltage, VSB is the source to substrate

bias, ǫS is the semiconductor permittivity, q is the electron charge, NA is the effective

substrate doping density, Cef f is the effective oxide capacitance, kB is Boltzmann’s

constant, T is the absolute temperature and ni is the intrinsic carrier concentration.

From Equation (3.9), the substrate doping concentration can be obtained from

the body effect parameter λn . Based on Equation (3.7), if we plot VT H ’s versus

√ √
VSB + 2φF − 2φF , then λn is the slope of this line. As depicted in Figure 3.8, the

extraction process starts with assuming a value for NA . Next, we can use this assumed
√ √
value to generate the line VT H versus VSB + 2φF − 2φF (as seen in Figure 3.9),

and compare the new NA extracted from the slope of this line with the assumed value.

One can employ certain numerical methods to accelerate the solving process. In this

work, the bi-sectional method is employed. Repeat this process until self-consistency.

68
 Start

Input NA
√ √
Plot VT H versus VSB + 2φF − 2φF

Calculate NA′ from the slope λn Bi-section for another NA

No
NA′ = NA

Yes
Save Results

End

Figure 3.8: Flowchart for extracting the effective substrate doping concentration NA .

The intercept of the curve gives the value of VT H0 , which is the threshold voltage at

zero VSB . The plots after achieving consistency for the measured samples are shown

in Figure 3.9, with the results listed in Figure 3.3.1 for both N and P type MOSFETs.

Parameter NMOS PMOS

VT H0 (V) 0.44 -0.46
NA (1/cm3 ) 3.8E17 2.0E17
VF B √
(V) -0.70 0.60
λn ( V ) 0.247 0.196
φF (V) 0.45 0.44

Table 3.1: Extracted parameters from I-V characteristics and VT H analysis.

69
 √ √
Figure 3.9: Plot of VT H versus VSB + 2φF − 2φF .

70
3.3.2 I-V Characteristics and Mobility
Effective Conductance Mobility

With the IDS -VGS characteristics one can study the effective conductance mobility

µcon of MOSFETs by
gd L
µcon = (3.11)
W Qn

where L and W are the length and the width of the device. Qn is the inversion carrier

density, and gd is the drain conductance and defined by


∂IDS 
gd = (3.12)
∂VDS VGS
IDS
≈ at small VDS (3.13)
VDS

The inversion carrier density Qn can be determined from the previously mentioned

Cgc verus Vgs curve (Section 3.2.1). If we subtract the overlap capacitance measured

at negative bias from the measured overall capacitance, we can obtain the real gate-

to-channel capacitance. As a further step, the inversion carrier density can also be

obtained by integrating the Cgc versus Vgs curve as

Z VGS
Qn = (Cgc − 2Cov ) dVGS . (3.14)
−∞

With the quantity Qn , we can determine the conductance mobility, according to

Equation (3.11). This obtained conductance mobility depends on the vertical effective

field, which is due to the space-charge region and the inversion layer charges as

QB + ηQn
Eef f = (3.15)
ǫs

where η in the inversion layer charge accounts for averaging of the electric field over the

electron distribution in the inversion layer, usually taken as η = 1/2 for the electron

71
mobility [63] and 1/3 for the hole mobility [64]. Note, p-channel devices are fabricated

in an n-well and the substrate doping is not uniform and can influence the effective

field by altering the QB term. If this it not taken into account, then researchers fit

their experiment with a 1/3 factor in front of the Qn term. Krutsick and White [65]

have made an argument to keep the 1/2 in front of the inversion charge Qn and to

use another factor in front of the QB for holes.

Employing such methodology and the inversion carrier density obtained previously

from Cgc −Vgs measurement, the conductance mobility µcon versus the effective electric

field Eef f for the measured SiON samples are shown in Figure 3.10. At low effective

field, the mobility decreases, which is believed to be due to Coulomb (or impurity)

scattering, which becomes more important when the doping concentration is high and

the gate voltage or the normal field is low [41]. At high normal field, the mobility

decreases as the field increases, which is because of the increased surface roughness

scattering [41].

Series Resistance and Surface Roughness

In devices with ultra-thin dielectric layer, the surface roughness and series re-

sistance impose non-negligible effects on the carrier transport and the device drive

current. In order to extract such information, we start with the equation for modeling

a MOSFET at low drain bias including series resistance (RSD ) and surface roughness

72
Figure 3.10: Plot of the measured conductance mobility µcon versus effective electric
field Eef f . The shown data is obtained from measurement under the gate biases from
0.5 V to 1.2 V for NMOS, -0.5 V to -1.2 V for PMOS.

73
parameter (θS ) [66]

A∗
ID = (3.16)
1 + B∗ − C ∗
where (3.17)
 
∗ 1+δ
A = βef f (VGS − VT H ) − VD ) VD (3.18)
2
p 1−δ
B ∗ = (θS∗ + 2βef f RSD )(VGS − VT H + 2λn 2φF + VSB − VD ) (3.19)
2
p
C ∗ = βef f RSD (4λn 2φF + VSB + 3VD δ) (3.20)

and (3.21)
W
βef f = µef f Cef f (3.22)
L
θS
θS∗ = (3.23)
1 + α · NT (ef f )
λn
δ = √ (3.24)
2 2φF + VSB
√
2ǫS qNA
λn = (3.25)
Cef f
p
VT H = VF B + 2φF + λn 2φF + VSB (3.26)
 
kB T NA
φF = ln (3.27)
q ni

where µef f is the effective mobility excluding the surface roughness scattering, α is the

effective remote Coulomb scattering parameter, NT (ef f ) is an effective trap density

located at the Si-SiO2 interface.

If we rearrange the expression in Equation (3.27) for ID , we have

 
1+δ VD
(VGS − VT H ) − VD )
2 ID
1
=
βef f (3.28)
θ∗ + 2βef f RSD p 1−δ
+ S (VGS − VT H + 2λn 2φF + VSB − VD )
βef f 2
p
− RSD (4λn 2φF + VSB + 3VD δ).

74
Figure 3.11: Plots to show the extraction of the carrier mobility, surface roughness
and series resistance from transfer characteristics. The lines are obtained from NMOS
only to show the employed technique. The analyzing procedure is similar for PMOS
devices.

Based on the work described in Section 3.3.1, with the extracted Vth ’s we can plot

the variable
 
1+δ
a = (VGS − VT H ) − VD ) · VD /ID (3.29)
2
versus
p
VGS − VT H + 2λn 2φF + VSB − VD (1 − δ)/2 (3.30)

(as shown in Figure 3.11 for measured NMOS sample). The intercept of each line

gives
1 p
b= − RSD (4λn 2φF + VSB + 3VD δ) (3.31)
βef f

75
 1
√ √
Figure 3.12: Plots of βef f
−RSD (4λn 2φF + VSB +3VD δ) vs. 4λn 2φF + VSB +3VD δ.

for each VSB value and the corresponding slope gives

θS∗ + 2βef f RSD
slope = . (3.32)
βef f
Afterward, the plot of the previously obtained intercepts b versus the expression
√
4λn 2φF + VSB + 3VD δ is shown in Figure 3.12, and the slope of this very curve gives

the value of series resistance, and from the intercept of this line we can calculated

the effective mobility. Together with Equation (3.32), we can determine the effective

surface roughness parameter θS∗ . The obtained values are listed in Figure 3.3.2 for

both N and P devices.

The mobility obtained in this section is greater than that obtained in Section 3.3.2,

especially for NMOS electron. The main reason is that the model utilized in this

76
 Parameter NMOS PMOS
RSD (Ω) 63 71
µef f (cm2 /Vs) 345 114
θS∗ (V−1 ) 0.04 e 0.11 0.41 e 0.43

Table 3.2: Extracted parameters from I-V characteristics.

method takes account of the series resistance and surface roughness, where as in

the previous case in Section 3.3.2, there is no specific consideration of these two

mechanisms. Thus the mobility obtained previously is lower than that obtained here,

where the surface roughness scattering and the impact of series resistance is excluded

from the measured mobility.

3.4 Interface Trap Characterization with Charge Pumping

Technique

Interface and near interface trap densities are important parameters in deter-

mining the overall performance of MOS devices for thin gate dielectrics. During

device operation, these trapping centers will capture electrons or holes, which shift

the threshold voltage of the device. As mentioned previously in Chapter 2, these

trapping centers also give rise to 1/f noise and degrade the carrier mobility. In our

work, we mainly employed charge pumping (CP) technique, which is a robust and fre-

quently used method, to directly measure the interface trap density. As the dielectric

layers are scaled thinner, it has become more difficult to differentiate the boundary

between the exact interface and near interface, because the entire dielectric layer is

no more than several nanometer thick. The interface trap density we measured from

77
 (a) Basic Setup (b) Pulse Shape

Figure 3.13: Basic experimental setup for charge pumping technique with charge
pumping current measured at the substrate.

these devices with ultra-thin dielectrics could be the sum of the interface trap and

near interface trap.

In the CP technique, one applies a certain shape of waveform to the gate and

measure the current through the substrate or source/drain. The basic experimental

setup is shown in Figure 3.13. In this setup, the source and drain of the transistor

are connected together and held at a zero bias voltage with respect to the substrate.

A small voltage can also be applied to slightly reverse bias the junction between the

substrate and source/drain to minimize the geometry component in the measured

charge pumping current, although this component is often negligible for device with

78
large width-to-length ratio or for gate pulse trains with moderate rise and fall times,

which give the channel electrons sufficient time to drift back to source and drain [61].

When the transistor is pulsed into inversion, the surface firstly becomes depleted

and electrons will flow from the source and drain regions into the channel inversion

layer, where some will be captured by interface traps. When the gate pulse is driving

the surface back into accumulation, the mobile charge drifts back to the source and

drain, but the charge trapped in the interface trap states will recombine with the

majority carriers from the substrate and give rise to a new flow of charge from the

substrate. The charge pumping current can be expressed as

ICP = f · AG · q 2 · Dit · ∆ψS (3.33)

where f is the frequency of the applied waveform, AG is the channel area, q is the

electron charge, Dit is the mean interface trap density per unit area per eV, averaged

over the energy levels swept through by the Fermi level, and ∆ψS is the total sweep

of the surface potential. ∆ψS is different for different shapes of waveforms, and it can

be calculated by capture and emission theories [67]. The detailed charge pumping

current is then given by [67]

   
 VT H − VF B  p
ICP = 2qDit f AG kB T ln υth ni 

 σn σp tr tf
 (3.34)
∆VG

for square pulses, and by

   
 VT H − VF B  1 q
ICP = 2qDit f AG kB T ln υth ni 

 f σn σp α(1 − α)
 (3.35)
∆VG

for triangular pulses, where υth is the thermal velocity of the carriers, σn and σp are

the capture cross section of electrons and holes respectively. ∆VG is the height of the

applied gate pulse, tf and tf is the rise and fall times of square pulses, α is the ratio

of the rising edge for triangular pulses (as defined in Figure 3.13).

79
 (a) Amplitude Voltage Sweep (b) Base Voltage Sweep

Figure 3.14: Base voltage sweep and amplitude voltage sweep methods for the charge
pumping technique.

Charge pumping measurements can be performed in different ways: base voltage

sweep and amplitude voltage sweep (as seen in Figure 3.14). In the base voltage

sweep, one varies the pulse base level while maintaining the amplitude of the pulse

constant to make the gate voltage go from accumulation to inversion. In the amplitude

voltage sweep, one maintains the pulse base level in accumulation and pulse the

surface into inversion with increasing the pulse amplitude. From the top of the base

voltage sweep curve or the flat region of the amplitude voltage sweep curve, one can

obtain the charge pumping current ICP .

80
 For the work presented in this thesis, the measurement setup is composed of a HP

4145A Semiconductor Parameter Analyzer and a Agilent 33120A Function Generator.

The function generator is used to apply pulses to the gate terminal. The semicon-

ductor parameter analyzer is used as source measurement units (SMU) to ground the

source, drain and the substrate. The parameter analyzer also measures the charge

pumping current, either from the substrate or the source and drain. The detailed

connection and operation are described in Section B.4.1. A LabVIEW program is

specially created to control the equipments and transfer the data. An important is-

sue in the setup is to construct a common ground between the function generator and

the analyzer, otherwise the setup will not work. For this purpose, one can connect the

chassis ground, or just the outer shield of the BNC connectors together, of HP 4145A

and Agilent 33120A. Averaging of the obtained value is also important to obtain a

smooth curve, thus for each base level, several samples are taken, out of which the

first one is eliminated and the rest of the measured sample are averaged to deliver

the resulted ICP .

Charge pumping techniques are successfully performed on the gated capacitors

structures of SiON devices, in which the source and drain terminals are wired together

on wafer, thus perfect for charge pumping measurements. For the results reported in

this dissertation, triangular wave is applied, to allow sufficient time for the carriers to

travel from the source and drain to the center of the channel, and thus minimize the

geometric component. The usage of triangular wave will also enable us to directly

extract the value Dit and σn σp .

As the first step, we have applied the amplitude sweep charge pumping to both

devices to find the optimal pulse amplitude that will provide the maximum charge

81
Figure 3.15: Measurement of amplitude voltage sweep of both NMOS and PMOS.
Based on the results, the selected amplitude levels are 1.3 V and 1.4 V for NMOS
and PMOS receptively.

pumping current and at the same time keep the gate current within a reasonable

range. As depicted in Figure 3.15, the measured charge pumping current increases

dramatically and begins to saturate at amplitude level of around 1.3 V and 1.4 V for

NMOS and PMOS devices respectively. Therefore, we selected these two amplitude

levels for further experiments.

For devices with thin dielectrics, there is a gate current component that adds to

the charge pumping current. One remedy for this issue is to measure the current

at sufficiently low frequencies, for which the measured current is dominated by the

gate leakage current. This portion can be subtracted from the total current measured

at high frequencies. This remedy provides a certain amount of correction to the

82
Figure 3.16: Measurement of base level sweep of NMOS before gate current correction.

charge pumping current, however, it is still desirable that the gate leakage should be

kept below a certain level to ensure valid charge pumping measurements. We have

performed base level sweeping charge pumping technique at different frequencies on

both N and P devices. Take the case of NMOS as an example, as shown in Figure 3.16,

the gate current raises the charge pumping current as the base level increases, thereby

raising the current floor.

We employed the current measured at 100 Hz and subtracted this current from

the total measured current to obtain the corrected base sweeping charge pumping

characteristics, as shown in Figure 3.17. The charge pumping current decreases for

lower pulse frequencies. The same procedure has been applied to PMOS device, and

the corrected base sweeping charge pumping characteristics are shown in Figure 3.18.

83
Figure 3.17: Measurement of base level sweep of NMOS after gate current correction.

Figure 3.18: Measurement of base level sweep of PMOS after gate current correction.

84
 With the measured charge pumping current Icp , plus the DC characterization

results VF B and VT H , we can extract the averaged interface trap density, with the

knowledge of parameters like σn , σp etc., according to Equation (3.35). As a more

direct approach, instead of assuming some values for these parameters, we can extract

them directly from experiments. By showing the recombined charge per cycle, which

is given by
ICP
QSS = (3.36)
f
as a function of the frequency on a semilogarithmic plot, one can obtain a straight

line when using triangular pulses [67]

 √

QSS =2qDit AG kB T ln υth ni σn σp
(3.37)
  
 VT H − VF B  1 p
+ ln  
 · f α(1 − α) .

∆VG
From the extrapolation of this curve to zero charge, the obtained frequency f0 gives a

value of the geometrical mean value of the capture cross section, as expressed below

as
 
√ 1  VT H − VF B 
 · p f0
σn σp = ·  . (3.38)
υth · ni ∆VG  α(1 − α)
The slope of this curve is given by

dQSS 2qkB T Dit

= · AG (3.39)
d log f log e

and this allows the determination of the mean value of the interface trap density

without the need for any other parameter than the temperature and the gate area.

Figure 3.19 includes the QSS versus frequency curves obtained from NMOS and

PMOS samples.

Following the analysis mentioned previously, the averaged interface trap density

and the mean capture cross-section can be obtained and he extracted parameters are

85
 √
Figure 3.19: QSS versus frequency used to determine σn σp and Dit .

compared in Figure 3.4. Siergiej et al. [68] have reported in the past that the electron

cross-section (σn ) is 100 times higher than the hole cross-section (σp ). If we use this

relation in our measurement, we find the values for σn and σp in our high-quality

SiON MOSFETs are approximately 5E-16 cm2 and 5E-18 cm2 respectively, which is

smaller than the values reported in Siergiej et al. [68] for Si-SiO2 interface.

Parameter NMOS PMOS

D (cm−2 · eV −1 ) 9.7E10 5.79E10
√it
σn σp (cm2 ) 3.3E-17 9.1E-17

Table 3.3: Extracted parameters from charge pumping measurement with triangular
pulses.

86
3.5 1/f Noise Characteristics

3.5.1 Measurement Setup

The noise measurement itself is quite a challenging task. The noise signal from

a transistor is usually small compared to the measured quantity in other character-

ization techniques, therefore amplification is needed to enhance the noise (wanted)

amplitude. At the same time, since there is a lot of interferences from the out-

side ambient, light and vibration will be picked up by the cables and probes during

measurement and make it very difficult to conduct noise measurements. The setup re-

quires excellent shielding capability, especially against the 60 Hz signal from the wall

socket power supply, which almost exists everywhere. The supply voltages which bias

the device under test (DUT) should be as clean as possible, i.e., containing almost

pure DC, to minimize the system noise from the setup itself.

The noise measurement system is comprised of biasing components, amplifiers,

proper filters and shielding facilities, as well as a spectrum analyzer. In our lab, there

are two types of setup, depending on the DUT. If the device can be wire-bonded and

packaged, which is the optimal case for eliminating the outside interferences, there is

a customized circuit board which provides the biasing, amplification and filtering at

the same time. Figure 3.20 shows the noise measurement setup for packaged device.

The DUT is wire bonded and packaged into a dual in line package. The package

containing the devices is mounted on a DIP socket soldered on the circuit board,

which is housed in the Faraday cage made with µ copper. A BNC cable connects the

circuit to the spectrum analyzer SR760 through a small exit hole in the cage. The

LabVIEW— program controls the analyzer and collects experimental data.

87
 Faraday Cage LabVIEW

System SR760
FFT Spectrum
Board Analyezr

Figure 3.20: Noise measurement system for packaged DUT.

The system circuit board is the central functional component of the measurement

setup - fulfilling the task of biasing the device, filtering the signal properly, as well

as providing sufficient gain to the signal prior to entering the spectrum analyzer.

Figure 3.21 depicts the final version of our modified measurement circuit [21]. Two

9 Volt batteries are used to bias the gate terminal and also supply the three op-

amps on the board. A 1.5 Volt battery, which is measured to be 1.59 Volt actually,

is used to bias the drain terminal. Using batteries for the biasing and to supply

the operational amplifiers eliminates the possibility of noise from a wall-powered

supply. Two precise potentiometers are used to adjust the biasing voltage applied to

the gate and drain terminals of the device. A LF412 is configured as a buffer and

connected between the gate controlling voltage and the gate terminal of the DUT.

Hence, the gate controlling voltage will not be affected by the conductance of the

DUT. There are two non-inverting amplifying stages, providing a voltage gain of 11

and 101, respectively. The first stage uses an ultra low-noise LT1793 operational

amplifier. In systems composed of multiple stages, noise added in the front end has

88
 Faraday Cage

1.6V

RD 0
0~100k
LT1793
+
V OP07
OUT +
9V LF412 10uF
- - OUT
SR760
D.U.T. FFT Spectrum Analyzer
OUT -
RG 100k
0 0~200k
+ NMOS 1k
9V V 10k
CL
0.047u
0
100 0 100

0
0

Figure 3.21: Schematic of the circuit for package-DUT noise measurement.

a larger impact than that in the subsequent stages, therefore, the noise in the first

gain stage should be kept as low as possible. A fairly small capacitor CL is added

across the feedback resistor to comprise a low-pass filter whose cut-off frequency is set

to be close to, but larger than, the upper bound of the spectrum analyzer frequency

span. This is important in order to reduce high-frequency noise, beyond the range of

interest, from coupling into the spectrum analyzer. The second gain stage employs an

ultra-low, offset voltage OP07 operational amplifier. A high-pass filter, in which the

cut-off frequency is designed to be approximately 0.16Hz, is inserted between the two

amplifying stages to block the DC voltage signal. In addition to the circuit design

and component selection, ten-turn wirewound potentiometers and metal film resistors

are used to further reduce any noise contributions from the circuit.

The total gain of the circuit, in terms of power, is calculated as

SV o
GAINpower = = (Rsd × 11 × 101)2 , (3.40)
SId

89
 Figure 3.22: Noise measurement system for on-wafer DUT.

where SV o is the measured output power spectral density, SId is the spectral density

of the drain current noise. Rsd is the channel resistance, which can be obtained by

VDS
Rsd = (3.41)
IDS

Although the packaged DUT setup excludes most of the external interference, it

lacks the flexibility when a lot of samples need to be measured on wafer. It also

lacks the automatic control of biasing levels since adjusting the voltage has to be

done manually through the potentiometers. For this purpose, an on-wafer setup is

developed to measure noise for devices on wafer. As shown in Figure 3.22, we use

two Stanford Research Systems SR570 low noise current preamplifier’s in the system:

one to provide the bias to the gate electrode, the other one to bias the drain terminal.

The Drain SR570 also filters the incoming drain signal with its internal filters, as the

same time converts the current into voltage signal and amplifies it.

90
 In our setup, the two SR570’s are housed inside a SemiProbe®shielding box,

together with the probing system. The SR570’s are battery-operated, and they are

controlled by the computer program via RS232 series port. The computer also controls

the spectrum analyzer via GPIB cable. During the measurement, once the DUT is

property probed and contacted, the shielding box is closed and all pieces of equipment

are controlled by the computer program.

We have performed the noise measurement on the SiON devices at a series of gate

bias. However, the measured noise level is only slightly larger than the background

noise level (due to intrinsic noise of SR570 etc.), thus the results are not included in

this chapter. This indicates the qualify of the SiON dielectric layer is very good in

which only a very limited amount of bulk oxide traps is presented.

91
 Chapter 4: Channel Carbon Implantation in Advanced
Replacement Gate Technology

Carbon has been utilized as a boron diffusion retarding material because it can

trap interstitial Si, which would otherwise enhance boron diffusion during high tem-

perature process steps [44, 69]. This feature has been utilized in CMOS application

usually in PFET source/drain extension and NFET halo regions, to promote ultra-

shallow junctions and improve performance and reduce short channel effects [69–71].

Researchers [72] have also attempted to implant carbon in the channel, in a gate-first

process, and employ the induced fixed charge to reduce the NFET threshold voltage.

In this work, we have introduced carbon with ion implantation (Cii) into the channel

area of 20 nm CMOS devices (high-K gate insulators and metal electrodes) fabri-

cated with a replacement gate technology, where the above-mentioned fixed charge

is removed. In this chapter, we have studies the effects of Cii on the quality of the

Si-SiO2 interface with charge pumping (CP) [67] and the influence of Cii on mobility

and threshold voltage (Vt).

92
4.1 Boron Transient Enhanced Diffusion and Carbon Co-
Implantation

Previously, it has been shown that carbon can attract these self-interstitial sites

and thus has the capability to retard boron diffusion in silicon. Ban et al. [44] pre-

sented a comprehensive study on this retarding effects and the importance of subse-

quent annealing. The long channel devices, used in this study, were fabricated with

gate oxide thickness of roughly 120 Å. Most of the interest and application of incor-

porating carbon into the substrate has been more aimed to stop the boron atoms

from diffusing into the source and drain region and therefore to achieve the so-called

“ultra-shallow” junction. The retarding effects have been confirmed, however carbon

introduction also tends to increase the off-state leakage in the MOSFET subthresh-

old region due to a reduction in generation lifetime [44]. Later, Gossmann et al. [70]

proposed fabrication techniques to incorporate the carbon for junction profile control

without increasing the junction leakage. Subsequently, attempts and improvement

have been made to fully utilize the carbon to prevent boron transient enhanced dif-

fusion (TED) [69, 71].

As MOSFETs are scaled further, the vertical dopant profile has become more

important. In low power technology, it is desired to have a low threshold voltage

and excellent Ion-Ioff performance at the same time, which requires strict control of

vertical doping concentration in the channel region - a quite challenging process due

to the boron TED. Very limited work report successful integration of carbon implants

in the channel area. Weber and Zawadzki [72] did attempt to implant carbon in the

channel where they aimed to employ the induced fixed charge to reduced the NFET

Vt. Very little work has been done to utilize the carbon implants in the channel to

93
prevent channel boron diffusion for better Vt control, especially in advanced high-

K metal gate CMOS technology below the 32 nm node with a ‘replacement gate’

technology.

4.2 Device Fabrication

CMOS devices have been fabricated with a replacement-gate sequence comprised

of a composite dielectric layer (EOT 1 nm). As shown in Figure 4.1, carbon is

implanted into the channel area after well formation, Vt-adjustment implants and

activation annealing, followed by a dummy interface layer (IL) thermal oxide growth.

Next, the devices undergo a dummy poly-Si gate deposition and spacer formation.

After source and drain definition, the dummy gate stacks are removed, followed by the

formation of a replacement composite gate dielectric. The gate consists of a chemical

deposited oxide IL and an ALD hafnium-based, high-K dielectric covered with a metal

gate. The control split skips the carbon implantation steps. After Vth-adjustment

implantation, the pad oxide for implantation is cleaned, and then the dummy IL oxide

layer is grown.

MOSFET devices of both short (L = 20 nm) and long (L = 0.5 nm) channel

lengths are fabricated. The short channel (SC) devices (of three voltage level: regular,

low, super-low) are utilized to extract DC benchmark point data, such as Ion, Ioff,

Vth etc. Long channel samples are used to measure electron and hole mobility.

Gated capacitors are also fabricated, where the source and drain terminals are wired

with the first metal layer on wafer, which can be used to perform charge pumping

measurements.

94
Figure 4.1: Process Flow of both the Cii and Control splits. The devices are fabricated
with advanced sub-45 nm CMOS technology.

4.3 Characterization and Results

Besides standard point data measurements, such as Ieff, Ioff, Vth etc., we have

also measured the trap density and the effective conductance mobility.

4.3.1 DC performance Ieff-Ioff

Figure 4.2 compares the Ieff-Ioff performance for short-channel (SC) devices (L=20

nm), where the drain current is defined by Ieff = (Ihigh+Ilow)/2. Ihigh is tested at

Vg = Vdd, Vd = Vdd/2, and Ilow is tested at Vg = Vdd/2, Vd = Vdd [73]. The

data include devices targeted for three Vt’s. As shown in Figure 4.2, for NMOS, the

Cii samples show significant improvement (20%) in the device Ieff over the control

samples at the same Ioff level.

95
Figure 4.2: Comparison of the NMOS Ieff-Ioff for standard short channel (L = 20
nm) devices. The Cii samples show significant improvement (20%) in the device Ieff
over the control sample at the same Ioff level. Data are normalized to the control
RVT (regular V t) median.

96
4.3.2 Charge Pumping

Charge pumping measurements are performed on large-area gated capacitor array

test structures to characterize the quality of the Si-SiO2 interface for both thin and

thick oxide devices. To correct for the DC gate current, which flows in the ultra-

thin gate insulators, a differential frequency method is used, where the difference is

taken between two charge pumping currents (Icp) measured at two frequencies (with

constant transition times in square wave) to extract Nit (interface trap density, in

cm−2 ) [74, 75], as

Icp1 − Icp2
Nit = (4.1)
(f1 − f2 )AG

where the Icp1 and Icp2 are the charge pumping current measured at two frequencies,

500 KHz and 50 KHz in this case, namely f1 and f2 in the denominator; AG is the

gate area.

Note, the measured Nit (in cm−2 ) is the product of Dit and ∆φs , where Dit is the

usually referred “interface trap density” in cm−2 eV−1 , and ∆φs is the swept surface

potential in eV, independent of the applied frequency in the case of square wave-

forms. Since the transition times are maintained the same for these two frequencies,

∆φs is the same. Thus, it is appropriate to compare different values of Nit to ac-

cess the interface quality for different treatment. Besides, our primary purpose is

to qualitatively compare the interface quality for samples with and without carbon

implantation, the results are extracted at a constant gate overdrive (OD), which is

VGS (OD) = VGS − V t (0.1 V for NMOS and 0.3 V for PMOS respectively), instead

of at the maximum Icp point in conventional charge pumping technique. The results,

shown in Figure 4.3, indicate an increase of 2:1 for Nit in thin-oxide PMOS, 1.2:1 for

97
Figure 4.3: Nit extracted for both thin and thick oxide. Results are obtained from
the average of four samples at a constant gate overdrive. The interface trap density
Nit shows an increase of 2:1 for Nit in thin-oxide PMOS, 1.2:1 for thick oxide PMOS
and 2.5:1 increase for thick oxide NMOS over the control sample.

thick oxide PMOS and 2.5:1 increase for thick oxide NMOS over the control sam-

ple. The observed increase in the device sub-threshold slope is not significant in SC

devices.

4.3.3 Effective Mobility

The effective mobility is obtained from C-V and I-V measurements on long channel

(LC) transistors with the methods described in Section 3.3.2 [63, 64, 76]. The carrier

mobility at Vds of both positive and negative 20 mV are averaged in the experiments.

The mobility is measured at 0.5 gate over drive (OD), therefore the vertical field

98
Figure 4.4: Comparison of the mobility of the NMOS long channel devices: the
electron mobility is enhanced by 10%. Results are normalized to the control RVT
(regular Vt) median.

are similar for all treatments. For each treatment group, 40 samples are taken and

statistically analyzed to compare the effects of carbon implants.

As shown in Figure 4.4, based on the mobility extracted from RVT long channel

MOSFETs, the NMOS mobility is increased by 10% in the Cii samples as compared

with the control samples.

4.3.4 Threshold Voltage Comparison

The threshold voltage (Vt) is extracted from standard short channel RVT devices

based on point-data characterization: the threshold voltage is defined at certain drive

current level (as described in Section 3.3.1). Figure 4.5 compare the Vt in the linear

99
region of the regular-Vt (RVT) short channel devices. The Vt is reduced by 0.1 V in

Cii NMOS samples and remains unchanged in PMOS devices. This 0.1 V reduction

in NMOS Vt is beneficial to low power application to reduce the power dissipation.

Given that the threshold voltage of in scaled CMOS technology are no more than 0.5

V, this 0.1 V reduction is quite significant. The NMOS Vt reduction is a result of

a better-controlled (sharper) “retrograde” (low concentration near the surface, high

concentration deep in the bulk region) boron channel profile due to carbon’s retarding

effects on boron diffusion [44]. Carbon acts mainly on boron diffusion to create a shift

in the Vt only in NMOS and not in PMOS devices. Although an increase in interface

states could also shift the Vt, there is not enough difference in the measured Nit to

cause the observed change in the Vt.

4.4 Discussion

The net performance enhancement in channel carbon implanted NMOS devices

can be explained by a lower concentration of active boron in the channel region. This

improvement can be attributed to the combination of retarding effects on the boron

diffusion and the deactivation of boron by Cii [77]. It is very interesting to see that the

PMOS performance is improved at the same time, which might be attributed to the

action of the implanted carbon to block the source-drain, lateral boron diffusion under

the gate electrode combined with a suppression of short-channel effects (SCE). We

did observe an increased junction current (10 times) in the Cii samples, in agreement

with [44]. However, we believe by carefully designing the implantation conditions, we

could further optimized the doping profile and minimize this current.

100
Figure 4.5: Threshold voltage change of the short channel devices: a) NMOS Vt is
reduced by 0.1 V in Cii samples and b) PMOS Vt remains the same. Results are
refereed to the Control RVT (regular Vt) median. The Vt is reduced by 0.1 V in Cii
NMOS samples and remains unchanged in PMOS devices.

101
 In addition to the fabrication process described in Section 4.2, comparison splits

have been made for which the Cii in introduced after the dummy interfacial oxide

growth. In this case, there is no significant performance improvement for either the

NMOS or PMOS devices. As consequent of these experiments, we believe most of

the boron diffusion takes place in the dummy IL oxide growth, which is done, as

mentioned previously, with a thermal process. Thus, the dummy interfacial layer

growth step should be performed after the Cii. In addition, this thermal process also

helps to move the carbon into substitutional sites, which enhances the suppression of

boron diffusion [44].

Another key point in our process integration is the replacement-gate method. In

this process, the dummy IL is removed after the major high-temperature thermal pro-

cess steps and the final IL oxide is grown in the later gate formation steps by chemical

oxidation (ozone). We believe any fixed charge in the interfacial region, caused by

the diffused carbon atoms, should be removed during the dummy IL removal. We

have observed only a Vt reduction in NMOS, rather than a reduced NMOS Vt and

increased PMOS Vt (in absolute value), which has been reported [72], where the shift

has been attributed to the existence of fixed charge by the carbon atoms diffusing

to the interface. These authors [72] utilized a gate-first scheme, where the final gate

dielectric layer is grown before the formation of the spacers and source/drain regions,

combined with low-energy carbon implantation, which might explain the observed

differences. We have also fabricated thick-oxide MOSFET in a similar manner except

the dummy IL is not removed. For these devices, the PMOS Vt (in absolute value) is

increased by roughly 100 mV, while the NMOS Vt is decreased by roughly 200 mV. In

this case, the fixed charge in the dummy IL causes the PMOS Vt shift and a portion

102
of the NMOS Vt shift (100 mV); however, the sharper boron profile is the reason for

the additional NMOS Vt reduction. This observation is in agreement with the case of

the thin-oxide device (no dummy IL) as described earlier (only NMOS Vt reduction).

As a result of these experiments, we propose a replacement-gate approach, with a

dummy gate, as compared with a gate-first approach.

103
 Chapter 5: Conclusions

This dissertation offers a quantum mechanical treatment for 1/f noise in nanoscaled

MOS devices. The simulation based on our model shows good agreement with the

experimental results obtained from a high-K NMOS transistor with ultra-thin oxide.

We have also addressed the modeling and characterization of scaled silicon CMOS

devices with: 1) a ultra-thin SiON and polysilicon gate, 2) a high-K NMOS device

with ultra-thin oxide. We present research on channel carbon ion implantation on

advanced replacement gate technology as a cost-effective approach to precisely control

the channel dopant profile in the next-generation CMOS technology. In this chapter,

we will discuss the conclusions of the research presented in the dissertation, based on

both experimental results and theoretical analysis. In addition, we will suggest some

recommendations for future work of nanoscaled CMOS devices.

5.1 Summaries of This Work

Motivated by pursuing better understanding of 1/f mechanisms in scaled MOS

transistors, both experimental and theoretical work have been conducted. With sur-

face roughness (β) taken into account, we extend the Unified Model to provide an

understanding of the 1/f noise in scaled MOSFET devices with ultra-thin gate di-

electrics. We have also developed a theoretical treatment for the remote Coulomb

104
scattering (α), which focuses on traps in the dielectrics and includes the charge cen-

troid and the finite extension of the charge centroid into the silicon. The modeled

remote Coulomb scattering parameter and the surface roughness scattering parame-

ter (β) show good agreement with the observed experimental values. The 1/f noise in

scaled CMOS devices may be interpreted in terms of the remote Coulomb scattering

(α) and the surface roughness scattering (β = qθS /µ0 Cef f ), in addition to the num-

ber fluctuations. Simulations, based on theoretical modeling, show good agreement

with experimental data obtained from a high-K NMOS device with ultra-thin oxide,

for both DC I-V transfer and noise characteristics. In our work, we find that the β

value exceeds α at high inversion levels, therefore it is necessary to take into account

the fluctuation in mobility induced by the variation in the normal electric field. We

believe as the devices scaled further, the surface roughness scattering parameter (β)

will become more important in the 1/f noise due to the increased normal field. Our

model can be extended to other material systems such as III-V devices, given that the

appropriate energy levels for carriers and parameters for the materials are utilized.

Several experimental setups, involving automatic data acquisition, have been built

with the help of computer programming, which greatly enhances the functionality

of the setups. With these setups we have evaluated device performance and certain

physical parameters of both NMOS and PMOS SiON MOSFET devices. For these de-

vices, the gate leakage current does not have strong impact on the CV characteristics.

The equivalent oxide thickness (EOT) is obtained from a 1 MHz CV measurement

as 2.4 nm (NMOS) and 2.6 nm (PMOS) at inversion, which is slightly larger than

the physical thickness of the SiON layer due to poly-gate depletion and the charge

centroid of carriers in the inversion layer. The substrate doping densities, extracted

105
from transfer characteristics under different body bias conditions, are 3.8E17 cm−3

for NMOS and 2.0E17 cm−3 for PMOS. The effective mobility values, obtained by

split-CV technique, are extracted to be 198 cm2 /V-s for electron in NMOS and 70

cm2 /V-s for hole in PMOS at around 0.5 V gate overdrive. With the exclusion of

series resistance and surface roughness scattering, the mobility containing only bulk

mobility and remote Coulomb scattering is 345 cm2 /V-s and 144 cm2 /V-s for N and

P samples. This indicates, for these high quality SiON devices, the surface roughness

imposes a great impact on the carrier mobility.

Variable frequency charge pumping measurement with a triangular waveform has

been performed on both N and P SiON MOSFET, to study and compare the interface

quality of these samples. After the gate current correction, the measured interface

trap densities are 9.7E10 cm−2 eV−1 and 5.8E10 cm−2 eV−1 respectively in NMOS and

PMOS samples. The geometric mean of the electron and hole capture cross section

is also extracted to be 3.3E-17 cm2 and 9.1E-17 cm2 receptively for N and P devices.

The extracted results indicate an excellent interface quality between the SiON layer

and the silicon substrate. Since the nitride concentration is not high, the interface

quality is comparable with devices with pure SiO2 gate dielectrics.

Carbon ion-implantation (Cii) into CMOS device channels improves NMOS high-

K, metal gate, device performance for replacement-gate, low power, technology. NMOS

samples with Cii demonstrate a desirable decrease (-0.1 V) in Vt and improved elec-

tron mobility (10%) as compared with control samples without the Cii. This im-

provement has been attributed to the retarding effects of boron diffusion as well as

deactivation of boron caused by the carbon, which results in a better-controlled ret-

rograde boron channel profile and a lower active boron concentration in the inversion

106
region. Considering the overall benefits, channel Cii is good for controlling the vertical

doping profile.

5.2 Recommendations for Future Research

Construct a fast sensing system with both high resolution and sampling rate, to

study the random telegraph signal (RTS) noise of MOSFET devices, which can be

observed in small area samples; and compare the RTS noise to 1/f noise, which is

usually measured in samples of larger area.

Develop quantum mechanical treatment of 1/f noise in PMOS devices. The scat-

tering and tunneling processes are similar with that in NMOS, however, the energy

subband structures and the 2D behavior will be different.

With the current setup, study the stressing behaviors of SiON devices, such as

trap creation and flatband voltage shift.

Incorporate temperature capability in the current setup, and study the tempera-

ture dependent behavior of 1/f noise in nanoscaled MOSFET devices.

Extend the 1/f noise mechanisms and behavior in a single transistor to circuit and

systems, and explore the noise benchmark methodology in modern VLSI systems.

107
 Bibliography

[1] Don Scansen. Noise in electronic devices. Technical report, Semiconductor In-
sights, 1996.

[2] M. M. Jevtic. Noise as a diagnostic and prediction tool in reliability physics.

Microelectronics and Reliability, 35(3):455 – 477, 1995. ISSN 0026-2714.
DOI:DOI: 10.1016/0026-2714(95)93070-Q. Reliability Physics of Advanced Elec-
tron Devices.

[3] S. Christensson, I. Lundstrm, and C. Svensson. Low frequency noise in mos

transistors–i theory. Solid-State Electronics, 11(9):797 – 812, 1968. ISSN 0038-
1101. DOI:DOI: 10.1016/0038-1101(68)90100-7.

[4] Stefan Machlup. Noise in semiconductors: Spectrum of a two-parameter random

signal. Journal of Applied Physics, 25(3):341–343, 1954. DOI:10.1063/1.1721637.

[5] L. K. J. Vandamme and F. N. Hooge. What do we certainly know about 1/f

noise in mosts? IEEE Transactions on Electron Devices, 55(11):3070–3085, Nov.
2008. DOI:10.1109/TED.2008.2005167.

[6] A. L. McWhorter. Semiconductor Surface Physics. University of Pennsylvania

Press, 1957.

[7] C. T. Sah and F. H. Hielscher. Evidence of the surface origin of the 1f noise.
Phys. Rev. Lett., 17(18):956–958, Oct 1966. DOI:10.1103/PhysRevLett.17.956.

[8] G. Reimbold. Modified 1/f trapping noise theory and experiments in mos tran-
sistors biased from weak to strong inversion-influence of interface states. Electron
Devices, IEEE Transactions on, 31(9):1190 – 1198, sep 1984. ISSN 0018-9383.
DOI:10.1109/T-ED.1984.21687.

[9] F. N. Hooge. 1/f noise sources. IEEE Transactions on Electron Devices, 41(11):
1926–1935, Nov. 1994. DOI:10.1109/16.333808.

[10] C.T. Sah. Theory of low-frequency generation noise in junction-gate field-effect

transistors. Proceedings of the IEEE, 52(7):795–814, July 1964. ISSN 0018-9219.

108
[11] Horng-Sen Fu and Chih-Tang Sah. Theory and experiments on surface 1/f noise.
Electron Devices, IEEE Transactions on, 19(2):273–285, 1972. ISSN 0018-9383.
DOI:10.1109/T-ED.1972.17407.
[12] Z. Celik-Butler and T.Y. Hsiang. Determination of si-sio2 interface trap density
by 1/f noise measurements. Electron Devices, IEEE Transactions on, 35(10):
1651–1655, Oct 1988. ISSN 0018-9383. DOI:10.1109/16.7368.
[13] R. Jayaraman and C. G. Sodini. A 1/f noise technique to extract the ox-
ide trap density near the conduction band edge of silicon. Electron Devices,
IEEE Transactions on, 36(9):1773 –1782, September 1989. ISSN 0018-9383.
DOI:10.1109/16.34242.
[14] M. J. Kirton and M. J. Uren. Capture and emission kinetics of individual
si:sio[sub 2] interface states. Applied Physics Letters, 48(19):1270–1272, 1986.
DOI:10.1063/1.97000. URL http://link.aip.org/link/?APL/48/1270/1.
[15] M.J. Kirton and M.J. Uren. Noise in solid-state microstructures: A new perspec-
tive on individual defects, interface states and low-frequency (1/) noise. Advances
in Physics, 38(4):367–468, 1989. DOI:10.1080/00018738900101122.
[16] F. N. Hooge and L. K. J. Vandamme. Lattice scattering causes 1/f noise. Physics
Letters A, 66:315–316, May 1978. DOI:10.1016/0375-9601(78)90249-9.
[17] Tanvir Hasan Morshed, Siva Prasad Devireddy, Zeynep elik Butler, Ajit Shan-
ware, Keith Green, J.J. Chambers, M.R. Visokay, and Luigi Colombo. Physics-
based 1/f noise model for mosfets with nitrided high-[kappa] gate dielectrics.
Solid-State Electronics, 52(5):711–724, May 2008.
[18] K. K. Hung, P. K. Ko, C. Hu, and Y. C. Cheng. A unified model for the flicker
noise in metal-oxide-semiconductor field-effect transistors. IEEE Transactions
on Electron Devices, 37(3):654–665, March 1990. DOI:10.1109/16.47770.
[19] E. P. Vandamme and L. K. J. Vandamme. Critical discussion on unified 1/f noise
models for mosfets. Electron Devices, IEEE Transactions on, 47(11):2146 –2152,
November 2000. ISSN 0018-9383. DOI:10.1109/16.877177.
[20] Zeynep Celik-Butler. Different noise mechanisms in high-k dielectric gate stacks.
In Alexander A. Balandin, Francois Danneville, M. Jamal Deen, and Daniel M.
Fleetwood, editors, Noise in Devices and Circuits III, volume 5844, pages 177–
184. SPIE, June 2005. DOI:10.1117/12.611250.
[21] Gino Giusi, F. Crupi, C. Pace, C. Ciofi, and G. Groeseneken. Comparative
study of drain and gate low-frequency noise in nmosfets with hafnium-based
gate dielectrics. IEEE Transactions on Electron Devices, 53(4):823–828, April
2006. DOI:10.1109/TED.2006.870287.

109
[22] H. D. Xiong, Dawei Heh, Shuo Yang, Xiaoxiao Zhu, M. Gurfinkel, G. Bersuker,
D. E. Ioannou, C. A. Richter, K. P. Cheung, and J. S. Suehle. Stress-
induced defect generation in hfosiostacks observed by using charge pumping
and low frequency noise measurements. In Proc. IEEE International Reliabil-
ity Physics Symposium IRPS 2008, pages 319–323, April 27 2008–May 1 2008.
DOI:10.1109/RELPHY.2008.4558905.

[23] Bigang Min, S.P. Devireddy, Z. Celik-Butler, A. Shanware, Luigi Colombo,

K. Green, J. J. Chambers, M. R. Visokay, and A.L.P. Rotondaro. Impact of
interfacial layer on low-frequency noise of hfsion dielectric mosfets. Electron
Devices, IEEE Transactions on, 53(6):1459–1466, June 2006. ISSN 0018-9383.
DOI:10.1109/TED.2006.874759.

[24] L. Zafari, J. Jomaah, G. Ghibaudo, and O. Faynot. Low frequency noise analysis
in hfo[sub 2]/sio[sub 2] gate oxide fully depleted silicon on insulator transistors.
volume 27, pages 402–405. AVS, 2009. DOI:10.1116/1.3072518. URL http://
link.aip.org/link/?JVB/27/402/1.

[25] E. Simoen, A. Veloso, N. Horiguchi, and C. Claeys. Low-frequency noise

assessment of the oxide quality of gate-last high- pmosfets. Electron De-
vice Letters, IEEE, 33(10):1366–1368, October 2012. ISSN 0741-3106.
DOI:10.1109/LED.2012.2210993.

[26] N. Tega, H. Miki, F. Pagette, D.J. Frank, A. Ray, M.J. Rooks, W. Haensch, and
K. Torii. Increasing threshold voltage variation due to random telegraph noise
in fets as gate lengths scale to 20 nm. In VLSI Technology, 2009 Symposium on,
pages 50–51, 2009.

[27] H. Miki, N. Tega, M. Yamaoka, D. J. Frank, A. Bansal, M. Kobayashi, K. Cheng,

C. P. D’Emic, Z. Ren, S. Wu, Yau J.-B., Y. Zhu, M. A. Guillorn, D.-G. Park,
W. Haensch, E. Leobandung, and K. Torii. Statistical measurement of ran-
dom telegraph noise and its impact in scaled-down high-k/metal-gate mosfets.
In Electron Devices Meeting, 2012. IEDM ’12. Technical Digest. International,
pages 450–453, 2012.

[28] ITRS. International technology roadmap for semiconductors. URL http://www.

itrs.net/.

[29] R.H. Dennard, F.H. Gaensslen, V.L. Rideout, E. Bassous, and A.R. LeBlanc.
Design of ion-implanted mosfet’s with very small physical dimensions. Solid-
State Circuits, IEEE Journal of, 9(5):256 – 268, October 1974. ISSN 0018-9200.
DOI:10.1109/JSSC.1974.1050511.

110
[30] G. Baccarani, M.R. Wordeman, and R.H. Dennard. Generalized scaling the-
ory and its application to a 1/4 micrometer mosfet design. Electron De-
vices, IEEE Transactions on, 31(4):452 – 462, April 1984. ISSN 0018-9383.
DOI:10.1109/T-ED.1984.21550.

[31] R.H. Dennard. Scaling limits of silicon vlsi technology. In MichaelJ. Kelly
and Claude Weisbuch, editors, The Physics and Fabrication of Microstructures
and Microdevices, volume 13 of Springer Proceedings in Physics, pages 352–369.
Springer Berlin Heidelberg, 1986. ISBN 978-3-642-71448-1.

[32] S. Ito, H. Namba, K. Yamaguchi, T. Hirata, K. Ando, S. Koyama, S. Kuroki,

N. Ikezawa, T. Suzuki, T. Saitoh, and T. Horiuchi. Mechanical stress effect of
etch-stop nitride and its impact on deep submicron transistor design. In Electron
Devices Meeting, 2000. IEDM ’00. Technical Digest. International, pages 247 –
250, 2000. DOI:10.1109/IEDM.2000.904303.

[33] K. Mistry, M. Armstrong, C. Auth, S. Cea, T. Coan, T. Ghani, T. Hoffmann,

A. Murthy, J. Sandford, R. Shaheed, K. Zawadzki, K. Zhang, S. Thompson,
and M. Bohr. Delaying forever: Uniaxial strained silicon transistors in a 90nm
cmos technology. In VLSI Technology, 2004. Digest of Technical Papers. 2004
Symposium on, pages 50 – 51, June 2004. DOI:10.1109/VLSIT.2004.1345387.

[34] B. Doyle, B. Boyanov, S. Datta, M. Doczy, S. Hareland, B. Jin, J. Kava-

lieros, T. Linton, R. Rios, and R. Chau. Tri-gate fully-depleted cmos tran-
sistors: fabrication, design and layout. In VLSI Technology, 2003. Di-
gest of Technical Papers. 2003 Symposium on, pages 133 – 134, June 2003.
DOI:10.1109/VLSIT.2003.1221121.

[35] T. Park, S. Choi, D.H. Lee, J.R. Yoo, B.C. Lee, J.Y. Kim, C.G. Lee, K.K. Chi,
S.H. Hong, S.J. Hynn, Y.G. Shin, J.N. Han, I.S. Park, U.I. Chung, J.T. Moon,
E. Yoon, and J.H. Lee. Fabrication of body-tied finfets (omega mosfets) using
bulk si wafers. In VLSI Technology, 2003. Digest of Technical Papers. 2003
Symposium on, pages 135 – 136, June 2003. DOI:10.1109/VLSIT.2003.1221122.

[36] K.J. Kuhn. Considerations for ultimate cmos scaling. Electron De-
vices, IEEE Transactions on, 59(7):1813–1828, June 2012. ISSN 0018-9383.
DOI:10.1109/TED.2012.2193129.

[37] Y. Taur. Cmos design near the limit of scaling. IBM Journal of Re-
search and Development, 46(2.3):213 –222, March 2002. ISSN 0018-8646.
DOI:10.1147/rd.462.0213.

111
[38] D.J. Frank, R.H. Dennard, E. Nowak, P.M. Solomon, Y. Taur, and Hon-
Sum Philip Wong. Device scaling limits of si mosfets and their application depen-
dencies. Proceedings of the IEEE, 89(3):259 –288, March 2001. ISSN 0018-9219.
DOI:10.1109/5.915374.

[39] G. D. Wilk, R. M. Wallace, and J. M. Anthony. High-kappa gate dielectrics: Cur-

rent status and materials properties considerations. Journal of Applied Physics,
89(10):5243–5275, 2001. DOI:10.1063/1.1361065.

[40] K. Mistry, C. Allen, C. Auth, B. Beattie, D. Bergstrom, M. Bost, M. Brazier,

M. Buehler, A. Cappellani, R. Chau, C.-H. Choi, G. Ding, K. Fischer, T. Ghani,
R. Grover, W. Han, D. Hanken, M. Hattendorf, J. He, J. Hicks, R. Huessner,
D. Ingerly, P. Jain, R. James, L. Jong, S. Joshi, C. Kenyon, K. Kuhn, K. Lee,
H. Liu, J. Maiz, B. Mclntyre, P. Moon, J. Neirynck, S. Pae, C. Parker, D. Par-
sons, C. Prasad, L. Pipes, M. Prince, P. Ranade, T. Reynolds, J. Sandford,
L. Shifren, J. Sebastian, J. Seiple, D. Simon, S. Sivakumar, P. Smith, C. Thomas,
T. Troeger, P. Vandervoorn, S. Williams, and K. Zawadzki. A 45nm logic tech-
nology with high-k+metal gate transistors, strained silicon, 9 cu interconnect
layers, 193nm dry patterning, and 100packaging. In Electron Devices Meet-
ing, 2007. IEDM 2007. IEEE International, pages 247 –250, December 2007.
DOI:10.1109/IEDM.2007.4418914.

[41] Yuan Taur and Tak H. Ning. Fundamentals of Modern VLSI Devices. Cambridge
University Press, New York, NY, USA, 2nd edition, 2009. ISBN 0521832942,
9780521832946.

[42] S. Ogura, C.F. Codella, N. Rovedo, J.F. Shepard, and J. Riseman. A half micron
mosfet using double implanted ldd. In Electron Devices Meeting, 1982 Interna-
tional, volume 28, pages 718 – 721, 1982. DOI:10.1109/IEDM.1982.190395.

[43] J.Y.-C. Sun, Yuan Taur, R.H. Dennard, and S.P. Klepner. Submicrometer-
channel cmos for low-temperature operation. Electron Devices, IEEE
Transactions on, 34(1):19 – 27, January 1987. ISSN 0018-9383.
DOI:10.1109/T-ED.1987.22881.

[44] I. Ban, M.C. Ozturk, and E.K. Demirlioglu. Suppression of oxidation-enhanced

boron diffusion in silicon by carbon implantation and characterization of mosfets
with carbon-implanted channels. Electron Devices, IEEE Transactions on, 44
(9):1544 –1551, September 1997. ISSN 0018-9383. DOI:10.1109/16.622613.

[45] Y. C. Cheng. Electron mobility in an mos inversion layer. In Proceeding of the

3rd Conference on Solid State Devices, page 173, 1971.

112
[46] A. Hartstein, A.B. Fowler, and M. Albert. Temperature dependence of scat-
tering in the inversion layer. Surface Science, 98:181 – 190, 1980. ISSN 0039-
6028. DOI:10.1016/0039-6028(80)90492-6. URL http://www.sciencedirect.
com/science/article/pii/0039602880904926.

[47] S. C. Sun and James D. Plummer. Electron mobility in inversion and

accumulation layers on thermally oxidized silicon surfaces. Electron De-
vices, IEEE Transactions on, 27(8):1497–1508, 1980. ISSN 0018-9383.
DOI:10.1109/T-ED.1980.20063.

[48] Yanli Zhang and Marvin H. White. A quantum mechanical mobility model
for scaled nmos transistors with ultra-thin high-k dielectrics and metal gate
electrodes. Solid-State Electronics, 52(11):1810 – 1814, 2008. ISSN 0038-
1101. DOI:10.1016/j.sse.2008.08.003. URL http://www.sciencedirect.com/
science/article/pii/S0038110108002761.

[49] Frank Stern. Self-consistent results for n-type si inversion layers. Phys. Rev. B,
5:4891–4899, June 1972. DOI:10.1103/PhysRevB.5.4891.

[50] Frank Stern and W. E. Howard. Properties of semiconductor surface inversion

layers in the electric quantum limit. Phys. Rev., 163:816–835, November 1967.
DOI:10.1103/PhysRev.163.816.

[51] C.T. Sah, T.H. Ning, and L.L. Tschopp. The scattering of electrons by
surface oxide charges and by lattice vibrations at the silicon-silicon diox-
ide interface. Surface Science, 32(3):561 – 575, 1972. ISSN 0039-6028.
DOI:10.1016/0039-6028(72)90183-5.

[52] T. H. Ning and C. T. Sah. Theory of scattering of electrons in a nondegenerate-

semiconductor-surface inversion layer by surface-oxide charges. Phys. Rev. B, 6:
4605–4613, December 1972. DOI:10.1103/PhysRevB.6.4605.

[53] Yu Anne Zeng, Marvin H. White, and Mrinal K. Das. Electron transport
modeling in the inversion layers of 4h and 6hsic mosfets on implanted re-
gions. Solid-State Electronics, 49(6):1017 – 1028, 2005. ISSN 0038-1101.
DOI:10.1016/j.sse.2005.03.002.

[54] Y.C. Cheng and E.A. Sullivan. On the role of scattering by surface roughness in
silicon inversion layers. Surface Science, 34(3):717 – 731, 1973. ISSN 0039-6028.
DOI:10.1016/0039-6028(73)90038-1.

[55] S. M. Goodnick, D. K. Ferry, C. W. Wilmsen, Z. Liliental, D. Fathy, and O. L.

Krivanek. Surface roughness at the si(100)-sio2 interface. Phys. Rev. B, 32:
8171–8186, December 1985. DOI:10.1103/PhysRevB.32.8171.

113
[56] Ming-Jer Chen, Li-Ming Chang, Shin-Jiun Kuang, Chih-Wei Lee, Shang-Hsun
Hsieh, Chi-An Wang, Sou-Chi Chang, and Chien-Chih Lee. Temperature-
oriented mobility measurement and simulation to assess surface roughness in
ultrathin-gate-oxide ( 1 nm) nmosfets and its tem evidence. IEEE Trans-
actions on Electron Devices, 59(4):949 –955, April 2012. ISSN 0018-9383.
DOI:10.1109/TED.2012.2182771.

[57] V.R. Vathulya and M.H. White. Characterization of inversion and accumulation
layer electron transport in 4h and 6h-sic mosfets on implanted p-type regions.
Electron Devices, IEEE Transactions on, 47(11):2018 –2023, November 2000.
ISSN 0018-9383. DOI:10.1109/16.877161.

[58] Y.T. Hou, M.F. Li, H.Y. Yu, and D.-L. Kwong. Modeling of tunnel-
ing currents through hfo2 and (hfo2)x(al2o3)/sub 1-x/ gate stacks. Elec-
tron Device Letters, IEEE, 24(2):96 –98, February 2003. ISSN 0741-3106.
DOI:10.1109/LED.2002.807708.

[59] National Instruments. Ni labview. URL http://www.ni.com/labview/.

[60] Jan Jacob. A (short) introduction to labview. tutotial, February 2012.

[61] Dieter K. Schroder. Semiconductor Material and Device Characterization. Wiley-

Interscience, 2006. ISBN 0471749095.

[62] K.J. Yang and Chenming Hu. Mos capacitance measurements for high-leakage
thin dielectrics. Electron Devices, IEEE Transactions on, 46(7):1500 –1501, July
1999. ISSN 0018-9383. DOI:10.1109/16.772500.

[63] Anant G. Sabnis and James T. Clemens. Characterization of the electron mo-
bility in the inverted lt;100 gt; si surface. In Electron Devices Meeting, 1979
Internationa, volume 25, pages 18–21, 1979. DOI:10.1109/IEDM.1979.189528.

[64] N.D. Arora and G.Sh. Gildenblat. A semi-empirical model of the mos-
fet inversion layer mobility for low-temperature operation. Electron De-
vices, IEEE Transactions on, 34(January):89–93, 1987. ISSN 0018-9383.
DOI:10.1109/T-ED.1987.22889.

[65] T.J. Krutsick and M.H. White. Consideration of doping profiles in mosfet mobil-
ity modeling. Electron Devices, IEEE Transactions on, 35(7):1153–1155, 1988.
ISSN 0018-9383. DOI:10.1109/16.3381.

[66] T.J. Krutsick, M.H. White, Hon-Sum Wong, and R. V H Booth. An im-
proved method of mosfet modeling and parameter extraction. Electron De-
vices, IEEE Transactions on, 34(August):1676–1680, 1987. ISSN 0018-9383.
DOI:10.1109/T-ED.1987.23136.

114
[67] G. Groeseneken, H.E. Maes, N. Beltran, and R.F. De Keersmaecker. A reli-
able approach to charge-pumping measurements in mos transistors. Electron
Devices, IEEE Transactions on, 31(1):42 – 53, January 1984. ISSN 0018-9383.
DOI:10.1109/T-ED.1984.21472.

[68] R.R. Siergiej, M.H. White, and N.S. Saks. Theory and measurement of quan-
tization effects on sisio2 interface trap modeling. Solid-State Electronics, 35(6):
843 – 854, 1992. ISSN 0038-1101. DOI:10.1016/0038-1101(92)90287-M. URL
http://www.sciencedirect.com/science/article/pii/003811019290287M.

[69] Victor Moroz, Yong-Seog Oh, Dipu Pramanik, Houda Graoui, and Majeed A.
Foad. Optimizing boron junctions through point defect and stress engineer-
ing using carbon and germanium co-implants. Applied Physics Letters, 87(5):
051908, 2005. DOI:10.1063/1.2001163. URL http://link.aip.org/link/?
APL/87/051908/1.

[70] H.-J. Gossmann, C.S. Rafferty, G. Hobler, H.-H. Vuong, D.C. Jacobson, and
M. Frei. Suppression of reverse short channel effect by a buried carbon layer.
In Electron Devices Meeting, 1998. IEDM ’98. Technical Digest., International,
pages 725 –728, December 1998. DOI:10.1109/IEDM.1998.746459.

[71] J. Ellis-Monaghan, Kam-Leung Lee, Meikei Ieong, and I. Yang. Carbon im-
planted halo for super halo characteristic nfets in bulk and soi. In Solid-State
Device Research Conference, 2001. Proceeding of the 31st European, pages 155 –
158, september 2001. DOI:10.1109/ESSDERC.2001.195224.

[72] Cory E. Weber and Keith E. Zawadzki. Carbon controlled fixed charge process,
2009. URL http://www.google.com/patents/US20090011581.

[73] M.-H. Na, E.J. Nowak, W. Haensch, and J. Cai. The effective drive current in
cmos inverters. In Electron Devices Meeting, 2002. IEDM ’02. International,
pages 121–124, 2002. DOI:10.1109/IEDM.2002.1175793.

[74] P. Masson, J.-L. Autran, and J. Brini. On the tunneling component of charge
pumping current in ultrathin gate oxide mosfets. Electron Device Letters, IEEE,
20(2):92 –94, February 1999. ISSN 0741-3106. DOI:10.1109/55.740662.

[75] S.S. Chung, S.-J. Chen, C.-K. Yang, S.-M. Cheng, S.-H. Lin, Y.-C. Sheng, H.-S.
Lin, K.-T. Hung, D.-Y. Wu, T.-R. Yew, S.-C. Chien, F.-T. Liou, and F. Wen. A
novel and direct determination of the interface traps in sub-100 nm cmos devices
with direct tunneling regime (12 sim;16 a) gate oxide. In VLSI Technology,
2002. Digest of Technical Papers. 2002 Symposium on, pages 74 – 75, 2002.
DOI:10.1109/VLSIT.2002.1015394.

115
[76] C.G. Sodini, T.W. Ekstedt, and J.L. Moll. Charge accumulation and mobil-
ity in thin dielectric mos transistors. Solid-State Electronics, 25(9):833 – 841,
1982. ISSN 0038-1101. DOI:10.1016/0038-1101(82)90170-8. URL http://www.
sciencedirect.com/science/article/pii/0038110182901708.

[77] K.R.C. Mok, F. Benistant, R.S. Teo, and S. Chu. Tcad model-
ing and simulation of boron deactivation in nmos carbon-implanted chan-
nel. Solid-State Electronics, 53(6):658 – 662, June 2009. ISSN 0038-
1101. DOI:10.1016/j.sse.2009.04.003. URL http://www.sciencedirect.com/
science/article/pii/S0038110109001075.

[78] Y. Zhang. Characterization and Modeling of Scaled NMOS Devices with High-
K Dielectrics and Metal Gate Electrodes http://www.youtube.com/watch?v=-
YJg4merJVs. Lehigh University, 2008. ISBN 9780549654858. URL http://
books.google.com/books?id=ti96sX9qmN4C.

[79] I.S. Gradshteyn and I.I.M. Ryzhik. Tables of Integrals, Series, and Products.
Academic Press, 1994.

[80] Jr. Albert Thomas Fromhold. Quantum Mechanics for Applied Physics and
Engineering. Dover Books on Engineering Series. Academic Press, 1981. ISBN
9780486667416. URL http://books.google.com/books?id=3SOwc6npkIwC.

[81] Tsuneya Ando, Alan B. Fowler, and Frank Stern. Electronic proper-
ties of two-dimensional systems. Rev. Mod. Phys., 54:437–672, Apr 1982.
DOI:10.1103/RevModPhys.54.437. URL http://link.aps.org/doi/10.1103/
RevModPhys.54.437.

[82] M.G. Martin. Charge Trapping in Ultra-thin MOS Dielectrics. Lehigh University,
1999. URL http://books.google.com/books?id=2A85OAAACAAJ.

[83] J.S. Brugler and P.G.A. Jespers. Charge pumping in mos devices. Electron
Devices, IEEE Transactions on, 16(3):297 – 302, March 1969. ISSN 0018-9383.
DOI:10.1109/T-ED.1969.16744.

[84] R.E. Paulsen and M.H. White. Theory and application of charge pumping for
the characterization of si-sio2 interface and near-interface oxide traps. Electron
Devices, IEEE Transactions on, 41(7):1213 –1216, July 1994. ISSN 0018-9383.
DOI:10.1109/16.293349.

116
 Appendix A: Derivation of the Remote Coulomb Scattering
Parameter in 1/f Noise Model

In this section of the appendix, we present a detailed derivation for the remote

Coulomb scattering parameter, i.e., “α” employed in the modified unified 1/f noise

model (previously included in Section 2.1.3).

The movement of electrons in the inversion channel, represented by QB (~ρ, z), is

influenced by the traps in the dielectrics represented by QA (~ρ, z) in Figure A.1. ‘x-y’

plan represents the Si-SiO2 interface.

Start with the effective mass Hamiltonian for electrons moving in the inversion

layers as [78]

~2 2
H=− ∇ − qφ(~r)
2m∗
~2
= − ∗ ∇2 − qφ◦ (z) − qδφ(~r)
2m
= H◦ + H′

where q is the electron charge, ~ is the reduced Plank’s constant, m∗ is the effective

electron mass and

~2 2
H◦ = − ∇ − qφ◦ (z) (A.1)
2m∗

117
Figure A.1: Coordinate system for calculating the remote Coulomb scattering param-
eter.

118
is the unperturbed Hamiltonian. We can write the perturbed Hamiltonian with ref-

erence to Figure A.1 as

−q X ∆Qi
H ′ = −qδφ(~r) = (A.2)
4πǭ i |~r − r~i |

ǫS +ǫox
where ǭ = 2
is the averaged permittivity and ∆Qi is the source charge. ǫS is the

semiconductor permittivity and ǫox is the oxide permittivity.

If we assume a Stern-Howard wavefunction [50] for the electron in the z-direction,

and a 2-D plane wave in the x-y plane associated with 2-D wave vector, ~k, for the

incident plane wave and ~k ′ for the scattered plane wave

r
−i~k·~
ρ b3 −bz/2
Ψk (r) = e ζ(z); ζ(z) = ze (A.3)
2

where
  1/3   1/3
12qm3 11 12qm3 21
b= |QB | + |Qn | = |Qs | − |Qn | (A.4)
~2 ǫS 32 ~2 ǫS 32

and m3 isthe mass normal to the plane of the interface. Qs = QB + Qn is the

semiconductor surface charge density, QB is the bulk charge density, and Qn is the

inversion layer charge density. These charge densities could be obtained by quantum

mechanical calculation, as previously described in Section 2.1.2. The matrix element

for the perturbed Hamiltonian is

Z
′ ′ ′
Hkk ′ = hk |H |ki = Ψ∗k′ H ′ Ψk d3~r. (A.5)

Since d3~r = dzd2 ρ~, d2 ρ~ = ρdρdθ, we then have

−q X ∆Qi
Z ZZ
′ ∗
Hkk ′ = dζ (z)ζ(z) d2 ρei~qs ·~ρ (A.6)
4πǭ i
|~r − ~ri |

where ~qs = ~k ′ − ~k and |~k ′ | = |~k| as shown in Figure A.2

119
 Figure A.2: Coulomb elastic scattering of a plane wave [78].

If we assume the effective scattering centers are randomly distributed in the x-y

plane, and take ρi = 0. For zi > 0 [53],

p
|~r − ~ri | = ρ2 + (z + zi )2 . (A.7)

Thus we can write

Z ∞  3
−q X b ei~qs ·~ρ
ZZ
′ 2 −bz
Hkk ′ = ∆Qi dz z e dθρdρ p
4πǭ i 0 2 ρ2 + (z + zi )2
∞ 2π ∞
b3 eiqs ρ cos θ
 
−q X
Z Z Z
= ∆Qi dz z 2 e−bz dθ ρdρ p (A.8)
4πǭ i 0 2 0 0 ρ2 + (z + zi )2
∞ ∞
b3
 
−q X ρdρ
Z Z
= ∆Qi dz z 2 e−bz 2π p J0 (qs ρ)
4πǭ i 0 2 0 ρ2 + (z + zi )2

where
2π
1
Z
J0 (qs ρ) = dθeiqs ρ cos θ (A.9)
2π 0

120
is the zero-order Bessel function. The integral
Z ∞
ρdρ e−qs (z+zi )
p J0 (qs ρ) = (A.10)
0 ρ2 + (z + zi )2 qs

is given as equation (6.554.1) in Gradshteyn and Ryzhik [79]’s book [78]. Thus we

have
Z ∞
−qb3 X e−qs(z+zi )
 
′ 2 −bz
Hkk ′ = ∆Qi dzz e 2π
8πǭ i 0 qs
∞
−qb3 X
Z
= ∆Qi e−qs zi dzz 2 e−(b+qs )z (A.11)
4ǭqs i 0

−q 1 X
= qs 3 ∆Qi e−qs zi
2ǭqs (1 + b ) i
and
 2
−q 1 X

[∆Qi ]2 e−2qs zi .

′ 2 
|Hkk′ | = qs 6 (A.12)
2ǭqs (1 + b ) i
We consider a 2-D random Poisson or Gaussian distribution of scattering centers in

the x-y plane, such that we may write [53]

[∆Qi ]2 = q 2 NI (zi )∆Vi


(A.13)

where ∆Vi is an elementary volume located at ri = (ρi , zi ). NI (z) is the effective

trap distribution in the SiO2 /HfO2 dielectric stack, where z is measured from the

Si-SiO2 interface and pointed to the gate electrode. Considering elastic scattering,

the transition probability is given by the Fermi Golden Rule [80],

2π
Wkk′ = |Hkk′ |2 δ(Ek′ − Ek ). (A.14)
~

The scattering rate

1 X
Γ(k) = = Wkk′ (1 − cos θ)
τ (k)
k′
 2
2 2π −q 1
ZZ
= k ′
dk ′
dθ (A.15)
(2π)2 ~ 2ǭqs (1 + qbs )6
Z ∞
× dzq 2 NI (z)e−2qs z (1 − cos θ)δ(Ek′ − Ek )
0

121
 md
By substituting k ′ dk ′ = ~2
dEk′ and qs = 2k sin θ/ 2 (from Figure A.2) into the above

expression, we can find a general expression for the reciprocal of the relaxation time
R∞ θ
1 q 4 md π
dzNI (z)e−4kz sin 2
Z Z
0
= 2 dEk′ δ(Ek′ − Ek ) dθ (A.16)
τ (k) 4ǭ π~ ~2 k 2 0 (1 + 2kb sin θ2 )6

where md is the density of state mass. If we define another variable ϕ = θ2 , and define

the averaged kinetic energy for the carriers located in the lowest subband E00 as
 EF n −E00

Ekin = kB T ln 1 + e kB T
, (A.17)

then the k vector is approximately

√
2mt kB T
kth = , (A.18)
~

the previous expression in Equation (A.16) becomes [53, 78]

2 Z R∞ √
π/2
q2 dzNI (z)e−4kth z ukin sin ϕ

1 1 0
= dϕ √ (A.19)
τ (E) 8π~Ekin ǭ 0 (1 + 2k3th z̄ ukin sin ϕ)6

where

Ekin
ukin = ; (A.20)
kB T
  −1/3
3 12qm3 21
z̄ = = 3 |Qs | − |Qn | (A.21)
b ~2 ǫS 32

and kB is the Boltzmann’s constant, T is the absolute temperature.

With screening considered [53, 80], the inverse of total relaxation time for remote

Coulomb scattering mobility can be written as

1
τC (E)
√
1

q2
2 Z π/2
R∞
dzNI (z)e−4kth z ukin sin ϕ (A.22)
0
= dϕ √
8π~Ekin ǭ 0 (1 + 2k3th z̄ ukin sin ϕ)6 (1 + 4kth kB Tq|Q√n
|
ǭ ukin sin ϕ
)2

q|Qn |
where the term (1 + √
4kth kB T ǭ ukin sin ϕ
)2 represents the screening effect.

122
 Since the inverse of the remote Coulomb scattering mobility can be written as

1 mC
= = αNT (A.23)
µC qτC (E)

2m1 m2
where mC is the conductivity mass and mC = m1 +m2
for 2DEG [81], m1 , m2 are the

effective mass in the plane. For the lowest subband E00 , this quantity equals the

transverse mass mt . If we approximate the film thickness z0 as ∞, the expression

presented in Section 2.1.3 is now derived as

R z0 √
π/2
4α0 dzNf (z)e−4kth z ukin sin ϕ
Z
0
αNT = 2 dϕ (A.24)
π 2kth z̄ √

6  eQn
0 ukin 1+ 3 ukin sin ϕ 1 + 4kth kB T ǭ√ukin sin ϕ

q 3 mt
where the constant α0 = 32~ǭ2 kB T
.

123
 Appendix B: Operation Details of Performing
Characterization in Our Lab

This appendix documents some of the characterization methods that are often

used in our lab. The equipment setups and the computer programs are developed

during the work for this dissertation. Although the theories behind the characteriza-

tion methods can be found in textbooks and journals, the details in actual experiments

can be confusing sometimes. This appendix will mainly serves as a reference for the

students and researchers who are interested in conducting these experiments in our

lab or constructing similar setups in their labs.

B.1 Designing the LabVIEW programs

National Instrument (NI) LabVIEW— system provides an environment for creat-

ing intuitive, graphically oriented programs for the automated control of laboratory

equipment. LabVIEW is build around the concept of the “Virtual Instrument”, or

VI. A VI can be thought as the software equivalent of a single piece of test equipment,

complete with an appropriately-designed “front panel” which provides the interface

for control. However, instead of representing any one physical instrument, a VI cor-

responds to a test procedure (or subprogram) [82].

124
B.1.1 Graphical Programming and User Interface

In LabVIEW, programming is accomplished in a graphical dataflow type of lan-

guage. Various VI’s are linked together by the transfer of data from one to the next

or within the context of various programming structures.

The power of this test oriented platform is strengthened by the availability of

instrument driver libraries, provided by the instrument suppliers, NI technical support

or user themselves. The drivers are themselves VI’s which handle the control of the

various laboratory test sets over the IEEE-488 or GPIB bus, or even RS232 in some

cases. The user only needs to include the appropriate driver VI in the program

wherever an action is needed from a piece of equipment. These drivers can be easily

shared and reused over the LabVIEW platform.

The front panel provides a new approach to interactive user control. In a well

designed panel, all of the measurement parameters can be varied by manipulating

the graphical equivalent of buttons and switches with the computer mouse or input

from the keyboard. Because it resembles the face of a test instrument or set, the front

panel is more intuitive to use, especially for the new user. Another attractive feature

is that the front panel serves to document the experiment: it displays the measured

results as well as a record of all of the input parameters on one screen.

B.2 Device Characterization Setup and Operation

Figure B.1 shows the probe system used in our lab. The probe station holds the

wafer and probes the devices, and it is housed inside a Faraday cage which provides

shielding from outside interferences. The probers are connected to the equipment

through the bulkhead connectors which are fixed in the wall of the Faraday cage.

125
 Figure B.1: Picture of the SemiProbe® probe station and measurement setup.

B.2.1 Setup and Operation of IV Measurement

The most straightforward method to parameterize the operation of any electrical

device is to measure its DC operating characteristics. For a MOSFET, common DC

measurement include transfer characteristics and output characteristics.

Equipment and Connectivity

The setup is composed of the HP4145A Semiconductor Parameter Analyzer and

the computer program (as in Figure B.2). The IV measurement procedure is fairly

standard. Because the HP4145A is very flexible in the definition of the measurement

channels, connection to the device under test (DUT) is arbitrary.

126
 Figure B.2: Equipment setup for the I-V measurement with HP4145A.

Transfer Characteristics

The MOSFET transfer characteristics, i.e., IDS - VGS characteristics are measured

at low drain bias voltages (VDS typically at 50 mV). A measurement consists of fixing

bulk to source and drain to source potentials and sweeping the gate terminal voltage

while monitoring the drain current. From the measured low drain characteristics, the

threshold voltage, transcendence and mobility information maybe determined.

Software Functionality The IdVgVb VI (Figure B.3) allows the user to take a fam-

ily of ID vs. VG curves over a range of substrate biases. The measurement software

instructs the 4145 to take one ID vs. VG curve at a time and downloads the data to

the PC for logging and interpretation. The transconductance is calculated by the

127
Figure B.3: The IDS -VGS characterization front panel for LabVIEW. Gate sweeps are
made for a range bulk biases. Transconductance curves are calculated and displayed.

software, gm = dIDS /dVGS , and displayed for each sweep taken. After the measure-

ment is completed, the program will ask the user whether or not the result should

be saved, if yes, the program will create a text file at the specified location.

Procedure

1. Probe and connect the electrode (G/S/D/B) and the SMUs accordingly.

2. Select the right SMU assignment in the LabVIEW— program, and set up the

biasing conditions.

128
 3. Start measuring and save the data.

Measurement Setup The front panel for this measurement allows the user to spec-

ify the corresponding SMU for each terminal. Item B.2.1 lists the required inputs

for making the measurement.

Control Name Purpose Typical Value

Gate Voltage Sweep applied gate bias depends on device
Bulk Voltage Sweep applied body bias NMOS 0 e -1 , PMOS 0 e 1
Channel Definition SMU assignment of HP4145A select accordingly
Drain Voltage drain bias NMOS 50, PMOS -50

Table B.1: Front panel control definitions for the ID -VG program.

Data Output Data is saved in ASCII to a file specified by the user upon completion

of the measurement. A header is first saved to the file, which gives the measurement

type and selected conditions. The remainder of the data is in row-colunmn format

with column one containing gate voltages, with the next adjacent N columns con-

taining the IDS measured for each of the N sweeps, and the last columns containing

the transconductance data.

Output Characteristics

The output characteristics, IDS - VDS is another measurement carried out in our

LabVIEW environment. The IdVdVg VI (Figure B.4) allows the user to take a family

of ID vs. VD curves over a range of VG biases. Figure B.2.1 lists the required inputs

for making the measurement.

129
Figure B.4: The IDS -VDS characterization front panel for LabVIEW. Drain sweeps
are made for a range gate biases. The displayed plot is an example of the output
characteristics of a MOSFET device.

Control Name Purpose Typical Value

Drain Voltage Sweep drain biasing conditions depends
Gate Voltage Sweep gate biasing conditions depends
Channel Definition SMU assignment of HP4145A select accordingly

Table B.2: Front panel control definitions for the ID -VD program.

130
B.2.2 Setup and Operation of Capacitance Voltage (C-V)
Measurement
Equipment and Connectivity

The setup contains the HP4192A LF Impedance Analyzer and the computer pro-

gram. Before measuring, first one needs to make sure what configuration and condi-

tions are best suited for the purpose. Typically speaking, for a MOS structure, one

can measure the capacitance and conductance between the gate and the source/drain,

the gate and the substrate, or the gate between source/drain/substrate tied together.

Consider, for example, the Cgb (gate and the substrate) as an example. Con-

nect the gate and substrate terminal to the “ HIGH” and “LOW” terminals of the

“UNKOWN” terminals respectively, with HIGH CUR connected to HIGH POT and

LOW CUR with LOW POT. At the same time, the source/drain terminals, if avail-

able, should be connected to the GROUND of the impedance analyzer. An important

consideration is that the outer shield of the UNKOWN terminals should not be con-

nected to the GROUND, in other words, the virtual ground of the unknown terminals

should be isolated from the chassis ground of the equipment. The gate terminal can

also be connected to the “LOW” terminals, which might be a better configuration if

the stray capacitance is large between the substrate and the chuck.

After connecting the cables, one should set the right frequency and oscillation level

through the front panel of HP4192A, as well as the circuit model (parallel/series/auto),

and then perform calibration (open and short, especially open) before measurement.

After the calibration, probe the device properly and then use the program to control

the measurement.

131
 The program is written using state variable machine methods, including setups

for N and P MOS measurements, up or down sweeping, bias on gate or not. The

program also sets the average mode to be on of the equipment. One has to select the

right setting in the program before starting the measurement.

An important detail specifically concerning the setup in our lab is the connectors.

When the GROUND terminal is used, one need to isolated it from the UNKNOWN

terminals. The UNKNOWN terminals of HP4192A are coaxial connectors, of which

the outer shields need to be isolated from the chassis ground. For our probing and

shielding system, the probe tips are connected to the equipments through the bulk

head connectors mounted on the wall the shielding box, and the outer shield of these

bulk head connector are shorted through the metal box. Thus when connecting the

unknown terminals to the DUT, one needs to use coaxial-to-triaxial adapters, for

which, in particular, the coaxial shield is connected to the triaxial ground with the

triaxial shield isolated from them. It’s important to use such adapters for the high

and low terminals, in order to obtain valid measurement results.

Software Functionality

Procedure

1. Connect the “HIGH” and “LOW” terminals of HP 4192A to the device accord-

ingly.

2. Select the right SMU assignment in the LabVIEW— program, and set up the

biasing conditions.

3. Start measuring and save the data.

132
 Figure B.5: Equipment setup for the CV measurement with HP4192A.

Measurement Setup The front panel for this measurement allows the user to spec-

ify the measurement conditions. item B.2.2 lists the required inputs when measuring

Data Output Data is saved in ASCII to a file specified by the user upon completion

of the measurement. A header is first save to the file which gives the measurement

type and selected conditions. The remainder of the data is in row-colunmn for-

mat with column one containing gate voltages, then second columns containing the

measured capacitance componentCm , and the last column containing the measured

conductance component Gm .

133
Figure B.6: The CG -VG characterization front panel for LabVIEW. The top tracer
shows the measured capacitance-voltage characteristics, the bottom tracer shows the
measured conductance-voltage characteristics.

Control Name Purpose Typical Value

Bias Sweep biasing conditions depends
Spot Frequency applied frequency 1 MHz
osc level (mV) small signal level 30
wait time (s) time between applying bias 3
and taking measurement
auto sweep sweeping direction either way
Bias on electrode connected to the HIGH terminal select accordingly

Table B.3: Front panel control definitions for the CG -VG program.

134
B.3 Setup and Operation of Leakage and Stress Induced Leak-
age Current (SILC) Measurement

The setup is composed of the HP4145A Semiconductor Parameter Analyzer and

the computer program. Note here that the HP4145A does not come with stress op-

tions, it is the computer programming that enables the kind of measurement which

only comes with much more expensive equipments. And the programming imple-

mentation gives a great deal of flexibility and convenience. The general steps are

described as below:

1. Probe and connect the electrode (G/S/D/B) and the designated SMUs accord-

ingly. Two SMUs are used for the leakage measurement.

2. Select the right SMU assignment in the LabVIEW— program, and set up the

biasing conditions.

3. Setup the stressing conditions for SILC measurement, e.g., stress time, sampling

interval etc. Or leave them blank for single leakage sweep.

4. Start measuring and save the data.

The program (SILC) is written using state variable machine methods. This scheme

is especially useful here since it enables flexible hopping between the stressing frame

and the sweeping frame. A global counter is implemented to decide whether or not

all the stressing time lengths have been applied, if not, the program will go on to the

next stress cycle after the sweep, if yes, the program will go to the finishing frames.

With this kind of programming design, one can apply different stress cycles to the

device and measure the induced leakage after each cycle, at the same time, the leakage

current is monitored on the fly during the stressing cycle.

135
Figure B.7: The stress and IV sweep front panel for LabVIEW. The left trace shows
the swept ID versus VG at the intitial sweep and after each stressing cycle, the right
trace shows the injecting current (which is measured at the gate) versus time.

B.4 Setup and Operation of Stress IV Measurement

Based on the same setup as the IV measurement, we can also measure the stressed-

IV characteristics for the changes of transfer characteristics under the impact of dif-

ferent constant voltage stress conditions. The setup of parameters are similar to the

SILC program described above, with the only difference is the SMU assignment. The

front panel is shown below in Figure B.7.

136
B.4.1 Setup and Operation of Charge Pumping Measure-
ment

Charge pumping is a measurement technique for the characterization of interface

traps [67, 83] which can also be extended to near interface oxide traps [84] in a MOS-

FET. The technique was first introduced by Brugler and Jespers [83] in its simplest

form, Bi-Level Charge Pumping, as a means for determining interface trap densities.

The technique gained increased acceptance after improved analysis was accomplished

by Groeseneken et al. [67].

A VI has been developed for bi-level charge pumping measurements for both base

sweep and amplitude sweep configurations. Both NMOS and PMOS transistors can

be measured.

Equipment and Connectivity

The setup in our lab is composed of HP-33120A Waveform Generator and HP-

4145A Semiconductor Parameter Analyzer, the connection is shown in Figure B.8.

The HP-33120A stimulates the current-mode measurements, while HP-4145A’s SMUs

are employed to measure the charge pumping currents.

Amplitude Level Sweep

Amplitude sweep configuration in charge pumping measurement is the procedure

where the base level of the gate pulse is fixed (usually below VF B ), but the amplitude

of the pulse is changed while the charge pumping current is monitored. This technique

is useful for determining the best pulse amplitude to use in the other configuration

– base sweep. If the amplitude of the pulse is too small to span the VF B − VT H

range, there will be little or no charge pumped. As the amplitude is increased, the

137
Figure B.8: Equipment setup for the charge pumping with HP33120A and HP4145A.

charge pumped will suddenly rise when the pulse spans the flatband-to-threshold

range. Generally, on uniformly fabricated transistors, the characteristics will exhibit

saturation when the sum of pulse amplitude and pulse base is above the threshold

level. The results of this technique are most meaningful if the gate pulse base level

voltage is chosen to be slightly below VF B for NMOS (above for a PMOS device). An

amplitude somewhat above the saturation point is generally chosen for subsequent

base varying cahrge pumping measurements on the same transistor. With the above

being said, sometimes, the optimal amplitude can be estimated from the transistors

I-V characteristics based on VF B and VT H .

Software Functionality The software performs the amplitude sweep charge pump-

ing measurement according to the parameters specified. Data is plotted and inter-

pretation is left to the user.

138
Figure B.9: The variable amplitude charge pumping characterization front panel
for LabVIEW. The trace shows the measured charge pumping current versus the
amplitude level of the applied waveform.

139
Procedure The procedure is similar to the base sweep configuration as described

previously.

Measurement Setup The setup for parameters is listed in Figure B.4.1. Note that

when varying base, one must follow the restrictions for the amplitude and offset

values of the pulse generator, in this case, Agilent 33120A in which the absolute

value of the offset voltage (middle point of the base and the peak) should be less

than 2 times of the peak-to-peak amplitude (in our case, the amplitude specification

itself).

Control Name Purpose Typical Value

S/D SMU connected to S/D select accordingly
SUBSTRATE SMU connected to bulk select accordingly
Amp Sweep applied amplitude levels 0.6e2
Fixed Base base level smaller than VF B
# of Samples number of samples taken 6
Monitor where the current is measured SUB
Waveform Function waveform shape triangle/square
Frequency waveform frequency 1 MHz
High Z output condition High Z for MOSFET
Vr reversed bias on S/D very small or 0

Table B.4: Front panel control definitions for the CPamp program.

Data Output Data is saved in ASCII to a file specified by the user upon completion

of the measurement. The file contains a header and two column data. The header

gives the measurement type and selected conditions. Data column one is the pulse

amplitude and column two is the measured charge pumping current.

140
Base Level Sweep

A base level sweep is the process of ramping the base level voltage of the gate pulse

while monitoring the charge pumping current. This technique allows the investigator

to separate the charge pumping current from any constant current offsets. Charge

pumping will only occur if the gate pulse spans the VF B − VT H range. For an NMOS

transistor, this requirement becomes

VT H − ∆VG < Vbase < VF B . (B.1)

Differencing the peak and background levels of Qcp (Vbase ) provides a stable means

for determining the charge pumped per cycle. For this value, the average density of

interface traps may be extracted.

    −1
√
 VT H − VF B  p
Dit = QCP 2kB T qAG ln υth ni σn σp + ln 

 tr tf
 (B.2)
∆VG

For devices with thin-dielectrics, sometime the gate leakage is fairly large and it is

mixed [74, 75]

Functionality

Prodecure 1. Make sure the chassis of HP33120A and HP4145A are shorted.

This can be achieved by clip the outer shield of the connectors of these two

equipments.

2. Probe and make connections accordingly: the Gate electrode is connected to

the function generator, the Substrate is connected to one SMU channel, and

the Source and Drain electrodes are connected together to another SMU, as

seen in Figure B.8.

141
Figure B.10: The variable base charge pumping characterization front panel for Lab-
VIEW. The trace shows the measured charge pumping current versus the base level
of the applied waveform.

142
 3. Select the designated SMU in the program accordingly and set up the mea-

surement conditions: 1) pulse train shape, height, base range and frequency; 2)

whether the charge pumping current is monitored at the substrate or source/drain;

3) sample size; 4) delay time between the onset of each base setting and current

monitoring.

4. Start measuring and save the data.

Control Name Purpose Typical Value

S/D SMU connected to S/D select accordingly
SUBSTRATE SMU connected to bulk select accordingly
# of Samples number of samples taken 6
Vr reversed bias on S/D very small or 0
Monitor where the current is measured SUB
Waveform Function waveform shape triangle/square
Frequency waveform frequency 1 MHz
Pulse Height pulse amplitude 1.1e1.5

Table B.5: Front panel control definitions for the CPbase program.

Measurement Setup

Data Output Data is saved in ASCII to a file specified by the user upon completion

of the measurement. The file contains a header and two column data. The header

gives the measurement type and selected conditions. Data column one is the pulse

base levels and column two is the measured charge pumping current.

B.4.2 Setup and Operation of Noise Measurement

The description of noise measurment setup can be found in Section 3.5. The

computer program is shown below. Just make sure for the two SR570 at the rear panel,

143
their AMP GND connectors should be tied tegether, the same applies to the chassis

connector. The setup of the equipment can be found Figure 3.22 in Section 3.5.

The front panel of the LabVIEW program is shown in Figure B.11. The only input

needed is the gate voltage sweep range. Data is save in ASCII to a file specified

by the user upon completion of the measurement. A header is first saved which

gives the measurement type and selected conditions. The remainder of the data is

in row-column format with column one containing the frequencies, the next columns

containing the power spectral density (PSD) measured for each gate biasing condition.

144
Figure B.11: The noise PSD spectrum versus bias front panel for LAbVIEW. The
trace includes the measured PSD at the applied gate voltage range. The box labelled
“Current Bias” is the current applied gate bias at the moment as a reference during
the measurement. Note, the spikes in the plots are mainly due to the 60 Hz from the
wall socket power supply, which is one of the reasons that make shielding extremely
important in noise measurement.

145
 Appendix C: Code

This appendix documents the MATLAB programs written for the work presented
in Chapter 2, to model and simulate the 1/f noise in a nanoscaled NMOS transistor
with ultra thin composite high-K dielectric layer.

1 % LFNoiseMain HK.m: main program for low frequency noise modeling ...
for HK
2 % (IMEC) sample;
3 % %
4 % call functions: funcFeff.m;
5 % intphiaHK,m;
6 % intphiaHK1.m;
7 % intphiaHK2,m;
8 % intphib.m;
9 %
10 % need to check the constant list for kox (to SiO2 = 3.9);
11

12 % Originally Created by Xiaochen (Deedee) Zhang, Aug 2011;

13 % Modified by Xiaochen (Deedee) Zhang, Apr 2012, for SSE resubmission;
14 % include alpha if w/o charge centroid;
15 % include alpha if w/o screening;
16 %==========================================================================
17 %% Setup
18 clear;
19

20 load constants;
21

22 global eta; % parameter infront of Ninv in Eeff

23 eta = 11/32;
24

25 %==========================================================================
26 %% Subband Part
27 % Define Variable
28
29 Na = 8.9e17*1e6; % substrate doping, 1/mˆ3
30 phiF = kBT/q*log(Na/ni); % Fermi level at the bulk, Volt
31
32 Ceff = 3.51e−6*1e4; % measured effective gate capacitance, F/mˆ2
33 xf = 16e−10; % HfO2 thickness, m

146
34 xox = 5e−10; % SiO2 interfacial layer thickness, m
35

36 Vfb = −0.38; % flatband voltage, Volt

37
38 phiS = 1.15:0.01:1.4; % surface potential, Volt
39 NN = length(phiS); % length of array phiS
40

41 Fs0 = zeros(1,NN); % surface field in tri−angular initiation, V/m

42 Fs = zeros(1,NN); % surface field after variational adjustment, V/m
43 FSH = zeros(1,NN); % Stern−Howard Field, V/m
44 Feff = zeros(1,NN); % Scattering effective Field, V/m
45 Ninv = zeros(1,NN); % inversion carrier density, 1/mˆ3
46 E00 = zeros(1,NN); % energy level, i=0, j=0, J
47 E01 = zeros(1,NN); % energy level, i=0, j=1, J
48 E10 = zeros(1,NN); % energy level, i=1, j=0, J
49 N00 = zeros(1,NN); % carrier density at E00
50 N01 = zeros(1,NN); % carrier density at E01
51 N10 = zeros(1,NN); % carrier density at E10
52 phid = zeros(1,NN);
53 Ndep = zeros(1,NN); % depletion charge density
54 Efn = zeros(1,NN); % Fermi level at the surface referred to Ec
55 z00 = zeros(1,NN);
56 z01 = zeros(1,NN);
57 z10 = zeros(1,NN);
58 zav = zeros(1,NN); % average seperation of charge away from the ...
interface
59 Eav = zeros(1,NN); % effective weighted subband
60 Vgs = zeros(1,NN); % gate to source voltage
61 %==========================================================================
62 % Construct Subbands
63 eta = 1; % define the field as the Fs w/ eta=1
64 % in trianglar well approximation;
65 for i = 1:NN % Find the self−consistent effective field
66 % by bi−section method
67 EFn = q*phiS(i)−EG/2−q*phiF;
68 Fs1 = 1e3*1e2;
69 Fs2 = Fs1*1e4;
70 err rel = 1/1E3;
71 err = Fs1*err rel;
72 Fsr = Fs1;
73 icounter = 0;
74 maxicounter = 100;
75

76 while (abs(funcFeff(Fsr, EFn, phiS(i), Na))) > err

77 icounter = icounter + 1;
78 Fsr = (Fs1+Fs2)/2;
79 if (funcFeff(Fsr, EFn, phiS(i), Na)*funcFeff(Fs2, EFn, ...
phiS(i), Na)<0)
80 Fs1=Fsr;
81 else
82 Fs2=Fsr;

147
83 end
84 err = Fsr*err rel;
85 if icounter > maxicounter break
86 end
87 end
88
89 % Store all the results in vectors
90 Efn(i) = EFn;
91 Fs0(i) = Fsr;
92 E00(i) = (hbarˆ2/2/m03)ˆ(1/3)*(3/2*pi*q*Fsr*3/4)ˆ(2/3);
93 E01(i) = (hbarˆ2/2/m03)ˆ(1/3)*(3/2*pi*q*Fsr*(1+3/4))ˆ(2/3);
94 E10(i) = (hbarˆ2/2/m13)ˆ(1/3)*(3/2*pi*q*Fsr*3/4)ˆ(2/3);
95 N00(i) = nv0*md0*kBT/pi/hbarˆ2*log(1+exp((EFn−E00(i))/kBT));
96 N01(i) = nv0*md0*kBT/pi/hbarˆ2*log(1+exp((EFn−E01(i))/kBT));
97 N10(i) = nv1*md1*kBT/pi/hbarˆ2*log(1+exp((EFn−E10(i))/kBT));
98 Ninv(i) = N00(i)+N01(i)+N10(i);
99 z00(i) = 2*E00(i)/3/q/Fsr;
100 z01(i) = 2*E01(i)/3/q/Fsr;
101 z10(i) = 2*E10(i)/3/q/Fsr;
102 zav(i) = (N00(i)*z00(i)+N01(i)*z01(i)+N10(i)*z10(i))/Ninv(i);
103 phid(i) = phiS(i) − kBT/q − q*Ninv(i)*zav(i)/eps0/ks;
104 Ndep(i) = sqrt(2*eps0*ks*phid(i)*Na/q);
105 Eav(i) = (E00(i)*N00(i)+E01(i)*N01(i)+E10(i)*N10(i))/Ninv(i);
106 Vgs(i) = Vfb+phiS(i) + q*(Ninv(i)+Ndep(i))/Ceff;
107 end
108

109 %save ...

('triangle','phiS','NN','Efn','Feff','E00','E01','E10','N00','N01','N10','Ninv',.
110 %'z00','z01','z10','zav','phid','Ndep','Eav','Vgs');
111
112 %==========================================================================
113 %% Variational Adjustment
114 % based on the results of triangular well approximation, using ...
variational
115 % method to adjusty the subband structures by self−consistent
116 eta = 11/32; % define the Stern−Howard Field FSH w/ eta=11/32;
117 iteration = zeros(1,NN);
118
119 for i=1:NN
120 for j = 1:maxicounter
121 iteration(i) = j;
122 z00bar = ...
(9*eps0*ks*hbarˆ2/4/m03/qˆ2/(Ndep(i)+11/32*Ninv(i)))ˆ(1/3);
123 z00∆ = 4*Na*z00barˆ2/9/(Ndep(i)+11/32*Ninv(i));
124 z00(i) = z00bar+z00∆;
125 E00bar = (3/2)ˆ(5/3)*(qˆ2*hbar/sqrt(m03)/eps0/ks)ˆ(2/3)...
126 *(Ndep(i)+55/96*Ninv(i))*(Ndep(i)+11/32*Ninv(i))ˆ(−1/3);
127 E00∆ = −[2*Na*qˆ2*z00barˆ2/3/eps0/ks/(Ndep(i)+11/32*Ninv(i))]...
128 *(Ndep(i)+11/96*Ninv(i));
129 E00(i) = E00bar+E00∆;
130

148
131 Fdep = q*Ndep(i)/eps0/ks;
132 Finv = q*Ninv(i)/eps0/ks;
133

134 E01d = (hbarˆ2/2/m03)ˆ(1/3)*(3/2*pi*q*Fdep*(1+3/4))ˆ(2/3);

135 E10d = (hbarˆ2/2/m13)ˆ(1/3)*(3/2*pi*q*Fdep*(0+3/4))ˆ(2/3);
136
137 zd = sqrt(2*eps0*ks*phid(i)/q/Na);
138 E01(i) = E01d−qˆ2*Fdep*Finv*zav(i)ˆ2/4/E01d...
139 −4*E01dˆ2/15/q/Fdep/zd+q*Finv*zav(i);
140 E10(i) = E10d−qˆ2*Fdep*Finv*zav(i)ˆ2/4/E10d...
141 −4*E10dˆ2/15/q/Fdep/zd+q*Finv*zav(i);
142
143 N00(i) = nv0*md0*kBT/pi/hbarˆ2*log(1+exp((Efn(i)−E00(i))/kBT));
144 N01(i) = nv0*md0*kBT/pi/hbarˆ2*log(1+exp((Efn(i)−E01(i))/kBT));
145 N10(i) = nv1*md1*kBT/pi/hbarˆ2*log(1+exp((Efn(i)−E10(i))/kBT));
146 Ninvnew = N00(i) + N01(i) + N10(i);
147
148 z00bar = ...
(9*eps0*ks*hbarˆ2/4/m03/qˆ2/(Ndep(i)+11/32*Ninvnew))ˆ(1/3);
149 z00∆ = 4*Na*z00barˆ2/9/(Ndep(i)+11/32*Ninvnew);
150 z00(i) = z00bar+z00∆;
151 Feff(i) = q*(Ndep(i)+eta*Ninvnew)/eps0/ks;
152 z01(i) = 2*E01(i)/3/q/Feff(i);
153 z10(i) = 2*E10(i)/3/q/Feff(i);
154 zav(i) = (N00(i)*z00(i)+N01(i)*z01(i)+N10(i)*z10(i))/Ninvnew;
155 phid(i) = phiS(i) − kBT/q − q*Ninvnew*zav(i)/eps0/ks;
156

157 Ndepnew = sqrt(2*eps0*ks*phid(i)*Na/q);

158

159 rerrNinv = (Ninvnew−Ninv(i))/Ninv(i);

160 rerrNdep = (Ndepnew−Ndep(i))/Ndep(i);
161

162 Ninv(i) = (Ninv(i)+Ninvnew)/2;

163 Ndep(i) = (Ndep(i)+Ndepnew)/2;
164

165 if abs(rerrNinv)<err rel && abs(rerrNdep)<err rel break

166 end
167 end
168

169 Eav(i) = (E00(i)*N00(i)+E01(i)*N01(i)+E10(i)*N10(i))/Ninv(i);

170 Vgs(i) = Vfb+phiS(i) + q*(Ninv(i)+Ndep(i))/Ceff;
171 Fs(i) = (Ndep(i)+Ninv(i))*q/eps0/ks;
172 FSH(i) = (Ndep(i)+11/32*Ninv(i))*q/eps0/ks;
173 Feff(i) = (Ndep(i)+1/2*Ninv(i))*q/eps0/ks;
174 end
175 disp('Var Done');
176 % save ...
('variational','phiS','Feff','E00','E01','E10','N00','N01','N10','Ninv',...
177 % 'z00','z01','z10','zav','phid','Ndep','Eav','Vgs');
178 %==========================================================================
179 %% Mobility Part −− w/ only the first level E00;

149
180 % Define Variables
181 a0 = 2/3*sqrt(2*md0*kBT)/hbar; % ai, i = 0
182 epsbar = eps0*(kox+ks)/2; % average epsilon
183 mc0 = mt; % conductivity mass, i = 0
184 alpha0 = qˆ3*mc0/32/hbar/epsbarˆ2/kBT; % alphai, i = 0
185 D00 = nv0*(0+1)*md0/pi/hbarˆ2; % DOS
186 mu0 = (88+1250/(1+Na/(1.26e17*1e6)*0.88))*1e−4; % in mˆ2/V−sec
187 kth = sqrt(2*mt*kBT)/hbar; % thermal k−vector
188 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
189 % Fitting Parameters %
190 Nteff = 4e10*1e4; % effective trap density, 1/mˆ2 %
191 Lc = 20e−10; % correlation length %
192 ∆ = 3e−10; % roughness rms value %
193 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
194 alpha = zeros(1,NN);
195 alpha1 = zeros(1,NN);
196 alpha2 = zeros(1,NN);
197 beta = zeros(1,NN);
198 mu = zeros(1,NN);
199 muc = zeros(1,NN);
200 muSR = zeros(1,NN);
201 Isd = zeros(1,NN);
202 xbar = zeros(1,NN);
203 Ekin = zeros(1,NN);
204 ukin = zeros(1,NN);
205 fa = zeros(1,NN);
206 fa1 = zeros(1,NN);
207 fa2 = zeros(1,NN);
208 fb = zeros(1,NN);
209 cbalpha = zeros(1,NN); % screened scattering parameter in C−B's paper
210

211 for i=1:NN

212 Ekin(i) = kBT*log(1+exp(((Efn(i)−E00(i))/kBT)));
213 ukin(i) = Ekin(i)/kBT;
214 b0 = (12*qˆ2*m03/hbarˆ2/eps0/ks*(Ndep(i) + 11/32*Ninv(i)))ˆ(1/3);
215 xbar(i) = 3/b0;
216

217 % calculate the integral for alpha

218 fa(i) = 1/pi/xf/kth/(ukin(i)ˆ(3/2))...
219 *quad(@(phi)intphiaHK(phi,kth,xox,xf,ukin(i),xbar(i),Ninv(i)),0,pi/2);
220
221 alpha(i) = alpha0*fa(i);
222 % calculate the integral for alpha1, w/o charge centroid
223 fa1(i) = 1/pi/xf/kth/(ukin(i)ˆ(3/2))...
224 *quad(@(phi)intphiaHK1(phi,kth,xox,xf,ukin(i),xbar(i),Ninv(i)),0,pi/2);
225 alpha1(i) = alpha0*fa1(i);
226

227 % calculate the integral for alpha2, w/o screening

228 fa2(i) = 1/pi/xf/kth/(ukin(i)ˆ(3/2))...
229 *quad(@(phi)intphiaHK2(phi,kth,xox,xf,ukin(i),xbar(i),Ninv(i)),0,pi/2);
230 alpha2(i) = alpha0*fa2(i);

150
231
232 % calculate the integral for beta
233 fb(i) = ...
quad(@(phi)intphib(phi,mt,kth,ukin(i),Lc,xbar(i),Ninv(i)),0,pi/2);
234 beta(i) = 9*∆ˆ2*qˆ2*sqrt(mt)/Lc/(2*kBT)ˆ(3/2)/eps0/ks...
235 *FSH(i)ˆ2/Feff(i)*fb(i);
236

237 muc(i) = 1/(alpha(i)*Nteff);

238 muSR(i) = 1/(beta(i)*(Ninv(i)+2*Ndep(i)));
239

240 mu(i)=1/(1/mu0 + 1/muc(i) +1/muSR(i));

241 end
242

243 muc0 = 0.4e10*1e−2; %muc0 in C−B's paper, in m/V/sec, under 300K

244 for i = 1:NN
245 cbalpha(i) = 1/muc0/sqrt(Ninv(i));
246 end
247

248 % plot out alpha and beta versus Vgs;

249 figure;
250 semilogy(Vgs, alpha, Vgs, beta);
251 legend('\alpha','\beta');
252

253 unNinv = [0.6e12*1e4 0.84e12*1e4 1.08e12*1e4 1.32e12*1e4 1.56e12*1e4 ...

1.8e12*1e4];
254 unalpha = [7.6e−15 7.2e−15 6.6e−15 5.5e−15 5.48e−15 4.4e−15];
255 figure;
256 semilogy(Ninv, alpha, Ninv, alpha1, Ninv, alpha2, Ninv, ...
alpha0.*ones(1,length(Vgs))...
257 ,unNinv, unalpha,'+',Ninv, cbalpha, 'd',Ninv, alpha+beta,'*');
258 legend('\alpha','w/o centroid','w/o ...
screening','\alpha 0','unalpha','cbalpha','\alpha + \beta');
259 %==========================================================================
260 %==========================================================================
261 %% Calculate current and plot
262 W = 100*1e−6; % width, in m
263 L = 10*1e−6; % length, in m
264 Vd = 0.05;
265 Rsd = 150;
266 for i = 1:NN
267 Isd(i) = Vd/(Rsd+1/(W/L*mu(i)*q*Ninv(i)));
268 end
269 load imecIsVgexp;
270 % plot the simulated Isd−Vgs curve versus the experiments Is−Vg;
271 % simulation are diamonds, experiments are the solid line;
272 figure;
273 cycle=[1:length(Vgsexp)];
274 plot(Vgs, Isd, Vgsexp(cycle), Isexp(cycle),'d');
275 %==========================================================================
276 %==========================================================================
277 %% Calculate LF Noise and plot

151
278 load imecSIdexp;
279 rhot = zeros(1,NN);
280

281 rhot0 =1e19*1e6; % traps/mˆ3−eV;

282 rhotc = 3e18*1e6;
283 zeta = 0.108;
284 phiB = 1.6*q;
285 mf = 0.18*me;
286 Ei = −EG/2; % intrinsic energy level, respect to Ec
287 freq = 4;
288 lambda = zeros(1,NN);
289 normalSId = zeros(1,NN);
290 AA = zeros(1,NN);
291
292 for i = 1:NN
293

294 rhot(i) = rhot0+rhotc*exp(−(0−Efn(i))/q/zeta);

295 lambda(i)=2/hbar*sqrt(2*mf*(phiB−Eav(i)));
296 % tunneling parameter, in 1/m;
297 normalSId(i) = (kBT/q)/lambda(i)/W/L/freq...
298 *(1/Ninv(i)+(alpha(i)+beta(i))*mu(i))ˆ2*rhot(i);
299 SId(i) = normalSId(i)*Isd(i)ˆ2;
300 %kBT/q counts for rhot is in per eV
301 end
302 %
303 normalSIdexp = zeros(1,length(SIdexp));
304 for i=1:length(SIdexp)
305 normalSIdexp(i) = SIdexp(i)/Idnoise(i)ˆ2;
306 end
307 cycle = 1:NN;
308 figure;
309 semilogy(Vgs(cycle),SId(cycle),Vgnoise,SIdexp,'o');
310 legend('Simulation','Experiment');

1 % function solveFeff.m
2 % function used to solve for Effective/Surface Field in iteration
3 %==========================================================
4
5 % Originally Created by Xiaochen (Deedee) Zhang, Aug 2011
6

7
8

9 function finv = funcFeff(Feff, EFn, phis, Na)

10 load constants;
11 global eta;
12
13 E00 = (hbarˆ2/2/m03)ˆ(1/3)*(3/2*pi*q*Feff*3/4)ˆ(2/3);
14 E01 = (hbarˆ2/2/m03)ˆ(1/3)*(3/2*pi*q*Feff*(1+3/4))ˆ(2/3);
15 E10 = (hbarˆ2/2/m13)ˆ(1/3)*(3/2*pi*q*Feff*3/4)ˆ(2/3);
16 N00 = nv0*md0*kBT/pi/hbarˆ2*log(1+exp((EFn−E00)/kBT));

152
17 N01 = nv0*md0*kBT/pi/hbarˆ2*log(1+exp((EFn−E01)/kBT));
18 N10 = nv1*md1*kBT/pi/hbarˆ2*log(1+exp((EFn−E10)/kBT));
19 Ninv = N00 + N01 + N10;
20
21 z00 = 2*E00/3/q/Feff;
22 z01 = 2*E01/3/q/Feff;
23 z10 = 2*E10/3/q/Feff;
24 zav = (N00*z00+N01*z01+N10*z10)/Ninv;
25
26 phid = phis − kBT/q − q*Ninv*zav/eps0/ks;
27 Ndep = sqrt(2*eps0*ks*phid*Na/q);
28
29 Feffnew = q*(Ndep + eta*Ninv)/eps0/ks;
30
31 finv = Feff − Feffnew;

1 % intphiaHK: function to calculate fa(xox, xf, ukin, Qb, Qn) for alpha
2 function intphiaHK = intphiaHK(phi,kth,xox,xf,ukin,xbar,Ninv)
3 load constants;
4
5 epsbar = eps0*(kox+ks)/2;
6 top = exp(−4*kth*sqrt(ukin)*xox.*sin(phi))...
7 .*(1 − exp(−4*kth*xf*sqrt(ukin).*sin(phi)));
8 bottom = sin(phi).*(1 + 2/3*kth*xbar*sqrt(ukin).*sin(phi)).ˆ6....
9 .*(1 + qˆ2*Ninv/4/kth/kBT/epsbar/sqrt(ukin)./sin(phi)).ˆ2;
10 intphiaHK = top./bottom;

1 % intphib: function to calculate fb(ukin, Qn, Qb) for beta

2 function intphib = intphib(phi,mt,kth,ukin,Lc,xbari,Ninv)
3
4 load constants;
5

6 epsbar = eps0*(kox+ks)/2;
7

8 top = sin(phi).ˆ2;
9 bottom = ((1/kthˆ2/Lcˆ2+2*ukin*(sin(phi).ˆ2)).ˆ(3/2))...
10 .*(1 + 2/3*kth*xbari*sqrt(ukin).*sin(phi)).ˆ6;
11 intphib = top./bottom;

153