Introducing Embedded Systems

and the Microcontrollers

Chapter One

1
 Outline
• Definition of Embedded Systems
• Examples
• Computer Essentials
• Microprocessors and Microcontrollers
• PIC Microcontrollers
• 12 Series PIC

2
 Definition of Embedded Systems
• Embedded system: is a system whose
principal function is not computational,
but which is controlled by a computer
embedded within it.

3
Examples: Refrigerator

4
Examples: Car Door

5
Examples: Electronic Ping-pong

6
Examples: Derbot Autonomous Guided
Vehicle

7
Examples: Derbot Autonomous Guided
Vehicle

8
Computer Essentials

9
 Computer Essentials
• Instruction Sets
– CISC: Complex Instruction Set Computer
– RISC: Reduced Instruction Set Computer

• Memory Types
– Volatile: Random Access Memory (RAM)
– Non-volatile: Read Only Memory (ROM)

10
Von Neumann and Harvard Computers

11
Microprocessors and Microcontrollers
• The microprocessor is a processor on one
silicon chip.

• The microcontrollers are used in embedded

computing.
• The microcontroller is a microprocessor with
added circuitry.

12
Microcontrollers

13
 Introduction to PIC
Microcontroller
• Common Microcontrollers

14
 Microcontroller Manufacturers
. There are lots of microcontroller manufacturers

15
Harvard vs von Neumann Block
Architecture

16
 Harvard vs von Neumann Block
Architecture
Von Neumann Architecture
. Used in: 80X86 (PCs), 8051, 68HC11, etc.)
. Only one bus between CPU and memory
. RAM and program memory share the same bus and the same
memory, and so must have the same bit width
. Bottleneck: Getting instructions interferes with accessing RAM

RISC Architecture
. Complex/Reduced Instruction Set Computers
. A minimal set of instructions, combined, can do every operation
. Usually execute in a single cycle
. CPU is smaller
. Other hardware can be added to the space: (overlapping register
windows)
17
 Harvard vs von Neumann Block
Architecture
Traditionally, CPUs are .CISC.
. Complex Instruction Set Computer (CISC)
. Used in: 80X86, 8051, 68HC11, etc.
. Many instructions (usually > 100)
. Many, many addressing modes
. Usually takes more than 1 internal clock cycle to execute

PICs and most Harvard chips are .RISC.

. Reduced Instruction Set Computer (RISC)
. Used in: SPARC, ALPHA, Atmel AVR, etc.
. Few instructions (usually < 50)
. Only a few addressing modes
. Executes 1 instruction in 1 internal clock cycle 18
 PIC Microcontroller
The PIC Family: Cores
. PICs come with 1 of 4 CPU cores:
. 12bit cores with 33 instructions: 12C50x, 16C5x
. 14bit cores with 35 instructions: 12C67x,16Cxxx
. 16bit cores with 58 instructions: 17C4x,17C7xx
. ‘Enhanced’ 16bit cores with 77 instructions: 18Cxxx

The PIC Family: Packages

. PICs come in a huge variety of packages:
. 8 pin DIPs, SOICs: 12C50x (12bit) and 12C67x (14bit)
. 18pin DIPs, SOICs: 16C5X (12bit), 16Cxxx (14bit)
. 28pin DIPs, SOICs: 16C5X (12bit), 16Cxxx (14bit)
. 40pin DIPs, SOICs: 16Cxxx (14bit), 17C4x (16bit)
. 44 - 68pin PLCCs*: 16Cxxx (14bit), 17C4x / 17Cxxx (16bit)

19
 PIC Microcontroller
The PIC Family: Speed
. PICs require a clock to work.
. Can use crystals, clock oscillators, or even an
RC circuit.
. Some PICs have a built in 4MHz RC clock
. Not very accurate, but requires no external
components!
. Instruction speed = 1/4 clock speed
20
 PIC Microcontroller
The PIC Family: Program Memory
. PIC program space is different for each chip.
. Some examples are:
12C508 512 12bit instructions
16C71C 1024 (1k) 14bit instructions
16F877 8192 (8k) 14bit instructions
17C766 16384 (16k) 16bit instructions

21
 The PIC Family: Program Memory
. PICs have two different types of program storage:
1. EPROM (Erasable Programmable Read Only Memory)
. Needs high voltage from a programmer to program (~13V)
. Needs windowed chips and UV light to erase
. Note: One Time Programmable (OTP) chips are EPROM chips, but
with no window!
. PIC Examples: Any .C. part: 12C50x, 17C7xx, etc.

2. FLASH
. Re-writable (even by chip itself)
. Much faster to develop on!
. Finite number of writes (~100k Writes)
. PIC Examples: Any .F. part: 16F84, 16F87x, 18Fxxx (future)
Flash memory is a non-volatile computer storage chip that can be electrically erased and reprogrammed. It was
developed from EEPROM (electrically erasable programmable read-only memory) and must be erased in fairly large
blocks before these can be rewritten with new data. 22
 The PIC Family: Data Memory
. PICs use general purpose .file registers. for RAM (each register
is 8bits for all PICs)
. Some examples are:
12C508 25 Bytes RAM
16C71C 36 Bytes RAM
16F877 368 Bytes (plus 256 Bytes of nonvolatile EEPROM)
17C766 902 Bytes RAM

. Don’t forget, programs are stored in program space (not in data

space), so low RAM values are OK.

23
 The PIC Family: Control Registers
. PICs use a series of “special function registers” for controlling
peripherals and PIC behaviors.
. Some examples are:
STATUS Bank select bits, ALU bits (zero, borrow, carry)
INTCON Interrupt control: interrupt enables, flags, etc.
TRIS Tristate control for digital I/O: which pins are “floating”
TXREG UART transmit register: the next byte to transmit

24
 The PIC Family: Peripherals
. Different PICs have different on-board peripherals
. Some common peripherals are:
. Tri-state (“floatable”) digital I/O pins
. Analog to Digital Converters (ADC) (8, 10 and 12bit, 50ksps)
. Serial communications: UART (RS-232C), SPI, I2C, CAN
. Pulse Width Modulation (PWM) (10bit)
. Timers and counters (8 and 16bit)
. Watchdog timers, Brown out detect, LCD drivers

25
 PIC Peripherals: Ports (Digital I/O)
. All PICs have digital I/O pins, called “Ports”.
. the 8pin 12C508 has 1 Port with 4 digital I/O pins
. the 68pin 17C766 has 9 Ports with 66 digital I/O pins

. Ports have 2 control registers

. TRISx sets whether each pin is an input or output
. PORTx sets their output bit levels

. Most pins have 25mA source/sink (directly drives LEDs)

. WARNING: Other peripherals SHARE pins!

26
 PIC Peripherals: ADCs
. Only available in 14bit and 16bit cores
. Fs (sample rate) < 54KHz
. Most 8bits, newer PICs have 10 or 12bits
. All are +/- 1LSB and are monotonic
. Theoretically higher accuracy when PIC is in sleep mode (less
digital noise)
. Can generate an interrupt on ADC conversion done
. Multiplexed 3 (12C671) - 12 (17C7xxx) channel input
. Must wait Tacq to charge up sampling capacitor

27
 PIC Peripherals: USART: UART
. Serial Communications Peripheral: Universal Synchronous/
Asynchronous Receiver/Transmitter
. Only available in 14bit and 16bit cores
. Interrupt on TX buffer empty and RX buffer full
. Asynchronous communication: UART (RS-232C serial)
. Can do 300bps - 115kbps
. 8 or 9 bits, parity, start and stop bits, etc.
. Outputs 5V so you need a RS232 level converter (e.g., MAX232)

28
 PIC Peripherals: USART: USRT
. Synchronous communication: i.e., with clock signal
. SPI = Serial Peripheral Interface
. 3 wire: Data in, Data out, Clock
. Master/Slave (can have multiple masters)
. Very high speed (1.6Mbps)
. Full speed simultaneous send and receive (Full duplex)
. I2C = Inter IC
. 2 wire: Data and Clock
. Master/Slave (Single master only; multiple masters clumsy)
. Lots of cheap I2C chips available; typically < 100kbps (For
example, 8pin EEPROM chips, ADC, DACs, etc.)
29
 PIC Peripherals: Timers
. Available in all PICs
. 14+bit cores may generate interrupts on timer
overflow
. Some 8bits, some 16bits, some have prescalers
. Can use external pins as clock in/clock out (ie,
for counting events or using a different Fosc)
. Warning: some peripherals share Timer
resources
30
 PIC Peripherals: CCP Modules
. Capture/Compare/PWM (CCP)
. 10bit PWM width within 8bit PWM period (frequency)
. Enhanced 16bit cores have better bit widths
. Frequency/Duty cycle resolution tradeoff
. 19.5KHz has 10bit resolution
. 40KHz has 8bit resolution
. 1MHz has 1bit resolution (makes a 1MHz clock!)
. Can use PWM to do DAC - See AN655
. Capture counts external pin changes
. Compare will interrupt on when the timer equals the value in a
compare register
31
 PIC Peripherals: Misc.
. Sleep Mode: PIC shuts down until external interrupt (or internal
timer) wakes it up.
. Interrupt on pin change: Generate an interrupt when a digital
input pin changes state (for example, interrupt on keypress).
. Watchdog timer: Resets chip if not cleared before overflow
. Brown out detect: Resets chip at a known voltage level
. LCD drivers: Drives simple LCD displays
. Future: CAN bus, 12bit ADC, better analog functions
. VIRTUAL PERIPHERALS:
. Peripherals programmed in software. UARTS, timers, and
more can be done in software (but it takes most of the
resources of the machine) 32
PIC Microcontrollers

INSTRUCTION SET
PIC16F877

33
 Harvard Architecture
von-Neumann Architecture

34
 Encoding of instruction
• Each instruction is of 14-bit long. These 14-
bits contain both op-code and the operand.
• bcf f, b Clear 'b' bit of register 'f
• Encoding:

• The instruction is executed in one instruction

cycle, i.e., 4 clock cycles.

35
 Encoding of instruction
• goto K Go to label 'k' instruction
• Encoding:

• Since this instruction requires modification of

program Counter, it takes two instruction
cycles for execution

36
37
GENERAL FORMAT FOR
INSTRUCTIONS

38
OPCODE FIELD
DESCRIPTIONS

39
Instruction Set
PIC16F877

40
Instruction Set
PIC16F877

41
 1)ADDLW - Add literal and W
Syntax: [label] ADDLW k
Description: The content of the register W is added to the 8-bit literal k. The
result is stored in the W register.
Operation: (W) + k -> W
Operand: 0 ≤ k ≤ 255
Status affected: C, DC, Z
Number of cycles: 1

movlw 0x0F
addlw 0x03

Kết quả: W = 0x12, Z=0 DC=1 C=0

42
 2)ADDWF - Add W and f
Syntax: [label] ADDWF f, d
Description: Add the contents of the W and f registers.
If d = w or d = 0 the result is stored in the W register.
If d = f or d = 1 the result is stored in register f.
Operation: (W) + (f) -> d cblock 0x20
Operand: 0 ≤ f ≤ 127, d [0,1] REG
Status affected: C, DC, Z Endc
Number of cycles: 1 movlw 0x20
movwf REG
movlw 0x17
ADDWF REG,w

Kết quả: W = 0x37, Z=0 DC=0 C=0

43
 2) ADDWF - Add W and f
cblock 0xC2
Kết quả:
REG
Endc
W = 0x17, movlw 0xC2
STAUS = 0x18 movwf FSR
FSR = 0xC2 movlw 0x20
REG = 0x37
movwf INDF
movlw 0x17
ADDWF INDF, f

44
Indirect addressing

45
 Indirect addressing
A simple program to clear RAM location 20h-
2Fh using indirect addressing

The INDF register is not a physical register.

Reading INDF itself indirectly will produce 00h.
Writing to the INDF register indirectly results in a no operation
46
 3) ANDLW - AND literal with W
Syntax: [label] ANDLW k
Description: The content of the register W is AND’ed with the 8-bit literal k. It
means that the result will contain one (1) only if both corresponding bits
of operand are ones (1). The result is stored in the W register.
Operation: (W) AND k -> W
Operand: 0 ≤ k ≤ 255
Status affected: Z
movlw 0xAA
Number of cycles: 1
ANDLW 0x55

Kết quả: W = 0x00, Z=1

47
 4) ANDWF - AND W with f
Syntax: [label] ANDWF f,d
Description: AND the W register with register f.
If d = w or d = 0, the result is stored in the W register.
If d = f or d = 1, the result is stored in register f.
Operation: (W) AND (f) -> d cblock 0x20
Operand: 0 ≤ f ≤ 127, d[0,1] REG
Endc
Status affected: Z movlw 0xC2
Number of cycles: 1 movwf REG
movlw 0x17
andwf REG, f

Kết quả: W = 0x17, REG=0x02 Z=0

andwf REG, w
Kết quả: W = 0x02, REG=0xC2 Z=0
48
 5) BCF - Bit Clear f
Syntax: [label] BCF f, b
Description: Bit b of register f is cleared.
Operation: (0) -> f(b)
cblock 0xC2
Operand: 0 ≤ f ≤ 127, 0 ≤ b ≤ 7 REG
Status affected: - endc
Number of cycles: 1 banksel REG
movlw 0xC7
movwf REG
bcf REG,7

Kết quả: REG = 0x47

49
 5) BCF - Bit Clear f
Kết quả: cblock 0xC2
REG
Endc
W = 0x17,
movlw 0xC2
FSR = 0xC2
movwf FSR
STAUS = 0x18 movlw 0x2F
REG = 0x27 movwf INDF
movlw 0x17
bcf INDF,3

50
 6) BSF - Bit set f
Syntax: [label] BSF f,b
cblock 0xC2
Description: Bit b of register f is set.
REG
Operation: 1 -> f (b) Endc
Operand: 0 ≤ f ≤ 127, 0 ≤ b ≤ 7
movlw 0xC2
Status affected: -
movwf FSR
Number of cycles: 1 movlw 0x20
movwf INDF
Kết quả: movlw 0x17
bsf INDF, 3

W = 0x17,
FSR = 0xC2
STAUS = 0x18
REG = 0x28
51
 7) BTFSC - Bit test f, Skip if Clear
Syntax: [label] BTFSC f, b
Description: If bit b of register f is 0, the next instruction is discarded and a
NOP is executed instead, making this a two-cycle instruction.
Operation: Discard the next instruction if f(b) = 0
cblock 0x20
Operand: 0 ≤ f ≤ 127, 0 ≤ b ≤ 7 REG Kết quả:
Status affected: - Endc
Number of cycles: 1 or 2 depending on bit b movlw 0x01
movwf REG W = 0x18
movlw 0x17
movlw 0x00 btfsc REG,0
Kết quả:
movwf REG addlw 0x01
movlw 0x17 addlw 0x00
btfsc REG,0
addlw 0x01 W = 0x17
addlw 0x00
52
 8) BTFSS - Bit test f, Skip if Set
Syntax: [label] BTFSS f, b
Description: If bit b of register f is 1, the next instruction is discarded and a
NOP is executed instead, making this a two-cycle instruction.
Operation: Discard the next instruction if f(b) = 1
cblock 0x20
Operand: 0 ≤ f ≤ 127, 0 ≤ b ≤ 7 REG Kết quả:
Status affected: - Endc
Number of cycles: 1 or 2 depending on bit b movlw 0x01
movwf REG W = 0x17
movlw 0x17
movlw 0x00 btfss REG,0
Kết quả:
movwf REG addlw 0x01
movlw 0x17 addlw 0x00
btfss REG,0
addlw 0x01 W = 0x18
addlw 0x00
53
 9) CALL - Calls Subroutine
Syntax:[ label ] CALL k
Operands:0 ≤ k ≤ 2047
Operation:(PC)+ 1→ TOS,
k → PC<10:0>, (PCLATH<4:3>) → PC<12:11>
Status Affected: None

Description:Call Subroutine. First, return address (PC + 1) is

pushed onto the stack. The eleven-bit immediate address is
loaded into PC bits <10:0>. The upper bits of the PC are
loaded from PCLATH.

CALL is a two-cycle instruction.

54
 PCL and PCLATH Registers
The Program Counter (PC) is 13 bits wide. The low byte comes from the PCL
register, which is a readable and writable register. The high byte (PC<12:8>) is not
directly readable or writable and comes from PCLATH.

• PCLATH Program Counter LATch High

• The size of the program memory of the
PIC16F887 is 8K (13 bits address)

55
 PCL and PCLATH Registers
On subroutine call or jump
execution (CALL and GOTO),
the microcontroller is able to
provide only 11-bit addressing.
For this reason, similar to
RAM which is divided in
“banks”, ROM is divided in
four “pages” in size of 2K
each

• Call Subroutine
– CALL k (2) 10 0kkk kkkk kkkk
• Go to address
– GOTO k (2) 10 1kkk kkkk kkkk 56
 PCL and PCLATH Registers
Such instructions are executed
within these pages without any
problems. Simply, since the
processor is provided with 11-
bit address from the program,
it is able to address any
location within 2KB.

org 0x0000
call wait
loop goto loop
wait nop
nop
return
0000 2002 CALL 0x2 13: call wait
0001 2801 GOTO 0x1 14: loop goto loop
0002 0000 NOP 16: wait nop
0003 0000 NOP 17: nop
57
0004 0008 RETURN 18: return
PCL and PCLATH Registers
However, if a subroutine or
jump address are not within
the same page as the location
from where the jump is, two
“missing”- higher bits
should be provided by writing
to the PCLATH register.
org 0x0000
movlw 0x08
movwf PCLATH
call wait
loop goto loop

org 0x0800
wait nop
nop
return
58
 10) CLRF - Clear f
Syntax: [label] CLRF f
Description: The content of register f is cleared and the Z flag of the STATUS
register is set.
Operation: 0 -> f
Operand: 0 ≤ f ≤ 127 banksel TRISB
movlw 0xff
Status affected: Z
movwf TRISB
Number of cycles: 1 clrf TRISB

Kết quả: TRISB = 0x00, Z=1

59
 11) CLRW - Clear W
Syntax: [label] CLRW
Description: Register W is cleared and the Z flag of the STATUS register is set.
Operation: 0 -> W
Operand: -
Status affected: Z movlw 0xff
clrw
Number of cycles: 1

Kết quả: W = 0x00, Z=1

60
12) CLRWDT - Clear Watchdog Timer

61
 13) COMF - Complement f
Syntax: [label] COMF f, d
Description: The content of register f is complemented (logic zeros (0) are
replaced by ones (1) and vice versa). If d = w or d = 0 the result is stored in
W. If d = f or d = 1 the result is stored in register f.
Operation: (f) -> d
Operand: 0 ≤ f ≤ 127, d[0,1]
Status affected: Z movlw 0x13
Number of cycles: 1 movwf REG
COMF REG,w

W = 0xEC, Z = 0

62
 14) DECF - Decrement f
Syntax: [label] DECF f, d
Description: Decrement register f by one. If d = w or d = 0, the result is stored
in the W register. If d = f or d = 1, the result is stored in register f.
Operation: (f) - 1 -> d
Operand: 0 ≤ f ≤ 127, d[0,1] movlw 0x01
Status affected: Z movwf REG
DECF REG,f
Number of cycles: 1

REG = 0x00, Z = 1

63
 15) DECFSZ - Decrement f, Skip if 0
Syntax: [label] DECFSZ f, d
Description: Decrement register f by one. If d = w or d = 0, the result is stored
in the W register. If d = f or d = 1, the result is stored in register f. If the
result is 0, then a NOP is executed instead, making this a two-cycle
instruction.
....
Operation: (f) - 1 -> d
MOVLW .10
Operand: 0 ≤ f ≤ 127, d[0,1] MOVWF CNT ;10 -> CNT
Status affected: - Loop ......
Number of cycles: ...... ;Instruction block
1 or 2 depending on the result. ......
DECFSZ CNT,f ; decrement REG by one
GOTO Loop ; Skip this line if CNT= 0
LAB_03 ....... ; Jump here if CNT = 0

64
16) GOTO - Unconditional Branch

65
 17) INCF - Increment f
Syntax: [label] INCF f, d
Description: Increment register f by one.
If d = w or d = 0, the result is stored in register W.
If d = f or d = 1, the result is stored in register f.
Operation: (f) + 1 -> d
Operand: 0 ≤ f ≤ 127, d[0,1]
movlw 0x10
Status affected: Z movwf REG
Number of cycles: 1 incf REG,w

REG = 0x10
W = 0x11,
Z=0
66
 18) INCFSZ - Increment f, Skip if 0
Syntax: [label] INCFSZ f, d
Description: Register f is incremented by one. If d = w or d = 0, the result is
stored in register W. If d = f or d = 1, the result is stored in register f. If the
result is 0, then a NOP is executed instead, making this a two-cycle
instruction.
Operation: (f) + 1 -> d
Operand: 0 ≤ f ≤ 127, d[0,1]
Status affected: -
Number of cycles: 1 or 2 depending on the result.

67
19) IORLW - Inclusive OR literal with W
Syntax: [label] IORLW k
Description: The content of the W register is OR’ed with the 8-bit literal k.
The result is stored in register W.
Operation: (W) OR (k) -> W
Operand: 0 ≤ k ≤ 255
movlw 0x9A
Status affected: Z iorlw 0x35
Number of cycles: 1

W = 0xBF,
Z=0

68
 20) IORWF - Inclusive OR W with f
Syntax: [label] IORWF f, d
Description: The content of register f is OR’ed with the content of W register.
If d = w or d = 0, the result is stored in the W register. If d = f or d = 1, the
result is stored in register f.
Operation: (W) OR (f) -> d movlw 0x13
Operand: 0 ≤ f ≤ 127, d -> [0,1] movwf REG
movlw 0x91
Status affected: Z
iorwf REG,w
Number of cycles: 1

REG = 0x13
W = 0x93,
Z=0
69
 21) MOVF - Move f
Syntax: [label] MOVF f, d
Description: The content of register f is moved to a destination determined
by the operand d. If d = w or d = 0, the content is moved to register W. If d
= f or d = 1, the content remains in register f. Option d = 1 is used to test
the content of register f because this instruction affects the Z flag of the
STATUS register.
movlw 0xC2
Operation: (f) -> d
movwf FSR
Operand: 0 ≤ f ≤ 127, d -> [0,1] clrw
Status affected: Z movf FSR,w
Number of cycles: 1
Before instruction execution: FSR=0xC2 W=0x00
After instruction: W=0xC2 Z = 0

70
 22) MOVLW - Move literal to W
Syntax: [label] MOVLW k
Description: 8-bit literal k is moved to register W.
Operation: k -> (W)
Operand: 0 ≤ k ≤ 255
Status affected: -
Number of cycles: 1 Const equ 0x40
MOVLW Const

W=0x40

71
 23) MOVWF - Move W to f
Syntax: [label] MOVWF f
Description: The content of register W is moved to register f.
Operation: (W) -> f
Operand: 0 ≤ f ≤ 127
Status affected: - banksel OPTION_REG
movlw 0x20
Number of cycles: 1 movwf OPTION_REG

OPTION_REG=0x20

72
 24) NOP - No Operation
Syntax: [label] NOP
Description: No operation.
Operation: - NOP ; 1us delay (oscillator 4MHz)
Operand: -
Status affected: - Before instruction execution: PC = x
Number of cycles: 1 After instruction: PC = x + 1

73
25) RETFIE - Return from Interrupt

74
 26) RETLW - Return with literal in W
Syntax: [label] RETLW k
Description: 8-bit literal k is loaded into register W. The value from the top of
stack is loaded to the program counter.
Operation: (k) -> W; top of stack (TOP) -> PC
Operand: -
Status affected: -
Number of cycles: 2

75
 27) RETURN - Return from Subroutine
Syntax: [label] RETURN
Description: Return from subroutine. The value from the top of stack is
loaded to the program counter. This is a two-cycle instruction.
Operation: TOS -> program counter PC.
Operand: -
Status affected: -
Number of cycles: 2

76
 28) RLF - Rotate Left f through Carry
Syntax: [label] RLF f, d
Description: The content of register f is rotated one bit to the left through the
Carry flag. If d = w or d = 0, the result is stored in register W. If d = f or d =
1, the result is stored in register f.
Operation: (f(n)) -> d(n+1), f(7) -> C, C -> d(0);
Operand: 0 ≤ f ≤ 127, d[0,1]
Status affected: C
Number of cycles: 1
banksel STATUS
bcf STATUS, 0 banksel STATUS
movlw 0xE6 bcf STATUS, 0
movwf REG movlw 0xE6
rlf REG,f movwf REG
rlf REG,w
REG = 0xCC C=1
W = 0xCC C=1 77
 29) RRF - Rotate Right f through Carry
Syntax: [label] RRF f, d
Description: The content of register f is rotated one bit right through the
Carry flag. If d = w or d = 0, the result is stored in register W. If d = f or d =
1, the result is stored in register f.
Operation: (f(n)) -> d(n-1), f(0) -> C, C -> d(7);
Operand: 0 ≤ f ≤ 127, d -> [0,1]
Status affected: C
Number of cycles: 1 banksel STATUS
banksel STATUS bcf STATUS, 0
bcf STATUS, 0 movlw 0xE6
movlw 0xE6 movwf REG
movwf REG rrf REG,w
rrf REG, f
W = 0x73 C=0
REG = 0x73 C=0 78
30) SLEEP - Enter Sleep mode

79
31) SUBLW - Subtract W from literal
movlw 0x01
sublw 0x03

W = 0x02, Z = 0, DC = 1, C = 1

movlw 0x03
sublw 0x03

W = 0x00, Z = 1, DC = 1, C = 1
movlw 0x04
sublw 0x03
W = 0xFF, Z = 0, DC = 0, C = 0

80
32) SUBWF - Subtract W from f
movlw 0x03
movwf REG
movlw 0x02
subwf REG,f
REG = 0x01, Z = 0, DC = 1, C = 1
movlw 0x02
movwf REG
movlw 0x02
subwf REG,f

REG = 0x00, Z = 1, DC = 1, C = 1
movlw 0x01
movwf REG
movlw 0x02
subwf REG,f

REG = 0xFF, Z = 0, DC = 0, C81= 0

33) SWAPF - Swap Nibbles in f
movlw 0xF3
movwf REG
swapf REG, w

REG = 0xF3, W = 0x3F

movlw 0xF3
movwf REG
swapf REG, f

REG = 0x3F, W = 0xF3

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34)XORLW - Exclusive OR literal with W
movlw 0xB5
XORLW 0xAF

W = 0x1A, Z = 0
Const equ 0x37

movlw 0xAF
XORLW Const

W = 0x98, Z = 0

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35) XORWF - Exclusive OR W with f
movlw 0xAF
movwf REG
movlw 0xB5
XORWF REG,f

REG = 0x1A, Z = 0
movlw 0xAF
movwf REG
movlw 0xB5
XORWF REG,w
W = 0x1A, Z = 0

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