PES University, Bangalore UE18EC254

(Established under Karnataka Act No. 16 of 2013)

MAY 2020: END SEMESTER ASSESSMENT (ESA) B.TECH IV SEMESTER

UE18EC254 –DIGITAL VLSI DESIGN
Scheme and Solution
Time: 3 Hrs Answer All Questions Max Marks: 100

1. Impact of design style on design cycle and achievable performance.

a) Two design styles
Semi-Custom Style: Use Standard cells / FPGA
Full Custom Design Style: Geometry and the placement of every transistor can be
optimized individually.

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Full Custom :
1. It requires longer time until the design maturity reached
2. The flexibility in geometry and placement allows more opportunity for performance
improvement. Final product has higher level of performance.
3. Silicon area is relatively small because of better area utilization 2M
Semi-Custom:
1. Less design Time as it reaches maturity early & less opportunity for performance
improvement
2. At the early design phase, the design performance is Higher than Full Custom
1. Explain operation of a CMOS inverter with region of operation with a neat graph and
b) specifying the condition

NMOS: Condition for ON condition

Vgs,n > VT0,n i.e., Vin> VT0,n
VDS,n ≥ Vgs,n –VT0,n 1M
Vout ≥Vin –VT0,n

PMOS: Condition for ON condition

Vgs,p < VT0,p
Vin-VDD < VT0,p
Vin < (VDD+VT0,p)
VDS,p ≤ Vgs,p – VT0,p 1M
1M
Vout – VDD ≤ - VDD+Vin –VT0,n
Vout ≤ ( Vin – VT0,n)

NMOS is ON iff Vin> VT0,n else NMOS is in Cutoff

If Vin> VT0,n then it operates in Saturation iff Vout < Vin –VT0,n else operates in Linear
as shown in the graph
PMOS is ON iff Vin < (VDD+VT0,p) else PMOS goes into CutOFF
If Vin < (VDD+VT0,p) is True then PMOS operates in Saturation iff
Vout ≤ ( Vin – VT0,n) else operates in Linear 7M

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1M
1. Derive the expression for critical voltages of depletion load NMOS Inverter
c)
VOL
To calculate VOL we assume that 𝑉𝑖𝑛=𝑉𝑂𝐻=𝑉𝑑𝑑 .In this the driver transistor is in
Linear region and D−nmos load in saturation

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VIL
VIH

Ckt diagram with voltage condition - 1M

3 Marks each for VIL, VIL and VOL

2. 1. Minimum Sized Transistor
a)

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2. Extensions and Separations

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1M-Diagram+1 M for Rule =2M

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2. Y= ( a+b).c
B) CMOS logic

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1M

NMOS logic

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 2. Realize the Boolean function Z=(D+E+A)(B+C) using CMOS logic and Using the Euler‟s graph
find the Euler‟s path
d)

6M

4M

1M 1M

3. Calculate the Absolute value of Cin and Cout for the given Multilayer Layout structure
a) given using orbit 2 𝞵m technologies

Cin=Cm+Cp+Cg

( )( ) ----------------------------1.5M

( )( ) ------------1.5M

( ) ------------------------------------- 1M
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Cin= (6+0.4125+5) = 11.4125 x 0.0032 Pf =0.03652 pF----0.5M

Cout = Cda + Cdp

( )

𝑑 ------------------------------------------------------------1.5M

Note: Cdp (Peripheral capacitance) is Negligible for Orbit 2.0 um technology

3. Derive the expression for Number of stages Inverter to be cascaded to drive large
b) capacitive load with minimum delay.
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Driving Large Off Chip Capacitive loads CL of the order of CL=104 Cg need Low
resistive paths
Cascaded Inverter as Driver to drive Large Capacitive Load
If CL= Cg - Delay = (nmos) & Delay=7 (nmos)
Now If CL=400 Cg
Delay = + 4Rs x 100 Cg = 401 Rs. Cg

It is clear that as the CL increases, delay keeps on Increasing. In order to reduce the
delay the pullup and pull down resistance should be made low i.e, Need to use larger
size transistor with Higher value of width (w)

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Increasing the width (increases the Id) of inverter driving CL will reduce the delay but
at the same time it should be driven by another inverter. As increase in width has
increased the gate capacitance, Now the Inverter driving this should be geometrically
scaled to drive the load( gate capacitance).
A Set of Cascaded Inverter may not optimize the delay. Therefore cascading of N
inverter starting with Minimum size Inverter such that the delay is minimized.
Each Inverter cascaded is larger than the preceding Inverter and Let us consider a
geometrical scaled up by factor f in each stage

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Now it becomes important to achieve Minimum delay . In order to obtain Minimum

delay we need to decide
i) The Number of Inverters (N) to be cascaded
ii) The geometrical Scale factor f
Delay per stage
For NMOS Inverter -
Delay = ( ) ( )

And for CMOS Inverter -----(1)

Delay

The ration (proportionality factor ) of Cout to Cin is defined

( )

( )( )( ) ( )

y =fN -------------------(2)
 ( ) -------------------(2)
Selection of CL and f are interdependent
Now by taking Natural Log on both sides
( ) ( )
( )
[ ] ( )
( )
From Eqn (1), Delay for N (even)stage Cascaded Inverter can be given as
Delay ( ) = (NMOS) &

Delay ( ) = 3.5 (CMOS) --------- (4)

Now for Minimum delay and Number of stages N for drving CL load will optimal
when f is found
For Minimum delay, Differentiate eqn (4) w.r.t f and equate to 0
𝑑( )
𝑑
From (3), N can be substituted
( )
( ( )
)
0
( )
* ( ) ( ) ( )+
--------------------(5)
Therefore
( ) ( )
[ ] [ ] ( ) ( )
( ) ( )
For N Even For N Even
Delay (NMOS) & Delay 3.5 (CMOS)
For N ODD For N ODD
Dis-Charging Dis-Charging
Delay ( ) (NMOS) Delay ( )
& Charging & Charging
Delay ( ) Delay ( )
(CMOS)

Numerical - 3M
3. i) Without Stray
c)

Ratios:
Inverter 1 – Lpu:Wpu = (8:1) & Lpd:Wpd = (1:1)
Inverter 1 – Lpu:Wpu = (1:1) & Lpd:Wpd = (1:4)
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Inverter pair Delay = τdis + τcharg = Ron,pd x CL + Ron,pu xCL
= Rs x 4 Cg + Rs x 16 Cg
= 20 Rs Cg
= 20 τ
5

ii) With strays and wiring added – A 4 g cross e ch output

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CL2= 20 Cg

CL1= 8
Cg

Inverter pair Delay = τdis + τcharg = Ron,pd x CL + Ron,pu xCL

= Rs x 8 Cg + Rs x 20 Cg
= 28 Rs Cg
= 28 τ
4. a) Explain how Full Adder is realized using TG
Sum = abc + a’b’c + a’bc’ + ab’c’ Cout = ab + bc + ac
= c ( ab + a’b’ ) + c’ ( a’b + ab’) = ab + bc( a+a‟)+ac( b+b‟)
= c (a xor b)’ + c’ ( a xor b ) = ab+ abc + a‟bc + abc + ab‟c
Sum = c (a xnor b) + c‟(a xor b) = ab + abc + c(a‟b + ab‟)
= ab (c+1) + c(a XOR b)
= ab + c( a XOR b)
= a (ab+a‟b‟) +c (a xor b)
Cout= a( a xnor b) + c( a xor b) 1M

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Operation – 3M

b) What is dynamic logic and what is the drawback of cascading dynamic logic? Explain
how it is overcome by domino logic

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 A dynamic logic gate uses clocking and charge storage properties of MOSFETs to
implement logic operations
The clock Provide a synchronized data flow.
Clock drives a Complementary pair of transistors Mp and Mn ; This intern Control
the operation of the circuit and provide synchronization.
Logic is Implemented using array of NMOS network placed between Output node
and drain of the Mn.
Less transistors, and may be faster than static cascades

c) Clocked CMOS

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5. a) Explain the design strategy to be used for designing 6T SRAM using Read „0‟ and
Write‟0‟ operation.
M3 & M1 will conduct a nonzero
current and the voltage level of
Column C will begin to drop
slightly.
The column capacitance Cc is
typically very large; therefore,
the amount of decrease in the
column voltage is limited to a
few hundred millivolts during the
read phase.
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While M1 & M3 are slowly discharging the column capacitance, the node voltage of V1
will increase from its initial value of 0V. Especially if the (W/L) ratio of the access
transistor M3 is large compared to (W/L) of M1.
If W3/L3 > W1/l1 , V1 will increase because M3 will have less resistance compared to
M1 (since resistance is proportional to (L/W). 8
The Key design issue for the data-read operation is then to guarantee that the voltage V1
does not exceed the threshold of M2, so that the transistor M2 remains turned OFF
during the read phase.
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We can assume that after the access transistors are turned on, the column voltage Vc
remains approximately equal to VDD. Hence , M3 operates in saturation while M1
operates in the linear region.

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Write „0‟
To write “0”, M3 and M4 are turned ON.
To change the stored information i.e., to force V1 to 0V and V2 to VDD, the node
voltage V1 must be reduced below the threshold voltage of M2.
So that M2 turns OFF first.
 1M

We have to make this node voltage less than the threshold voltage of M2. Making the
node voltage V1 = 0V entirely depends on the design of M5 and M3 transistors
When V1 = Vtn, the transistor M3 operates in linear region and M5 operates in the
saturation mode

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Rearranging the conditions, results in

To summarize, the transistor M2 will be forced into cut-off mode during the write”0”
operation if the above conditions are satisfied.
This will guarantee that M1 subsequently turns ON , charging the stored information.
Note: a symmetrical condition also dictates the aspect ratios of M6 and M4.
b) The flip-flops with a setup time of 18ns, hold time of 6 ns, propagation delay of 7ns,
and contamination delay of 5ns.

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c

2M –Circuit
2M -
explanation