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6 Pipelining Instruction Cycle Machine Cycle

This document discusses instruction pipelining, where the fetching of one instruction can overlap with the execution of a previously fetched instruction. It shows how an example program executes over multiple clock cycles both without and with pipelining. With pipelining, different stages of instruction processing - fetch, execute - can occur simultaneously for different instructions to improve performance. However, some instructions like a subroutine call require stalling or flushing the pipeline.

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Zain UL ABIDIN
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0% found this document useful (0 votes)
93 views5 pages

6 Pipelining Instruction Cycle Machine Cycle

This document discusses instruction pipelining, where the fetching of one instruction can overlap with the execution of a previously fetched instruction. It shows how an example program executes over multiple clock cycles both without and with pipelining. With pipelining, different stages of instruction processing - fetch, execute - can occur simultaneously for different instructions to improve performance. However, some instructions like a subroutine call require stalling or flushing the pipeline.

Uploaded by

Zain UL ABIDIN
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Instruction Pipelining – Review

o  Instruction fetch is overlapped with execution of previously fetched


instruction Instruction Cycles

T0 T1 T2 T3 T4 T5 T6 T7
Example Program
1 MAIN movlw 0x37 Fetch Execute Time to execute normal instruction

2 movwf REG0 Fetch Execute

3 movlw 0x92 Fetch Execute

4 movwf REG1 Fetch Execute


Instruction Pipelining
Pre-Fetched Instruction

addwf REG0
Instruction Cycles

T0 T1 T2 T3 T4 T5 T6 T7
Example Program
1 MAIN movlw 0x37 Fetch Execute

2 movwf REG0 Fetch Execute

3 rcall SUB1 Fetch Execute

4 addwf REG0 Fetch Flush

Rcall is calling the subroutine SUB1 à 2 cycles


Execution of an Instruction
o  Instruction: MOVLW 0x37 ; Load 37H in W

Memory Hex Mnemonics


Address Code

000020 37 MOVLW 0x37


000021 0E
Execution of an Instruction

Execution of MOVLW 0x37 instruction

NOTES:
Each instruction take 4 clock periods
Pipeline Fetch and Execution

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