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Compal Confidential 2

Broadwell M/B Schematics Document

Intel ULV Processor with DDR3L

3
Date : 2015/04/14 3

Version 1.0
Project : Puccini (15")
ABW50

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Cover Page
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 1 of 63
A B C D E
 A B C D E

Compal Confidential
Model Name : Broadwell U
Broadwell U Block Diagram
Memory Bus Memody down 8Gbx8pcs 13"/14" only
1.35V DDR3L 1600MHz DDR3L (SO-DIMM) P.XX
1
File Name : 1

LA-C501PR01 15"/17" only

DDR3L (SO-DIMMx2)
P.15 - P.16

14"/17" eDP/LVDS eDP/LVDS eDP to LVDS eDP 1.4 x4

Port 0 Port 1
13"/15" eDP only RTD2132 USB 2.0 USB 2.0/USB 3.0 Conn.
conn P.19 P.18 P.26
<Co-layout>
Port 1 USB 2.0/USB 3.0 Conn. Port 2
Touch Panel I2C Port 0
EHCI Port1 : DebugPort P.26
P.19
Port 2 USB chnarger USB 2.0/USB 3.0 Conn.Port 3
Broadwell U TI TPS2546 P.27 P.27
DDR3L DGPU
13" only nVIDIA N16S-GT-S PCIE x4
VRAMx4pcs 15"/17" only
(23x23) Port 3 USB 2.0/USB 3.0 Conn. Port 4
P.XX P.XX
P.26
2
1168P BGA 2

Port 4 NGFF WLAN+BT PCIEx1 Port 6

(Key E) P.23
DDR3L DGPU Port 5
14"/15"/17" only nVIDIA N16P-GT B PCIE x4
Interleaved Memory symbol Port 5
VRAMx8pcs Camera
(29x29) P.39 - P.43 P.19
P.44 - P.47
Port 7 Finger print
<BOM opt i on N16S- GT- B and VRA Mx4>> Dual Core P.35
USB 3.0

SATA Port 1 HDD Conn. 14"/15"/17" only

TDP:15W/28W P.21

HDMI 1.4 Cost Reduce DDI1 DisplayPort Port 2 ODD Conn. 15"/17" only
Level Shift P.21
P.20 P.20 BGA 1168 balls Port 0
3 NGFF SSD (Key B) 3

P.22

LAN(GbE) Port 3 PCIE x2

42 x 24 mm
14"/15"/17" only RTL8111HSH-CG
P.24

SD Socket Card reader HP AMP Combo Jack

Port 4 HPA022642 (HP&MIC) P.28
RTS5237S-GR P.29
P.25 P.25 HDA AUDIO CODEC Int. Speaker
Realtek ALC 3241 P.28
SYS BIOS ROM SPI SPK AMP Int. Speaker 14"/15"/17" only
8MB P.28 ALC123-CGT P.30
P.7 P.30
P.4 - P.14
Charger IC Battery G-sensor LPC Subwoofer Woofer Speaker
P.52 P.51 P.32 SMBus1
4 DMIC P.19 ALC1301 P.31 P.31 4

SMBus2 ENE KB9022

P.49
GPU eDP to LVDS THERMAL CPU I2C/PS2
P.39 RTD2132 P.18 SENSOR P.7 P.7 Touch Pad Int.KBD Security Classification Compal Secret Data Compal Electronics, Inc.
P.34 P.34 2015/04/13 2018/04/13 Title
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Block Diagrams
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 2 of 63
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 A B C D E

ZZZ
Power rail Control (EC) Source (CPU)
45@ ROYALTY HDMI W/LOGO
+RTCVCC X X
VIN X X
@ is NO SMT part (empty) Part Number

RO0000002HM
Description

HDMI W/Logo:RO0000002HM
PCB
BATT+ X X Part Number = DAZ1DO00100 RO0000003HM

+19VB X X
short@ : short pad , don't pop. PCB 1DO LA-C501P REV0 M/B 4

+VL X X
+3VL X X
@EMI@,@ESD@,@RF@ : Reserve , don't pop. <USB2.0 port>
+5VALW EC_ON X RF@ : RF team request, must add.
+3VALW EC_ON X
DESTINATION
1
+3VL_EC EC_ON X EMI@ : EMI team request, must add. SOC SMBUS Address Table 1

+3V_PCH PCH_PWR_EN X
USB2.0 port UMA Dis
Address (8bit)
+1.35V_VDDQ SYSON PM_SLP_S5#/PM_SLP_S4# ESD@ : ESD team request, must add. SOC_SMBUS Net Name Power Rail Device Address (7 bit)
Write Read
+5VS SUSP# PM_SLP_S3#
0 USB 2.0/3.0(left side) USB 2.0/3.0(left side)
DIMMA 0xA0 TBC TBC
+3VS SUSP# PM_SLP_S3# LVDS@ : Support LVDS panel. +3VS
1 USB 2.0/3.0(left side) USB 2.0/3.0(left side)
+1.5VS SUSP# PM_SLP_S3#
SOC_SMBCLK
SOC_SMBDATA DIMMB 0xA4 TBC TBC
+1.05VS SUSP# PM_SLP_S3# DIS@ : GPU BOM conf i g.
+0.6V_0.675VS SUSP#
+3V_PCH Touch Pad 0X2C TBC TBC 2 USB 2.0/3.0(left side) USB 2.0/3.0(left side)
+VCC_CORE X VR12.5_VR_ON
+3VS +3VS
SOC_SML0CLK
SOC_SML0DATA +3V_PCH NA NA TBC TBC 3 USB 2.0/3.0(right side) USB 2.0/3.0(right side)
R=10K
PCH_SMBCLK 0x1A
PCH_SMBDATA EC TBC TBC 4 WLAN/BT WLAN/BT
2N7002 SO-DIMM A +3VS 0X19
SOC_SML1CLK DGPU 0X96 TBC TBC
UCPU1 5 Camera Camera
+3V_PCH +3VS +3VS SOC_SML1DATA
Thermal Sensor 0x4C TBC TBC
R=2.2K R=10K
0X94~97 6 X X
AP2 SMBCLK PCH_SMBCLK
LVDS 0X6A 0X6B TBC TBC
AH1 SMBDATA 2N7002 PCH_SMBDATA
SO-DIMM B 7 FingerPrint FingerPrint

CPU +3V_PCH +3V_PCH +3VALW

R=2.2K
EC SMBUS Address Table
Address (8bit) <PCI-E,SATA,USB3.0>
R=1K TP_SMBCLK EC_SMBUS Port Power Rail Device Address (7 bit)
2 SML0CLK TP_SMBDAT Write Read 2
AN1 SML0DATA 2N7002 Touch Pad DESTINATION
AK1
BAT 0x14 0X15 TBC TBC Lane# PCI-E SATA USB3.0
+3V_PCH +3VS +3VS UMA Dis
SMBUS Port 1 +3VLP_EC
1 1 USB3.0 USB3.0
R=2.2K R=2.2K
CHGR 0x12 TBC TBC
AU3 SML1CLK
2 2 USB3.0 USB3.0
AH3 SML1DATA
2N7002
3 1 3 USB3.0 USB3.0
EC_SMB_CK2
DGPU_PEX_RST# G-Sensor 0x29 TBC TBC
4 2 4 USB3.0 USB3.0
EC_SMB_DA2 +3VGS_AON
+3VS 5 3 10/100/1000 LAN 10/100/1000 LAN
SMBUS Port 2 Card reader(PCI-E) Card reader(PCI-E)
I2C_0_SCL R=2.2K
6 4
I2C_0_SDA R=1K 7 GPU(DIS only)
F3
F2 2N7002 GPU 8 GPU(DIS only)
Touch Screen I2CS_SCL 5
I2CS_SDA 9 GPU(DIS only)
+3VS
10 GPU(DIS only)
F1 I2C_1_SCL R=1K
11 L0 3 WLAN WLAN
G4 I2C_1_SDA I2C Address Table 12
6 L1
2 ODD ODD
Address (8bit) 13 L2 1 HDD HDD
Thermal Sensor :NCT7718W_MSOP8 I2C Port Power Rail Device Address (7 bit)
UK1:+3VALW_EC (+3VL) Address : 0x4C
Write Read 14 L3 0 SSD SSD
I2C 0 +3VS Touch Panel 0x20 TBC TBC
+3VS
79 EC_SMB_CK2
80 EC_SMB_DA2 I2C 1 +3VS NA TBC TBC TBC
eDP to LVDS bridge RTD2132S
3

EC +3VL_EC
3

77 EC_SMB_CK1
R=2.2K CPU Memory down vender control table
78 EC_SMB_DA1
G-Sensor CPU_GPIO50 CPU_GPIO49 CPU_GPIO48 CPU_GPIO47
Vender MD size Vender descipt i on Note Project
SDRAM_ID4 SDRAM_ID3 SDRAM_ID2 SDRAM_ID1
0 0 0 0 X X X SODIMMx2 (A,B) 15"/17"
R=100 BAT 0 0 0 1 X X X SODIMMx1(A) No MDx16bitx4pcs (B) 13"
0 0 1 0 Micron 256x16 MT41K512M16TNA-125:E SODIMMx1(A) MDx16bitx4pcs (B) 13"
0 0 1 1 Samsung 256x16 4B8G1646Q-MYK0 SODIMMx1(A) MDx16bitx4pcs (B) 13"
Charger 0 1 0 0 Hynix 256x16 H5TC8G63AMR-PBA SODIMMx1(A) MDx16bitx4pcs (B) 13"
0 1 0 1 Micron 512x8 MT41K512M8RG-107:N MDx8bitx8pcs (A) SODIMMx1(B) 14"
0 1 1 0 Samsung 512x8 K4B4G0846Q-HYK0 MDx8bitx8pcs (A) SODIMMx1(B) 14"
0 1 1 1 Hynix 512x8 H5TC4G83BFR-PBA MDx8bitx8pcs (A) SODIMMx1(B) 14"

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Notes List
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 3 of 63
A B C D E
 5 4 3 2 1

UCPU1A BDW_ULT_DDR3L(Interleaved)
UCPU1 5500@ UCPU1 5200@

C54 C45
<20> PCH_DPB_N2 DDI1_TXN0 EDP_TXN0 EDP_CPU_LANE_N0_C <18>
C55 B46
<20> PCH_DPB_P2 DDI1_TXP0 EDP_TXP0 EDP_CPU_LANE_P0_C <18>
I7-5500 I5-5200 B58 A47
<20> PCH_DPB_N1 DDI1_TXN1 EDP_TXN1 EDP_CPU_LANE_N1_C <18>
<HDMI> C58 B47
<20> PCH_DPB_P1 DDI1_TXP1 EDP_TXP1 EDP_CPU_LANE_P1_C <18>
SA000089A30 SA000089930 B55 <eDP>
<20> PCH_DPB_N0 DDI1_TXN2
A55 C47
<20> PCH_DPB_P0 DDI1_TXP2 EDP_TXN2 EDP_CPU_LANE_N2_C <18>
A57 C46
<20> PCH_DPB_N3 DDI1_TXN3 EDP_TXP2 EDP_CPU_LANE_P2_C <18>
B57 A49
D <20> PCH_DPB_P3 DDI1_TXP3 DDI EDP EDP_TXN3 EDP_CPU_LANE_N3_C <18> D
B49
C51 EDP_TXP3 EDP_CPU_LANE_P3_C <18>
C50 DDI2_TXN0 A45
C53 DDI2_TXP0 EDP_AUXN B45 EDP_CPU_AUX#_C <18>
B54 DDI2_TXN1 EDP_AUXP EDP_CPU_AUX_C <18>
C49 DDI2_TXP1 D20 EDP_COMP
B50 DDI2_TXN2 EDP_RCOMP A43 T22 @ COMPENSATION PU FOR eDP DG V2.0 PEG_COMP
A53 DDI2_TXP2 EDP_DISP_UTIL +VCCIOA_OUT
B53 DDI2_TXN3 Trace width=20mil and spacing=25mil
DDI2_TXP3
EDP_COMP
Max length=100mil
2 1
24.9_0402_1% RC3
+3V_PCH
1 OF 19
BDW-ULT-DDR3L-IL_BGA1168

1
@
RC234
+VCCIO_OUT 10K_0402_5%
UCPU1B BDW_ULT_DDR3L(Interleaved)

2
1

RC4 PROC_DETECT# D61

62_0402_5% @ T51 K61 PROC_DETECT MISC
N62 CATERR J62 XDP_PRDY# T58 @
<33> H_PECI PECI PRDY K62 XDP_PREQ#
2

PREQ E60 XDP_TCK

PROC_TCK E61 XDP_TMS_CPU XDP_TCK <6>
PROCHOT# RC6 1 2 56_0402_5% H_PROCHOT#_R K63 JTA G PROC_TMS E59 XDP_TRST#_CPU
<33> PROCHOT# PROCHOT PROC_TRST XDP_TDI_CPU XDP_TRST#_CPU <6>
THERMAL F63
PROC_TDI F62 XDP_TDO_CPU +1.05VS_VCCST
1 PROC_TDO XDP_TDO_CPU <6>
@ESD@ @
C295 RC7 1 2 H_CPUPWRGD_R C61
C <6,11> +1.05VS_PG PROCPWRGD C
10P_0402_50V8J 1K_0402_1% PWR
2 RC11 2 1 10K_0402_5% J60 XDP_OBS0_R T80 @ XDP_TDI_CPU @ RC12 2 1 51_0402_1%
BPM#0 H60 XDP_OBS1_R T79 @
BPM#1 H61 XDP_OBS2_R T52 @ XDP_PREQ# @ RC13 2 1 51_0402_1%
BPM#2 H62 XDP_OBS3_R T53 @
SM_RCOMP0 AU60 BPM#3 K59 XDP_OBS4_R T54 @
SM_RCOMP1 AV60 SM_RCOMP0 DDR3L BPM#4 H63 XDP_OBS5_R T55 @ XDP_TRST#_CPU
SM_RCOMP2 AU61 SM_RCOMP1 BPM#5 K60 XDP_OBS6_R T56 @
DDR3_DRAMRST# AV15 SM_RCOMP2 BPM#6 J61 XDP_OBS7_R T57 @
DDR_PG_CNTL SM_DRAMRST BPM#7 1
AV61 @ESD@
SM_PG_CNTL1 CC99
0.1U_0402_16V7K
2 OF 19 2
BDW-ULT-DDR3L-IL_BGA1168
@ @ T86 XDP_TMS_CPU

+1.35V_VDDQ +1.35V_VDDQ

DG V2.0 Trace width=12~15 mil

1
Max length=500mil RC308
UC10
DDR3 COMPENSATION SIGNALS 470_0402_5%
5 1
VCC NC
2

200_0402_1% 2 1 RC18 SM_RCOMP0 DDR3_DRAMRST# 2 DDR_PG_CNTL

DDR3_DRAMRST# <15,16> 4 A
SM_RCOMP1 1 <15> SM_PG_CTRL Y
120_0402_1% 2 1 RC19 3
@ESD@ CC88 GND
100_0402_1% 2 1 RC20 SM_RCOMP2 74AUP1G07GW_TSSOP5
0.1U_0402_16V7K
B 2 B

+1.35V_VDDQ

1
@ESD@ CC130
0.1U_0402_16V7K
2
2015/02/13 ESD reserve for cocoa

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDI,MSIC,XDP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 4 of 63
5 4 3 2 1
 5 4 3 2 1

Interleaved Memory
D D

<15> DDR_A_D[0..63]
<16> DDR_B_D[0..63]

UCPU1D BDW_ULT_DDR3L(Interleaved)
UCPU1C BDW_ULT_DDR3L(Interleaved)
<DDR3L> <DDR3L>
DDR_A_D0 AH63 AU37 DDR_B_D0 AP58 AM38
DDR_A_D1 SA_DQ0 SA_CLK#0 M_CLK_DDR#0 <15> DDR_B_D1 SB_DQ0 SB_CK#0 M_CLK_DDR#2 <16>
AH62 AV37 AR58 AN38
DDR_A_D2 SA_DQ1 SA_CLK0 M_CLK_DDR0 <15> DDR_B_D2 SB_DQ1 SB_CK0 M_CLK_DDR2 <16>
AK63 AW36 AM57 AK38
DDR_A_D3 SA_DQ2 SA_CLK#1 M_CLK_DDR#1 <15> DDR_B_D3 SB_DQ2 SB_CK#1 M_CLK_DDR#3 <16>
AK62 AY36 AK57 AL38
DDR_A_D4 SA_DQ3 SA_CLK1 M_CLK_DDR1 <15> DDR_B_D4 SB_DQ3 SB_CK1 M_CLK_DDR3 <16>
AH61 AL58
DDR_A_D5 AH60 SA_DQ4 AU43 DDR_B_D5 AK58 SB_DQ4 AY49
DDR_A_D6 SA_DQ5 SA_CKE0 DDR_CKE0_DIMMA <15> DDR_B_D6 SB_DQ5 SB_CKE0 DDR_CKE0_DIMMB <16>
AK61 AW43 AR57 AU50
DDR_A_D7 SA_DQ6 SA_CKE1 DDR_CKE1_DIMMA <15> DDR_B_D7 SB_DQ6 SB_CKE1 DDR_CKE1_DIMMB <16>
AK60 AY42 AN57 AW49
DDR_A_D8 AM63 SA_DQ7 SA_CKE2 AY43 DDR_B_D8 AP55 SB_DQ7 SB_CKE2 AV50
DDR_A_D9 AM62 SA_DQ8 SA_CKE3 DDR_B_D9 AR55 SB_DQ8 SB_CKE3
DDR_A_D10 AP63 SA_DQ9 AP33 DDR_B_D10 AM54 SB_DQ9 AM32
DDR_A_D11 SA_DQ10 SA_CS#0 DDR_CS0_DIMMA# <15> DDR_B_D11 SB_DQ10 SB_CS#0 DDR_CS0_DIMMB# <16>
AP62 AR32 AK54 AK32
DDR_A_D12 SA_DQ11 SA_CS#1 DDR_CS1_DIMMA# <15> DDR_B_D12 SB_DQ11 SB_CS#1 DDR_CS1_DIMMB# <16>
AM61 AL55
DDR_A_D13 AM60 SA_DQ12 AP32 T84 @ DDR_B_D13 AK55 SB_DQ12 AL32
DDR_A_D14 AP61 SA_DQ13 SA_ODT0 PAD SODIMM No Need ODT DDR_B_D14 AR54 SB_DQ13 SB_ODT0
DDR_A_D15 AP60 SA_DQ14 AY34 DDR_B_D15 AN54 SB_DQ14 AM35
DDR_A_D16 SA_DQ15 SA_RAS DDR_A_RAS# <15> DDR_B_D16 SB_DQ15 SB_RAS DDR_B_RAS# <16>
AY58 AW34 AK40 AK35
DDR_A_D17 SA_DQ16 SA_WE DDR_A_WE# <15> DDR_B_D17 SB_DQ16 SB_WE DDR_B_WE# <16>
AW58 AU34 AK42 AM33
C DDR_A_D18 SA_DQ17 SA_CAS DDR_A_CAS# <15> DDR_B_D18 SB_DQ17 SB_CAS DDR_B_CAS# <16> C
AY56 AM43
DDR_A_D19 AW56 SA_DQ18 AU35 DDR_B_D19 AM45 SB_DQ18 AL35
DDR_A_D20 SA_DQ19 SA_BA0 DDR_A_BS0 <15> DDR_B_D20 SB_DQ19 SB_BA0 DDR_B_BS0 <16>
AV58 AV35 AK45 AM36
DDR_A_D21 SA_DQ20 SA_BA1 DDR_A_BS1 <15> DDR_B_D21 SB_DQ20 SB_BA1 DDR_B_BS1 <16>
AU58 AY41 AK43 AU49
DDR_A_D22 SA_DQ21 SA_BA2 DDR_A_BS2 <15> DDR_B_D22 SB_DQ21 SB_BA2 DDR_B_BS2 <16>
AV56 AM40
DDR_A_D23 SA_DQ22 DDR_A_MA0 DDR_A_MA[0..15] <15> DDR_B_D23 SB_DQ22 DDR_B_MA0 DDR_B_MA[0..15] <16>
AU56 AU36 AM42 AP40
DDR_A_D24 AY54 SA_DQ23 SA_MA0 AY37 DDR_A_MA1 DDR_B_D24 AM46 SB_DQ23 SB_MA0 AR40 DDR_B_MA1
DDR_A_D25 AW54 SA_DQ24 SA_MA1 AR38 DDR_A_MA2 DDR_B_D25 AK46 SB_DQ24 SB_MA1 AP42 DDR_B_MA2
DDR_A_D26 AY52 SA_DQ25 SA_MA2 AP36 DDR_A_MA3 DDR_B_D26 AM49 SB_DQ25 SB_MA2 AR42 DDR_B_MA3
DDR_A_D27 AW52 SA_DQ26 SA_MA3 AU39 DDR_A_MA4 DDR_B_D27 AK49 SB_DQ26 SB_MA3 AR45 DDR_B_MA4
DDR_A_D28 AV54 SA_DQ27 SA_MA4 AR36 DDR_A_MA5 DDR_B_D28 AM48 SB_DQ27 SB_MA4 AP45 DDR_B_MA5
DDR_A_D29 AU54 SA_DQ28 SA_MA5 AV40 DDR_A_MA6 DDR_B_D29 AK48 SB_DQ28 SB_MA5 AW46 DDR_B_MA6
DDR_A_D30 AV52 SA_DQ29 SA_MA6 AW39 DDR_A_MA7 DDR_B_D30 AM51 SB_DQ29 SB_MA6 AY46 DDR_B_MA7
DDR_A_D31 AU52 SA_DQ30 DDR CHANNEL A SA_MA7 AY39 DDR_A_MA8 DDR_B_D31 AK51 SB_DQ30 SB_MA7 AY47 DDR_B_MA8
DDR_A_D32 AY31 SA_DQ31 SA_MA8 AU40 DDR_A_MA9 DDR_B_D32 AM29 SB_DQ31 DDR CHANNEL B SB_MA8 AU46 DDR_B_MA9
DDR_A_D33 AW31 SA_DQ32 SA_MA9 AP35 DDR_A_MA10 DDR_B_D33 AK29 SB_DQ32 SB_MA9 AK36 DDR_B_MA10
DDR_A_D34 AY29 SA_DQ33 SA_MA10 AW41 DDR_A_MA11 DDR_B_D34 AL28 SB_DQ33 SB_MA10 AV47 DDR_B_MA11
DDR_A_D35 AW29 SA_DQ34 SA_MA11 AU41 DDR_A_MA12 DDR_B_D35 AK28 SB_DQ34 SB_MA11 AU47 DDR_B_MA12
DDR_A_D36 AV31 SA_DQ35 SA_MA12 AR35 DDR_A_MA13 DDR_B_D36 AR29 SB_DQ35 SB_MA12 AK33 DDR_B_MA13
DDR_A_D37 AU31 SA_DQ36 SA_MA13 AV42 DDR_A_MA14 DDR_B_D37 AN29 SB_DQ36 SB_MA13 AR46 DDR_B_MA14
DDR_A_D38 AV29 SA_DQ37 SA_MA14 AU42 DDR_A_MA15 DDR_B_D38 AR28 SB_DQ37 SB_MA14 AP46 DDR_B_MA15
DDR_A_D39 AU29 SA_DQ38 SA_MA15 DDR_B_D39 AP28 SB_DQ38 SB_MA15
DDR_A_D40 SA_DQ39 DDR_A_DQS#[0..7] <15> SB_DQ39 DDR_B_DQS#[0..7] <16>
AY27 AJ61 DDR_A_DQS#0 DDR_B_D40 AN26 AM58 DDR_B_DQS#0
DDR_A_D41 AW27 SA_DQ40 SA_DQSN0 AN62 DDR_A_DQS#1 DDR_B_D41 AR26 SB_DQ40 SB_DQSN0 AM55 DDR_B_DQS#1
DDR_A_D42 AY25 SA_DQ41 SA_DQSN1 AV57 DDR_A_DQS#2 DDR_B_D42 AR25 SB_DQ41 SB_DQSN1 AL43 DDR_B_DQS#2
DDR_A_D43 AW25 SA_DQ42 SA_DQSN2 AV53 DDR_A_DQS#3 DDR_B_D43 AP25 SB_DQ42 SB_DQSN2 AL48 DDR_B_DQS#3
DDR_A_D44 AV27 SA_DQ43 SA_DQSN3 AW30DDR_A_DQS#4 DDR_B_D44 AK26 SB_DQ43 SB_DQSN3 AN28 DDR_B_DQS#4
DDR_A_D45 AU27 SA_DQ44 SA_DQSN4 AV26 DDR_A_DQS#5 DDR_B_D45 AM26 SB_DQ44 SB_DQSN4 AN25 DDR_B_DQS#5
DDR_A_D46 AV25 SA_DQ45 SA_DQSN5 AW22DDR_A_DQS#6 DDR_B_D46 AK25 SB_DQ45 SB_DQSN5 AN21 DDR_B_DQS#6
DDR_A_D47 AU25 SA_DQ46 SA_DQSN6 AV18 DDR_A_DQS#7 DDR_B_D47 AL25 SB_DQ46 SB_DQSN6 AN18 DDR_B_DQS#7
DDR_A_D48 AY23 SA_DQ47 SA_DQSN7 DDR_B_D48 AR21 SB_DQ47 SB_DQSN7
DDR_A_D49 AW23 SA_DQ48 AJ62 DDR_A_DQS0 DDR_A_DQS[0..7] <15> DDR_B_D49 AR22 SB_DQ48 AN58 DDR_B_DQS0 DDR_B_DQS[0..7] <16>
DDR_A_D50 AY21 SA_DQ49 SA_DQSP0 AN61 DDR_A_DQS1 DDR_B_D50 AL21 SB_DQ49 SB_DQSP0 AN55 DDR_B_DQS1
DDR_A_D51 AW21 SA_DQ50 SA_DQSP1 AW57DDR_A_DQS2 DDR_B_D51 AM22 SB_DQ50 SB_DQSP1 AL42 DDR_B_DQS2
DDR_A_D52 AV23 SA_DQ51 SA_DQSP2 AW53DDR_A_DQS3 DDR_B_D52 AN22 SB_DQ51 SB_DQSP2 AL49 DDR_B_DQS3
B DDR_A_D53 AU23 SA_DQ52 SA_DQSP3 AV30 DDR_A_DQS4 DDR_B_D53 AP21 SB_DQ52 SB_DQSP3 AM28 DDR_B_DQS4 B
DDR_A_D54 AV21 SA_DQ53 SA_DQSP4 AW26DDR_A_DQS5 DDR_B_D54 AK21 SB_DQ53 SB_DQSP4 AM25 DDR_B_DQS5
DDR_A_D55 AU21 SA_DQ54 SA_DQSP5 AV22 DDR_A_DQS6 DDR_B_D55 AK22 SB_DQ54 SB_DQSP5 AM21 DDR_B_DQS6
DDR_A_D56 AY19 SA_DQ55 SA_DQSP6 AW18DDR_A_DQS7 DDR_B_D56 AN20 SB_DQ55 SB_DQSP6 AM18 DDR_B_DQS7
DDR_A_D57 AW19 SA_DQ56 SA_DQSP7 DDR_B_D57 AR20 SB_DQ56 SB_DQSP7
DDR_A_D58 AY17 SA_DQ57 AP49 +V_SM_VREF_CNT DDR_B_D58 AK18 SB_DQ57
DDR_A_D59 SA_DQ58 SM_VREF_CA +V_SM_VREF_CNT SB_DQ58
AW17 AR51 +V_DDR_REFA_R +V_DDR_REFA_R
DDR_B_D59 AL18
DDR_A_D60 AV19 SA_DQ59 SM_VREF_DQ0 AP51 +V_DDR_REFB_R DDR_B_D60 AK20 SB_DQ59
DDR_A_D61 SA_DQ60 SM_VREF_DQ1 +V_DDR_REFB_R DDR_B_D61 SB_DQ60
AU19 AM20
DDR_A_D62 AV17 SA_DQ61 DDR_B_D62 AR18 SB_DQ61
DDR_A_D63 AU17 SA_DQ62 DDR_B_D63 AP18 SB_DQ62
SA_DQ63 SB_DQ63

4 OF 19
3 OF 19 BDW-ULT-DDR3L-IL_BGA1168
BDW-ULT-DDR3L-IL_BGA1168 @
@

A
Interleaved Memory A

Security Classification Compal Secret Data Compal Electronics, Inc.

2015/04/13 2018/04/13 Title
Issued Date Deciphered Date DDRIII
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 5 of 63
5 4 3 2 1
 5 4 3 2 1

PCH_RTCX1 RTC BAT conn

1 2 PCH_RTCX2
RC31 10M_0402_5% +RTCBATT_R +RTCBATT
1 +RTCVCC

1
+RTCVCC 1K_0402_5%
CC2 JCMOS1 CMOS YC1 32.768KHZ_X1A000141000500
RC33
1U_0402_6.3V6K SHORT PADS 1 2 DC1 15mils 15mils JRTC1

2
2 2 2 1 1
1 2 PCH_RTCRST# 15mils 1 2 1
1 SJ10000MH00 1
RC32 20K_0402_5% CC3 CC4 3 2
PCH_SRTCRST# 1 +3VL
1 2 15P_0402_50V8J CC6 3
RC34 20K_0402_5% 15P_0402_50V8J 1U_0402_6.3V6K BAV70W SOT-323 4 GND
1 GND

1
2 2
CC5 JME1 2
1U_0402_6.3V6K SHORT PADS
ME CMOS ACES_50271-0020N-001
D D

2
2

UCPU1E BDW_ULT_DDR3L(Interleaved)

PCH_RTCX1 AW5
RC35 PCH_RTCX2 AY5 RTCX1
1 2 1M_0402_5% SM_INTRUDER# AU6 RTCX2 J5
HDA_BIT_CLK +RTCVCC PCH_INTVRMEN INTRUDER SATA_RN0/PERN6_L3 SATA_PRX_DTX_N0 <22>
<28> HDA_BITCLK_AUDIO RC157 1 2 1 2 330K_0402_5% AV7 H5 SATA_PRX_DTX_P0 <22>
EMI@ PCH_SRTCRST# AV6 INTVRMEN SATA_RP0/PERP6_L3 B15
PCH_RTCRST# AU7 SRTCRST
RTC
SATA_TN0/PETN6_L3 A15 SATA_PTX_DRX_N0 <22> M2 SSD
33_0402_5% RC236

：：
RTCRST SATA_TP0/PETP6_L3 SATA_PTX_DRX_P0 <22>
INTVRMEN
1
RP1
8
* H Integrated
L Integrated
VRM
VRM
enable
disable SATA_RN1/PERN6_L2
J8
H8
SATA_PRX_DTX_N1
SATA_PRX_DTX_P1
<21>
<21>
HDA_RST_AUDIO# 2 7 HDA_RST# SATA_RP1/PERP6_L2 A17
<28> HDA_RST_AUDIO#
3 6 HDA_SYNC SATA_TN1/PETN6_L2 B17 SATA_PTX_DRX_N1 <21> 2.5" HDD
<28> HDA_SYNC_AUDIO HDA_SDOUT SATA_TP1/PETP6_L2 SATA_PTX_DRX_P1 <21>
4 5
<28> HDA_SDOUT_AUDIO HDA_BIT_CLK AW8 J6 SATA_PRX_DTX_N2 <21>
33_0804_8P4R_5% HDA_SYNC AV11 HDA_BCLK/I2S0_SCLK SATA_RN2/PERN6_L1 H6
HDA_RST# HDA_SYNC/I2S0_SFRM SATA_RP2/PERP6_L1 SATA_PRX_DTX_P2 <21>
AU8 B14 ODD
HDA_SDIN0 HDA_RST/I2S_MCLK AUDIO S ATA SATA_TN2/PETN6_L1 SATA_PTX_DRX_N2 <21>
9/17 add RF solution AY10 C15
<28> HDA_SDIN0 HDA_SDI0/I2S0_RXD SATA_TP2/PETP6_L1 SATA_PTX_DRX_P2 <21>
AU12
HDA_SDOUT AU11 HDA_SDI1/I2S1_RXD F5
HDA_SDO/I2S0_TXD SATA_RN3/PERN6_L0 PCIE_PRX_DTX_N6 <23>
AW10 E5 PCIE_PRX_DTX_P6 <23>
AV10 HDA_DOCK_EN/I2S1_TXD SATA_RP3/PERP6_L0 C17 PCIE_PTX_DRX_N6 CC71 2 0.1U_0402_16V7K
@
CM28
HDA_SDOUT: AY8 HDA_DOCK_RST/I2S1_SFRM SATA_TN3/PETN6_L0 D17 PCIE_PTX_DRX_P6 CC81 2 0.1U_0402_16V7K PCIE_PTX_C_DRX_N6 <23> WLAN
1 2 HDA_BITCLK_AUDIO ME Flash Descriptor Security Override I2S1_SCLK SATA_TP3/PETP6_L0 PCIE_PTX_C_DRX_P6 <23> (PCIe#6_SATA#3)
Intel ME update Low : Disabled(Default)
C High : Enabled C
2014-10-01: V1 +3VS
22P_0402_50V8J Follow skyfall/pixar Direct shorted SATA0GP/GPIO34 U1 PCH_GPIO35 T159@
SATA1GP/GPIO35 V6 ODD_PLUG# ODD_PLUG# RC218 1 2 10K_0402_5%
CM29 SATA2GP/GPIO36 ODD_PLUG# <21>
@ RC317 short@ AC1 MSATA_DET#
HDA_RST_AUDIO# PCH_JTAG_RST# SATA3GP/GPIO37 MSATA_DET# <9>
1 2 0_0201_5% AU62
1 2 XDP_TRST#_CPU PCH_JTAG_TCK AE62 PCH_TRST A12
PCH_JTAG_TDI AD61 PCH_TCK SATA_IREF L11
+1.05VS_VCCSATA3PLL <Page 12>
@ T162 RC39
22P_0402_50V8J PCH_JTAG_RST# @ T166 PCH_JTAG_TDO AE61 PCH_TDI RSVD K10 3K_0402_1%
@ T167 PCH_JTAG_TMS AD62 PCH_TDO RSVD C12 SATA_COMP 1 2
PCH_AL11_RSVD AL11 PCH_TMS
JTAG
SATA_RCOMP U3 SATA_LED# L DG V0.9 SATA_COMP
@ T156
@ T160 PCH_ALC_RSVD AC4 RSVD SATALED SATA_LED# <7,35> Width=12mil
@ T168 XDP_TCK_JTAGX AE63 RSVD Max length=500mil
@ T157 PCH_AV2_RSVD AV2 JTAGX
RSVD

5 OF 19
BDW-ULT-DDR3L-IL_BGA1168
@

+1.05VS_VCCST

1
R6 PCH_JTAG_TCK 51_0402_5% 1 @ 2 RC38 +3V_PCH
R511
U16 @ 10K_0402_5%
1 5

2
NC VCC
EC_+1.05VS_PG 2
<EC output> <33> EC_+1.05VS_PG A 4
XDP_TRST#_CPU Y +1.05VS_PG <4,11> <CPU,XDP,XDP Switch>
RC16 2 @ 1 51_0402_1% 3
R9 <4> XDP_TRST#_CPU GND
B 74AUP1G07GW_TSSOP5 B

RC8 short@
1 2
0_0201_5%
2014-09-26: Reserved bypass RC8
2014-10-14: Bypass U1. EC Need to set OD type
+1.05VS_VCCST
Resistors Resistors
Topolog Description Be st Use for Stuffed ufStuffed
XDP_TDO_CPU RC10 2 1 51_0402_1%
R1d <4> XDP_TDO_CPU

Default Setting: Dual In this topology, the - Run control oper. R1d,R2,R3d, J1s, J2s,
TCK S can Chains CPU JTAG chain will be - ME/Sx debug R4,R5,J1d J3s
(also known as controlled by TCK0 and J2d,J3d* R6,R7,R8,R9
XDP_TCK
R2 <4> XDP_TCK RC15 2 1 51_0402_1% "Shared JTAG" in TCK1 will control J4d and Rs5*
other docum ent) the PCH JTAG chain.

In th is topolog y, PCH -B oundary Scan/ J1s,J2s,J3s** R1d,r3d,J1d,J2d

Single TCK scan chain TDI- TDO and CPU TDI-TDO Manufacturing est R2,R4,R5,R5s** J3d**,J4d,
PIR Item 4 (also known as "Com m on will be chained to form R6,R7,R8,R9
JTAG" in other docum one JTAG scan chain
Check ME update ent) controlled by TCK0
<33> ME_FLASH_EN
A A
2

+1.5VS
G

1 2 RC383 1 3 HDA_SDOUT
1K_0402_1% QC380
D

MESS138W-G_SOT323-3

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RTC,SATA,HDA,JTAG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 6 of 63
5 4 3 2 1
 5 4 3 2 1

CPU_XTAL24_IN

CPU_XTAL24_OUT
RPH14
UCPU1F BDW_ULT_DDR3L(Interleaved) SATA1_PWREN 5 4 2 1
<9> SATA1_PWREN TOUCH_PANEL_PWREN 6 3 1M_0402_5% RC48
<9> TOUCH_PANEL_PWREN TESTLOW2 7 2
Intel #521772 : PCICLKRQ_Usage_Guidelines
Mapping TESTLOW1 8 1
– Eac h PCI ECL KR Qn# needs t o be r out ed t o PCI E Port ( n+1) – New to LPT- LP and what 3 1
C43 A25 CPU_XTAL24_IN 10K_0804_8P4R_5% 3 1
is not clear in EDS. Updated in LPT-LP EDS SU Rev1.5.1 (#508767). C42 CLKOUT_PCIE_N0 XTAL24_IN B25 CPU_XTAL24_OUT GND GND
– Eac h CLK OUT_PCI E[ 5: 0] c an be assi gned t o any PCI ECL KR Qn# CLKOUT_PCIE_P0 XTAL24_OUT 1 1
PCIECLKREQ0# U2 CC9 CC10
PCIECLKRQ0/GPIO18 K21 RC52 4 2 15P_0402_50V8J
B41 RSVD M21 3K_0402_1% 15P_0402_50V8J YC2
A41 CLKOUT_PCIE_N1 RSVD C26 PCH_CLK_BIASREF 1 2
<Page12> 2 2
+1.05VS_AXCK_LCPLL 24MHZ 12PF 20PPM X3G024000DC1H
D PCIECLKREQ1# Y5 CLKOUT_PCIE_P1 DIFFCLK_BIASREF D
<9> PCIECLKREQ1# PCIECLKRQ1/GPIO19 C35 TESTLOW1
CLK_PCIE_LAN# C41 CLOCK TESTLOW_C35 C34 TESTLOW2
<24> CLK_PCIE_LAN# CLK_PCIE_LAN B42 CLKOUT_PCIE_N2 TESTLOW_C34 AK8
LAN(PCIe#3) TESTLOW3
<24> CLK_PCIE_LAN LAN_CLKREQ# AD1 CLKOUT_PCIE_P2 SIGNALS TESTLOW_AK8 AL8 TESTLOW4 TESTLOW3 <9>
<9,24> LAN_CLKREQ# PCIECLKRQ2/GPIO20 TESTLOW_AL8 TESTLOW4 <9>
CLK_PCIE_CR# B38 AN15 CLK_PCI0 EMI@ RC61 1 2 22_0402_5% CLK_PCI_LPC
<25> CLK_PCIE_CR# CLK_PCIE_CR C37 CLKOUT_PCIE_N3 CLKOUT_LPC_0 AP15 CLK_PCI1 EMI@ RC62 1 2 22_0402_5% CLK_PCI_TPM CLK_PCI_LPC <33> <EC>
CardReader(PCIe#4) <25> CLK_PCIE_CR CR_CLKREQ# N1 CLKOUT_PCIE_P3 CLKOUT_LPC_1 CLK_PCI_TPM <32>
<9,25> CR_CLKREQ# PCIECLKRQ3/GPIO21 CLK_CPU_ITP#
B35 T82 @
CLK_PCIE_GPU# A39 CLKOUT_ITPXDP A35 CLK_CPU_ITP T81 @
<39> CLK_PCIE_GPU# CLK_PCIE_GPU B39 CLKOUT_PCIE_N4 CLKOUT_ITPXDP_P
GPU(PCIe#5) <39> CLK_PCIE_GPU GPU_CLKREQ# U5 CLKOUT_PCIE_P4
<9,39> GPU_CLKREQ# PCIECLKRQ4/GPIO22 <XDP CLK reserve TP>
+3V_PCH CLK_PCIE_MINI1# B37 9/17 add RF solution
<23> CLK_PCIE_MINI1# CLK_PCIE_MINI1 A37 CLKOUT_PCIE_N5
+3VS WLAN(PCIe#6_SATA#3) <23> CLK_PCIE_MINI1 MINI1_CLKREQ# T2 CLKOUT_PCIE_P5
<23> MINI1_CLKREQ# PCIECLKRQ5/GPIO23
RPH2 @RF@
4 5 EC_LID_OUT# CM30
3 6 PCH_GPIO16 EC_LID_OUT# <9,33> 1 2 CLK_PCI_LPC
6 OF 19
2 7 SATA_LED# PCH_GPIO16 <9> BDW-ULT-DDR3L-IL_BGA1168
1 8 PCIECLKREQ0# SATA_LED# <6,35> @
2014-09-29: 22P_0402_50V8J
Change GPU_CLKREQ# PU to +3VS on CPU side. BDW_ULT_DDR3L(Interleaved)
10K_0804_8P4R_5% Remove GPU side RG8 UCPU1G @RF@
CM31
RC130 LPC_AD0 AU14 AN2 SMBALERT# 1 2 CLK_PCI_TPM
2 1 MINI1_CLKREQ# <32,33> LPC_AD0 LPC_AD1 AW12 LAD0 SMBALERT/GPIO11 AP2 SMBCLK SMBALERT# <9>
<32,33> LPC_AD1 LPC_AD2 AY12 LAD1 LPC
SMBCLK AH1 SMBDATA SMBCLK <34>
<32,33> LPC_AD2 LPC_AD3 AW11 LAD2 SMBUS SMBDATA AL2 SML0ALERT# SMBDATA <34> 22P_0402_50V8J
10K_0402_5% SML0ALERT# <9>
<32,33> LPC_AD3 LPC_FRAME# AV12 LAD3 SML0ALERT/GPIO60 AN1 SML0CLK
<32,33> LPC_FRAME# LFRAME SML0CLK AK1
RPH11 SML0DATA 2014-09-29:
PCH_SPI_HOLD# 1 8 PCH_SPI_SIO3 SML0DATA AU4 SML1ALERT# Change USB_CR_PWREN to SMK0ALERAT#
C PCH_SPI_SI_R 2 7 PCH_SPI_SI SML1ALERT/PCHHOT/GPIO73 AU3 SML1CLK SML1ALERT# <9> C
PCH_SPI_SO_R 3 6 PCH_SPI_SO SML1CLK/GPIO75 AH3 SML1DATA
PCH_SPI_CS0#_R 4 5 PCH_SPI_CS0# PCH_SPI_CLK AA3 SML1DATA/GPIO74
PCH_SPI_CS0# Y7 SPI_CLK AF2
15_0804_8P4R_5% Y4 SPI_CS0 CL_CLK AD2
PCH_SPI_CLK_R 2 RC368 1 PCH_SPI_CLK AC2 SPI_CS1 SPI C-LINK
CL_DATA AF4
<33> PCH_SPI_CLK_R PCH_SPI_SI AA2 SPI_CS2 CL_RST
2 1@EMI@ 15_0402_5% EMI@ PCH_SPI_SO AA4 SPI_MOSI +3V_PCH
CM18 22P_0402_50V8J PCH_SPI_SIO2 Y6 SPI_MISO
RC382 PCH_SPI_SIO3 AF1 SPI_IO2
PCH_SPI_WP# 2 1 PCH_SPI_SIO2 SPI_IO3
15_0402_5%

RPH12 SML0CLK 1K_0402_5% 1 2 RC72

8 1 PCH_SPI_CS0#_R 7 OF 19
<33> EC_SPI_CS0# 7 2 PCH_SPI_SO_R BDW-ULT-DDR3L-IL_BGA1168 SML0DATA 1 2 RC73
1K_0402_5%
<33> EC_SPI_SO 6 3 @
5 4 PCH_SPI_SI_R RP2
<33> EC_SPI_SI 1 8
SMBDATA
15_0804_8P4R_5% SMBCLK 2 7
SML1DATA 3 6
+3V_PCH SML1CLK 4 5
EON SA000046400 S IC FL 64M EN25Q64-104HIP SOP 8P
MXIC SA00006N100 S IC FL 64M MX25L6473EM2I-10G SOP 8P 2.2K_0804_8P4R_5%
WINBOND SA000039A30 S IC FL 64M W25Q64FVSSIQ SOIC 8P SPI ROM
2

@ RC80
3.3K_0402_5%
SPI ROM 8M Micron SA00005L100 S IC FL 64M N25Q064A13ESEC0F SO8W 8P
+3V_PCH
+3VS +3VS
1

UC2
PCH_SPI_CS0#_R 1 8
CS# VCC

2
PCH_SPI_SO_R 2 7 PCH_SPI_HOLD# 2 1 RC84 3.3K_0402_5%
PCH_SPI_WP# SO/SIO1 HOLD# PCH_SPI_CLK_R 1
B 1 2 3 6 RC78 RC79 B
+3V_PCH WP# SCLK PCH_SPI_SI_R
RC85 3.3K_0402_5% 4 5 CC11 10K_0402_5% 10K_0402_5%
GND SI/SIO0
0.1U_0402_16V7K

2
GD25B64BSIGR 2 @ QC2A

1
SMBCLK 6 1
PCH_SMBCLK <15,16,18>
2N7002EDW_SOT363-6

5
QC2B
SMBDATA 3 4
PCH_SMBDATA <15,16,18>
2N7002EDW_SOT363-6

+3VS

+3VS CPU THERMAL SENSOR

2
2N7002EDW_SOT363-6
0.1U_0402_16V7K

SML1CLK 6 1
EC_SMB_CK2 <18,33,39>
CC127

1 Thermal sensor SMBus address -->100-1_100xb : 0x4C

5
(x=0)Write Address(0x98h) QC6A
(x=1)Read Address(0x99h)
SML1DATA 3 4
2 EC_SMB_DA2 <18,33,39>
UC3 2N7002EDW_SOT363-6
1 8 EC_SMB_CK2
VDD SCLK QC6B
A A
H_THERMDA 2 7 EC_SMB_DA2 THERMAL_ALERT# <33>
CC14 D+ SDATA
1 2 H_THERMDC 3 6 THERMAL_ALERT# 2 1
D- ALERT# +3VS
2200P_0402_50V7K RC44 10K_0402_5%
1 2 CPU_THERM# 4 5
+3VS THERM# GND
RC45 33K_0402_5%

NCT7718W_MSOP8
SA000067P00
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title
Thermal sensor SMBus address -->0111_100xb (0x78h) CLK,SPI,SMB,LPC
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 7 of 63
5 4 3 2 1
 5 4 3 2 1

+RTCVCC
C931 @ DSWODVREN - On Die DSW VR Enable
：E n a bl e
1 2 SUSACK#
H DSWODVREN RC254 2 1 330K_0402_5%
*
：Di s a bl e
D D
0.047U_0402_16V7K DSWODVREN RC255 2 1 330K_0402_5%
L @
Non Deep S3 RC91-->SMT
Deep S3 RC93-->SMT @
UCPU1H BDW_ULT_DDR3L(Interleaved) C930
1 2 0.047U_0402_16V7K
SUSWARN#_R
RC91 1 @ 2 0_0201_5% SYSTEM POWER MANAGEMENT Check with EC, EC doesn't control AOAC_PME# on Cocoa project
<9> SUSWARN#_R
RC93 1 short@ 2 0_0201_5% SUSACK#_R AK2 AW7 DSWODVREN RC3711 2 0_0402_5% AOAC_PME#
<33> SUSACK# SYS_RESET# SUSACK DSWVRMEN
AC3 AV5 PCH_DPWROK_R @
<9> SYS_RESET# SYS_PWROK SYS_RESET DPWROK
AG2 AJ5 WAKE#
<33> SYS_PWROK SYS_PWROK WAKE WAKE# <25>
RC99 1 short@ 2 0_0402_5% PM_PWROK_R AY7 +3V_DSW_P
PCH_PWROK 1 2 APWROK_R AB5 PCH_PWROK
<33> PCH_PWROK PLT_RST#_PCH APWROK PM_CLKRUN#
RC100 short@ 0_0402_5% AG7 V5
PLTRST CLKRUN/GPIO32 AG4 SUS_STAT# T62 @ WAKE# RC98 1 2 1K_0402_5%
SUS_STAT/GPIO61 AE6 SUSCLK
SUSCLK/GPIO62 SUSCLK <23>
AP5 @
PCH_RSMRST# AW6 SLP_S5/GPIO63 PM_SLP_S5# <33>
T142@ SUSCLK RC102 1 2 1K_0402_5%
<33> PCH_RSMRST# RSMRST
Deep S3 <33> PCH_SUSWARN# RC104 1 short@ 2 0_0402_5% SUSWARN#_R AV4 T143@
RC103 1 short@ 2 0_0402_5% PBTN_OUT#_R AL7 SUSWARN/SUSPWRDNACK/GPIO30 AJ6
<33> PBTN_OUT# ACIN_R PWRBTN SLP_S4 PM_SLP_S3# PM_SLP_S4# <33>
1 2 AJ8 AT4
<33,52> ACIN PM_BATLOW# ACPRESENT/GPIO31 SLP_S3 PM_SLP_A# PM_SLP_S3# <33>
DC2 AN4 AL5
CH751H-40PT_SOD323-2 PM_SLP_S0#_R AF3 BATLOW/GPIO72 SLP_A AP4 1 2 0_0201_5%
PCH_SLP_WLAN# AM5 SLP_S0 SLP_SUS PM_SLP_SUS# <33>
AJ7 RC106
@ T178 SLP_WLAN/GPIO29 SLP_LAN short@ RC286 T26 @ PCH_RSMRST# 2 1 10K_0402_5%
T27 @
@
C933 1 2 @ PBTN_OUT#_R C932 1 2 0.047U_0402_16V7K
Non Deep S3 RC286-->@
8 OF 19 Deep S3 RC286-->SMT
0.047U_0402_16V7K BDW-ULT-DDR3L-IL_BGA1168
@
10/15 add RSMRST protect circuit
C C70 1 2 ESD@ PCH_PWROK C
CH751H-40PT_SOD323-2
0.047U_0402_16V7K PCH_RSMRST# 1 2 DC3 PCH_PWROK

CH751H-40PT_SOD323-2
RC112 2 1 SYS_PWROK DC4 2 1 +3V_DSW_P
SPOK <27,53>
100K_0402_5% ACIN_R 2 1
PCH_DPWROK_R RC316 1 20_0201_5% 10K_0402_5% RC101
PCH_DPWROK <33>
short@ RPH6
RC64 PCH_SLP_WLAN#8 1
1 2 PCH_GPIO80 PM_BATLOW# 7 2
<35> HDDHALT_LED# PCH_GPIO9 6 3
BDW_ULT_DDR3L(Interleaved) <9> PCH_GPIO9 PCH_GPIO43
0_0402_5% short@ UCPU1I 5 4
<10> PCH_GPIO43 +3V_PCH

PANEL_BKEN_CPU PD 100K on Page20 10K_0804_8P4R_5%

10/24 100K Change 10K
BKL_PWM_CPU B8 B9 PCH_DDPB_CLK +3VS
<18,19> BKL_PWM_CPU ENBKL A9 EDP_BKLCTL DDPB_CTRLCLK C9 PCH_DDPB_DAT PCH_DDPB_CLK <20>
<33> ENBKL ENVDD_CPU C6 EDP_BKLEN eDP SIDEBAND DDPB_CTRLDATA D9 PCH_DDPB_DAT <20> <HDMI> RC110
<19> ENVDD_CPU EDP_VDDEN DDPC_CTRLCLK D11 PM_CLKRUN# 2 1
DDPC_CTRLDATA
8.2K_0402_5%
PCH_GPIO77 U6
<9> PCH_GPIO77 PCH_GPIO78 P4 PIRQA/GPIO77 C5
GPU_EVENT# N4 PIRQB/GPIO78 DDPB_AUXN B6
<39> GPU_EVENT# PCH_GPIO80 N2 PIRQC/GPIO79 DISPLAY DDPC_AUXN B5
<9> PCH_GPIO80 AOAC_PME# 1 2 AOAC_PME#_R AD4 PIRQD/GPIO80 DDPB_AUXP A6
<33> AOAC_PME# PME PCIE DDPC_AUXP
RC305 @ 0_0402_5%
@ T173 PCH_GPIO55 U7
2 1 TS_RST#_PCH L1 GPIO55
B <19,33> TS_RST# PCH_MC_WAKE# L3 GPIO52 C8 B
RC74 @ 0_0402_5% <HDMI>
PCH_MIC_DET R5 GPIO54 DDPB_HPD A8 PCH_DDPB_HPD <20>
@ T154
PCH_HP_DET L4 GPIO51 DDPC_HPD D6
<9> PCH_HP_DET GPIO53 EDP_HPD EDP_HPD <18>
<eDP HPD>

1
RC5
100K_0402_5%
9 OF 19 2014-09-15:
BDW-ULT-DDR3L-IL_BGA1168
Move EDP_HPD Pull-Down 100k from Translator to CPU Page

2
@
+3VS

RC126 2 1 10K_0402_5% PCH_GPIO78

RC127 2 1 10K_0402_5% GPU_EVENT# @
DIS@ 1 2
RC300 0_0402_5%
RC125 2 1 10K_0402_5% PCH_MC_WAKE#
+3VS
5

UC9
1 PLT_RST#_PCH
<CPU>
P

RC121 1 @ 2 100K_0402_5% TS_RST# PLT_RST# 4 IN1

<23,24,25,32,33,39> PLT_RST# O 2
IN2
G

2014-09-24: GPU_CLKREQ# PU on GPU side MC74VHC1G08DFT2G SC70 5P

3

2014-09-26: Add TS_RST# PD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PM,GPIO,DDI
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 8 of 63
5 4 3 2 1
 5 4 3 2 1

+1.05VS_VCCST

1
UCPU1J BDW_ULT_DDR3L(Interleaved) RC242
1K_0402_5%

short@ RC129

2
0_0402_5%
PCH_GPIO76 P1 D60 H_THERMTRIP#_C 1 H_THEMTRIP#
2
AU2 BMBUSY/GPIO76 THRMTRIP V4 EC_KBRST#
PCH_GPIO12 GPIO8 RCIN/GPIO82 EC_KBRST# <33>
AM7 T4 SERIRQ
EC_LID_OUT# AD6 LAN_PHY_PWR_CTRL/GPIO12 CPU/ SERIRQ AW15 PCH_OPIRCOMP 2 1 SERIRQ <32,33>
D <7,33> EC_LID_OUT# PCH_GPIO16 GPIO15 MISC PCH_OPI_RCOMP D
Y1 AF20 RC131 49.9_0402_1%
1 DIS@ <7>
2 PCH_GPIO16 PCH_GPIO17 T3 GPIO16 RSVD AB21
<39> GC6_FB_EN RC123 DG V2.0 PCH_OPIRCOMP
0_0201_5% UART_WAKE# AD5 GPIO17 RSVD
EC_PME# AN5 GPIO24 Width=12mil,spacing=12mil
<24,33> EC_PME# GPIO27
@ T148 AD7 Max length=500mil
Boot BIOS Strap
2014-09-29: @ T149 AN3 GPIO28
Change BT_ON to PCH_GPIO56 GPIO26 R6 PCH_GPIO83
PCH_GPIO56 AG6 GSPI0_CS/GPIO83 L6 PCH_GPIO84
<10> PCH_GPIO56 GPIO56 GSPI0_CLK/GPIO84
RC108 short@ PCH_GPIO86 Boot BIOS Location
short@ AP1 N6 PCH_GPIO85 1 2
PCH_GPIO58 GPIO57 GSPI0_MISO/GPIO85 PCH_GPIO86 DGPU_PWR_EN <48>
RC119 1 2 0_0201_5% AL4 L8 0 SPI
<39> DGPU_HOLD_RST#
<23> WL_OFF#
WL_OFF#
NMI_DBG#_CPU
AT5 GPIO58
GPIO59
GSPI0_MOSI/GPIO86
GSPI1_CS/GPIO87
R7 0_0201_5% *
AK4 GPIO L5
<33> NMI_DBG#_CPU SDRAM_ID1 GPIO44 GSPI1_CLK/GPIO88 TOUCH_PANEL_PWREN
AB6 N7
SDRAM_ID2 U4 GPIO47 GSPI1_MISO/GPIO89 K2 SATA1_PWREN TOUCH_PANEL_PWREN <7>
SDRAM_ID3 Y3 GPIO48 GSPI_MOSI/GPIO90 J1 PCH_LAN_RST# SATA1_PWREN <7>
SDRAM_ID4 P3 GPIO49 UART0_RXD/GPIO91 K3 PCH_LAN_WAKE# 9/12 reserve DGPU_PWR_EN on GPIO85
2014-09-29: MPHY_PWREN Y2 GPIO50 UART0_TXD/GPIO92 J2 PCH_CR_RST#
No Add 1.05MPHY Power Switch. GPIO71 Just Noraml GPIO PCH_GPIO13 AT3 HSIOPC/GPIO71 SERIAL IO UART0_RTS/GPIO93 G1 PCH_CR_WAKE#
<10> PCH_GPIO13 GPIO13 UART0_CTS/GPIO94
AH4 K4
USB_CAM_PWREN AM4 GPIO14 UART1_RXD/GPIO0 G2
TS_INT# AG5 GPIO25 UART1_TXD/GPIO1 J3
<19> TS_INT# ACCEL_INT# GPIO45 UART1_RST/GPIO2 ODD_DA# +3VS
AG3 J4 2014-10-17:
<32> ACCEL_INT# GPIO46 UART1_CTS/GPIO3 I2C_0_SDA ODD_DA# <21> Chnage PCH_AUDIO_PWREN => PCH_GPIO76
F2 And PU to +3VS
PCH_GPIO9 AM3 I2C0_SDA/GPIO4 F3 I2C_0_SCL I2C_0_SDA <19>
<8> PCH_GPIO9 RPH13
EC_SCI# AM2 GPIO9 I2C0_SCL/GPIO5 G4 I2C_1_SDA I2C_0_SCL <19> GPU_CLKREQ# 4 5
<33> EC_SCI# PCH_GPIO33 GPIO10 I2C1_SDA/GPIO6 I2C_1_SCL <7,39> GPU_CLKREQ# PCH_GPIO77
P2 F1 3 6
PCH_GPIO70 DEVSLP0/GPIO33 I2C1_SCL/GPIO7 PROJECT_ID1 <8> PCH_GPIO77 PCH_GPIO84
@ T158 C4 E3 2 7
PCH_GPIO38 L2 SDIO_POWER_EN/GPIO70 SDIO_CLK/GPIO64 F4 PROJECT_ID2 PCH_GPIO86 1 8
PCH_GPIO39 N5 DEVSLP1/GPIO38 SDIO_CMD/GPIO65 D3 PCH_GPIO66 GPIO66 : Boot strap used for "Top Swap Overide".
HDA_SPKR V2 DEVSLP2/GPIO39 SDIO_D0/GPIO66 E4 PROJECT_ID3 T170@ internal weak pull-down , disabled af t er PLTRST# 10K_0804_8P4R_5%
<28> HDA_SPKR SPKR/GPIO81 SDIO_D1/GPIO67 C3 ODD_PWR
SDIO_D2/GPIO68 E2 PCH_GPIO69 ODD_PWR <21>
C +3V_PCH SDIO_D3/GPIO69 T169@ C
10 OF 19 +3VS
RPH5 4 5 SML1ALERT# BDW-ULT-DDR3L-IL_BGA1168
3 6 SUSWARN#_R SML1ALERT# <7> @ MPHY_PWREN 1 2
RC217
2 7 WL_OFF# SUSWARN#_R <8>
1 8 PCH_GPIO12 10K_0402_5%
+3V_DSW_P
10K_0804_8P4R_5%
+3V_PCH +3VS
+3VS
RPH15 4 5 ACCEL_INT# RPH20
3 6 UART_WAKE# PCH_CR_WAKE# 5 4
2 7 EC_KBRST# PCH_CR_RST# 6 3
1 8 SERIRQ PCH_LAN_WAKE# 7 2
+3V_PCH 10K_0804_8P4R_5% PCH_LAN_RST# 8 1

RPH16 4 5 SMBALERT# @ 10K_0804_8P4R_5%

3 6 EC_SCI# SMBALERT# <7>
2 7 USB_OC0# RPH10
1 8 SML0ALERT# USB_OC0# <10,26> I2C_0_SCL 8 1
SML0ALERT# <7> I2C_0_SDA
10K_0804_8P4R_5% NOTE: the recommended pull-up resistor is 7 2
I2C_1_SCL 6 3
PCH_GPIO42 1 Kohm for 400 KHz speed and I2C_1_SDA
RC278 1 2 0.5 Kohm for 1MHz speed 5 4
PCH_GPIO42 <10>
10K_0402_5%
+3VS short@ 1K_0804_8P4R_5%
@ RC378
RC2791 2 PCH_GPIO33 1 2 DEVSLP0
DEVSLP0 <22> +3V_PCH +3VS
10K_0402_5%
RC2821 @ 2 PCH_GPIO39 0_0201_5% RPH3
10K_0402_5% 2014-09-23: intel PDG 2.0 NMI_DBG#_CPU 5 4
RC1242 UMA@ 1 PCH_GPIO17 Align DEVSLP pin assignment 1 host pin to 1 device pin as follows: PCH_GPIO80 6 3
— SAT A DEVSL P0 t o DEVSL P Port 0; or <8> PCH_GPIO80
10K_0402_5% — SAT A DEVSL P0 t o DEVSL P Port 3 PCH_GPIO76 7 2
B RC1322 1 PCH_GPIO85 — SAT A DEVSL P1 t o DEVSL P Port 1 8 1 B
— SAT A DE VSLP2 t o DE VSLP Port 2
10K_0402_5%
2014-09-24: 10K_0804_8P4R_5%
1. Add RC124 for UMA
2. Stuf f RC123 f or GP U GC6
2014-09-25:
Add PU 10 for PCH_GPIO85(DGPU_PWR_EN)
+3VS
RPH4
4 5 LAN_CLKREQ#
3 6 SYS_RESET# LAN_CLKREQ# <7,24>
2 7 PCIECLKREQ1# SYS_RESET# <8>
1 8 MSATA_DET# PCIECLKREQ1# <7>
T174@
MSATA_DET# <6>
10K_0804_8P4R_5%
RPH18
4 5 PCH_GPIO83 +3VS +3VS +3VS
3 6 PCH_HP_DET +3V_PCH +3VS +3VS +3VS
2 7 PCH_GPIO38 PCH_HP_DET <8> PROJECT_ID3 PROJECT_ID2 PROJECT_ID1

1
1 8 CR_CLKREQ#
CR_CLKREQ# <7,25> 13" (Valrhona) 0 0 0
1

10K_0804_8P4R_5% RC375 RC372 RC374 14" (Lindt) 0 0 1

RC135 RC261 RC262 RC134 10K_0402_5% 10K_0402_5% 10K_0402_5%
RPH1 10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @ @ 15" (Puccini) 0 1 0

2
4 5 USB_CAM_PWREN @ @ @ @ PROJECT_ID3
2

3 6 TESTLOW4 SDRAM_ID1 PROJECT_ID2

TESTLOW4 <7> SDRAM_ID2 PROJECT_ID1
17" (Maison) 0 1 1
2 7 TESTLOW3
1 8 PCH_GPIO58 TESTLOW3 <7> SDRAM_ID3
SDRAM_ID4

1
10K_0804_8P4R_5% 2014-09-23: nVidia Review
1

RC119: Stuf f by def ault RC376 RC373 RC377

PCH_GPIO58: pull low 10K by default, not pull high RC263 RC264 RC265 RC381 10K_0402_5% 10K_0402_5% 10K_0402_5%
10K_0402_5% 10K_0402_5% 10K_0402_5% 10K_0402_5% @
A A

2
2

+3V_DSW_P
PCH_GPIO27 (Have internal Pull-High)
RC277 1 2 EC_PME# High: VCCVRM VR Enable
Low: VCCVRM VR Disable
10K_0402_5%
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title
+3VS

ODD_DA# THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GPIO,UART,I2C
RC380 1 2 AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
10K_0402_5%
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 9 of 63
5 4 3 2 1
 5 4 3 2 1

UCPU1K BDW_ULT_DDR3L(Interleaved)

change AC cap to 0.22uF review by Nvidia

PEG_PRX_C_DTX_N0 F10 AN8
<39> PEG_PRX_C_DTX_N0 PEG_PRX_C_DTX_P0 PERN5_L0 USB2N0 USB20_N0 <26>
<39> PEG_PRX_C_DTX_P0 E10 AM8 USB2.0/USB3.0
PERP5_L0 USB2P0 USB20_P0 <26>
D 0.22U_0402_6.3V6K DIS@ 1 2 CC90 PEG_PTX_DRX_N0 C23 AR7 D
<39> PEG_PTX_C_DRX_N0 PEG_PTX_DRX_P0 PETN5_L0 USB2N1 USB20_N1 <26>
0.22U_0402_6.3V6K DIS@ 1 2 CC91 C22 AT7 USB2.0/USB3.0 EHCI Port1 : DebugPort
<39> PEG_PTX_C_DRX_P0 PETP5_L0 USB2P1 USB20_P1 <26>
PEG_PRX_C_DTX_N1 F8 AR8
<39> PEG_PRX_C_DTX_N1 PEG_PRX_C_DTX_P1 PERN5_L1 USB2N2 USB20_N2 <27>
<39> PEG_PRX_C_DTX_P1 E8 AP8 USB2.0/USB3.0(ChargingPort)
PERP5_L1 USB2P2 USB20_P2 <27>
0.22U_0402_6.3V6K DIS@ 1 2 CC89 PEG_PTX_DRX_N1 B23 AR10
<39> PEG_PTX_C_DRX_N1 PEG_PTX_DRX_P1 PETN5_L1 USB2N3 USB20_N3 <26>
0.22U_0402_6.3V6K DIS@ 1 2 CC92 A23 AT10 USB2.0/USB3.0 15"/17" only
<39> PEG_PTX_C_DRX_P1 PETP5_L1 USB2P3 USB20_P3 <26>
PEG(PCIe#5) PEG_PRX_C_DTX_N2 H10 AM15
<39> PEG_PRX_C_DTX_N2 PEG_PRX_C_DTX_P2 PERN5_L2 USB2N4 USB20_N4 <23>
<39> PEG_PRX_C_DTX_P2 G10 AL15 WLAN/BT
PERP5_L2 USB2P4 USB20_P4 <23>
0.22U_0402_6.3V6K DIS@ 1 2 CC93 PEG_PTX_DRX_N2 B21 AM13
<39> PEG_PTX_C_DRX_N2 PEG_PTX_DRX_P2 PETN5_L2 USB2N5 USB20_N5 <19>
0.22U_0402_6.3V6K DIS@ 1 2 CC94 C21 AN13 Camera
<39> PEG_PTX_C_DRX_P2 PETP5_L2 USB2P5 USB20_P5 <19>
PEG_PRX_C_DTX_N3 E6 AP11
<39> PEG_PRX_C_DTX_N3 PEG_PRX_C_DTX_P3 PERN5_L3 USB2N6
<39> PEG_PRX_C_DTX_P3 F6 AN11 Touch screen
PERP5_L3 USB2P6
0.22U_0402_6.3V6K DIS@ 1 2 CC95 PEG_PTX_DRX_N3 B22 AR13
<39> PEG_PTX_C_DRX_N3 PEG_PTX_DRX_P3 PETN5_L3 USB2N7 USB20_N7 <35>
0.22U_0402_6.3V6K DIS@ 1 2 CC96 A21 AP13 Finger print
<39> PEG_PTX_C_DRX_P3 PETP5_L3 USB2P7 USB20_P7 <35>
PCIE_PRX_DTX_N3 G11
<24> PCIE_PRX_DTX_N3 PCIE_PRX_DTX_P3 PERN3
<24> PCIE_PRX_DTX_P3 F11 G20 USB3_RX1_N <26>
PERP3 USB3RN1 H20
LAN(PCIe#3) CC12 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N3 C29 USB3RP1 USB3_RX1_P <26>
<24> PCIE_PTX_C_DRX_N3
CC13 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P3 B30 PETN3 PCIE USB C33
USB2.0/USB3.0
<24> PCIE_PTX_C_DRX_P3 PETP3 USB3TN1 USB3_TX1_N <26>
B34
PCIE_PRX_DTX_N4 USB3TP1 USB3_TX1_P <26>
<25> PCIE_PRX_DTX_N4 F13
PCIE_PRX_DTX_P4 G13 PERN4 E18
<25> PCIE_PRX_DTX_P4 PERP4 USB3RN2 USB3_RX2_N <26>
C F18 USB3_RX2_P <26>
C
CC16 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_N4 B29 USB3RP2
CardReader(PCIe#4) <25> PCIE_PTX_C_DRX_N4
CC17 2 1 0.1U_0402_16V7K PCIE_PTX_DRX_P4 A29 PETN4 B33
USB2.0/USB3.0(ChargingPort)
<25> PCIE_PTX_C_DRX_P4 PETP4 USB3TN2 USB3_TX2_N <26>
A33
USB3TP2 USB3_TX2_P <26>
<27> USB3_RX3_N G17
F17 PERN1/USB3RN3
<27> USB3_RX3_P PERP1/USB3RP3
USB2.0/USB3.0 C30
<27> USB3_TX3_N PETN1/USB3TN3
C31 AJ10 USBRBIAS RC148 1 2 22.6_0402_1%
<27> USB3_TX3_P PETP1/USB3TP3 USBRBIAS AJ11
F15 USBRBIAS AN10
<26> USB3_RX4_N PERN2/USB3RN4 RSVD
<26> USB3_RX4_P G15 AM10 DG V2.0 USBRBIAS
PERP2/USB3RP4 RSVD
15"/17" only USB2.0/USB3.0 B31 Trace width=50ohm and spacing=15mil
<26> USB3_TX4_N PETN2/USB3TN4
<26> USB3_TX4_P
A31
PETP2/USB3TP4
Max length=500mil
AL3 USB_OC0#
OC0/GPIO40 USB_OC1# USB_OC0# <9,26>
AT1 USB_OC1# <27>
OC1/GPIO41 AH2 PCH_GPIO42
OC2/GPIO42 PCH_GPIO43 PCH_GPIO42 <9>
RC151 E15 AV3
RSVD OC3/GPIO43 PCH_GPIO43 <8>
3K_0402_1% E13
1 2 PCH_PCIE_RCOMP A27 RSVD +3V_PCH
<Page12> +1.05VS_VCCUSB3PLL
B27 PCIE_RCOMP
PCIE_IREF RPH9
PCH_GPIO56 5 4
<9> PCH_GPIO56 PCH_GPIO13
DG V2.0 PCIE_RCOMP <9> PCH_GPIO13 6 3
11 OF 19 USB_OC1# 7 2
Width=12mil,spacing=12mil BDW-ULT-DDR3L-IL_BGA1168 8 1
Max length=500mil @
OC#: Signals must NOT f l oat if t hey ar e not bei ng used. 10K_0804_8P4R_5%
B B
intel BDW PDG v2.0
Overcurrent Pin Default Usage:
OC0# : Port0,1
OC1# : Port 2,3
OC2# : Port 4,5
OC3# : Port 6,7

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PCIE,USB
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 10 of 63
5 4 3 2 1
 5 4 3 2 1

+VCC_CORE@10000mA
+VCC_CORE
UCPU1L BDW_ULT_DDR3L(Interleaved)

+1.35V_VDDQ L59 C36

J58 RSVD VCC C40
RSVD VCC C44
2500mA AH26 VCC C48
AJ31 VDDQ VCC C52
AJ33 VDDQ VCC C56
D AJ37 VDDQ VCC E23 D
AN33 VDDQ VCC E25
AP43 VDDQ VCC E27
AR48 VDDQ VCC E29
AY35 VDDQ VCC E31
AY40 VDDQ VCC E33
AY44 VDDQ VCC E35
+VCC_CORE AY50 VDDQ VCC E37
+1.05VS_VCCST VDDQ VCC E39
DG V0.5 H_CPU_SVIDALRT# F59 VCC E41
L RC154 close to CPU<300mil
VCC_SENSE N58 VCC
RSVD
VCC
VCC
E43
Max length=1000~2000mil PH on power page AC58 E45
SVID ALERT RSVD VCC

1
E47
RC154 VCCSENSE E63 VCC E49
<PWR VR12.6> <56> VCCSENSE
AB23 VCC_SENSE VCC E51
75_0402_5% A59 RSVD VCC E53
+VCCIO_OUT VCCIO_OUT VCC
<VR IV and CPU> E20 E55
+VCCIOA_OUT

2
AD23 VCCIOA_OUT VCC E57
H_CPU_SVIDALRT#
<EDP_COMP power rail> RSVD VCC
<PWR VR12.6> RC1551 2 AA23 F24
<56> VR_SVID_ALRT# AE59 RSVD VCC F28
43_0402_1%
RSVD VCC F32
H_CPU_SVIDALRT# L62 VCC F36
+1.05VS_VCCST VR_SVID_CLK N63 VIDALERT HSW ULT POWER VCC F40
<56> VR_SVID_CLK VR_SVID_DAT VIDSCLK VCC
L63 F44
SVID DATA <4,6> +1.05VS_PG
B59 VIDSOUT
VCCST_PWRGD
VCC
VCC
F48
1

F60 F52
<56> VR12.5_VR_ON VR12.6PG_MCP VR_EN VCC
RC156 VGATE RC87 1 2 C59 F56
<56> VGATE VR_READY VCC G23
130_0402_1% short@ 0_0402_5%
D63 VCC G25
CPU_PWR_DEBUG H59 VSS VCC G27
2014-09-23:
2

P62 PWR_DEBUG VCC G29

1.Follow intel VR12.6 and skyfall HSW VSS VCC
P60 G31
C VR_SVID_DAT 2.Remove UC8(74AUP1G07GW Buf f er) and RC288( 10k) RSVD_TP VCC C
<PWR VR12.6> P61 G33
<56> VR_SVID_DAT 3.Need to make sure VGATE is Pull-High 1.5kohm to VR_ON N59 RSVD_TP VCC G35
N61 RSVD_TP VCC G37
T59 RSVD_TP VCC G39
AD60 RSVD VCC G41
AD59 RSVD VCC G43
AA59 RSVD VCC G45
AE60 RSVD VCC G47
AC59 RSVD VCC G49
AG58 RSVD VCC G51
+VCCIO_OUT +1.05VS_VCCST U59 RSVD VCC G53
@ V59 RSVD VCC G55
RC294 1 2 0_0402_5% +VCC_CORE RSVD VCC G57
+1.05VS 600mA AC22 VCC H23
AE22 VCCST VCC J23
AE23 VCCST VCC K23
VCCST VCC K57
L DG V0.5 VIDSOUT AB57 VCC L22
RC156 close to CPU<500mil AD57 VCC VCC M23
VCC VCC
Max length=1000~2000mil AG57
VCC VCC
M57
C24 P57
C28 VCC VCC U57
C32 VCC VCC W57
VCC VCC
12 OF 19
BDW-ULT-DDR3L-IL_BGA1168
@

+1.05VS_VCCST

B +1.05VS +1.05VS_VCCST +1.35V_VDDQ +1.35V_VDDQ <PV> Reserve CC24 B

150_0402_5%
1

330U 2V D2 LESR9M EEFSX H1.9

CC24
short@
RC166

2.2U_0402_6.3V6M
CC20

2.2U_0402_6.3V6M
CC21

2.2U_0402_6.3V6M
CC22

2.2U_0402_6.3V6M
CC23

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M
RC2231 2 1 SGA20331E10
22U_0805_6.3V6M

1U_0402_6.3V6K

1 1 1 1 1 1 @ 1 1 @ 1 1 @
0_0805_5% +

CC26

CC27

CC28

CC29

CC30

CC31
1 1 @
2

CC71

CPU_PWR_DEBUG 2 2 2 2 2 2 2 2 2 2 2
CC72

@
2 2
10K_0402_5%
1

@
RC167

<Cocoa> Del reserve CC25 330u OSCON cap

2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 11 of 63

5 4 3 2 1
 5 4 3 2 1

+1.05VS_VCCUSB3PLL short@
+1.05VS_VCCHSIO

1U_0402_6.3V6K
+1.05VS_MODPHY RC1681 2 short@
RC170 +3V_DSW_PRTCSUS RC1692 1 0_0402_5%
+1.05VS_VCCUSB3PLL 1 +3V_PCH

1U_0402_6.3V6K

1U_0402_6.3V6K
1 2 0_0805_5% 1 1
+1.05VS_MODPHY

47U_0805_6.3V6M

CC32
CC33

CC34
1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30%
2
1 1 2 2

CC35

CC36
+RTCVCC +RTCVCC
UCPU1M BDW_ULT_DDR3L(Interleaved)
2 2

0.1U_0402_16V7K
CC37

1U_0402_6.3V6K
K9 1 1
L10 VCCHSIO
VCCHSIO

CC39
M9
D N8 VCCHSIO HSIO RTC AH11 @ D
+1.05VS_VCCSATA3PLL +1.05VS VCC1_05 VCCSUS3_3 2 2

1U_0402_6.3V6K
1 P9 AG10
+1.05VS_VCCUSB3PLL B18 VCC1_05 VCCRTC AE7 CC40 1 2 0.1U_0402_16V7K
+1.05VS_VCCSATA3PLL VCCUSB3PLL DCPRTC

CC41
RC171 B11
1 2 +1.05VS_VCCSATA3PLL 2014-09-19 : Change Use +1.05VS VCCSATA3PLL
+1.05VS_MODPHY 2

47U_0805_6.3V6M

1U_0402_6.3V6K
2.2UH_LQM2MPN2R2NG0L_30% RC173 Y20 SPI Y8 SPI ROM power rail
+1.05VS_APPLOPI RSVD VCCSPI +3V_PCH
1 1 0_0402_5% 1 @ 2 AA21 OPI 1
CC42 +1.05VS VCCAPLL
W21
VCCAPLL

CC43
AG14 CC44 @
VCCASW +1.05VS
2 @1 AG13 0.1U_0402_16V7K
2 2 10U_0603_6.3V6M CC45 VCCASW 2
+1.05V_DCPSUS

10U_0603_6.3V6M
USB3

1U_0402_6.3V6K

1U_0402_6.3V6K
2 @1 J13
1U_0402_6.3V6K CC46 DCPSUS3 J11
VCC1_05 +1.05VS
H11 1 1 1
HDA VCC1_05

CC48

CC49

CC50
+VCCSUSHDA AH14 H15
VCCHDA VCC1_05

1U_0402_6.3V6K
1 AE8 RC174 CC52
short@ VCC1_05 AF22 5.11_0402_1% 1U_0402_6.3V6K
VCC1_05 2 2 2

CC51
RC172 1 2 0_0402_5% AH13 VRM AG19 2 1 1 2
<DB>Aduio code power rail +1.5VS DCPSUS2 CORE DCPSUSBYP AG20 short@
2 DCPSUSBYP AE9 +1.05VS_VCCASW RC1751 2
VCCASW +1.05VS
RC176 AF9
+1.05VS_APPLOPI VCCASW

22U_0805_6.3V6M
1U_0402_6.3V6K
1 2 AC9 AG8 1 1 0_0805_5%
+1.05VS +3V_PCH VCCSUS3_3 VCCASW +1.05V_DCPSUS
22U_0805_6.3V6M

CC53

CC54
AA9 GPIO/LPC AD10
+3V_DSW_P VCCSUS3_3 DCPSUS1

22U_0805_6.3V6M
1U_0402_6.3V6K

CC55
2.2UH_LQM2MPN2R2NG0L_30% 1 AH10 AD8
V8 VCCDSW3_3 DCPSUS1
1 1 VCC3_3 2 2
CC57

W9
+3VS VCC3_3

22U_0805_6.3V6M
CC58

CC59
1 J15
2 THERMAL SENSOR VCCTS1_5 +1.5VS
K14
2 2 VCC3_3 +3VS
K16
VCC3_3
2 1 2
C +1.05VS_AXCKDCB J18 CC76 0.1U_0402_16V7K C
K19 VCCCLK SERIAL IO U8 +3V_1V8_SDIO
+1.05VS_AXCK_LCPLL VCCCLK VCCSDIO

1U_0402_6.3V6K
RC280 A20 T9 RC178 short@
1 2 +V1.05S_SSCF100 +V1.05S_SSCF100 J17 VCCACLKPLL VCCSDIO 1 2 0_0603_5%
+1.05VS +V1.05S_SSCFF VCCCLK 1 +3VS
R21
VCCCLK LPT LP POWER

CC60
1U_0402_6.3V6K

short@ T21
0_0603_5% K18 VCCCLK SUS OSCILLATOR AB8 +1.05V_AOSCSUS
1 RSVD DCPSUS4 2
M20
RSVD
CC61

V21
RC281 AE20 RSVD AC20
2 +V1.05S_SSCFF +3V_PCH VCCSUS3_3 RSVD
1 2 AE21 AG16
+1.05VS VCCSUS3_3 VCC1_05
1U_0402_6.3V6K

USB2 AG17 @
VCC1_05 +1.05VS

1U_0402_6.3V6K
short@ 1 RC180
0_0603_5% +1.05V_AOSCSUS 1 2
1 +1.05VS
CC62

CC65

1U_0402_6.3V6K
13 OF 19 2.2UH_LQM2MPN2R2NG0L_30%
2

100U_1206_6.3V6K
BDW-ULT-DDR3L-IL_BGA1168
2 1 1
@

CC67
+3V_DSW_P

CC66
RC179
+1.05VS_AXCKDCB Deep S3 and Non Deep S3 2 2
47U_0805_6.3V6M

1 2 @
+1.05VS
short@
1U_0402_6.3V6K

2.2UH_LQM2MPN2R2NG0L_30% 1 1 RC285 1 2 0_0402_5% Deep S3 RC285-->SMT Total 1.05VS=1838+2274=4111mA 2014-09-19 :

+3VALW 1. Change Use +1.05VS
CC63

2. Stuffed CC66 by following CRB.

2 0_0402_5% +3V_DSW_P
CC64

RC182 1 Non Deep S3 RC182-->SMT

+3V_PCH Total 1.5VS=3mA 3. Design Guide : Required only on external SUS.

2 2 1

1U_0402_6.3V6K
+1.05VS_AXCK_LCPLL
@ Total 1.8VS=7mA

CC70
2 Total 3VS=0mA
RC181
1 2 +1.05VS_AXCK_LCPLL
+1.05VS Total 3VALW=200+62=262mA
47U_0805_6.3V6M

B B
1U_0402_6.3V6K

2.2UH_LQM2MPN2R2NG0L_30% Total 3V_PCH=99mA

1 1
CC68

Total 1.05V=540+109=649mA
CC69

2 2

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Power
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 12 of 63
5 4 3 2 1
 5 4 3 2 1

UCPU1N BDW_ULT_DDR3L(Interleaved)

A11 AJ35 UCPU1O BDW_ULT_DDR3L(Interleaved)

A14 VSS VSS AJ39
A18 VSS VSS AJ41 AP22 AV59
A24 VSS VSS AJ43 AP23 VSS VSS AV8
D D
A28 VSS VSS AJ45 AP26 VSS VSS AW16
A32 VSS VSS AJ47 AP29 VSS VSS AW24
A36 VSS VSS AJ50 AP3 VSS VSS AW33
A40 VSS VSS AJ52 AP31 VSS VSS AW35
A44 VSS VSS AJ54 AP38 VSS VSS AW37
A48 VSS VSS AJ56 AP39 VSS VSS AW4 UCPU1P BDW_ULT_DDR3L(Interleaved)
A52 VSS VSS AJ58 AP48 VSS VSS AW40 H17
A56 VSS VSS AJ60 AP52 VSS VSS AW42 D33 VSS H57
AA1 VSS VSS AJ63 AP54 VSS VSS AW44 D34 VSS VSS J10
AA58 VSS VSS AK23 AP57 VSS VSS AW47 D35 VSS VSS J22
AB10 VSS VSS AK3 AR11 VSS VSS AW50 D37 VSS VSS J59
AB20 VSS VSS AK52 AR15 VSS VSS AW51 D38 VSS VSS J63
AB22 VSS VSS AL10 AR17 VSS VSS AW59 D39 VSS VSS K1
AB7 VSS VSS AL13 AR23 VSS VSS AW60 D41 VSS VSS K12
AC61 VSS VSS AL17 AR31 VSS VSS AY11 D42 VSS VSS L13
AD21 VSS VSS AL20 AR33 VSS VSS AY16 D43 VSS VSS L15
AD3 VSS VSS AL22 AR39 VSS VSS AY18 D45 VSS VSS L17
AD63 VSS VSS AL23 AR43 VSS VSS AY22 D46 VSS VSS L18
AE10 VSS VSS AL26 AR49 VSS VSS AY24 D47 VSS VSS L20
AE5 VSS VSS AL29 AR5 VSS VSS AY26 D49 VSS VSS L58
AE58 VSS VSS AL31 AR52 VSS VSS AY30 D5 VSS VSS L61
AF11 VSS VSS AL33 AT13 VSS VSS AY33 D50 VSS VSS L7
AF12 VSS VSS AL36 AT35 VSS VSS AY4 D51 VSS VSS M22
AF14 VSS VSS AL39 AT37 VSS VSS AY51 D53 VSS VSS N10
AF15 VSS VSS AL40 AT40 VSS VSS AY53 D54 VSS VSS N3
AF17 VSS VSS AL45 AT42 VSS VSS AY57 D55 VSS VSS P59
AF18 VSS VSS AL46 AT43 VSS VSS AY59 D57 VSS VSS P63
AG1 VSS VSS AL51 AT46 VSS VSS AY6 D59 VSS VSS R10
C AG11 VSS VSS AL52 AT49 VSS VSS B20 D62 VSS VSS R22 C
AG21 VSS VSS AL54 AT61 VSS VSS B24 D8 VSS VSS R8
AG23 VSS VSS AL57 AT62 VSS VSS B26 E11 VSS VSS T1
AG60 VSS VSS AL60 AT63 VSS VSS B28 E17 VSS VSS T58
AG61 VSS VSS AL61 AU1 VSS VSS B32 F20 VSS VSS U20
AG62 VSS VSS AM1 AU16 VSS VSS B36 F26 VSS VSS U22
AG63 VSS VSS AM17 AU18 VSS VSS B4 F30 VSS VSS U61
AH17 VSS VSS AM23 AU20 VSS VSS B40 F34 VSS VSS U9
AH19 VSS VSS AM31 AU22 VSS VSS B44 F38 VSS VSS V10
AH20 VSS VSS AM52 AU24 VSS VSS B48 F42 VSS VSS V3
AH22 VSS VSS AN17 AU26 VSS VSS B52 F46 VSS VSS V7
AH24 VSS VSS AN23 AU28 VSS VSS B56 F50 VSS VSS W20
AH28 VSS VSS AN31 AU30 VSS VSS B60 F54 VSS VSS W22
AH30 VSS VSS AN32 AU33 VSS VSS C11 F58 VSS VSS Y10
AH32 VSS VSS AN35 AU51 VSS VSS C14 F61 VSS VSS Y59
AH34 VSS VSS AN36 AU53 VSS VSS C18 G18 VSS VSS Y63
AH36 VSS VSS AN39 AU55 VSS VSS C20 G22 VSS VSS
AH38 VSS VSS AN40 AU57 VSS VSS C25 G3 VSS
AH40 VSS VSS AN42 AU59 VSS VSS C27 G5 VSS V58
AH42 VSS VSS AN43 AV14 VSS VSS C38 G6 VSS VSS AH46
AH44 VSS VSS AN45 AV16 VSS VSS C39 G8 VSS VSS V23
AH49 VSS VSS AN46 AV20 VSS VSS C57 H13 VSS VSS E62
AH51 VSS VSS AN48 AV24 VSS VSS D12 VSS VSS_SENSE AH16
VSSSENSE <56> <PWR VR12.6>
AH53 VSS VSS AN49 AV28 VSS VSS D14 16 OF 19 VSS
AH55 VSS VSS AN51 AV33 VSS VSS D18 BDW-ULT-DDR3L-IL_BGA1168
AH57 VSS VSS AN52 AV34 VSS VSS D2 @
AJ13 VSS VSS AN60 AV36 VSS VSS D21
AJ14 VSS VSS AN63 AV39 VSS VSS D23
AJ23 VSS VSS AN7 AV41 VSS VSS D25
B AJ25 VSS VSS AP10 AV43 VSS VSS D26 B
AJ27 VSS VSS AP17 AV46 VSS VSS D27
AJ29 VSS VSS AP20 AV49 VSS VSS D29
VSS VSS AV51 VSS VSS D30
AV55 VSS VSS D31
VSS 15 OF 19 VSS
14 OF 19 BDW-ULT-DDR3L-IL_BGA1168
BDW-ULT-DDR3L-IL_BGA1168 @
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GND/VSSSEN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 13 of 63
5 4 3 2 1
 5 4 3 2 1

UCPU1Q BDW_ULT_DDR3L(Interleaved) CFG4

1
DC_TEST_AY2_AW 2 AY2 A3 TP_DC_TEST_A3_B3
DC_TEST_AY3_AW 3 AY3 DAISY_CHAIN_NCTF_AY2 DAISY_CHAIN_NCTF_A3 A4 RC185
AY60 DAISY_CHAIN_NCTF_AY3 DAISY_CHAIN_NCTF_A4 1K_0402_1%
DC_TEST_AY61_AW 61 AY61 DAISY_CHAIN_NCTF_AY60 A60

2
DC_TEST_AY61_AW 62 AY62 DAISY_CHAIN_NCTF_AY61 DAISY_CHAIN_NCTF_A60 A61 DC_TEST_A61_B61
B2 DAISY_CHAIN_NCTF_AY62 DAISY_CHAIN_NCTF_A61 A62
TP_DC_TEST_A3_B3 B3 DAISY_CHAIN_NCTF_B2 DAISY_CHAIN_NCTF_A62 AV1
DC_TEST_A61_B61 B61 DAISY_CHAIN_NCTF_B3 DAISY_CHAIN_NCTF_AV1 AW1
DC_TEST_B62_B63 B62 DAISY_CHAIN_NCTF_B61 DAISY_CHAIN_NCTF_AW1 AW2 DC_TEST_AY2_AW 2
B63 DAISY_CHAIN_NCTF_B62 DAISY_CHAIN_NCTF_AW2 AW3 DC_TEST_AY3_AW 3
D
DC_TEST_C1_C2 C1 DAISY_CHAIN_NCTF_B63 DAISY_CHAIN_NCTF_AW3 AW61DC_TEST_AY61_AW 61 Display Port Presence Strap D
C2 DAISY_CHAIN_NCTF_C1 DAISY_CHAIN_NCTF_AW61 AW62DC_TEST_AY61_AW 62
DAISY_CHAIN_NCTF_C2 DAISY_CHAIN_NCTF_AW62 AW63
17 OF 19 DAISY_CHAIN_NCTF_AW63 1 : Disabled; No Physical Display Port
BDW-ULT-DDR3L-IL_BGA1168
@ CFG4 at t ac hed t o E mbedded Dis pl ay Port
UCPU1R BDW_ULT_DDR3L(Interleaved)
0 : Enabled; An external Display Port device is
* connected to the Embedded Display Port
N23
RSVD R23
RSVD T23
AT2 RSVD
RSVD U10
AU44 RSVD
AV44 RSVD
D15 RSVD
RSVD AL1
RSVD AM11
RSVD AP7
F22 RSVD
RSVD AU10
H22 RSVD
RSVD AU15
J21 RSVD
RSVD AW14
RSVD AY14
RSVD

18 OF 19
BDW-ULT-DDR3L-IL_BGA1168
@

UCPU1S BDW_ULT_DDR3L(Interleaved)
C C

@ T59 CFG0 AC60 AV63

@ T60 CFG1 AC62 CFG0 RSVD_TP AU63
@ T61 CFG2 AC63 CFG1 RSVD_TP
@ T63 CFG3 AA63 CFG2
@ T64 CFG4 AA60 CFG3 C63
@ T65 CFG5 Y62 CFG4 RSVD_TP C62
@ T66 CFG6 Y61 CFG5 RSVD_TP B43
@ T67 CFG7 Y60 CFG6 RSVD
@ T68 CFG8 V62 CFG7 A51
@ T69 CFG9 V61 CFG8 RSVD_TP B51
@ T70 CFG10 V60 CFG9 RSVD_TP
@ T71 CFG11 U60 CFG10 L60
@ T72 CFG12 T63 CFG11 RSVD_TP
@ T73 CFG13 T62 CFG12 RESERVED N60
@ T74 CFG14 T61 CFG13 RSVD
@ T75 CFG15 T60 CFG14 W23
CFG15 RSVD Y22 MCP_RSVD_29 RC296 2 @ 1 49.9_0402_1%
@ T76 CFG16 AA62 RSVD AY15 PROC_OPI_COMP RC186 2 1 49.9_0402_1%
@ T77 CFG18 U63 CFG16 PROC_OPI_RCOMP L DG V0.9 PROC_OPI_COMP
@ T78 CFG17 AA61 CFG18 AV62 Width=12mil,spacing=12mil
CFG17 RSVD
@ T85 CFG19 U62
CFG19 RSVD
D58 Max length=500mil
2 1 CFG_RCOMP V63 P22
RC188 49.9_0402_1% CFG_RCOMP VSS N21
B A5 VSS B
RSVD P20
E1 RSVD R20
D1 RSVD RSVD
J20 RSVD
H18 RSVD
1 2 TD_IREF B12 RSVD
RC191 8.2K_0402_5% TD_IREF
19 OF 19
BDW-ULT-DDR3L-IL_BGA1168
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
RSVD/CFG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 14 of 63
5 4 3 2 1
 5 4 3 2 1

+V_VDDR_REFA_DQ +1.35V_VDDQ +1.35V_VDDQ

+1.35V_VDDQ

JDIMM1 2 2
+V_VDDR_REFA_DQ 1 2
3 VREF-DQ VSS1 4 DDR_A_D4 C239 C238
DDR_A_D0 VSS2 DQ4 DDR_A_D5

0.1U_0402_16V7K
5 6 82P_0402_50V8J 68P_0402_50V8J
D <5> DDR_A_D[0..63] DDR_A_D1 DQ0 DQ5 1 1 D

CD1
1 7 8 RF@ RF@
9 DQ1 VSS3 10 DDR_A_DQS#0
<5> DDR_A_DQS[0..7] VSS4 DQS0# DDR_A_DQS0
11 12
13 DM0 DQS0 14
<5> DDR_A_DQS#[0..7] 2 DDR_A_D2 VSS5 VSS6 DDR_A_D6
15 16
DDR_A_D3 17 DQ2 DQ6 18 DDR_A_D7
<5> DDR_A_MA[0..15] DQ3 DQ7
19 20
DDR_A_D8 21 VSS7 VSS8 22 DDR_A_D12
DDR_A_D9 23 DQ8 DQ12 24 DDR_A_D13
25 DQ9 DQ13 26
DDR_A_DQS#1 27 VSS9 VSS10 28
DDR_A_DQS1 29 DQS1# DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <4,16>
31 32 1
DDR_A_D10 33 VSS11 VSS12 34 DDR_A_D14 @ESD@
DDR_A_D11 35 DQ10 DQ14 36 DDR_A_D15 CD99 +1.35V_VDDQ
37 DQ11 DQ15 38
DDR_A_D16 DDR_A_D20 0.1U_0402_16V7K
39 VSS13 VSS14 40 2
DDR_A_D17 41 DQ16 DQ20 42 DDR_A_D21
43 DQ17 DQ21 44 +5VALW QD1
DDR_A_DQS#2 45 VSS15 VSS16 46 BSS138_NL_SOT23-3
DDR_A_DQS2 47 DQS2# DM2 48
49 DQS2 VSS17 50 DDR_A_D22 1 3 RD20 1 2 66.5_0402_1% M_ODT0

S
VSS18 DQ22

1
DDR_A_D18 51 52 DDR_A_D23
DDR_A_D19 53 DQ18 DQ23 54 RD21 RD22 1 2 66.5_0402_1% M_ODT1
55 DQ19 VSS19 56 DDR_A_D28

G
2
DDR_A_D24 57 VSS20 DQ28 58 DDR_A_D29 220K_0402_5% RD23 1 2 66.5_0402_1% M_ODT2
DDR_A_D25 DQ24 DQ29 M_ODT2 <16>
59 60

2
61 DQ25 VSS21 62 DDR_A_DQS#3 RD24 1 2 66.5_0402_1% M_ODT3
VSS22 DQS3# DDR_A_DQS3 M_ODT3 <16>
63 64
65 DM3 DQS3 66
VSS23 VSS24

1
DDR_A_D26 67 68 DDR_A_D30 @
DDR_A_D27 69 DQ26 DQ30 70 DDR_A_D31 RD25 SM_PG_CTRL
DQ27 DQ31 SM_PG_CTRL <4>
71 72
VSS25 VSS26 2M_0402_5%
DDR_CKE0_DIMMA 73 74 DDR_CKE1_DIMMA
<5> DDR_CKE0_DIMMA DDR_CKE1_DIMMA <5>

2
75 CKE0 CKE1 76
77 VDD1 VDD2 78 DDR_A_MA15
DDR_A_BS2 79 NC1 A15 80 DDR_A_MA14
<5> DDR_A_BS2 BA2 A14
81 82
DDR_A_MA12 83 VDD3 VDD4 84 DDR_A_MA11
DDR_A_MA9 85 A12/BC# A11 86 DDR_A_MA7
87 A9 A7 88
C DDR_A_MA8 VDD5 VDD6 DDR_A_MA6 C
89 90
DDR_A_MA5 91 A8 A6 92 DDR_A_MA4
93 A5 A4 94
DDR_A_MA3 95 VDD7 VDD8 96 DDR_A_MA2
DDR_A_MA1 97 A3 A2 98 DDR_A_MA0
99 A1 A0 100
M_CLK_DDR0 101 VDD9 VDD10 102 M_CLK_DDR1
<5> M_CLK_DDR0 M_CLK_DDR#0 CK0 CK1 M_CLK_DDR#1 M_CLK_DDR1 <5>
103 104
<5> M_CLK_DDR#0 CK0# CK1# M_CLK_DDR#1 <5>
105 106
DDR_A_MA10 107 VDD11 VDD12 108 DDR_A_BS1
DDR_A_BS0 A10/AP BA1 DDR_A_RAS# DDR_A_BS1 <5>
<5> DDR_A_BS0
109 110 DDR_A_RAS# <5>
111 BA0 RAS# 112
DDR_A_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMA#
<5> DDR_A_WE# DDR_A_CAS# WE# S0# M_ODT0 DDR_CS0_DIMMA# <5>
<5> DDR_A_CAS# 115 116
117 CAS# ODT0 118
DDR_A_MA13 119 VDD15 VDD16 120 M_ODT1 +V_VDDR_REFA_CA
DDR_CS1_DIMMA# 121 A13 ODT1 122
<5> DDR_CS1_DIMMA# S1# NC2
123 124
125 VDD17 VDD18 126 +V_VDDR_REFA_CA
127 TEST VREF-CA 128
DDR_A_D32 VSS27 VSS28 DDR_A_D36

0.1U_0402_16V7K
129 130
DDR_A_D33 131 DQ32 DQ36 132 DDR_A_D37
DQ33 DQ37

CD3
133 134 1
DDR_A_DQS#4 135 VSS29 VSS30 136
DDR_A_DQS4 137 DQS4# DM4 138
139 DQS4 VSS31 140 DDR_A_D38
DDR_A_D34 141 VSS32 DQ38 142 DDR_A_D39 2
DDR_A_D35 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_A_D44
DDR_A_D40 147 VSS34 DQ44 148 DDR_A_D45
DDR_A_D41 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_A_DQS#5
153 VSS36 DQS5# 154 DDR_A_DQS5
155 DM5 DQS5 156
DDR_A_D42 157 VSS37 VSS38 158 DDR_A_D46
DDR_A_D43 159 DQ42 DQ46 160 DDR_A_D47
161 DQ43 DQ47 162
DDR_A_D48 163 VSS39 VSS40 164 DDR_A_D52
DDR_A_D49 165 DQ48 DQ52 166 DDR_A_D53
+1.35V_VDDQ 167 DQ49 DQ53 168
DDR_A_DQS#6 169 VSS41 VSS42 170
DDR_A_DQS6 171 DQS6# DM6 172
B B
173 DQS6 VSS43 174 DDR_A_D54
DDR_A_D50 VSS44 DQ54 DDR_A_D55
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

175 176
DDR_A_D51 DQ50 DQ55
CD6

CD7

CD8

CD9

CD10

CD11

CD12

CD13

1 1 1 1 1 1 1 1 177 178
179 DQ51 VSS45 180 DDR_A_D60
@ DDR_A_D56 181 VSS46 DQ60 182 DDR_A_D61
ESD@ ESD@ DDR_A_D57 183 DQ56 DQ61 184
2 ESD@ 2 2 2 2 2 2 2 185 DQ57 VSS47 186 DDR_A_DQS#7
187 VSS48 DQS7# 188 DDR_A_DQS7
189 DM7 DQS7 190
DDR_A_D58 191 VSS49 VSS50 192 DDR_A_D62
DDR_A_D59 193 DQ58 DQ62 194 DDR_A_D63
195 DQ59 DQ63 196 +0.6V_0.675VS
+1.35V_VDDQ 197 VSS51 VSS52 198
SA0 EVENT# PCH_SMBDATA
330U_D3_2.5VY_R6M

199 200
+3VS VDD-SPD SDA PCH_SMBCLK PCH_SMBDATA <7,16,18>
0.1U_0402_16V7K

201 202
SA1 SCL PCH_SMBCLK <7,16,18>
CD17

203 204
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 VTT1 VTT2 +0.6V_0.675VS

0.1U_0402_16V7K

0.1U_0402_16V7K

CD24

10U_0603_6.3V6M
1 1 1 1 1 1 1 1 205 206
GND1 GND2
C174

CD19

CD21
+
1 1 1
CD55

CD56

CD57

CD58

CD63

CD64

CD65

CD66

207 208
2 NC3 NC4
2 2 @ 2 @ 2 2 2 2 2 2
ESD@ FOX_AS0A626-U4R6-7H 2 2 2

CONN@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L DIMM0
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 15 of 63
5 4 3 2 1
 5 4 3 2 1

+V_VDDR_REFB_DQ +1.35V_VDDQ +1.35V_VDDQ

JDIMM2
+V_VDDR_REFB_DQ 1 2
3 VREF-DQ VSS1 4 DDR_B_D22
DDR_B_D23 VSS2 DQ4 DDR_B_D16

0.1U_0402_16V7K
5 6
<5> DDR_B_D[0..63] DDR_B_D17 DQ0 DQ5

CD27
1 7 8
9 DQ1 VSS3 10 DDR_B_DQS#2
<5> DDR_B_DQS[0..7] VSS4 DQS0# DDR_B_DQS2
11 12
13 DM0 DQS0 14
<5> DDR_B_DQS#[0..7] 2 DDR_B_D21 VSS5 VSS6 DDR_B_D19
15 16
D DDR_B_D18 17 DQ2 DQ6 18 DDR_B_D20 D
<5> DDR_B_MA[0..15] DQ3 DQ7
19 20
DDR_B_D3 21 VSS7 VSS8 22 DDR_B_D4
DDR_B_D2 23 DQ8 DQ12 24 DDR_B_D5
25 DQ9 DQ13 26
DDR_B_DQS#0 27 VSS9 VSS10 28
DDR_B_DQS0 29 DQS1# DM1 30 DDR3_DRAMRST#
DQS1 RESET# DDR3_DRAMRST# <4,15>
31 32
DDR_B_D0 33 VSS11 VSS12 34 DDR_B_D6
DDR_B_D1 35 DQ10 DQ14 36 DDR_B_D7
37 DQ11 DQ15 38
DDR_B_D12 39 VSS13 VSS14 40 DDR_B_D13
DDR_B_D8 41 DQ16 DQ20 42 DDR_B_D9
43 DQ17 DQ21 44
DDR_B_DQS#1 45 VSS15 VSS16 46
DDR_B_DQS1 47 DQS2# DM2 48
49 DQS2 VSS17 50 DDR_B_D11
DDR_B_D14 51 VSS18 DQ22 52 DDR_B_D10
DDR_B_D15 53 DQ18 DQ23 54
55 DQ19 VSS19 56 DDR_B_D30
DDR_B_D31 57 VSS20 DQ28 58 DDR_B_D26
DDR_B_D25 59 DQ24 DQ29 60
61 DQ25 VSS21 62 DDR_B_DQS#3
63 VSS22 DQS3# 64 DDR_B_DQS3
65 DM3 DQS3 66
DDR_B_D27 67 VSS23 VSS24 68 DDR_B_D29
DDR_B_D24 69 DQ26 DQ30 70 DDR_B_D28
71 DQ27 DQ31 72
VSS25 VSS26
DDR_CKE0_DIMMB 73 74 DDR_CKE1_DIMMB
<5> DDR_CKE0_DIMMB CKE0 CKE1 DDR_CKE1_DIMMB <5>
75 76
77 VDD1 VDD2 78 DDR_B_MA15
DDR_B_BS2 79 NC1 A15 80 DDR_B_MA14
<5> DDR_B_BS2 BA2 A14
81 82
DDR_B_MA12 83 VDD3 VDD4 84 DDR_B_MA11
DDR_B_MA9 85 A12/BC# A11 86 DDR_B_MA7
87 A9 A7 88
DDR_B_MA8 89 VDD5 VDD6 90 DDR_B_MA6
DDR_B_MA5 91 A8 A6 92 DDR_B_MA4
93 A5 A4 94
DDR_B_MA3 95 VDD7 VDD8 96 DDR_B_MA2
DDR_B_MA1 97 A3 A2 98 DDR_B_MA0
C A1 A0 C
99 100
M_CLK_DDR2 101 VDD9 VDD10 102 M_CLK_DDR3
<5> M_CLK_DDR2 M_CLK_DDR#2 CK0 CK1 M_CLK_DDR#3 M_CLK_DDR3 <5>
103 104
<5> M_CLK_DDR#2 CK0# CK1# M_CLK_DDR#3 <5>
105 106
DDR_B_MA10 107 VDD11 VDD12 108 DDR_B_BS1
DDR_B_BS0 A10/AP BA1 DDR_B_RAS# DDR_B_BS1 <5>
109 110
<5> DDR_B_BS0 BA0 RAS# DDR_B_RAS# <5>
111 112
DDR_B_WE# 113 VDD13 VDD14 114 DDR_CS0_DIMMB#
<5> DDR_B_WE# DDR_B_CAS# WE# S0# M_ODT2 DDR_CS0_DIMMB# <5>
<5> DDR_B_CAS# 115 116 M_ODT2 <15>
117 CAS# ODT0 118
DDR_B_MA13 119 VDD15 VDD16 120 M_ODT3 +V_VDDR_REFA_CA
DDR_CS1_DIMMB# A13 ODT1 M_ODT3 <15>
121 122
<5> DDR_CS1_DIMMB# S1# NC2
123 124
125 VDD17 VDD18 126 +V_VDDR_REFA_CA
127 TEST VREF-CA 128
DDR_B_D32 VSS27 VSS28 DDR_B_D33

0.1U_0402_16V7K
129 130
DDR_B_D35 131 DQ32 DQ36 132 DDR_B_D34
DQ33 DQ37

CD29
133 134 1
DDR_B_DQS#4 135 VSS29 VSS30 136
DDR_B_DQS4 137 DQS4# DM4 138
139 DQS4 VSS31 140 DDR_B_D39
DDR_B_D36 141 VSS32 DQ38 142 DDR_B_D37 2
DDR_B_D38 143 DQ34 DQ39 144
145 DQ35 VSS33 146 DDR_B_D44
DDR_B_D40 147 VSS34 DQ44 148 DDR_B_D41
DDR_B_D45 149 DQ40 DQ45 150
151 DQ41 VSS35 152 DDR_B_DQS#5
153 VSS36 DQS5# 154 DDR_B_DQS5
155 DM5 DQS5 156
DDR_B_D43 157 VSS37 VSS38 158 DDR_B_D47
DDR_B_D42 159 DQ42 DQ46 160 DDR_B_D46
161 DQ43 DQ47 162
DDR_B_D52 163 VSS39 VSS40 164 DDR_B_D51
DDR_B_D49 165 DQ48 DQ52 166 DDR_B_D55
167 DQ49 DQ53 168
DDR_B_DQS#6 169 VSS41 VSS42 170
DDR_B_DQS6 171 DQS6# DM6 172
173 DQS6 VSS43 174 DDR_B_D48
DDR_B_D50 175 VSS44 DQ54 176 DDR_B_D54
+1.35V_VDDQ DDR_B_D53 177 DQ50 DQ55 178
179 DQ51 VSS45 180 DDR_B_D56
DDR_B_D63 181 VSS46 DQ60 182 DDR_B_D57
B B
DDR_B_D62 183 DQ56 DQ61 184
DQ57 VSS47 DDR_B_DQS#7
10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

10U_0603_6.3V6M

185 186
VSS48 DQS7# DDR_B_DQS7
CD33

CD34

CD35

CD36

CD37

CD38

CD39

CD40

1 1 1 1 1 1 1 1 187 188
189 DM7 DQS7 190
DDR_B_D58 191 VSS49 VSS50 192 DDR_B_D60
ESD@ @ @ ESD@ DDR_B_D59 193 DQ58 DQ62 194 DDR_B_D61
2 2 2 2 2 2 2 2 195 DQ59 DQ63 196
197 VSS51 VSS52 198 +0.6V_0.675VS
199 SA0 EVENT# 200 PCH_SMBDATA
+3VS VDD-SPD SDA PCH_SMBCLK PCH_SMBDATA <7,15,18>
0.1U_0402_16V7K

201 202
SA1 SCL PCH_SMBCLK <7,15,18>
CD44

1 203 204
VTT1 VTT2 +0.6V_0.675VS
1
10K_0402_5%
RD4

205 206
GND1 GND2

0.1U_0402_16V7K

0.1U_0402_16V7K

CD50

10U_0603_6.3V6M

0.1U_0402_16V7K
CD45

CD46

CD100
207 208 1 1 1 1
2 +3VS NC3 NC4 @ESD@
2

+1.35V_VDDQ FOX_AS0A626-U4S6-7H
2 2 2 2
2015/02/13 ESD reserve for cocoa
CONN@
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1 1 1 1 1 1 1 1
CD59

CD60

CD61

CD62

CD67

CD68

CD69

CD70

2 2 2 2 2 2 @ 2 2
@

ESD@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L DIMM1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 16 of 63
5 4 3 2 1
 5 4 3 2 1

+1.35V_VDDQ
DDR3L VREF +1.35V_VDDQ

1
D D
RD5 RD6
1.8K_0402_1% 1.8K_0402_1%
RD7 RD8

2
<CPU> +V_DDR_REFA_R 1 2 +V_VDDR_REFA_DQ <DDR3L_A> +V_SM_VREF_CNT 1 2 +V_VDDR_REFA_CA <DDR3L_A_CA>
1 <CPU> 1
2_0402_1% 2_0402_1% <DDR3L_B_CA>
CD52 CD53

1
0.022U_0402_25V7K 0.022U_0402_25V7K
2 RD9 2 RD10

1
1.8K_0402_1% 1.8K_0402_1%
RD11 RD12
24.9_0402_1% 24.9_0402_1%

2
2

2
+1.35V_VDDQ

1
RD13
1.8K_0402_1%
RD15
C
<CPU> +V_DDR_REFB_R 1 2 2 +V_VDDR_REFB_DQ <DDR3L_B> C
1
CD54 2_0402_1%
1

0.022U_0402_25V7K
2 RD17
1

1.8K_0402_1%
RD19
24.9_0402_1%
2
2

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DDR3L VREF
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 17 of 63
5 4 3 2 1
 5 4 3 2 1

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title
LVDS Translator-RTD2132R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 18 of 63
5 4 3 2 1
 5 4 3 2 1

eDP LCD Power

+3VS
W=60mils W=60mils
UT3 INVPWR_B+ +19VB

5 1 +LCDVDD short@
IN OUT RT20 1 2 0_0402_5%

0.1U_0402_16V7K
2 CT33
short@ GND short@
1
RT37 1 2 0_0201_5% 4 3 RT21 1 2 0_0402_5%
SS EN
D 1 D
CT34 1 1
G5243AT11U SOT-23 2 @EMI@ CT29 CT30 SM010014520 3000ma
1500P_0402_50V7K SA000028Y10 680P_0402_50V7K 68P_0402_50V8J 220ohm@100mhz
2
2 2 DCR 0.04

RT23 1 2 0_0402_5%
<41> ENVDD_CPU

1
RT41
100K_0402_5%

2
Camera
MCM1012B900F06BP_4P
4 3 USB20_P5_R
<10> USB20_P5
EMI@ +LCDVDD
1 2 USB20_N5_R
<10> USB20_N5

LT4 2 2

2
short@ C249 C246

2
RT19 1 2 0_0201_5% INVTPWM 2200P_0402_50V7K 68P_0402_50V8J
<8,18> BKL_PWM_CPU 1 1
RF@ RF@
1

@
RT28
DT2
LCD/LED PANEL Conn.

1
100K_0402_5% @ESD@
DT1

1
D_MIC_L_CLK 2 L03ESDL5V0CG3-2_SOT-523-3
PIR Item 1
2

C 2 SCA00002A00 +LCDVDD C

1 4.7U_0603_6.3V6K JLCD1
1 PIR Item 9 CT35 1 2 40
39 40
D_MIC_L_DATA 3 EDP_CPU_AUX# 38 39
3 EDP_CPU_AUX 37 38
<Colay with eDP AUX> 36 37
35 36
34 35
L03ESDL5V0CG3-2_SOT-523-3 33 34
SCA00002A00 32 33
31 32
@ESD@ 31
30
PIR Item 9 29 30
28 29
CT22 1 2 .1U_0402_16V7K EDP_LCD_LANE_P1 short@ 27 28
<4> EDP_CPU_LANE_P1_C D_MIC_CLK D_MIC_L_CLK <18> EDP_LCD_LANE_N3 27
RT30 1 2 0_0402_5% 26
EDP_LCD_LANE_N1 <28> D_MIC_CLK D_MIC_DATA D_MIC_L_DATA <18> EDP_LCD_LANE_P3 26
CT23 1 2 .1U_0402_16V7K RT31 1 2 0_0402_5% 25
<4> EDP_CPU_LANE_N1_C <28> D_MIC_DATA <18> EDP_LCD_LANE_N2 25
24
EDP_LCD_LANE_P2 <18> EDP_LCD_LANE_P2 24
CT24 1 2 .1U_0402_16V7K short@ 23
<4> EDP_CPU_LANE_P2_C <18> EDP_LCD_LANE_N1 23
22
EDP_LCD_LANE_N2 <18> EDP_LCD_LANE_P1 22
CT25 1 2 .1U_0402_16V7K 21
<CPU> <4> EDP_CPU_LANE_N2_C <18> EDP_LCD_LANE_N0
20 21
EDP_LCD_LANE_P3 <18> EDP_LCD_LANE_P0 20
CT26 1 2 .1U_0402_16V7K 19
<4> EDP_CPU_LANE_P3_C +3VS_EDP_HPD 19
18
CT27 1 2 .1U_0402_16V7K EDP_LCD_LANE_N3 DISPOFF# 17 18
<4> EDP_CPU_LANE_N3_C <18> DISPOFF# 17
INVTPWM 16
15 16
USB20_N5_R 14 15
CT19 1 2 .1U_0402_16V7K EDP_LCD_LANE_P0 USB20_P5_R 13 14
<4> EDP_CPU_LANE_P0_C D_MIC_L_CLK 13
2014-10-16: 12
<CPU> CT20 1 2 .1U_0402_16V7K EDP_LCD_LANE_N0
1. Chnage TouchScreen from USB Port6 => I2C Port0 Only
D_MIC_L_DATA 11 12
<4> EDP_CPU_LANE_N0_C 11
2. Remove LT5/DT3 10
+3VS 10
Touch Screen 9
B short@ I2C_0_SCL_TS 8 9 B
+LCDVDD RT36 1 2 0_0402_5% I2C_0_SCL_TS +3VS I2C_0_SDA_TS 7 8 46
<9> I2C_0_SCL Touch Screen TS_INT#_R 6 7 G6 45
short@
RT38 1 2 0_0402_5% I2C_0_SDA_TS TS_RST# 5 6 G5 44
<9> I2C_0_SDA <8,33> TS_RST# 5 G4
1

1
TS_STOP# 4 43
<33> TS_STOP# 4 G3
RT39 RTS3 3 42
2 3 G2 41
100K_0402_1% INVPWR_B+ 2 G1
short@ 10K_0402_5% 1
@ 1
RTS4
2

2
CT17 1 2 .1U_0402_16V7K EDP_CPU_AUX 1 2 TS_INT#_R STARC_107K40-000001-G2
<7> EDP_CPU_AUX_C <9> TS_INT#
3

2
CONN@
CT18 1 2 .1U_0402_16V7K EDP_CPU_AUX# <LCD> 0_0402_5% 1 CTS3
3

<7> EDP_CPU_AUX#_C
2014-10-20:Follow ZPT10 MV: LA-B151PR10 2 68P_0201_25V8
Intel recommends having a pull-up @RF@
resistor of 100 k? for AUXN and a
1

pull-down resistor of 100 k? for AUXP

RT40 2
100K_0402_1%
between the AC capacitor and the
connector, to assist source detect i on 12/19_Add diode by ESD
by the sink device.
1

@ @ESD@
DT3
2

L03ESDL5V0CG3-2_SOT-523-3
PIR Item 8 SCA00002A00

short@
EDP_HPD RT18 1 2 0_0402_5% +3VS_EDP_HPD
<43> EDP_HPD

<Panel>
short@
EC_BKOFF# RT17 1 2 0_0402_5% DISPOFF#
<EC CTRL> <33> EC_BKOFF#
1

A A

RT16
100K_0402_5%
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title
LVDS Translator-RTD2132R
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 19 of 63

5 4 3 2 1
 5 4 3 2 1

+3VS
PCH_DPB_P0 0.1U_0402_16V7K 1 2 CM1 PCH_DPB_P0_C
<4> PCH_DPB_P0 PCH_DPB_N0 0.1U_0402_16V7K PCH_DPB_N0_C
1 2 CM2
<4> PCH_DPB_N0
PCH_DPB_P1 0.1U_0402_16V7K 1 2 CM3 PCH_DPB_P1_C
<4> PCH_DPB_P1 PCH_DPB_N1 0.1U_0402_16V7K PCH_DPB_N1_C
<CPU> 1 2 CM4
<4> PCH_DPB_N1

1
RM1
PCH_DPB_P2 0.1U_0402_16V7K 1 2 CM5 PCH_DPB_P2_C
<4> PCH_DPB_P2 PCH_DPB_N2 0.1U_0402_16V7K PCH_DPB_N2_C
1 2 CM6 1M_0402_5%
<4> PCH_DPB_N2

2
PCH_DPB_P3 0.1U_0402_16V7K 1 2 CM7 PCH_DPB_P3_C
<4> PCH_DPB_P3

2
D
PCH_DPB_N3 0.1U_0402_16V7K 1 2 CM8 PCH_DPB_N3_C D
<4> PCH_DPB_N3 HP_DETECT
1 6
<8> PCH_DDPB_HPD

20K_0402_5%
QM1A 1

5
6
7
8

5
6
7
8

1
2N7002EDW _SOT363-6 CM10 @
5V Level RM2 220P_0402_50V7K
2N7002EDW _SOT363-6 2
QM1B

4
3
2
1

4
3
2
1
3 4

2
RMP1 RMP2
470_0804_8P4R_5% 470_0804_8P4R_5%

5
+3VS

+3VS

EMI@
PCH_DPB_N3_C RM3 1 2 18_0402_5% HDMI_R_CK- +HDMI_5V_OUT

2 RM12 +3VS
@EMI@ 150_0402_5% RM11
C 1 8 HDMI_SDATA C

5
2 7 HDMI_SCLK
1

PCH_DPB_P3_C RM4 1 2 18_0402_5% HDMI_R_CK+ 3 6 PCH_DDPB_DAT QM2B

EMI@ 4 5 PCH_DDPB_CLK PCH_DDPB_CLK 4 3 HDMI_SCLK
<8> PCH_DDPB_CLK
EMI@ 2.2K_0804_8P4R_5% 2N7002EDW _SOT363-6
PCH_DPB_P0_C RM5 1 2 18_0402_5% HDMI_R_D0+ SB00000I700
+3VS
2

SC300002800
RM13 @ESD@ DM1
@EMI@ 150_0402_5% HP_DETECT 1 1 10 9 HP_DETECT

2
HDMI_SDATA 2 2 9 8 HDMI_SDATA
1

PCH_DPB_N0_C RM6 1 2 18_0402_5% HDMI_R_D0-

EMI@ HDMI_SCLK 4 4 7 7 HDMI_SCLK PCH_DDPB_DAT 1 6 HDMI_SDATA
<8> PCH_DDPB_DAT
PCH_DPB_N1_C RM7 1 EMI@ 2 18_0402_5% HDMI_R_D1- 5 5 6 6 2N7002EDW _SOT363-6
SB00000I700 QM2A
2

3 3
RM14
@EMI@ 150_0402_5% 8

IP4292CZ10-TB
1

PCH_DPB_P1_C RM8 1 2 18_0402_5% HDMI_R_D1+

EMI@
PCH_DPB_N2_C RM9 1 EMI@ 2 18_0402_5% HDMI_R_D2- DM4 @ESD@
HDMI_R_D0- 1 9 HDMI_R_D0-
2

B RM15 HDMI_R_D0+ 2 8 HDMI_R_D0+ B

@EMI@ 150_0402_5%
HDMI_R_CK- 4 7 HDMI_R_CK-
HDMI Conn.
1

PCH_DPB_P2_C RM10 1 2 18_0402_5% HDMI_R_D2+ HDMI_R_CK+ 5 6 HDMI_R_CK+

EMI@

JHDMI1
3 HP_DETECT 19
PIR Item 14 18 HP_DET
+HDMI_5V_OUT +5V
TVW DF1004AD0_DFN9 17
SC300002800 HDMI_SDATA 16 DDC/CEC_GND
DM5 @ESD@ HDMI_SCLK 15 SDA
HDMI_R_D1- 1 9 HDMI_R_D1- 14 SCL
W=40mils 13 Reserved
FM1 +HDMI_5V_OUT HDMI_R_D1+ HDMI_R_D1+ HDMI_R_CK- CEC
2 8 12 20
@ @ 11 CK- GND 21
HDMI_R_D2- HDMI_R_D2- HDMI_R_CK+ CK_shield GND

10P_0402_50V8J

10P_0402_50V8J
3 4 7 1 1 10 22
OUT CM11 CM12 HDMI_R_D0- 9 CK+ GND 23
1 HDMI_R_D2+ 5 6 HDMI_R_D2+ 8 D0- GND
+5VS IN HDMI_R_D0+ D0_shield
1 7
2 2 2 HDMI_R_D1- 6 D0+
GND 5 D1-
CM9 3 HDMI_R_D1+ 4 D1_shield
0.1U_0402_16V7K 2 HDMI_R_D2- 3 D1+
AP2330W-7_SC59-3 TVW DF1004AD0_DFN9 2 D2-
SC300002800 HDMI_R_D2+ 1 D2_shield
D2+

A
YUQIU_HD072-F19M1BR_A A
CONN@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HDMI Conn/Level shift
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 20 of 63
5 4 3 2 1
 5 4 3 2 1

+5VS +5VS_HDD1
JPHW6 need to short +5VS_HDD1 +5VS_HDD1
@ JPHW 6 JUMP_43X79 JHDD1
1
1 2 2 1
1 2 C155 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P1 3 2
<6> SATA_PTX_DRX_P1 SATA_PTX_C_DRX_N1 3

10U_0603_6.3V6M

47U_0805_6.3V6M

0.1U_0402_16V7K
<6> SATA_PTX_DRX_N1 C156 1 2 0.01U_0402_16V7K 4
+5VS_HDD1 4

C150
1 1@ 1 5
SATA_PRX_C_DTX_N1 5

C149

C88
C153 1 2 0.01U_0402_16V7K 6 9
<6> SATA_PRX_DTX_N1 C154 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P1 7 6 G1 10
<6> SATA_PRX_DTX_P1 8 7 G2
2 2 2 8
D 2 2 D
ACES_51524-0080N-001
C251 C250 CONN@
2200P_0402_50V7K 68P_0402_50V8J
RF@ 1 1 RF@

+5VS_ODD

10U_0603_6.3V6M

22U_0805_6.3V6M
1 1

C147

C157
Change to dual load switch for ODD and WLAN
+5VALW +3VALW +5VS <MV>Add 22UF for RF suggest i on, 4/10.
2 2 @
Q22
1 14
2 VIN1 VOUT1 13
VIN1 VOUT1
ODD_PW R 3 12 C151 1 2 100P_0402_50V8J
<9> ODD_PW R ON1 CT1
4 11
VBIAS GND

<33> W LAN_PW R_EN 5 10 C152 1 2 100P_0402_50V8J

ON2 CT2
6 9
7 VIN2 VOUT2 8 +3VS_W LAN
VIN2 VOUT2
15 +5VS_ODD
GPAD Pleace near ODD Connector
C EM5209VF DFN 14P 1 C

10U_0603_6.3V6M
C148
SA00007PM00

1000P_0402_50V7K

0.1U_0402_16V7K

10U_0805_10V6K
2 1 1 1

C160
C163

C159
2 2 2

JODD1

1
C158 2 1 0.01U_0402_16V7K SATA_PTX_C_DRX_P2 2 GND
<6> SATA_PTX_DRX_P2 SATA_PTX_C_DRX_N2 A+
<6> SATA_PTX_DRX_N2 C161 2 1 0.01U_0402_16V7K 3
4 A-
C162 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_N2 5 GND
<6> SATA_PRX_DTX_N2 C165 2 1 0.01U_0402_16V7K SATA_PRX_C_DTX_P2 6 B-
<6> SATA_PRX_DTX_P2 7 B+
GND

8
<6> ODD_PLUG# 9 DP
10 +5V
ODD_DA# 11 +5V
<9> ODD_DA# 12 MD 14
13 GND GND 15
GND GND
B B

1 SANTA_201501-2
C164 CONN@
0.1U_0402_16V7K
ESD@
2

10/17 Delete Q84,R954 2N7002 Place C164 close to JODD

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
ODD/SATA Conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 21 of 63
5 4 3 2 1
 5 4 3 2 1

D
JPHW5 need to short
+3VS +3VS_SSD
JSSD1
Refer Skyfall test board D

@ JPHW 5 JUMP_43X79
1 2 +3VS_SSD
1_CONFIG_3 3.3V_2

10U_0805_6.3V6M
1 2 3 4
1 2 5 3_GND 3.3V_4 6
1 5_NA NA_6

1
7 8
7_NA NA_8

CS105
CS100 9 10 T161@
11 9_NA DAS# _10
0.1U_0201_10V6K

2
2 11_NA
12
13 NA_20 14
15 21_CONFIG_0 NA_22 16
17 23_NA NA_24 18
19 25_NA NA_26 20
21 27_GND NA_28 22
23 29_NA NA_30 24
25 31_NA NA_32 26
27 33_GND NA_34 28
29 35_NA NA_36 30 DEVSLP0
37_NA DEVSLP_38 DEVSLP0 <9>
31 32
CS101 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_P0 33 39_GND NA_40 34
<6> SATA_PRX_DTX_P0 41_SATA-B+/PETn0 NA_42

1
<6> SATA_PRX_DTX_N0 CS102 1 2 0.01U_0402_16V7K SATA_PRX_C_DTX_N0 35 36
37 43_SATA-B-/PETp0 NA_44 38 RC379
CS104 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_N0 39 45_GND NA_46 40 10K_0402_5%
<SSD> <6> SATA_PTX_DRX_N0
CS103 1 2 0.01U_0402_16V7K SATA_PTX_C_DRX_P0 41 47_SATA-A-/PERn0 NA_48 42 @
<6> SATA_PTX_DRX_P0 49_SATA-A+/PERp0 NA_50
43 44

2
C 45 51_GND NA_52 46 C
47 53_NA NA_54 48
49 55_NA MFG1_56 50
51 57_GND MFG2 _58 52
53 59_Notch M Notch M_60 54
55 61_Notch M Notch M_62 56
57 63_Notch M Notch M_64 58
59 65_Notch M Notch M_66 60
61 67_NA SUSCLK _68 62
63 69_CONFIG_1 3.3V_70 64
65 71_GND 3.3V_72 66
67 73_GND 3.3V_74
75_CONFIG_2

68
GND 69
GND

LOTES_APCI0103-P002A
CONN@

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
eDP to CRT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 22 of 63
5 4 3 2 1
 5 4 3 2 1

Refer Skyfall NGFF

+3VS_W LAN
+3VS_W LAN
+3VS_W LAN
D WLAN NGFF_E D

1
RN10
JW LAN1

0.1U_0201_10V6K

0.1U_0201_10V6K
4.7K_0402_5% 2 2

1
CS110

CS109
C237 C235

2
@ 1 2 82P_0402_50V8J 68P_0402_50V8J

2
USB20_P4 RN1 1 2 0_0402_5% USB20_P4_R USB20_P4_R 3 1_GND 3.3V_2 4 RF@ 1 1 RF@
<10> USB20_P4 USB20_N4_R 3_USB_D+ 3.3V_4 MINI1_LED#
5 6
@ 7 5_USB_D- LED1#_6 8
USB20_N4 RN2 1 2 0_0402_5% USB20_N4_R 9 7_GND N/C_8 10
<10> USB20_N4 9_N/C N/C_10
11 12
13 11_N/C N/C_12 14
15 13_N/C N/C_14 16
17 15_N/C LED2#_16 18
19 17_N/C GND_18 20
21 19_N/C N/C_20 22
23 21_N/C N/C_22
23_N/C

25 24
+3VS_W LAN 27 33_GND N/C_32 26
<6> PCIE_PTX_C_DRX_P6 35_PERp0 N/C_34
<6> PCIE_PTX_C_DRX_N6 29 28
37_PERn0 N/C_36
1
31 30 E51TXD_P80DATA
39_GND CLink Reset_38 E51RXD_P80CLK E51TXD_P80DATA <33>
33 32 E51RXD_P80CLK <33>
<6> PCIE_PRX_DTX_P6 41_PETp0 CLink DATA_40
RN6 @ 35 34
<6> PCIE_PRX_DTX_N6 43_PETn0 CLink CLK_42
10K_0402_5% 37 36
39 45_GND COEX3_44 38 short@ RN9
<7> CLK_PCIE_MINI1
2

41 47_REFCLKP0 COEX2_46 40 0_0201_5%

<7> CLK_PCIE_MINI1# 49_REFCLKN0 COEX1_48 SUSCLK_W LAN1
C 43 42 2 SUSCLK <8>
C
0_0201_5% 45 51_GND SUSCLK_50 44
<7> MINI1_CLKREQ# 53_CLKREK0# PERST0#_52 PLT_RST# <8,24,25,32,33,39>
<33> EC_PCIE_W AKE# 1 2 47 46 BT_ON_EC <33>
49 55_PEWake 0# W_DISABLE2#_54 48
57_GND W_DISABLE1#_56 W L_OFF# <9>
short@ 51 50
RN7 53 59_N/C N/C_58 52
55 61_N/C N/C_60 54
57 63_GND N/C_62 56
59 65_N/C RESERVED_64 58
61 67_N/C N/C_66 60
63 69_GND N/C_68 62
65 71_N/C N/C_70 64
67 73_N/C 3.3V_72 66
75_GND 3.3V_74
68
GND 69
2014-09-25: GND 70
Chnage WLAN Power form dual switch with ODD NC_70 71
NC_71

LOTES_APCI0019-P003H
CONN@

B WLAN B

NGFF Key_E 67P P0.5 CH 0.32 H2.2 STD

Del +1.5VS_WLAN

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WLAN
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 23 of 63
5 4 3 2 1
 5 4 3 2 1

Place Note :
CL12&CL13 close UL1 Pin 3,8
RTL8111HSH-CG=> Switching Regulator Only CL14 & CL15
JHW1 need to short +LAN_VDD_3V3 Rising t i me close UL1_Pin22
CL26 & CL27 close UL1_Pin30
+3VALW
need>0.5mS and <100mS
JHW1
@ +LAN_VDD_1V0
1 2 @
1 2 +LAN_VDD_3V3
LL1 1 20_0603_5%
JUMP_43X79
LL2
+LAN_REGOUT 1 2

1U_0402_6.3V6K

1U_0402_6.3V6K
2.2UH +-5% NLC252018T-2R2J-N

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
4.7U_0603_6.3V6K
D D
1 1 1 1 1 1 1 1 1

0.1U_0402_16V7K
+VDDREG

CL23
+LAN_VDD_3V3 1 @ CL12 CL13

CL8
@ CL11 CL14 CL15 CL26 CL27
CL21 @ @
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
2 2 2 2 2 2 2 2 2

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
2
1 1 1 1 1 1

CL10

CL16
@ @
CL20 CL19 CL9 CL5
EC_LAN_ISOLATEB# 2 1
2 2 2 2 2 2 Place CL11~CL13 close UL1 Pin 3, 8 , 22 +3VS
LL2, CL8, CL23 for 8161 1K_0402_5% RL5

2
CL8 & CL123 close LL2
RL8

15K_0402_5%
+LAN_VDD_3V3=40mil

1
CL9 & CL5 close to UL1: Pin 11,32 CL10& CL16 close to UL1: Pin 23 UL1 +LAN_VDD_1V0 +VDDREG=40mil
L
CL19 close to UL1: Pin 32 LAN_MDIP0 1 3
+LAN_REGOUT=60mil
LAN_MDIN0 2 MDIP0 AVDD10 8
CL20 close to UL1: Pin 11 LAN_MDIP1 4 MDIN0 AVDD10 30 +LAN_VDD_3V3
LAN_MDIN1 5 MDIP1 AVDD10 22 +LAN_VDD_3V3
LAN_MDIP2 6 MDIN1 DVDD10 +LAN_VDD_3V3 XTLI
LAN_MDIN2 7 MDIP2 11
MDIN2 AVDD33

1
LAN_MDIP3 9 32 @ 2 1 XTLO
LAN_MDIN3 10 MDIP3 AVDD33 short@ RL15 1M_0402_5% RL7
MDIN3 23 +VDDREG RL10 1 2
VDDREG(VDD33) 10K_0402_5%
24 +LAN_REGOUT
LAN_CLKREQ#2 @ RL6 1 0_0201_5% LAN_CLKREQ#_R 12 REGOUT 0_0603_5%
<7,9> LAN_CLKREQ#

2
PLT_RST# 19 CLKREQB 21 LANWAKEB 2 @ RL9 1 0_0201_5%
<8,23,25,32,33,39> PLT_RST# PERSTB LANWAKEB EC_LAN_ISOLATEB# EC_PME# <9,33>
20
CLK_PCIE_LAN 15 ISOLATEB
<7> CLK_PCIE_LAN REFCLK_P

3
CLK_PCIE_LAN# 16 27 LED0 YL1
C <7> CLK_PCIE_LAN# REFCLK_N LED0 C

10P_0402_50V8J

10P_0402_50V8J
26 LED1/GPO T164@ 1 1

GNDOSC_1

GNDOSC_3
PCIE_PTX_C_DRX_P3 13 LED1/GPO 25 LED2 CL25 CL24
<10> PCIE_PTX_C_DRX_P3 PCIE_PTX_C_DRX_N3 HSIP LED2(LED1)
14
<10> PCIE_PTX_C_DRX_N3 PCIE_PRX_DTX_P3 HSIN
CL6 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_P3 17 28 XTLI
<10> PCIE_PRX_DTX_P3 PCIE_PRX_DTX_N3 HSOP CKXTAL1 2 2
CL7 1 2 0.1U_0402_10V7K PCIE_PRX_C_DTX_N3 18 29 XTLO
<10> PCIE_PRX_DTX_N3 HSON CKXTAL2
RSET 31 33

4
RSET GND

2
SP050005L00 Footprint +LAN_VDD_3V3
RL11 25MHZ_20PF_FSX3M-25.M20FDO
TSL1 2.49K_0402_1% RTL8111HSH-CG_QFN32
SA000084T00
+V_DAC 1 24

1
LAN_MDIP0 2 TCT1 MCT1 23 RJ45_TX0+ RP5 JLAN1
LAN_MDIN0 3 TD1+ MX1+ 22 RJ45_TX0- 1 8
Amber
TD1- MX1- 2 7 12
LED1 RJ45_TX3- GND
4 21 3 6 RL36 8
LAN_MDIP1 5 TCT2 MCT2 20 RJ45_RX1+ 4 5 LED0 2 1 LAN_ACTIVITY# 1 2 PR4- 11
LAN_MDIN1 6 TD2+ MX2+ 19 RJ45_RX1- 220_0402_5% RJ45_TX3+ 7 GND
TD2- MX2- 75_0804_8P4R_1% PR4+
7 18 SD300002E80 HT-110UD_1204 RJ45_RX1- 6
LAN_MDIP2 TCT3 MCT3 RJ45_TX2+ 2 PR2-
8 17 CL2 SC5110UD000 LANGND
LAN_MDIN2 9 TD3+ MX3+ 16 RJ45_TX2- SE167100J80 RJ45_TX2- 5
TD3- MX3- 10P_1808_3KV
White PR3-
1 LED2 RJ45_TX2+
10 15 RL37 4
LAN_MDIP3 11 TCT4 MCT4 14 RJ45_TX3+ LED2 2 1 LINK_100_1000# 1 2 PR3+
LAN_MDIN3 12 TD4+ MX4+ 13 RJ45_TX3- 1 EMI@ 33_0402_5% RJ45_RX1+ 3
TD4- MX4- PR2+
3

CL3
HT-F196BP5_WHITE RJ45_TX0-
YSLC05CH_SOT23-3

ESD@ LANGND 120P_0402_50V8 2

2

DL1 SC500004W00 PR1- 10

S XFORM_ NS892407 1G RJ45_TX0+ 1 GND
2 1 PR1+
EMI@ EMI@ SP050006800 9
CL1 CL4 GND
0.01U_0402_16V7K 0.1U_0402_16V7K
1 2 SINGA_2RJ1660-000111F
B
CONN@ LANGND B
1

SCA00000U10

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LAN 8111G
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 24 of 63
5 4 3 2 1
 5 4 3 2 1

CardReader on Suboard

D D

+3VS +3VS_CR +3VALW +CR_AVDD33

RR1 RR2
1 2 1 2

0_0603_5% 1 0_0603_5% 1
short@ CR1 @ CR2
0.1U_0201_10V6K 0.1U_0201_10V6K
2 2

JCR1
+CR_AVDD33 1
2 1
+3VS_CR 2
3
CLK_PCIE_CR 4 3
<7> CLK_PCIE_CR CLK_PCIE_CR# 4
5
<7> CLK_PCIE_CR# 5
6
PCIE_PTX_C_DRX_P4 7 6
<10> PCIE_PTX_C_DRX_P4 PCIE_PTX_C_DRX_N4 7
8
<10> PCIE_PTX_C_DRX_N4 8
9
PCIE_PRX_DTX_P4 10 9
<10> PCIE_PRX_DTX_P4 PCIE_PRX_DTX_N4 10
11
<10> PCIE_PRX_DTX_N4 11
12
CR_CLKREQ# 13 12
<7,9> CR_CLKREQ# PLT_RST# 13
14
<8,23,24,32,33,39> PLT_RST# CR_W AKE# 14
15
C 16 15 C

16
17
18 GND1
GND2
JXT_FP225H-016G1AM

+3VS +3VS_CR
2

@
2014-10-08: RR3
Refer Pixar NonCS. Reserved WAKE# 100K_0402_5%
2
G

W AKE# 1 3 CR_W AKE#

<8> W AKE#
D

@
QR1
2N7002H_SOT23-3

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Card Reader_RTS5237S-CG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, April 22, 2015 Sheet 25 of 63
5 4 3 2 1
 5 4 3 2 1

@
USB3_TX1_N 2 1 CS2 USB3_TX1_C_N RS1 1 2 0_0402_5% USB3TXDN1_C_R +USB_VCC1
<10> USB3_TX1_N +5VALW W=100mils
0.1U_0402_16V7K
US1

0.1U_0402_16V7K
1

47U_0805_6.3V6M
W=100mils

150U_B2_6.3VM_R35M
@ 5 OUT
USB3_TX1_P IN 1
<10> USB3_TX1_P
2 1 CS1 USB3_TX1_C_P RS2 1 2 0_0402_5% USB3TXDP1_C_R 1 2 1 1
4 GND +

CS6

CS106
0.1U_0402_16V7K
@ CS3 EN 3 CS5
OCB
0.1U_0402_16V7K
2 SY6288D20AAC_SOT23-5 2 2 2@
@ @
RS3 1 2 0_0402_5% USB3RXDN1_C @
<10> USB3_RX1_N USB_ON#
<EC> 1 2 RS4
D <33> USB_ON# D
0_0402_5%
@
RS6 1 2 0_0402_5% USB3RXDP1_C RS5 1 @ 2 USB_OC0#
USB_OC0# <9,10>
<10> USB3_RX1_P
0_0402_5%

intel BDW PDG v2.0

@ESD@ Overcurrent Pin Default Usage:
DS1 SCA00000U10 OC0# : Port0,1
2 USB20_N0_C
1
OC1# : Port 2,3
USB20_P0_C 3 USB20_P0_C OC2# : Port 4,5
<10> USB20_P0 OC3# : Port 6,7
MCM1012B900F06BP_4P YSLC05CH_SOT23-3 USB2.0/USB3.0 port 1
4 3
+USB_VCC1
EMI@
1 2 JUSB1
SC300002800 1
LS3 ESD@ DS2 USB20_N0_C 2 VBUS
USB20_N0_C USB3RXDN1_C 1 USB3RXDN1_C USB20_P0_C D-
<10> USB20_N0 1 10 9 3
4 D+
USB3RXDP1_C 2 2 9 8 USB3RXDP1_C USB3RXDN1_C 5 GND
USB3RXDP1_C 6 STDA_SSRX-
USB3TXDN1_C_R 4 4 7 7 USB3TXDN1_C_R 7 STDA_SSRX+
USB3TXDN1_C_R 8 GND
USB3TXDP1_C_R 5 5 6 USB3TXDP1_C_R USB3TXDP1_C_R 9 STDA_SSTX-
6
STDA_SSTX+
3 3 10
11 GND
8 12 GND
13 GND
IP4292CZ10-TB GND
TAITW_PUBAUF-09FLBS1FF4H0
CONN@

EHCI Port1 : DebugPort

C C

+USB_VCC3
Close to JUSB2
@
W=80mils +USB_VCC1
USB3_TX2_N 2 1 CS23 USB3_TX2_C_N RS20 1 2 0_0402_5% USB3TXDN2_C_R US4 JPV5 JP@
<10> USB3_TX2_N

0.1U_0402_16V7K
0.1U_0402_16V7K +5VALW 1 1 2
W=80mils 5 OUT 1 2
@ @ IN 2 JUMP_43X79

47U_0805_6.3V6M
USB3_TX2_P USB3_TX2_C_P USB3TXDP2_C_R USB_ON# GND 1 1
2 1 CS28 RS19 1 2 1 2 RS41 4

CS25
<10> USB3_TX2_P 0_0402_5%
0.1U_0402_16V7K 0_0402_5% EN 3
OCB CS26
SY6288D20AAC_SOT23-5 2 2 PIR Item 6
@
RS24 1 2 0_0402_5% USB3RXDN2_C
<10> USB3_RX2_N
@
RS26 1 2 0_0402_5% USB3RXDP2_C RS40 1 @ 2 USB_OC0#
<10> USB3_RX2_P
0_0402_5%

@ESD@ USB2.0/USB3.0 port 4

DS3 SCA00000U10
2 USB20_N1_C
1
3 USB20_P1_C

USB20_P1_C YSLC05CH_SOT23-3
<10> USB20_P1
MCM1012B900F06BP_4P +USB_VCC3
4 3
JUSB2
EMI@ SC300002800 1
1 2 ESD@ DS4 USB20_N1_C 2 VBUS
USB3RXDN2_C 1 USB3RXDN2_C USB20_P1_C D-
1 10 9 3
LS6 4 D+
USB20_N1_C USB3RXDP2_C 2 2 8 USB3RXDP2_C USB3RXDN2_C 5 GND
9
<10> USB20_N1 USB3RXDP2_C STDA_SSRX-
6
USB3TXDN2_C_R 4 4 7 7 USB3TXDN2_C_R 7 STDA_SSRX+
B B
USB3TXDN2_C_R 8 GND
USB3TXDP2_C_R 5 5 6 6 USB3TXDP2_C_R USB3TXDP2_C_R 9 STDA_SSTX-
STDA_SSTX+
3 3 10
11 GND
8 12 GND
13 GND
IP4292CZ10-TB GND
TAITW_PUBAUF-09FLBS1FF4H0
CONN@

IO Suboard
+3VALW +USB_VCC4
USB20_N3_C JUSB4
<10> USB20_N3
1
2 1
MCM1012B900F06BP_4P 3 2
4 3 4 3
5 4
EMI@ USB3_RX4_N 6 5
<10> USB3_RX4_N USB3_RX4_P 6
1 2 7
<10> USB3_RX4_P 7
8
LS10 USB3_TX4_N 9 8
<10> USB3_TX4_N USB3_TX4_P 9
<10> USB3_TX4_P
10
USB20_P3_C 11 10
<10> USB20_P3 USB20_N3_C 11
12
USB20_P3_C 13 12
14 13
14
15
16 GND
+USB_VCC4 Close to JUSB4 GND

CVILU_CF31142D0R4-05-NH
US5
47U_0805_6.3V6M
0.1U_0402_16V7K

CONN@
+5VALW 1
A 5 OUT +USB_VCC4 A
IN 1 1
2
CS32

@ CS33
USB_ON# 1 2 RS42 4 GND
0_0402_5% EN 3
OCB 2 2
2 2
SY6288D20AAC_SOT23-5 C935 C934
82P_0402_50V8J 68P_0402_50V8J
@RF@ 1 1 @RF@
PIR Item 3

12/23 Reserve for RF Security Classification Compal Secret Data Compal Electronics, Inc.
PIR Item 13 Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB 3.0/2.0 conn
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 26 of 63
5 4 3 2 1
 5 4 3 2 1

+5VL
+2546PW R +USB_VCC2

Refer Pixar

47U_0805_6.3V6M
RS9

1U_0402_6.3V6K
0_0402_5% +5VALW
1
1 +2546PW R

CS9
short@
SI7326DN-T1-E3_PAK1212-8 W=80mils

CS8
1
W=80mils US3
2 1
1 2
D 2 D

10U_0603_6.3V6M
CS7 3 5

0.1U_0402_16V7K
CS107
0.1U_0402_16V7K 1 1 1
2

CS22
CS21

4
.1U_0402_16V7K @
US2 2 2 2
+3VL
1 12
@ IN OUT
2

RS10
1 2 13 10mil
RS17 <10> USB_OC1# FAULT# USB_IN_STATUS#
0_0402_5% 9
STATUS# USB_IN_STATUS# <33>
2 2 1
10K_0402_5% <10> USB20_N2
<10> USB20_P2
3 DM_OUT 11 U2D_DN2 +19VB RS39
DP_OUT DM_IN 10 U2D_DP2 20K_0402_5%
1

ILIM_SEL 4 DP_IN
ILIM_SEL 2014-10-13:Change Correct Power Net Name

6
USB_CHARGE_EN_R 5 15 RS13 2 1 19.1K_0402_1% QS1A
EN ILIM_LO 16 RS14 2 1 19.1K_0402_1% B+ => +19VB 1
USB_CTL1 6 ILIM_HI 2014-10-21: Change from single load switch back to MOS. CS108

2N7002EDW_SOT363-6
<33> USB_CTL1 USB_CTL2 CTL1
<33> USB_CTL2 USB_CTL3_R
7
CTL2 GND
14 Load Swt i c h have body di ode w
ill l eakage fr o m out t o i n. SPOK# 2 0.1U_0603_25V7K
+3VL 1 2 8 17
CTL3 GPAD QS1B 2
10K_0402_5%

1
3
RS15 TPS2546RTER_QFN16_3X3

2N7002EDW_SOT363-6
2014-10-20: Change USB_IN_STATUS# PU to +3VL SPOK 5
(same power level as EC) <8,53> SPOK
short@ RS16
+19VB

4
1 2 USB_CHARGE_EN_R
C
<EC> <33> USB_CHARGE_EN 2014-10-20: Change USB_IN_STATUS# PU to +3VL C
0_0402_5% RSP1 +3VL (same power level as EC)
SPOK# 8 1 Pixar PV# 2013.01.07 Change
USB_IN_STATUS# 7 2
USB_CTL2 6 3
+VL to B+ to prevent
USB_CTL1 5 4 leakage
100K_0804_8P4R_5%

@ESD@
@ DS5 SCA00000U10
USB3_TX3_N 2 1 CS29 USB3_TX3_C_N RS28 1 2 0_0402_5% USB3TXDN3_C_R 2 USB20_N2_C
<10> USB3_TX3_N
0.1U_0402_16V7K 1
3 USB20_P2_C

@ YSLC05CH_SOT23-3
<10> USB3_TX3_P
USB3_TX3_P 2 1 CS34 USB3_TX3_C_P RS27 1 2 0_0402_5% USB3TXDP3_C_R USB2.0/USB3.0 port 2
0.1U_0402_16V7K
+USB_VCC2
SC300002800
@ ESD@ DS6 JUSB3
RS32 1 2 0_0402_5% USB3RXDN3_C USB3RXDN3_C 1 1 10 9 USB3RXDN3_C 1
B <10> USB3_RX3_N USB20_N2_C VBUS B
2
USB3RXDP3_C 2 2 USB3RXDP3_C USB20_P2_C D-
9 8 3
@ 4 D+
RS34 1 2 0_0402_5% USB3RXDP3_C USB3TXDN3_C_R 4 4 USB3TXDN3_C_R USB3RXDN3_C GND
7 7 5
<10> USB3_RX3_P USB3RXDP3_C STDA_SSRX-
6
USB3TXDP3_C_R 5 5 USB3TXDP3_C_R STDA_SSRX+
6 6 7
USB3TXDN3_C_R 8 GND
3 3 USB3TXDP3_C_R 9 STDA_SSTX-
STDA_SSTX+
8 10
11 GND
IP4292CZ10-TB 12 GND
13 GND
GND
U2D_DP2 USB20_P2_C TAITW _PUBAUF-09FLBS1FF4H0
CONN@
MCM1012B900F06BP_4P
4 3

EMI@
1 2

LS9

U2D_DN2 USB20_N2_C

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
USB Charger
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 27 of 63

5 4 3 2 1
 5 4 3 2 1

Amperf i er:
Port-A: Headphone SA000079Z00 :HPA022642RTJR
SA00007CO00:TPA6133A2RTJR JHP1
(Fixed 138mW Amp)
Codec :
ALC3241-CG Port-B: Rear Speaker Amperf i er
SA00008AO00:ALC123-CGT JSPK1
SA00008AN00

Port-C: MIC Input

JHP1
Port-D: Front Speaker JSPK2

Port-H: SubWoofer Amperf i er JSPK3

SA00008BR00:ALC1301 +3VS +DVDD +DVDD_IO +1.5VS +3VS

UA1 1 @ 2 1 2
LA2
D D

0.1U_0402_16V7K
CA5

10U_0603_6.3V6M
CA1

0.1U_0402_16V7K
CA6

10U_0603_6.3V6M
CA2
CA3 1 2 10U_0603_6.3V6M 1 9 +DVDD RA1 SUPPRE_ KC FBMA-10-100505-101T 0402
RA2 CA4 Combo Jack DVDD 3 0_0603_5% PCB Footprint = R_0402
Rear Speaker 2K_0603_1% 1U_0805_25V7K FR_SPK_R+ 20 Port-B DVDD_IO +DVDD_IO 1 1 1 1
1 2
FR_SPK_R+_IN 1 2 FR_SPK_R+_1 2 1 FR_SPK_R+ FR_SPK_L+ 19 MIC1_R 27 LA1 @
<30> FR_SPK_R+_IN MIC1_L AVDD1 +5VS_AVDD
38 SUPPRE_ KC FBMA-10-100505-101T 0402
FR_SPK_L+_IN 1 2 FR_SPK_L+_1 2 1 FR_SPK_L+ MUTE_LED_CTR 30 AVDD2 2 2 2 2 PCB Footprint = R_0402
<30> FR_SPK_L+_IN MIC1_VREFO
RA3 CA7 39
PVDD1 +5VS_PVDD
2K_0603_1% 1U_0805_25V7K 15 45 HSW/BDW Stuff LA2 : +1.5V
16 I2S_MCLK PVDD2 SKY Stuff : LA1: +3.3V
17 I2S_SCLK
18 I2S_DOUT Port-D 44 SPK_R+
I2S_LRCK SPK_OUT_R+ SPK_R- Place near Pin1 Place near Pin9
24 43
BAT54AW-L_SOT323 Pin7 : I2S-Float-Control: 7 I2S_DIN SPK_OUT_R-
3 EC_MUTE# Internally pulled low by a 47k ohm resistor. GPIO4/I2S-Float-Control Internal Front Speaker +5VS_AVDD +5VS
RA4 Port-D 40 SPK_L+ HP mini Spec Reserved LDO +5VS_AVDD LA3
1 1K_0402_5% CA8 1 2 4.7U_0402_6.3V6M INT_MICR_C 28 Port-C SPK_OUT_L+ 41 SPK_L- 2014-09-18: HP_OUT +5VS UA2 1 2
<29> EAPD# INT_MIC INT_MICR
1 2 CA9 1 2 4.7U_0402_6.3V6M INT_MICL_C 29 LINE1_L SPK_OUT_L- With Headphone Amp. : 0 ohm 5 FBMA-L11160808601LMA10T_2P
EAPD#_L LINE1_R No Amp. : 75 or 100 ohm Headphone W=40Mil VOUT

.1U_0402_16V7K
CA10

10U_0603_6.3V6M
CA11
2 48 1
GPIO3/SPDIFO Port-A HPOUT_R VIN

.1U_0402_16V7K
CA13

10U_0603_6.3V6M
CA14
32 RA5 1 2 0_0402_5% 1 1 1 600ohms @100MHz 1A
DA1 HPOUT_R HPOUT_L HP_OUT_R <29>
31 RA6 1 2 0_0402_5% RA7 4
2014-10-09: 23 HPOUT_L HP_OUT_L <29>
2 1 3 NC 1 P/N: SM01000BU00
Change Pin21/34 to refer GNDA +MIC2_VREFO LINE1-VREFO EN
1 10K_0402_5%
CA12 1 2 10U_0603_6.3V6M ALDO_CAP 21 5 @AUDIO_LDO@ 2 2 2 2
GNDA LDO-CAP SDATA_OUT SDATA_IN HDA_SDOUT_AUDIO <6> GND 2
8 RA8 1 2 33_0402_5% CA15
SUB_OUT Port-H SDATA_IN HDA_SDIN0 <6>
37 0.1U_0402_16V7K HPA01091DBVR _SOT23-5
SubWoofer <31> SUB_OUT MONO_OUT 6 HDA_BITCLK_AUDIO_R RA9 1 2 22_0402_5% 2 @AUDIO_LDO@ @AUDIO_LDO@
PC_BEEP BCLK HDA_BITCLK_AUDIO <6>
12 CA16 1 2 300mA Place near Pin38
PCBEEP 22P_0402_50V8J
Place near Pin27
GNDA
HDA_SYNC_AUDIO 10 13 SENSEA 39.2K_0402_1% 2 1 RA10 PLUG_IN# GNDA
<6> HDA_SYNC_AUDIO SYNC SENSE_A 14
HDA_RST_AUDIO# 11 SENSE_B
<6> HDA_RST_AUDIO# RESET# +5VS_PVDD +5VS
22 JDREF RA11 2 1 20K_0402_1%
1 2 JDREF 25 CA17 1 2
+3VS @
VREF
AVREF 2.2U_0402_6.3V6M GNDA LA4 600ohms @100MHz 2A MUTE_LED <34>
RA12 1 2
4.7K_0402_5%
GNDA
CA18 1 2 2.2U_0402_6.3V6M ACPVEE 34 42 1 2 FBMA-L11-201209601LMA20T_2P
P/N: SM01000EE00
CPVEE PVSS +1.5VS

.1U_0402_16V7K
CA21

.1U_0402_16V7K
CA22

10U_0603_6.3V6M
CA23

10U_0603_6.3V6M
CA24
CBN 35 CA19 .1U_0402_16V7K
CA20 1 2 2.2U_0402_6.3V6M CBP 36 CBN 26
CBP AVSS1 1 1 2 2

1
EMI@ LA6 33 +DVDD
D_MIC_CLK_R AVSS2 GNDA
BLM15PX221SN1D 2 1 2
<19> D_MIC_CLK D_MIC_DATA GPIO0/DMIC_CLK AUDIO_PD#
4 47 RA13
<19> D_MIC_DATA GPIO1/DMIC_DATA12 EAPD

1
MIC_JD 46 2.2K_0402_5% 2 2 1 1

1
GPIO2/DMIC_DATA34 49 D

2 2
C GND_PAD 10K_0402_5% MUTE_LED_CTR C
2
ALC3241-CG_QFN48P_7X7 RA14

B
G
QA2 S QA1

3
1
1 3 HDA_RST_AUDIO# 2N7002_SOT23-3

E
C
MMBT3904WH_SOT323-3 10K_0402_5%

1
SB000008E10 RA15

2
10K_0402_5% 2 1
EC_MUTE# <33>
@ RA16 DA3
CH751H-40PT_SOD323-2
Internal SPK PIR Item 10

2
<DB>Relace RA13/RA14/RA15/RA16 close to UA1
SM01000FC00 JSPK2
SPK_R- EMI@ RA17 1 2 CHILISIN PBY160808T-471Y-N 0603 SPK_R-_CONN SPK_R+_CONN 1
AUDIO_PD# <30,31> SPK_R+ EMI@ RA18 1 SPK_R+_CONN SPK_R-_CONN 1
2 CHILISIN PBY160808T-471Y-N 0603 2
SPK_L- EMI@ RA19 1 2 CHILISIN PBY160808T-471Y-N 0603 SPK_L-_CONN SPK_L+_CONN 3 2
SPK_L+ EMI@ RA20 1 2 CHILISIN PBY160808T-471Y-N 0603 SPK_L+_CONN SPK_L-_CONN 4 3
SM01000FC00 4
Power down (PD#) power stage for save power 5
0V: Power down power stage 6 GND1
3.3V: Power up power stage wide 40 MIL Delete ESD Diode GND2

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K

220P_0402_50V7K
JXT_WB201H-004G10M
1 1 1 1 CONN@

@EMI@ CA25

@EMI@ CA26

@EMI@ CA27

@EMI@ CA28
SPK_R-_CONN SPK_L-_CONN
2 2 2 2
SPK_R+_CONN SPK_L+_CONN
PC Beep

2
EC Beep 1 2 PC_BEEP_R @ESD@ DA4 @ESD@ DA5
<33> EC_BEEP#
CA29 SCA00002900 SCA00002900
.1U_0402_16V7K RA21 L03ESDL5V0CC3-2_SOT23-3 L03ESDL5V0CC3-2_SOT23-3
47K_0402_5%
1 2 1 2 1 2 PC_BEEP
SB Beep <9> HDA_SPKR +MIC2_VREFO
CA30 CA31
Jack detect

1
1

.1U_0402_16V7K .1U_0402_16V7K
B Combo Mic = High B

1
RA22
10K_0402_5% Reserve for ESD request. Normal HP = Low
INT_MIC_R HP_OUTR_R HP_OUTL_R RA23
GNDA
2

2.2K_0402_5%
Close to Codec pin12

2
2

3
DA6 MIC_JD 1 2 INT_MIC
YSLC05CH_SOT23-3 DA7 RA24

10U_0603_6.3V6M
CA32
SCA00002900 YSLC05CH_SOT23-3 2.2K_0402_5%
ESD@ SCA00000U10 10K_0402_5% 2
@ESD@ 2014-09-18:RealtekReview
RA25
1. Chnage RA24 from
1 22k(old project) to 2.2k(Realtek Reference Circuit)

2
1
2. Add 10k Pull Down for MIC_JD

1
PIR Item 5 GNDA
2014-12-15:
RA69 1 2 0_0805_5%
Add 0 ohm for DGND and
@ AGDN plane bridge by HP
RA70 1 2 0_0805_5% 2014-09-18:RealtekReview
COMBO AUDIO JACK
@ 1. Remove 22k(old project) Pull Down for INT_MIC
RA26 1 2 0_0402_5%
(follow Realtek Reference Circuit) HPR, HPL, 15mil Keep 30mil JHP1
@ INT_MIC EMI@ RA28 1 2 BLM15AX601SN1D_0402 INT_MIC_R INT_MIC_R 3
2014-09-18: SM01000KL00 HP_OUTL_R 1 3
1
RA27 1
@
2 0_0402_5% Follow Old Project to
Use 2 Shorted Pad <29> HP_L_CONN
HP_L_CONN EMI@ RA29 1 2 BLM15AX601SN1D_0402 HP_OUTL_R PLUG_IN# 5
SM01000KL00 5
1 2
CA33 EMI@ HP_R_CONN EMI@ RA30 1 2 BLM15AX601SN1D_0402 HP_OUTR_R 6
<29> HP_R_CONN 6
.1U_0402_16V7K SM01000KL00
HP_OUTR_R 2
4 2
4
100P_0402_50V8J
CA38

10P_0402_50V8J
CA39

10P_0402_50V8J
CA40

1 2 1 1 1
CA34 EMI@ 7
.1U_0402_16V7K 2015 Cocoa Audio Design Requirements v1.2docx GND
Combo jack pin conf i gur at i on:
@EMI@

@EMI@

@EMI@

A A
2 2 2 GNDA SINGA_2SJ3095-056111F
1 2 Tip = Lef t CONN@
CA35 @EMI@
.1U_0402_16V7K
1 st ring = Right Pin6 and Pin5
Normal OPEN
2 nd ring = Ground
1 2 GNDA GNDA GNDA
CA36 @EMI@
Sleeve = Mono microphone
.1U_0402_16V7K

1 2
CA37 EMI@
.1U_0402_16V7K
Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title
GNDA
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AUDIO ALC3241-CG
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 28 of 63
5 4 3 2 1
 A B C D E

+3VS +HP_5V

1 1
+HP_5V +5VS
LB7 Bead Max I=580mA

1
LA7 1 2
RA31
10K_0402_5% BLM15AX221SN1D _0402
2014-09-18:Realtek Review
CA42/CA43/CA45/CA46 SM01000MK00
2014-09-19:Delete 2 Input 1uF
Change to 2.2uF for bet t er audi o perf or mance

2
short@ CA41 UA3 SA000079Z00
HP_OUT_R RA32 1 2 0_0603_5% HP_OUT_R+_IN2 1 2 HP_OUT_R+_IN3 5 12 PIR Item 33
<28> HP_OUT_R HP_OUT_R-_IN3 RIGHTINM VDD_12
4
2.2U_0402_6.3V6M RIGHTINP
short@ CA42 11 HP_R RA33 1 2 30_0402_1%
HPRIGHT HP_R_CONN <28>
HP_OUT_L RA34 1 2 0_0603_5% HP_OUT_L+_IN2 1 2 HP_OUT_L+_IN3 1 14 HP_L RA35 1 2 30_0402_1%
<28> HP_OUT_L LEFTINM HPLEFT HP_L_CONN <28>
HP_OUT_L-_IN3 2
2.2U_0402_6.3V6M LEFTINP
3
EAPD# 6 GND_3 9
2 2 <28> EAPD# SD# GND_9
CA43 CA44 RA36 10
2.2U_0402_6.3V6M 2.2U_0402_6.3V6M 2.2K_0402_5% HP_AMP_TEST2 7 GND_10 13
HP_AMP_TEST1 8 TEST2 GND_13 19
1 1 +HP_5V TEST1 GND_19
2014-09-18: RA37
Ti Applicat i on Circ uit : 2. 2k f or Pi n7/8 Test Pi n.
On HPA00929 : Pin7:SDA , Pin8:SCL 2.2K_0402_5% 20 15
VDD_20 CPVSS_15
2

2
16
RA38 RA39 RA40 RA41 CPVSS_16
0_0402_5% 0_0402_5% 22K_0402_5% 22K_0402_5% 18 17
short@ short@ CPP CPN
@ @
21

1
GND
1

2 2
HPA022642RTJR

CA47

CA48

CA49
1U_0402_6.3V6K
0.1U_0402_16V7K
SA000079Z00 :HPA022642RTJR

1U_0402_6.3V6K

0.1U_0402_16V7K
2.2U_0402_6.3V6M
1 1 SA00007CO00:TPA6133A2RTJR 1 2 1
GNDA
CA45 CA46
GNDA GNDA
2 2 2 1 2
2014-09-18:Realtek Review CA50 1U_0402_6.3V6K
close codec for bet t er noi sel evel perf or mance
=> Extend 1 trace GNDA from Codec to HP Amp. 1 2

GNDA

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio HP Amp
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 29 of 63
A B C D E
 5 4 3 2 1

+PVDD_ALC123 +5VS
1. 靠 端端 端 隔 隔隔
2014-09-17:RealtekReview
c hi p 1u
1
LA8
2
FBMA-L11160808601LMA10T_2P
+AVDD_ALC123
UA4 LA9
CA51 1 2
1U_0805_25V7K 19 FR_SPK_L+_OUT FBMA-L11160808601LMA10T_2P
FR_SPK_L+_IN 2 1 INPUT-L 10 OUT-LP
<28> FR_SPK_L+_IN INPUT-L FR_SPK_L-_OUT +AVDD_ALC123 +PVDD_ALC123
20
OUT-LN
D D
FR_SPK_R+_IN 2 1 INPUT-R 9
<28> FR_SPK_R+_IN INPUT-R FR_SPK_R+_OUT

0.1U_0201_10V6K

10U_0603_6.3V6M

0.1U_0201_10V6K

10U_0603_6.3V6M

0.1U_0201_10V6K

10U_0603_6.3V6M
CA52 24
OUT-RP

CA55
1U_0805_25V7K 1 1 1 1 1 1
FR_SPK_L+_IN FR_SPK_R-_OUT

CA53

CA54

CA56

CA57

CA58
23
OUT-RN
FR_SPK_R+_IN AUDIO_PD# 4
<28,31> AUDIO_PD# SDb 2 2 2 2 2 2
21 +PVDD_ALC123
PVDDL
1

8 22
PBTL PVDDR
1.5K_0402_1%
RA42

1.5K_0402_1%
RA43

CA59 7 +AVDD_ALC123
2 1 5 AVDD JSPK1
GNDA BYPASS 2 GNDA 1
2.2U_0402_6.3V6M GND 3 close to Pin7/6 close to Pin21/22 2 1
2

GND 13 2
ALC123_G1 11 GND 17
ALC123_G2 12 G1 GND RA44 EMI@ 3
G2 FR_SPK_L+_OUT 1 2 FR_SPK_L+_OUT_CONN 4 G1
GNDA 1 CHILISIN PBY160808T-471Y-N 0603 G2
PGND
預預預預 預 預
2014-09-18:RealtekReview GNDA 6 18 RA45 EMI@ E&T_3806K-F02N-03R
AGND PGND 15 FR_SPK_L-_OUT 1 2 FR_SPK_L-_OUT_CONN
1 . LDOGND CONN@
14 CHILISIN PBY160808T-471Y-N 0603
16 NC_14 25 RA46 EMI@
NC_16 Thernal_PAD FR_SPK_R+_OUT 1 2 FR_SPK_R+_OUT_CONN
FR_SPK_R+_OUT_CONN <31>
ALC123-CGT_QFN24_4X4 CHILISIN PBY160808T-471Y-N 0603
2014-09-17:NuRealtekReview RA47 EMI@
FR_SPK_R-_OUT 1 2 FR_SPK_R-_OUT_CONN
Pin5~10 : AGND FR_SPK_R-_OUT_CONN <31>
CHILISIN PBY160808T-471Y-N 0603
other : DGND

680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K

680P_0402_50V7K
1 1 1 1

CA60

CA61

CA62

CA63
C C

2 2 2 2

@EMI@

@EMI@

@EMI@

@EMI@
close to Amp:ALC123

+PVDD_ALC123
FR_SPK_L+_OUT_CONN FR_SPK_R+_OUT_CONN

G2 G1 Differential
FR_SPK_L-_OUT_CONN FR_SPK_R-_OUT_CONN
1

1
0_0402_5%
RA48

0_0402_5%
RA49

2
@ @ *Default Fix Gain:11dB
0 0 11dB
2

ALC123_G1 @ESD@ DA8 @ESD@ DA9

ALC123_G2
14dB
SCA00002900 SCA00002900
0 1 L03ESDL5V0CC3-2_SOT23-3 L03ESDL5V0CC3-2_SOT23-3
1

1
0_0402_5%

0_0402_5%

1 0 19dB
short@

short@

1
RA50

RA51

1 1 24dB
2

B B

2014-09-18:RealtekReview : 改 DGND

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
Audio Front Speaker Amp:ALC123-CGT
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 30 of 63
5 4 3 2 1
 此此此此此此 此與此此
2014-09-15:Relatek Review
端
此此走 走 即寬即寬 （寬 寬A 寬G寬N1 D0與milDsGND s h o r t點點 點點COD EC端）
1. C O DEC A GN D
3. 將將端 鋪 此
2. TRACE R1_IN P
A GND Amp
, trace
p i n19, 2 0 2014-10-13:Change Correct Power Net Name
B+ => +19VB +19VB : 9V~19.5V
CA64 0_0603_5% RA65 0_0402_5% CA96 0.1U_0402_25V6K 2014-10-14:Realtek Review
1 2 R1_INP 1 2 R1_INP_R 2 1 R1_INP_RC Change all ALC1301 refer to DGND. Only Input Refer to AGND from Codec
<28> SUB_OUT
0.1U_0402_25V6K 2014-10-15: +PVDD_ALC1301 +19VB
CA65 1 2 R1_INN 2014-10-15:RealtekReview Change CA69/70/81/83 from 1000pF to 10uF LA10
GNDA

1
1. Add RA65/RA66:10kohm for f i ne-t une out put s peaker 4 W/8oh m
UA5 1 2

10K_0402_5%
2. Change CA64 from 1uF to 4.7uF
L1_INP PBY160808T-181Y-N

RA66
SUBWOOFER+_R/SUBWOOFER-_R : 40mils
L1_INN L1_INP BSD Return : 20mils SUBW OOFER+_R

1000P_0402_50V7K

0.1U_0603_50V7K

1000P_0402_50V7K

0.1U_0603_50V7K
22 36
1U 25V K X5R 0402 L1_INN L1_INP(AI) (O)OUT_D_36

1U 25V K X5R 0402

@ 21 37
L1_INN(AI) (O)OUT_D_37 1 1 1 2014-10-15:

1
CA67 R1_INP_RC

CA69

CA74

CA70

CA71

22U_0805_25V6M
CA72

22U_0805_25V6M
CA97

22U_0805_25V6M
CA98
20 34 2 1 CA66

2
R1_INP(AI) (P)BST_D
1

1 R1_INN
Change 2x220uF to 6x22uF
CA73
19 0.033U_0402_25V7K
R1_INN(AI) 40 SUBW OOFER-_R
Need Realtek Conf i r m

2
GNDA L2_INP 23 (O)OUT_C_40 42 2 1 CA68 2 2 2
2

L2_INN 24 L2_INP(AI) (P)BST_C 0.033U_0402_25V7K

R2_INP 28 L2_INN(AI)
R2_INN 29 R2_INP(AI) 1
R2_INN(AI) (O)OUTA_1 48
(O)OUTA_48 3 2 1 CA75
GNDA L2_INP (P)BST_A 0.033U_0402_25V7K Close to Pin44 Close to Pin2 +PVDD_ALC1301
L2_INN 45
R2_INP GAIN2 10 (O)OUT_B_45 43 2 1 CA76
R2_INN GAIN1 11 GAIN2(DI) (P)BST_B 0.033U_0402_25V7K
PIR Item 11
GAIN0 12 GAIN1(DI)
GAIN0(DI)
1

+PVDD_ALC1301
1U 25V K X5R 0402

1U 25V K X5R 0402

1U 25V K X5R 0402

1U 25V K X5R 0402

1000P_0402_50V7K

0.1U_0603_50V7K

1000P_0402_50V7K

0.1U_0603_50V7K
CA77

CA78

CA79

CA80

MUXSEL 14
PIR Item 18 MUXSEL(I) 1 1 1

1
CA81

CA82

CA83

CA84

22U_0805_25V6M
CA85

22U_0805_25V6M
CA99

22U_0805_25V6M
CA100
PBTL 6 2
2

AUDIO_PD# 13 PBTL(DI) (P)PVDD_A 44

<28,30> AUDIO_PD# SDB(DI) (P)PVDD_B 41

2
1 RA67 2AMP_MUTE#_R 15 (P)PVDD_C 35 2 2 2
0_0402_5% 16 MUTE(DI) (P)PVDD_D +GVDD_AB
1 2 17 TF(DO) +AVDD_ALC1301
<33> AMP_MUTE# FAULTB(DO)
GNDA @ RA75 0_0402_5% 30
+PVDD_ALC1301 +PVDD_ALC1301 31 (P)AVDD
32 SYNC_OUT(DO) 4 +GVDD_AB CA86 1 2 1U 25V K X5R 0402
SYNC_IN(DI) (P)GVDD_AB 33 Close to Pin41 Close to Pin35
(P)GVDD_CD
1

CA87 1 2 1U 25V K X5R 0402

RA52 RA53 46 +AVDD_ALC1301 +19VB
@ 10K_0402_5% @ 10K_0402_5% (P)PGND_AB 47 LA11
OC_ADJ 7 (P)PGND_AB 38 1 2
PLIMIT 8 OC_ADJ(AO) (P)PGND_CD 39 PBY160808T-181Y-N
2

PLIMIT(AI) (P)PGND_CD

10U_0805_25V6K

0.1U_0603_50V7K
MUXSEL PBTL
1

1
CA88

CA89
18
RA54 RA55 5 (P)AGND 26
10K_0402_5% 10K_0402_5% 9 NC_5 (P)AGND 27

2
25 NC_9 (P)AGND
Input Source Select : PBTL Mode Select : NC_25
2

High : L2&R2 High : Mono(default) 49 GNDA

Low : L1&R1(default) Low : Stero Thermal_PAD

+5VS +GVDD_AB ALC1301-CGT_QFN48_6X6 GNDA

PIR Item 11 Close to Pin30
1

Close to Amp Output

RA68 RA56 AUDIO_PD# 1 2 AMP_MUTE#_R
10K_0402_5% @ 10K_0402_5% DA10
LB12 LB13 Bead Max I=2A
+5VS CH751H-40PT_SOD323-2 EMI@
OC_ADJ SUBW OOFER+_R LA12 1 2 PBY160808T-221Y-N_0603 SUBW OOFER+
@
2

PLIMIT SM01000EY00
1
1

RA57 RA58 1 RA74 2 AMP_MUTE# EMI@

1

CA101 @ 22.1K_0402_1% 10K_0402_5% SUBW OOFER-_R LA13 1 2 PBY160808T-221Y-N_0603 SUBW OOFER-

1U 25V K X5R 0402 10K_0402_5% @ SM01000EY00

1
330P_0402_50V8J
CA90 @EMI@

330P_0402_50V8J
CA91 @EMI@
no 22.2K Resistor in CIS
2

JSPK3

1
Power Limiter
CA92 CA93
2

Range : 0.6~5V SUBW OOFER+ 1

改 DGND PIR Item 18

2
2014-09-18:RealtekReview : 680P_0603_50V7K 680P_0603_50V7K SUBW OOFER- 2 1

2
+PVDD_ALC1301 EMI@ EMI@ FR_SPK_R+_OUT_CONN 3 2
<30> FR_SPK_R+_OUT_CONN 3

1
FR_SPK_R-_OUT_CONN

10_0402_5%
CA94 @EMI@

10_0402_5%
CA95 @EMI@
4
<30> FR_SPK_R-_OUT_CONN 4
5
6 GND1
GND2
1

1
10K_0402_5%

10K_0402_5%
RA60

10K_0402_5%

2
RA59

RA61

JXT_W B201H-004G10M
CONN@
@
2

GAIN2
GAIN1 Rear Speaker
GAIN0
1

1
10K_0402_5%
RA62

10K_0402_5%

10K_0402_5%
RA64
RA63

@ @
2

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title
Audio Subwoofer AMP : ALC1301-CGT
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 31 of 63
 5 4 3 2 1

2014-10-14: 12/23 Reserve for RF

1. Upated Pin def i ne t o TP M2. 0 +3VALW
2014-10-14: Follow Phelps
2. Default Using Firmware TPM 1. Keep Power Rail +3VL. Reserved +3VALW
+3VS
2. Remove INT# PU RH2.
(ACCEL_INT# have PU 10K to +3V_PCH to PCH_GPIO46) ACCELEROMETER 2 2

TPM2.0 TPM@ TPM@ TPM@

3. SCL/SDA Direct Connect to EC_SMBus1.
EC_SMBus PU to +3VL C937 C936

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
82P_0402_50V8J 68P_0402_50V8J
+3VS 1 1
1 C9 1 C10 1 C11
PIR Item 17 @RF@ @RF@
DH5
2 1
D 2 2 2 +3VL +3V_GSEN PIR Item 13 D
1 DH1
TPM@ CH751H-40PT_SOD323-2
C12 1 2
1 RH2 2 ACCEL_INT#_R ACCEL_INT# <9>
0.1U_0402_16V7K

24
19
10
U26 TPM@ 2 @ 0_0402_5% +3V_GSEN
5 RB751V-40_SOD323-2

VDD
VDD
VDD
VSB/VDD_5 U3
TPM@ 1 9 +3V_GSEN
LPC_AD0 26 28 Vdd_IO INT2 11
<7,33> LPC_AD0 LPC_AD1 23 LAD0 LPCPD#/NC_28 9 1 R2747 2 PLT_RST# 1 short@ 2 0_0201_5% GS_SMB_CK1 4 INT1 14
BADD RH3
<7,33> LPC_AD1 LPC_AD2 20 LAD1 TESTB1/BADD/NC_9 8 <33,51,52> EC_SMB_CK1 1 short@ 2 0_0201_5% GS_SMB_DA1 6 SCL/SPC VDD
0_0402_5% RH4
<7,33> LPC_AD2 LPC_AD3 17 LAD2 TEST1/NC_8 <33,51,52> EC_SMB_DA1 7 SDA/SDI/SDO 5
<7,33> LPC_AD3 LAD3 14 2 SDO/SA0 GND
+3V_GSEN RH5 1 8 12
XTALO/NC_14 13 10K_0402_5% CS GND 10
XTALI/NC_13 RES

1
TPM 13 1 1
CLK_PCI_TPM 21 SLB 9665 TT 2.0
RH6 2 RES 15 CH1 CH2
<7> CLK_PCI_TPM LPC_FRAME# 22 LCLK 2 3 NC_2 RES 16
T171@ 0_0201_5%
<7,33> LPC_FRAME# PLT_RST# 16 LFRAME# GPIO2/NC_2 6 NC_3 RES
T172@ short@ 0.1U_0402_16V7K 10U_0603_6.3V6M
<8,23,24,25,33,39> PLT_RST# 27 LRESET# GPIO 2 2
SERIRQ
<9,33> SERIRQ SERIRQ HP3DC2TR

2
15
1 @ 2 7 NC_15/CLKRUN# 1 GS_SDO_SA0
+3VS PP NC_1
R2746 3
NC_3
1

1
4.7K_0402_5% 12 HP3DC2 : Slave ADdress (SAD) : 010,100xb

GND
GND
GND
GND
PP:Physical Presence R2745 NC_12 @ RH7
This pin should connect the
x : SDO/SA0
pin to GND. If the pin is connected to VDD, some 0_0201_5% 0_0402_5% 7bits Address: 0x29h
special commands are enabled. short@ SLB9665TT2.0-FW-5.00_TSSOP28

4
11
18
25
This pin does not have an internal pull-up or pull-

2
2

down resistor and must not be lef t f l oat in

g
.

C C

PIR Item 2

H32 H33 H31

H13 H14 H9 H10 H11 H12 H_1P7N H_1P7N H_2P2N H8 H20 H19
Screw Hole H_5P0

HOLEA
H_5P0

HOLEA
H_5P0

HOLEA
H_5P0

HOLEA
H_5P0

HOLEA
H_5P0

HOLEA
HOLEA HOLEA HOLEA
H_3P3

HOLEA
H_3P3

HOLEA
H_2P8

HOLEA

@ @ @

1
@ @ @ @ @ @ @ @ @
1

1
FD1 FD2

@ @
1

H4 H7 H21 H15 H3 H2 H1 H17 H16 H18

FIDUCIAL_C40M80 FIDUCIAL_C40M80 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8 H_2P8

FD3 FD4 HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA HOLEA

@ @ @ @ @ @ @ @ @ @ @ @
1

1
B B
FIDUCIAL_C40M80 FIDUCIAL_C40M80

H5
H_2P3 H23
H_2P8X2P3
HOLEA
HOLEA

@
1

@
1

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
LED/14"Screw hole
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 32 of 63
5 4 3 2 1
 5 4 3 2 1

+3VL +3VL_EC
+3VL_EC
Board ID control for 15
LK1
short@ RK57 FBMA-L11-160808-800LMT_0603
+3VL_EC 2 +EC_VCCA

0.1U_0402_16V7K

0.1U_0402_16V7K
1 2 1

2
CK2

CK3
1 1 1 15" DB SI PV MV
0_0603_5% RK6
CK7 100K_0402_1% UMA

ECAGND
0.1U_0402_16V7K 0 ohm 15K ohm 27K ohm 43K ohm

1
2 2 RK63 2 RK13
PV# 2013.01.29 Add CK4 for ESD protect i on Board ID control

1
0_0402_5% DIS
short@ BOARD_ID
12k ohm 20k ohm 33k ohm 56k ohm
DIS@ RK13
RK13

1
2
ESD@ 56K_0402_1%
CK4 +EC_VCCLPC
2014-10-13: SD034560280
2 1 PLT_RST# Chnage to the same connect i on as L A- A721 RK13
D for EC Power D
43K_0402_1%
UMA@

2
0.1U_0402_16V7K SD034430280

125

111
22
33
96

67
UK1

9
+3VALW
@ 2014-10-16:

VCC_LPC
VCC
VCC
VCC
VCC

AVCC
VCC0
RK15 2 1 330K_0402_5% EC_RST# 1. Use PCH_GPIO85((DGPU_PWR_EN)) to turn on "ALL" power for DGPU. TP_CLK RK2 1 2 4.7K_0402_5%
+3VL_EC Remove from EC_GPIO00.
@ 2. Assign THERMAL_ALERT# from thermal sensor to EC_GPIO00
1 2 short@ RK1 0_0402_5% TP_DATA RK4 1 2 4.7K_0402_5%
CK9 0.1U_0402_16V7K THERMAL_ALERT# 2 1 EC_GPIO00 1 21 EC_+1.05VS_PG
<7> THERMAL_ALERT# EC_KBRST# GATEA20/GPIO00 EC_VCCST_PG/GPIO0F EC_+1.05VS_PG <6>
2014-09-25: Unpop RC for EC_RST# 2 23 EC_BEEP# <28>
2014-09-23:
For KB9022, the ECRST# is internally pull-up to VCC via <9> EC_KBRST# 3 KBRST#/GPIO01 BEEP#/GPIO10 26 EC_FAN_PWM1 Delete Pin:27 AC_AND_CHAG
SERIRQ
40Kohm resistor, so you can remove external pull-up <9,32> SERIRQ LPC_FRAME# SERIRQ EC_FAN_PWM/GPIO12 EC_FAN_PWM1 <35>2014-09-30 : Need EC Check
resistor and capacitor. 4 PWM Output 27 T175@ Pin27 : CR_WAKE#
<7,32> LPC_FRAME# LPC_AD3 LPC_FRAME# AC_OFF/GPIO13
5
<7,32> LPC_AD3 LPC_AD2 LPC_AD3
7
<7,32> LPC_AD2 LPC_AD1 LPC_AD2
8 63 B/I# CH751H-40PT_SOD323-2
<7,32> LPC_AD1 LPC_AD0 LPC_AD1 VCIN1_BATT_TEMP/AD0/GPIO38 KBL_ON# B/I# <51> EC_ACIN
10 LPC & MISC 64 2 1 ACIN <8,52>
<7,32> LPC_AD0 LPC_AD0 VCIN1_BATT_DROP/AD1/GPIO39 ADP_I KBL_ON# <34>
65 DK1
CLK_PCI_LPC ADP_I/AD2/GPIO3A BOARD_ID ADP_I <50,52>
12 AD Input 66
<7> CLK_PCI_LPC PLT_RST# CLK_PCI_EC AD_BID/AD3/GPIO3B ADP_ID
<8,23,24,25,32,39> PLT_RST# 13 75 CK8 2 1 100P_0402_50V8J
EC_RST# PCIRST#/GPIO05 AD4/GPIO42 EC_PME# ADP_ID <50>
37 76 EC_PME# <9,24>
EC_SCI# 20 EC_RST# AD5/GPIO43
PIR Item 12 <9> EC_SCI# AOAC_PME# 38 EC_SCI#/GPIO0E TS_RST#_EC 1 2
<8> AOAC_PME# CLKRUN#/GPIO1D TS_RST# <8,19>
RK24 0_0201_5%
68
+3V_SMBUS DA0/GPIO3C 70 USB_IN_STATUS#
<34> KSI[0..7] DA Output EN_DFAN1/DA1/GPIO3D TS_RST#_EC USB_IN_STATUS# <27>
KSI0 55 71 short@ RK17
KSI1 56 KSI0/GPIO30 DA2/GPIO3E 72 USB_CTL2 0_0402_5%
+3VS 10/21 +3VALW Change +3VALW_EC KSI2 57 KSI1/GPIO31 DA3/GPIO3F USB_CTL2 <27> VR_HOT# 1 2
58 KSI2/GPIO32 83
<PWR> <56> VR_HOT# PROCHOT# <4>
KSI3 2014-09-30:
1 8 EC_SMB_CK1 KSI3/GPIO33 EC_MUTE#/PSCLK1/GPIO4A USB_ON# EC_MUTE# <28> Change USB_ON# from pin:108 to 84 by following LA-A721
RP7 KSI4 59 84
EC_SMB_DA1 KSI4/GPIO34 USB_EN#/PSDAT1/GPIO4B USB_ON# <26>
2 7 KSI5 60 85
3 6 EC_SMB_CK2 KSI6 61 KSI5/GPIO35 PSCLK2/GPIO4C 86 GPU_THERMAL_DET#
KSI6/GPIO36 PS2 Interface PSDAT2/GPIO4D GPU_THERMAL_DET# <39>

2
4 5 EC_SMB_DA2 KSI7 62 87 TP_CLK @ D
<34> KSO[0..17] KSI7/GPIO37 TP_CLK/GPIO4E TP_DATA TP_CLK <34> H_PROCHOT#_EC 2
KSO0 39 88 RK25
C KSO0/GPIO20 TP_DATA/GPIO4F TP_DATA <34> C
KSO1 40 G 0_0201_5%
2.2K_0804_8P4R_5% KSO2 41 KSO1/GPIO21 QK1 S

3
KSO3 42 KSO2/GPIO22 97 ENBKL 2N7002_SOT23-3
ENBKL <8>

1
KSO4 43 KSO3/GPIO23 ENKBL/GPXIOA00 98
KSO4/GPIO24 WOL_EN/GPXIOA01 ME_Flash_EN WLAN_PWR_EN <21>
KSO5 44 99
KSO6 45 KSO5/GPIO25 Int. K/B ME_EN/GPXIOA02 109 VCIN0_PH ME_Flash_EN <6>
KSO7 46 KSO6/GPIO26 Matrix VCIN0_PH1/GPXIOD00 VCIN0_PH <50> EC_SPI_CLK RC369 1 2 PCH_SPI_CLK_R
KSO7/GPIO27 PCH_SPI_CLK_R <7>
KSO8 47 SPI Device Interface EMI@ 15_0402_5%
KSO9 48 KSO8/GPIO28 119
KSO9/GPIO29 MISO/GPIO5B EC_SPI_SO <7>
KSO10 49 120 CC128 RC369 place near EC Side CC128
KSO10/GPIO2A MOSI/GPIO5C EC_SPI_CLK EC_SPI_SI <7>
KSO11 50 SPI Flash ROM SPICLK/GPIO58 126 22P_0402_50V8J
KSO12 51 KSO11/GPIO2B 128 @EMI@
52 KSO12/GPIO2C SPICS#/GPIO5A EC_SPI_CS0# <7>
KSO13
KSO14 53 KSO13/GPIO2D +3VL_EC
KSO15 54 KSO14/GPIO2E 73 TS_STOP#
KSO15/GPIO2F EC_CIR_RX/AD6/GPIO40 TS_STOP# <19>
KSO16 81 74 SYS_PWROK <8>
2014-10-16:
@ KSO17 82 KSO16/GPIO48 SYS_PWROK/AD7/GPIO41 89 EC_PCIE_WAKE# 1.Remove RK14 PCH_GPIO16(EC_FB_CLAMP_TGL_REQ#) to EC:GPIO41.
KSO17/GPIO49 GPIO50 EC_PCIE_WAKE# <23> 2. Connect 1.05VGS_PWR_PG from PowerGood +1.05VGS for N16P.
RK36 1 2 10K_0402_5% EC_SCI# 90
+3VS BATT_CHG_LED#/GPIO52 CAP_LOCK# BAT_CHG_LED <50>
91
EC_SMB_CK1 CAPS_LED#/GPIO53 PWR_LED# CAP_LOCK# <34> GPU_THERMAL_DET#
EC_SCI#
<32,51,52> EC_SMB_CK1
77 GPIO 92 RK23 1 2 10K_0402_5%
From PCH:GPIO10 (VccSus3_3) EC_SMB_DA1 EC_SMB_CLK1/GPIO44 PWR_LED#/GPIO54 PWR_LED# <35>
to EC: GPIO0E 78 93 2014-10-08:NV Review
<32,51,52> EC_SMB_DA1 EC_SMB_CK2 EC_SMB_DAT1/GPIO45 BATT_LOW_LED#/GPIO55 [Crit i c al]: Add a 10K pull up t o +3V f or GP U_T HER MAL_ DET# on EC si de.
KB9022 Circuit Checking List
<7,18,39> EC_SMB_CK2 79 95 SYSON
Change control method from push-pull to open-drain EC_SMB_DA2 EC_SMB_CLK2/GPIO46 SYSON/GPIO56 BT_ON_EC SYSON <54> This pin should be drive high by default. +3VL
Pull-High on PCH side to +3V_PCH 80 121 Add RK23
<7,18,39> EC_SMB_DA2 EC_SMB_DAT2/GPIO47 VR_ON/GPIO57 PCH_DPWROK BT_ON_EC <23>
127
DPWROK_EC/GPIO59 PCH_DPWROK <8>
SM Bus
RP8
PM_SLP_S3# PCH_RSMRST# PCH_RSMRST# <8> PCH_PWR_EN 8
<8> PM_SLP_S3# 6 100 CK10 2 1 100P_0402_50V8J ECAGND 1
PCH_SUSWARN# PM_SLP_S5# 14 PM_SLP_S3#/GPIO04 EC_RSMRST#/GPXIOA03 101 PLT_RST# 7 2
<8> PM_SLP_S5# GPIO07 GPXIOA04 VCIN1_PH EC_LID_OUT# <7,9> EC_ACIN
SUSACK# 15 102 6 3
<8> SUSACK# PM_SLP_SUS# GPIO08 VCIN1_ADP_PROCHOT/GPXIOA05 H_PROCHOT#_EC VCIN1_PH <50> EC_ON
CC129 <8> PM_SLP_SUS#
16 103 5 4
22P_0402_50V8J PCH_SUSWARN# 17 GPIO0A VCOUT1_PROCHOT#/GPXIOA06 104 MAINPWON
<8> PCH_SUSWARN# DGPU_OVT# 18 GPIO0B VCOUT0_MAIN_PWR_ON/GPXIOA07 105 EC_BKOFF# MAINPWON <53>
@ EC_BKOFF# <18> 100K_0804_8P4R_5%
<48> DGPU_OVT# GPIO0C BKOFF#/GPXIOA08 USB_CTL1
19 GPIO GPO 106
<59> GPU_HOT# AMP_MUTE# AC_PRESENT/GPIO0D GPXIOA09 PCH_PWR_EN USB_CTL1 <27>
25 107
PIR Item 11 <31> AMP_MUTE# FAN_SPEED1 28 PWM2/GPIO11 PCH_PWR_EN/GPXIOA10 108 1.05V_VS_PG_PWR PCH_PWR_EN <37>
<35> FAN_SPEED1 FAN_SPEED1/GPIO14 PWR_VCCST_PG/GPXIOA11 1.05V_VS_PG_PWR <55>
B @ T177 29 B
E51TXD_P80DATA 30 FANFB1/GPIO15
<23> E51TXD_P80DATA E51RXD_P80CLK EC_TX/GPIO16 EC_ACIN
2014-09-30 : Need EC Check
31 110 Pin106 : USB_CTL1 SYSON R2748 1 2 100K_0402_5%
<23> E51RXD_P80CLK PCH_PWROK EC_RX/GPIO17 VCIN1_AC_IN/GPXIOD01 EC_ON
32 112 Pin108 : USB_CTL2
<8> PCH_PWROK AC_LED# PCH_PWROK/GPIO18 EC_ON/GPXIOD02 EC_ON <53>
34 114
ON/OFF#
E51TXD_P80DATA <50> AC_LED# USB_CHARGE_EN SUSP_LED#/GPIO19 ON/OFF#/GPXIOD03 LID_SW# ON/OFF# <35>
36 GPI 115 LID_SW# <35> SUSP# R2749 1 2 100K_0402_5%
<27> USB_CHARGE_EN NUM_LED#/GPIO1A LID_SW#/GPXIOD04 116
SUSP#
SUSP#/GPXIOD05 NMI_DBG# SUSP# <37,54,55,58>
HW Module OLB Def i ne t hi s f unc t i n
o 117 @
GPXIOD06
2

EC_PECI RK34 1
118 2
PBTN_OUT# PECI/GPXIOD07 H_PECI <4>
122 short@ 43_0402_1%
<8> PBTN_OUT# PM_SLP_S4# PBTN_OUT#/GPIO5D +3VL_EC
RK26 <8> PM_SLP_S4# 123 124 +V18R 2 1 +3VL_EC
100K_0402_5% 2014-09-30: PM_SLP_S4#/GPIO5E V18R/VCC_IO2 RK62
1
AGND

PM_SLP_S4# Change to from pin:84 to pin:123. 0_0402_5%

GND
GND
GND
GND
GND

PBTN_OUT# Change from pin:106 to 122.

1

CK17 LID_SW# RK44 2 1 47K_0402_5%

due to it needs to support BayTrial M 1.8V
plat f or m
. 4.7U_0603_6.3V6K 2014-09-25: Add RK62
This pin can support V1.8 power plan. KB9022QD LQFP 128P_14X14 2 For 1.8V power plane: VCC_IO2 and VCC_LPC pull up +1.8VALW or
+1.8VL(P). (ex: for Bay Trial M plat f or m)
11
24
35
94
113

69

20mil For 3.3V power plane: VCC_IO2 and VCC_LPC pull up +3.3VALW or
+3.3VL(P).

LK2
ECAGND 2 1
FBMA-L11-160808-800LMT_0603

@ RK49 100K_0402_5% +3VL_EC

1 2 PCH_DPWROK ECAGND <50>
@ RK50 100K_0402_5%
1

1 2 PCH_PWROK
RK18
10K_0402_5%
2

SUSP#
NMI_DBG# 1 2
+5VL NMI_DBG#_CPU <9>
A DK2 A
1
0.1U_0402_16V7K

CH751H-40PT_SOD323-2
C938

1
ESD@
CK0402101V05_0402-2
D63 @ESD@
2
2

2015/02/12 ESD reserve for cocoa Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
EC ENE-KB9012
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 33 of 63
5 4 3 2 1
 Touch pad conn <33> KSI[0..7]
KSI7 Keyboard conn
KSI6
+3VALW KSI5
+3V_PCH CONN@
KSI4
KSI3 JXT_FP257AH-032S10M
KSI2
KSI1 KSI1 32
KSI0 KSI7 31 32
KSI6 30 31
30

2
KSO9 29
R533 R534 KSI4 28 29 34
2.2K_0402_5% KSI5 27 28 GND 33
2.2K_0402_5% <33> KSO[0..17] 27 GND
KSO17 KSO0 26
KSO16 KSI2 25 26

1
25

2
Q32A KSO15 KSI3 24
KSO14 KSO5 23 24
1 6 TP_SMBDATA ESD@ KSO13 KSO1 22 23
<7> SMBDATA 22
KSI0 C193 2 1 100P_0402_50V8J KSO12 KSI0 21
2N7002EDW _SOT363-6 KSO11 KSO2 20 21
KSO10 KSO4 19 20
PCH_SMBus 19

5
KSO9 KSO7 18
KSO8 KSO8 17 18
4 3 TP_SMBCLK KSO7 KSO6 16 17
<7> SMBCLK 16
KSO6 KSO3 15
Q32B KSO5 KSO12 14 15
2N7002EDW _SOT363-6 KSO4 KSO13 13 14
KSO3 KSO14 12 13
KSO2 KSO11 11 12
KSO1 KSO10 10 11
KSO0 KSO15 9 10
KSO16 8 9
2014-10-14: 8
Conf i r m w
i t h Synapti cs "Onl y" PS2+ SMBus" i nter face. KSO17 7
6 7
Remove I2C components. CAP_LOCK# R203 1 +5VS 6
2 3.3K_0402_5% 5
+3VALW <33> CAP_LOCK# MUTE_LED R207 1 5
C16 <28> MUTE_LED 2 3.3K_0402_5% 4
.1U_0402_16V7K 3 4
1 2 2 3
JTP1 CONN@ 1 2
+5VS 1
1
TP_DATA 2 1
<33> TP_DATA 2 JKB1
TP_CLK 3
EC PS2 <33> TP_CLK
4 3
TP_SMBCLK 5 4 7
TP_SMBDATA 6 5 G1 8
6 G2
JXT_FP202DH-006M10M_6P
DM6
TP_DATA 4 1 TP_CLK
I/O3 I/O1
+3VALW

5 2 CAP_LOCK#
VDD GND MUTE_LED

TP_SMBDATA 6 3 TP_SMBCLK
I/O4 I/O2
1 1
AZC099-04S.R7G_SOT23-6 PIR Item 7 ESD@ CC122 ESD@ CC123
ESD@ 12/19_Change ESD type tp 6 pin 100P_0402_50V8J 100P_0402_50V8J
2 2

+5VS +5VALW
1

R23
100K_0402_5%
KB backlight Conn +5VS_KBL Q9
3

S
2

2
SP01000R400 G KBL_ON# <33>
ACES 88514-00401-071 D
1

6 4
5 G2 4 3 LP2301ALT1G SOT-23-3
G1 3 2
2 1
1
CONN@ JKBL1

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
KB/TP
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 34 of 63
 A B C D E

+5VALW

Powert Button Switch ESD Diode

1
ON/OFF# LID_SW #

+3VL R1 to LED Board

270_0402_5%

2
+3VS +5VALW

2
1
SW 1 SN100000W 00 ESD@ JLED1 CONN@
R215 LED1_R 1
2 1

2
100K_0402_5% TJG-533-V-T/R_6P D1
1 1 3 LED11 PW R_LED# 3 2 1
YSLC05CH_SOT23-3 <33> PW R_LED# SATA_LED# 4 3
<6,7> SATA_LED#

2
ON/OFF# 2 4 HT-F196BP5_W HITE HDDHALT_LED# 5 4 7
<33> ON/OFF# <8> HDDHALT_LED#
1 6 5 G1 8
SC500004W 00 6 G2

6
5

1
ESD@ C127 ACES_51524-0060N-001
100P_0402_50V8J PW R_LED#
2
chang D1 to SCA00000U10 for limit high

Lid Switch (Hall Effect Sensor) +3VS

Finger printer
RB751V-40_SOD323-2

+3VL +3V_LID
1
C929
+3V_LID

1
0.1U_0402_16V7K
2

R126 +3VL 2
U2 4.7K_0402_5% JXT_FP202DH-006M10M_6P
DH2

AH1806-W -7 SC59 3P 0_0402_5% @ 6 8

5 6 G2 7

2
SA000058600 R1335 2 1 USB20_P7_R
<10> USB20_P7

2
2 1 USB20_N7_R 4 5 G1
<10> USB20_N7
1

2 3 LID_SW #_OUT 6 1 R1334 3 4

GND

VDD VOUT LID_SW # <33>

0_0402_5% @ 2 3
1 2

3
10P_0402_50V8J

1 1 Q20A 1
C5

100P_0402_50V8J
2 C124 ESD@ D62 2
1

3
1

2N7002EDW _SOT363-6 SCA00000U10 JFP1 CONN@

C4 YSLC05CH_SOT23-3
2 2

1
ESD@
2 0.1U_0402_16V7K

1
PIR Item 12 +5VS

+3V_LID

FAN conn
2

+3VL
R13
2014-09-26: +3VS +5VS
100K_0402_5%
Change to PWM Fan. Remove Fan Driver APE8873M
5

1
+5VS
1

1
RE50
4 3 40mil 10K_0402_5% RE51 @
10K_0402_5%
40mil JFAN1

2
Q20B +3V_LID
10U_0603_6.3V6M
CE22
1 1 1

2
2N7002EDW _SOT363-6 1

0.1U_0402_16V7K
CE25
2
+3V_LID <33> FAN_SPEED1 EC_FAN_PW M1 2
3
<33> EC_FAN_PW M1 3
4
4
2

2 2
1
LID_SW #_OUT 1 8 R125 5
3 CP VCC CE24 6 GND 3
10K_0402_5% GND
2 1 R124 2 7 0.01U_0402_16V7K
10K_0402_5% D PR# 2 ACES_50278-0040N-001
1

3 6
Q# CLR#
4 5
GND Q
U1
NL17SZ74USG US 8P

RB751V-40_SOD323-2
+3V_SMBUS
2 1

DH3
DH4
+3VL 2 1

RB751V-40_SOD323-2

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title
PWRBTN/FAN
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 35 of 63
A B C D E
 5 4 3 2 1

Reserve for HW

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
GCLK
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 36 of 63
5 4 3 2 1
 A B C D E

+5VS

10U_0603_6.3V6M

22U_0805_6.3V6M
1 1

C575

CC56
+3VALW +5VALW
2 2 @RF@
Q21
1 14
2 VIN1 VOUT1 13
+5VALW VIN1 VOUT1
1 1
SUSP# 3 12 C554 1 2 100P_0402_50V8J
ON1 CT1
4 11
VBIAS GND
<33,54,55,58> SUSP# SUSP# 5 10 C557 1 2 680P_0402_50V7K
ON2 CT2
6 9
7 VIN2 VOUT2 8
VIN2 VOUT2
15
GPAD
+3VS
EM5209VF DFN 14P DUAL LOAD SW
+3VS
SA00007PM00 1

10U_0603_6.3V6M
C570
2
2 2
C245 C241
82P_0402_50V8J 68P_0402_50V8J
RF@ 1 1 RF@

2014-09-19 Delete +1.05V Jump Point J1

(PWR have added Jump Pont PJH1)
2 2
+3VALW Q30 +3V_PCH
AO3413L_SOT23-3

+3VALW 3 1

D
20mils

G
2
1

2
C590
R559
+V1.05A +V1.05DX_MODPHY 100K_0402_5% 1U_0402_6.3V6K
2
+1.05VS +1.05VS_MODPHY

1
short@ R570 1 20_0805_5%

1
D

0.1U_0402_16V7K
<33> PCH_PW R_EN 2 1
G

C591
From UK1.107 : EC Control S Q31 @

3
2N7002_SOT23-3
2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
DC Interface
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 37 of 63
A B C D E
 5 4 3 2 1

Reserve for HW

D D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date Title
Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
WAKE and RST-1
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: W ednesday, April 22, 2015 Sheet 38 of 63

5 4 3 2 1
 5 4 3 2 1

UG1A +3VGS_AON

PEG_PTX_C_DRX_P0 AN12 Part 1 of 7 @

<10> PEG_PTX_C_DRX_P0 PEG_PTX_C_DRX_N0 PEX_RX0 GC6_FB_EN XTAL_OUTBUFF
AM12 P6 1 2 TO PCH 1 2
<10> PEG_PTX_C_DRX_N0 PEG_PTX_C_DRX_P1 PEX_RX0_N GPIO0 GC6_FB_EN <9>
AN14 M3 RG34 0_0402_5% RG1 10K_0402_5%
<10> PEG_PTX_C_DRX_P1 PEG_PTX_C_DRX_N1 PEX_RX1 GPIO1
AM14 L6 DIS@ 9/29: NV for debug.
<10> PEG_PTX_C_DRX_N1 PEG_PTX_C_DRX_P2 PEX_RX1_N GPIO2 PWR_LEVEL_R
AP14 P5 1 DIS@ 2
<10> PEG_PTX_C_DRX_P2 PEG_PTX_C_DRX_N2 PEX_RX2 GPIO3
AP15 P7 RG2 10K_0402_5%
<10> PEG_PTX_C_DRX_N2 PEG_PTX_C_DRX_P3 PEX_RX2_N GPIO4 DGPU_MAIN_EN DIS@
AN15 L7
<10> PEG_PTX_C_DRX_P3 PEG_PTX_C_DRX_N3 PEX_RX3 GPIO5 GPU_EVENT#_D 2 DGPU_MAIN_EN <48>
AM15 M7 1 GPU_EVENT# TO PCH XTAL_OUTBUFF 1 DIS@ 2
<10> PEG_PTX_C_DRX_N3 PEX_RX3_N GPIO6 GPU_EVENT# <8>
AN17 N8 DV1 RB751S40T1G_SOD523-2 RG3 10K_0402_5%
AM17 PEX_RX4 GPIO7 L3 SYS_PEX_RST_MON#
PEX_RX4_N GPIO8
TO PCH THRMTRIP#
AP17 M2 VGA_ALERT# TO EC XTAL_SSIN 1 DIS@ 2
D AP18 PEX_RX5 GPIO9 L1 DIS@ RG8 10K_0402_5% D
AN18 PEX_RX5_N GPIO10 M5 NVVDD_PWM_VID PWR_LEVEL_R 2 1
PEX_RX6 GPIO11 PWR_LEVEL_R NVVDD_PWM_VID <59> GPU_THERMAL_DET# <33> 9/29:NV review don't use R-PACK.
AM18 N3 TO EC

GPIO
AN20 PEX_RX6_N GPIO12 M4 DG1 RB751V-40_SOD323-2
AM20 PEX_RX7 GPIO13 N4 NVVDD_PSI <59> +3VGS_AON
AP20 PEX_RX7_N GPIO14 P2
AP21 PEX_RX8 GPIO15 R8 RGP1
AN21 PEX_RX8_N GPIO16 M6 VGA_ALERT# 1 8
AM21 PEX_RX9 GPIO17 R1 GPU_OVERT# 2 7
AN23 PEX_RX9_N GPIO18 P3 <40,48> GPU_OVERT# DGPU_MAIN_EN 3 6
AM23 PEX_RX10 GPIO19 P4 GPU_EVENT#_D 4 5
AP23 PEX_RX10_N GPIO20 P1 DGPU_RST_HOLD#
AP24 PEX_RX11 GPIO21 +1.05VGS 10K_8P4R_5%
AN24 PEX_RX11_N DIS@
AM24 PEX_RX12 L1 DIS@ SMB_CLK_GPU
1 DIS@ 2
PEX_RX12_N

10U_0603_6.3V6M
AN26 +PLLVDD 1 2 RG68 4.7K_0402_5%
PEX_RX13 SMB_DATA_GPU 1 DIS@ 2

0.1U_0402_16V7K
AM26 PBY160808T-300Y-N 0603 1
PEX_RX13_N

22U_0603_6.3V6M

CG1
AP26 1 RG69 4.7K_0402_5%
PEX_RX14

1
DIS@

DIS@
AP27 @ 9/29:NV review 4.7KVGA_EDID_CLK
PU. RGP2
PEX_RX14_N

CG2

CG3
AN27 AK9 1 8
SE095224K00 AM27 PEX_RX15 DACA_RED AL10 2 VGA_EDID_DATA 2 7

2
S CER CAP 0.22U 10V K X5R 0402 PEX_RX15_N DACA_GREEN AL9 2 3 6
DACA_BLUE 4 5
PEG_PRX_C_DTX_P0 0.22U_0402_10V6KPEG_PRX_DTX_P0 AK14

DACs
CG4 1 2 DIS@
<10> PEG_PRX_C_DTX_P0 PEG_PRX_C_DTX_N0 PEX_TX0
CG5 1 2 DIS@ 0.22U_0402_10V6KPEG_PRX_DTX_N0 AJ14 AM9 I2C 2.2K_8P4R_5%
<10> PEG_PRX_C_DTX_N0 PEG_PRX_C_DTX_P1 PEX_TX0_N DACA_HSYNC
CG6 1 2 DIS@ 0.22U_0402_10V6KPEG_PRX_DTX_P1AH14 AN9 DIS@
<10> PEG_PRX_C_DTX_P1 PEG_PRX_C_DTX_N1 PEX_TX1 DACA_VSYNC
CG8 1 2 DIS@ 0.22U_0402_10V6KPEG_PRX_DTX_N1AG14 under GPU 22U 0603 C941,C945 9/29:NV review unuse I2C PD..
<10> PEG_PRX_C_DTX_N1 PEG_PRX_C_DTX_P2 PEX_TX1_N
CG7 1 2 DIS@ 0.22U_0402_10V6KPEG_PRX_DTX_P2 AK15 for layout limitation RGP3
<10> PEG_PRX_C_DTX_P2 PEG_PRX_C_DTX_N2 CG9 1 2 DIS@ 0.22U_0402_10V6KPEG_PRX_DTX_N2 AJ15 PEX_TX2 AG10
close to AD8 VGA_CRT_CLK 1 8
<10> PEG_PRX_C_DTX_N2 PEG_PRX_C_DTX_P3 PEX_TX2_N DACA_VDD
CG10 1 2 DIS@ 0.22U_0402_10V6KPEG_PRX_DTX_P3 AL16 AP9 HDCP_SCL 2 7

PCI EXPRESS
<10> PEG_PRX_C_DTX_P3 PEG_PRX_C_DTX_N3 PEX_TX3 DACA_VREF
CG11 1 2 DIS@ 0.22U_0402_10V6KPEG_PRX_DTX_N3 AK16 AP8 VGA_CRT_DATA 3 6
<10> PEG_PRX_C_DTX_N3 AK17 PEX_TX3_N DACA_RSET HDCP_SDA 4 5
DIS@
C AJ17 PEX_TX4 GC6_FB_EN 3 C
AH17 PEX_TX4_N 1 1.35VGS_PWR_EN 2.2K_8P4R_5%
AG17 PEX_TX5 DGPU_PWROK 2 1.35VGS_PWR_EN <48>
DIS@
PEX_TX5_N <59> DGPU_PWROK

2
AK18
AJ18 PEX_TX6 DG2 DIS@ RGP4
AL19 PEX_TX6_N DAN202UT106 SC70-3 RG4 1 8
AK19 PEX_TX7 R4 VGA_CRT_CLK 100K_0402_5% 2 7
AK20 PEX_TX7_N I2CA_SCL R5 VGA_CRT_DATA
Note GC6_FB_EN 3 6 V0.2

1
AJ20 PEX_TX8 I2CA_SDA DGPU_RST_HOLD# 4 5
AH20 PEX_TX8_N R7 HDCP_SCL
AG20 PEX_TX9 I2CB_SCL R6 HDCP_SDA 10K_8P4R_5%
AK21 PEX_TX9_N I2CB_SDA DIS@
PEX_TX10 VGA_EDID_CLK

I2C
AJ21 R2
AL22 PEX_TX10_N I2CC_SCL R3 VGA_EDID_DATA RGP5
AK22 PEX_TX11 I2CC_SDA 1 8
PEX_TX11_N SMB_CLK_GPU <40> TESTMODE
AK23 T4 2 7
PEX_TX12 I2CS_SCL SMB_DATA_GPU <40> JTAG_TRST
AJ23 T3 3 6
AH23 PEX_TX12_N I2CS_SDA GPU_CLKREQ#_R 4 5
AG23 PEX_TX13
AK24 PEX_TX13_N 10K_8P4R_5%
AJ24 PEX_TX14 DIS@
AL25 PEX_TX14_N
AK25 PEX_TX15
PEX_TX15_N
AD8 +PLLVDD
AJ11 PLLVDD
NC_AJ11 AE8 L2 +1.05VGS
AL13 SP_PLLVDD PBY160808T-301Y-N
<7> CLK_PCIE_GPU PEX_REFCLK +GPU_PLLVDD
AK13 AD7 1 2 DIS@
<7> CLK_PCIE_GPU# GPU_CLKREQ#_R PEX_REFCLK_N VID_PLLVDD

10U_0603_6.3V6M

47U_0805_6.3V6M

10U_0603_6.3V6M
0.1U_0402_16V7K

0.1U_0402_16V7K
AK12 DIS@ YG1 27MHZ_10PF_7V27000050 V0.2
PEX_CLKREQ_N

10P_0402_50V8J
SM01000EU00
CLK

1 1 1 1

1
PEX_TSTCLK_OUT 3 XTAL_OUT

10P_0402_50V8J
1 @ 2 AJ26 H3 XTALIN DIS@ DIS@ DIS@ DIS@ @ XTALIN 1
B PEX_TSTCLK_OUT# AK26 PEX_TSTCLK_OUT XTAL_IN H2 XTAL_OUT 1 3 B
Default unstuffed RG6 200_0402_1%
PEX_TSTCLK_OUT_N XTAL_OUT 1 1
GND GND

CG101

CG36

CG37

CG38

CG39
2
DGPU_PEX_RST# XTAL_OUTBUFF 2 2 2 2

CG40

CG41
AJ12 J4 DIS@ DIS@
<48> DGPU_PEX_RST# AP29 PEX_RST_N XTAL_OUTBUFF H1 XTAL_SSIN 2 4
PEX_TERMP XTAL_SSIN 2 2
2

RG7 C640 under GPU

DGPU_PWROK

2.49K_0402_1% DIS@
close to ball : AE8,AD7
N15P-GT_BGA908
@
1

9/29: use R-pack in RPH2. UG1 N16P@ UG1 N16S@

+3VGS_AON
2

DIS@ +3VGS_AON
QG2A
GPU_CLKREQ#_R 1 6 GPU_CLKREQ#
GPU_CLKREQ# <7,9>
2N7002KDWH_SOT363-6 N16P N16S 2 DIS@ 9/29:NV review

1
When REFCLK current is below 20mA, don't need CG42 2 DIS@
1 @ 2 above gate control for CLKREQ_GPU#, and keep SA00008CW00 SA000087E10 0.1U_0402_16V7K RG66 CG43
RG9 0_0402_5% REFCLK free running 10K_0402_5% 0.1U_0402_16V7K

5
UG2 1 @

5
V0.2 UG3 1

VCC

2
<9> DGPU_HOLD_RST# 1

VCC
IN1 4 SYS_PEX_RST_MON# 1
2 OUT IN1 4 DGPU_PEX_RST#
<8,23,24,25,32,33> PLT_RST#

GND
Internal Thermal Sensor IN2 DGPU_RST_HOLD# 2 OUT

GND
IN2

1
1
MC74VHC1G08DFT2G SC70 5P RG54

3
DGPU_PEX_RST# DIS@ RG55 MC74VHC1G08DFT2G SC70 5P 10K_0402_5%

3
A 10K_0402_5% DIS@ DIS@ A

9/29: NV review. DIS@

2
2
9/19:NV review
5

DIS@
SMB_CLK_GPU 4 3
EC_SMB_CK2 <7,18,33>
QG1B 2N7002KDWH_SOT363-6
Security Classification Compal Secret Data Compal Electronics, Inc.
2

DIS@ Issued Date 2015/04/13 2018/04/13 Title

SMB_DATA_GPU 1 6 Deciphered Date
QG1A 2N7002KDWH_SOT363-6
EC_SMB_DA2 <7,18,33>
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (1/5) PEG & DAC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 39 of 63
5 4 3 2 1
 5 4 3 2 1

Physical Logical Logical Logical Logical

Strapping pin Power Rail Strapping Bit3 Strapping Bit2 Strapping Bit1 Strapping Bit0

+3VGS_MAIN SOR3_EXPOSED SOR2_EXPOSED SOR1_EXPOSED SOR0_EXPOSED

ROM_SCLK
UG1D
ROM_SO +3VGS_MAIN RAM_CFG[3] RAM_CFG[2] RAM_CFG[1] RAM_CFG[0]
Part 4 of 7
AM6 trace width: 16mils
IFPA_TXC +3VGS_MAIN
AN6
IFPA_TXC_N 3V3AUX_NC
P8
differential voltage sensing. ROM_SI DEVID_SEL PCIE_CFG SMB_ALT_ADDR VGA_DEVICE
AP3 AC6
D AN3 IFPA_TXD0 NC_AC6 AJ28 differential signal routing. STRAP0 Keep pull-up to 3V3_AON and pull-down to GND foot print and stuff 50K ohm pull-up D
AN5 IFPA_TXD0_N NC_AJ28 AJ4
IFPA_TXD1 NC_J4
AM5
IFPA_TXD1_N NC_AJ5
AJ5 STRAP1
AL6 AL11
AK6 IFPA_TXD2
IFPA_TXD2_N
NC_AL11
NC_C15
C15 RG10/RG11 put it close STRAP2
AJ6 D19 RESERVED
AH6 IFPA_TXD3 NC_D19 D20 to power supply.

NC
IFPA_TXD3_N NC_D20 D23 STRAP3
NC_D23 D26
AJ9 NC_D26 H31 STRAP4
AH9 IFPB_TXC NC_H31 T8
AP6 IFPB_TXC_N NC_T8 V32
AP5 IFPB_TXD4 NC_V32
AM7 IFPB_TXD4_N
IFPB_TXD5 Pull-up to +3VGS
AL7 SKU Device ID bit5 to bit0 Resistor Values Pull-down to Gnd
AN8 IFPB_TXD5_N _MAIN
AM8 IFPB_TXD6
IFPB_TXD6_N 5K 1000 =8 0000 =0
AK8 N16P-GT
AL8 IFPB_TXD7
IFPB_TXD7_N VCCSENSE_VGA
10K 1001 =9 0001 =1
L4
VDD_SENSE VCCSENSE_VGA <59>
15K 1010 =A 0010 =2
AK1
AJ1 IFPC_L0
IFPC_L0_N VSSSENSE_VGA
20K 1011 =B 0011 =3
AJ3 L5
AJ2 IFPC_L1 GND_SENSE VSSSENSE_VGA <59>
IFPC_L1_N 25K 1100 =C 0100 =4
AH3
AH4 IFPC_L2
IFPC_L2_N 30K 1101 =D 0101 =5
AG5
AG4 IFPC_L3
IFPC_L3_N 35K 1110 =E 0110 =6
TEST 45K 1111 =F 0111 =7
AM1 AK11
C AM2 IFPD_L0 TESTMODE TESTMODE <39> C
AM3 IFPD_L0_N AM10 JTAG_TCK T1 @
AM4 IFPD_L1 JTAG_TCK AM11 JTAG_TDI T2 @
AL3 IFPD_L1_N JTAG_TDI AP12 JTAG_TDO +3VGS_AON
T3 @ MULTI LEVEL STRAPS +3VGS_MAIN
AL4 IFPD_L2 JTAG_TDO AP11 JTAG_TMS T4 @
AK4 IFPD_L2_N JTAG_TMS AN11
AK5 IFPD_L3 JTAG_TRST_N JTAG_TRST <39>
IFPD_L3_N

1
10K_0402_1%
LVDS/TMDS

49.9K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

45.3K_0402_1%

4.99K_0402_1%
10K_0402_1%
14.7K_0402_1%
@ @ @ @ @ @ @

RG12

RG13

RG14

RG15

RG16
AD2 DIS@
IFPE_L0

RG17
AD3
IFPE_L0_N

RG18

RG19
AD1
SERIAL

2
AC1 IFPE_L1
AC2 IFPE_L1_N H6 STRAP0 ROM_SI
AC3 IFPE_L2 ROM_CS_N H4 ROM_SCLK STRAP1 STRAP3 ROM_SO
AC4 IFPE_L2_N ROM_SCLK H5 ROM_SI STRAP2 STRAP4 ROM_SCLK
AC5 IFPE_L3 ROM_SI H7 ROM_SO
IFPE_L3_N ROM_SO

1
4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

45.3K_0402_1%

4.99K_0402_1%

4.99K_0402_1%

4.99K_0402_1%
RG20

RG21

RG22

RG23

RG24
AE3 @ @ @ @ @ @ DIS@ DIS@
AE4 IFPF_L0
AF4 IFPF_L0_N
IFPF_L1

RG25

RG26

RG27
AF5
GENERAL

2
AD4 IFPF_L1_N @
AD5 IFPF_L2 L2 1 2
AG1 IFPF_L2_N BUFRST_N RG28 10K_0402_5%
AF1 IFPF_L3 M1 GPU_OVERT#
IFPF_L3_N OVERT GPU_OVERT# <39,48>
J1 MULTI_STRAP_REF0_GND 1 DIS@ 2
MULTI_STRAP_REF0_GND RG29 40.2K_0402_1%
AG3
AG2 IFPC_AUX_I2CW_SCL
B IFPC_AUX_I2CW_SDA_N J2 STRAP0 B
STRAP0 J7 STRAP1
AK3 STRAP1 J6 STRAP2
AK2 IFPD_AUX_I2CX_SCL STRAP2 J5 STRAP3
IFPD_AUX_I2CX_SDA_N STRAP3 J3 STRAP4
STRAP4 GPU FB Memory DDR3L(1.35V) RAM_CFG[3:0]
AB3 (ROM_SI)
AB4 IFPE_AUX_I2CY_SCL
IFPE_AUX_I2CY_SDA_N K3
THERMDP K4
THERMDN Samsung 1.35V 900MHz K4W4G1646E-BC1A 0x1(PD 10K)
AF3
AF2 IFPF_AUX_I2CZ_SCL
IFPF_AUX_I2CZ_SDA_N
2
5
6 Hynix 1.35V 900MHz H5TC4G63CFR-N0C 0x2(PD 15K)
M
N15P-GT_BGA908
@ N16P-GT x
N16S-GT Hynix 1.35V 900MHz H5TC4G63AFR-11C 0x3(PD 20K)
1
6
MT41J256M16HA-093G:E
ZZZ1 X76L01@ ZZZ1 X76L02@ ZZZ1 X76L03@ Micron 1.35V 900MHz DateCode_Min:1332 0x4(PD 24.9K) V

Samsung 1.35V 900MHz K4W4G1646D-BC1A 0x5(PD 30.1K)

15K_0402_1% 10K_0402_1% 24.9K_0402_1%
A X7661932L01 X7661932L02 X7661932L03 A

ZZZ1 X76L04@ ZZZ1 X76L05@ ZZZ1 X76L06@

Security Classification Compal Secret Data Compal Electronics, Inc.

15K_0402_1% 10K_0402_1% 24.9K_0402_1% Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

X7661932L04 X7661932L05 X7661932L06

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (2/5) TMDS/LVDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 40 of 63
5 4 3 2 1
 5 4 3 2 1

MDA[15..0] MDC[15..0]
<44> MDA[15..0] <46> MDC[15..0]
MDA[31..16] MDC[31..16]
<44> MDA[31..16] <46> MDC[31..16]
MDA[47..32] MDC[47..32]
<45> MDA[47..32] <47> MDC[47..32]
MDA[63..48] MDC[63..48]
<45> MDA[63..48] <47> MDC[63..48]

UG1B UG1C
CMDA[31..0] <44,45> CMDC[31..0] <46,47>
Part 2 of 7 Part 3 of 7
D MDA0 L28 U30 CMDA0 MDC0 G9 D13 CMDC0 D
MDA1 M29 FBA_D0 FBA_CMD0 T31 T5 @ MDC1 E9 FBB_D0 FBB_CMD0 E14 T6 @
MDA2 L29 FBA_D1 FBA_CMD1 U29 CMDA2 MDC2 G8 FBB_D1 FBB_CMD1 F14 CMDC2
MDA3 M28 FBA_D2 FBA_CMD2 R34 CMDA3 MDC3 F9 FBB_D2 FBB_CMD2 A12 CMDC3
MDA4 N31 FBA_D3 FBA_CMD3 R33 CMDA4 MDC4 F11 FBB_D3 FBB_CMD3 B12 CMDC4
MDA5 P29 FBA_D4 FBA_CMD4 U32 CMDA5 MDC5 G11 FBB_D4 FBB_CMD4 C14 CMDC5
MDA6 R29 FBA_D5 FBA_CMD5 U33 CMDA6 MDC6 F12 FBB_D5 FBB_CMD5 B14 CMDC6
MDA7 P28 FBA_D6 FBA_CMD6 U28 CMDA7 MDC7 G12 FBB_D6 FBB_CMD6 G15 CMDC7
MDA8 J28 FBA_D7 FBA_CMD7 V28 CMDA8 MDC8 G6 FBB_D7 FBB_CMD7 F15 CMDC8
MDA9 H29 FBA_D8 FBA_CMD8 V29 CMDA9 MDC9 F5 FBB_D8 FBB_CMD8 E15 CMDC9
MDA10 J29 FBA_D9 FBA_CMD9 V30 CMDA10 MDC10 E6 FBB_D9 FBB_CMD9 D15 CMDC10
MDA11 H28 FBA_D10 FBA_CMD10 U34 CMDA11 MDC11 F6 FBB_D10 FBB_CMD10 A14 CMDC11
MDA12 G29 FBA_D11 FBA_CMD11 U31 CMDA12 MDC12 F4 FBB_D11 FBB_CMD11 D14 CMDC12
MDA13 E31 FBA_D12 FBA_CMD12 V34 CMDA13 MDC13 G4 FBB_D12 FBB_CMD12 A15 CMDC13
MDA14 E32 FBA_D13 FBA_CMD13 V33 CMDA14 MDC14 E2 FBB_D13 FBB_CMD13 B15 CMDC14
MDA15 F30 FBA_D14 FBA_CMD14 Y32 CMDA15 MDC15 F3 FBB_D14 FBB_CMD14 C17 CMDC15
MDA16 C34 FBA_D15 FBA_CMD15 AA31 CMDA16 MDC16 C2 FBB_D15 FBB_CMD15 D18 CMDC16
MDA17 D32 FBA_D16 FBA_CMD16 AA29 T7 @ MDC17 D4 FBB_D16 FBB_CMD16 E18 T8 @
MDA18 B33 FBA_D17 FBA_CMD17 AA28 CMDA18 MDC18 D3 FBB_D17 FBB_CMD17 F18 CMDC18
MDA19 C33 FBA_D18 FBA_CMD18 AC34 CMDA19 MDC19 C1 FBB_D18 FBB_CMD18 A20 CMDC19
MDA20 F33 FBA_D19 FBA_CMD19 AC33 CMDA20 MDC20 B3 FBB_D19 FBB_CMD19 B20 CMDC20
MDA21 F32 FBA_D20 FBA_CMD20 AA32 CMDA21 MDC21 C4 FBB_D20 FBB_CMD20 C18 CMDC21
MDA22 H33 FBA_D21 FBA_CMD21 AA33 CMDA22 MDC22 B5 FBB_D21 FBB_CMD21 B18 CMDC22
MDA23 H32 FBA_D22 FBA_CMD22 Y28 CMDA23 MDC23 C5 FBB_D22 FBB_CMD22 G18 CMDC23
MDA24 P34 FBA_D23 FBA_CMD23 Y29 CMDA24 MDC24 A11 FBB_D23 FBB_CMD23 G17 CMDC24
MDA25 P32 FBA_D24 FBA_CMD24 W31 CMDA25 MDC25 C11 FBB_D24 FBB_CMD24 F17 CMDC25
MDA26 P31 FBA_D25 FBA_CMD25 Y30 CMDA26 MDC26 D11 FBB_D25 FBB_CMD25 D16 CMDC26
MDA27 P33 FBA_D26 FBA_CMD26 AA34 CMDA27 MDC27 B11 FBB_D26 FBB_CMD26 A18 CMDC27

MEMORY INTERFACE B
MDA28 L31 FBA_D27 FBA_CMD27 Y31 CMDA28 MDC28 D8 FBB_D27 FBB_CMD27 D17 CMDC28 +1.35VGS
MDA29 L34 FBA_D28 FBA_CMD28 Y34 CMDA29 +1.35VGS MDC29 A8 FBB_D28 FBB_CMD28 A17 CMDC29
MDA30 L32 FBA_D29 FBA_CMD29 Y33 CMDA30 MDC30 C8 FBB_D29 FBB_CMD29 B17 CMDC30
MDA31 L33 FBA_D30 FBA_CMD30 V31 T9 @ MDC31 B8 FBB_D30 FBB_CMD30 E17 T10 @
C MDA32 AG28 FBA_D31 FBA_CMD31 R28 RG51 2 @ 1 60.4_0402_1% MDC32 F24 FBB_D31 FBB_CMD31 G14 RG49 2 @ 1 60.4_0402_1% C
MDA33 AF29 FBA_D32 FBA_CMD32 AC28 RG50 2 @ 1 60.4_0402_1% MDC33 G23 FBB_D32 FBB_CMD32 G20 RG48 2 @ 1 60.4_0402_1%
FBA_D33 FBA_CMD33 R32 FBA_DEBUG0 RG30 FBB_D33 FBB_CMD33 C12 FBC_DEBUG0 RG31
MEMORY INTERFACE

MDA34 AG29 2 @ 1 60.4_0402_1% Debug use. MDC34 E24 2 @ 1 60.4_0402_1% Debug use.
MDA35 AF28 FBA_D34 FBA_CMD34 AC32 FBA_DEBUG1 RG32 2 @ 1 60.4_0402_1% MDC35 G24 FBB_D34 FBB_CMD34 C20 FBC_DEBUG1 RG33 2 @ 1 60.4_0402_1%
MDA36 AD30 FBA_D35 FBA_CMD35 MDC36 D21 FBB_D35 FBB_CMD35
MDA37 AD29 FBA_D36 MDC37 E21 FBB_D36
MDA38 AC29 FBA_D37 GK107/GK208/GF117:USE CMD32/CMD33 FOR DEBUG MDC38 G21 FBB_D37 GK107/GK208/GF117:USE CMD32/CMD33 FOR DEBUG
MDA39 AD28 FBA_D38 GM107/GM108:USE CMD34/CMD35 FOR DEBUG MDC39 F21 FBB_D38 GM107/GM108:USE CMD34/CMD35 FOR DEBUG
MDA40 AJ29 FBA_D39 FBA_DOT_L CMDA2 MDC40 G27 FBB_D39 FBB_DOT_L CMDC2
MDA41 AK29 FBA_D40 FBA_DOT_H CMDA18 MDC41 D27 FBB_D40 FBB_DOT_H CMDC18
MDA42 AJ30 FBA_D41 FBA_CKE_L CMDA3 MDC42 G26 FBB_D41 FBB_CKE_L CMDC3
MDA43 AK28 FBA_D42 FBA_CKE_H CMDA19 MDC43 E27 FBB_D42 FBB_CKE_H CMDC19
MDA44 AM29 FBA_D43 FBA_RST CMDA5 MDC44 E29 FBB_D43 FBB_RST CMDC5
MDA45 AM31 FBA_D44 R30 MDC45 F29 FBB_D44 D12
FBA_D45 FBA_CLK0 CLKA0 <44> FBB_D45 FBB_CLK0 CLKC0 <46>

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%

10K_0402_5%
MDA46 AN29 R31 MDC46 E30 E12
FBA_D46 FBA_CLK0_N CLKA0# <44> FBB_D46 FBB_CLK0_N CLKC0# <46>

2
RG56

RG57

RG58

RG59

RG60

RG61

RG62

RG63

RG64

RG65
MDA47 AM30 AB31 MDC47 D30 E20
FBA_D47 FBA_CLK1 CLKA1 <45> FBB_D47 FBB_CLK1 CLKC1 <47>

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@

DIS@
MDA48 AN31 AC31 MDC48 A32 F20
FBA_D48 FBA_CLK1_N CLKA1# <45> FBB_D48 FBB_CLK1_N CLKC1# <47>
MDA49 AN32 MDC49 C31
A

MDA50 AP30 FBA_D49 MDC50 C32 FBB_D49

MDA51 AP32 FBA_D50 MDC51 B32 FBB_D50

1
MDA52 AM33 FBA_D51 K31 MDC52 D29 FBB_D51 F8
MDA53 AL31 FBA_D52 FBA_WCK01 L30 MDC53 A29 FBB_D52 FBB_WCK01 E8
MDA54 AK33 FBA_D53 FBA_WCK01_N H34 MDC54 C29 FBB_D53 FBB_WCK01_N A5
MDA55 AK32 FBA_D54 FBA_WCK23 J34 MDC55 B29 FBB_D54 FBB_WCK23 A6
MDA56 AD34 FBA_D55 FBA_WCK23_N AG30 MDC56 B21 FBB_D55 FBB_WCK23_N D24
MDA57 AD32 FBA_D56 FBA_WCK45 AG31 MDC57 C23 FBB_D56 FBB_WCK45 D25
MDA58 AC30 FBA_D57 FBA_WCK45_N AJ34 MDC58 A21 FBB_D57 FBB_WCK45_N B27
MDA59 AD33 FBA_D58 FBA_WCK67 AK34 MDC59 C21 FBB_D58 FBB_WCK67 C27
MDA60 AF31 FBA_D59 FBA_WCK67_N MDC60 B24 FBB_D59 FBB_WCK67_N
MDA61 AG34 FBA_D60 MDC61 C24 FBB_D60
MDA62 AG32 FBA_D61 MDC62 B26 FBB_D61
MDA63 AG33 FBA_D62 J30 MDC63 C26 FBB_D62 D6 +FB_PLLAVDD300mA L3 +1.05VGS
B FBA_D63 NC_J30 J31 FBB_D63 NC_D6 D7 DIS@ B
<44> DQMA[3..0] DQMA0 P30 NC_J31 J32 <46> DQMC[3..0] DQMC0 E11 NC_D7 C6 +FB_PLLAVDD 1 2
FBA_DQM0 NC_J32 FBB_DQM0 NC_C6

22U_0805_6.3V6M
DQMA1 F31 J33 DQMC1 E3 B6 PBY160808T-300Y-N 0603
FBA_DQM1 NC_J33 FBB_DQM1 NC_B6

DIS@ CG44
DQMA2 F34 AH31 DQMC2 A3 F26 1
DQMA3 M32 FBA_DQM2 NC_AH31 AJ31 DQMC3 C9 FBB_DQM2 NC_F26 E26
<45> DQMA[7..4] FBA_DQM3 NC_AJ31 <47> DQMC[7..4] FBB_DQM3 NC_E26
Or use same as L10 PN: SM01000FE00
DQMA4 AD31 AJ32 DQMC4 F23 A26
DQMA5 AL29 FBA_DQM4 NC_AJ32 AJ33 DQMC5 F27 FBB_DQM4 NC_A26 A27
DQMA6 AM32 FBA_DQM5 NC_AJ33 DQMC6 C30 FBB_DQM5 NC_A27 2
DQMA7 AF34 FBA_DQM6 DQMC7 A24 FBB_DQM6
FBA_DQM7 FBB_DQM7
<44> DQSA[3..0] DQSA0 M31 E1 GC6_FB_EN_R <46> DQSC[3..0] DQSC0 D10
DQSA1 G31 FBA_DQS_WP0 FB_CLAMP DQSC1 D5 FBB_DQS_WP0
L15= 30ohm
DQSA2 E33 FBA_DQS_WP1 DQSC2 C3 FBB_DQS_WP1
FBA_DQS_WP2 Under GPU FBB_DQS_WP2
DQSA3 M33 DQSC3 B9
<45> DQSA[7..4]
DQSA4 AE31 FBA_DQS_WP3 K27
close to ball : K27 <47> DQSC[7..4]
DQSC4 E23 FBB_DQS_WP3 H17 +FB_PLLAVDD
DQSA5 AK30 FBA_DQS_WP4 FB_DLL_AVDD CG45 DIS@ DQSC5 E28 FBB_DQS_WP4 FBB_PLL_AVDD
FBA_DQS_WP5 FBB_DQS_WP5 100mA
DQSA6 AN33 1 2 DQSC6 B30
FBA_DQS_WP6 FBB_DQS_WP6

0.1U_0402_16V7K
DQSA7 AF33 0.1U_0402_16V7K DQSC7 A23
FBA_DQS_WP7 U27 +FB_PLLAVDD FBB_DQS_WP7
<44> DQSA#[3..0] FBA_PLL_AVDD <46> DQSC#[3..0] 1

CG47
DQSA#0 M30 DQSC#0 D9
DQSA#1 H30 FBA_DQS_RN0 1 2 DQSC#1 E4 FBB_DQS_RN0 DIS@
DQSA#2 E34 FBA_DQS_RN1 CG46 0.1U_0402_16V7K DQSC#2 B2 FBB_DQS_RN1
DQSA#3 M34 FBA_DQS_RN2 H26 T11 DIS@ DQSC#3 A9 FBB_DQS_RN2 2
<45> DQSA#[7..4] DQSA#4 AF30 FBA_DQS_RN3 FB_VREF <47> DQSC#[7..4] DQSC#4 D22 FBB_DQS_RN3
@
DQSA#5 AK31 FBA_DQS_RN4 DQSC#5 D28 FBB_DQS_RN4
FBA_DQS_RN5 Under GPU FBB_DQS_RN5
DQSA#6 AM34 DQSC#6 A30 Under GPU
DQSA#7 AF32 FBA_DQS_RN6 close to ball : U27 DQSC#7 B23 FBB_DQS_RN6
FBA_DQS_RN7 FBB_DQS_RN7 close to ball : H17

N15P-GT_BGA908 N15P-GT_BGA908
A GC6_FB_EN_R A
@ @

9/29: Del by NV review.

2

DIS@ RG35
Near GPU 10K_0402_5%

Security Classification Compal Secret Data Compal Electronics, Inc.

1

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (3/5) TMDS/LVDS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 41 of 63
5 4 3 2 1
 5 4 3 2 1

Under GPU Near GPU +1.05VGS

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

4.7U_0603_6.3V6K
D

DIS@ CG51

DIS@ CG52

DIS@ CG53

DIS@ CG54

DIS@ CG55

DIS@ CG56
D

1U_0402_6.3V6K
1 1 1 1 1 1

DIS@ CG50
UG1E 1
+1.35VGS Under GPU Part 5 of 7
2 2 2 2 2 2
9000mA 2
AA27 AG19
FBVDDQ_0 PEX_IOVDD_0

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K

0.1U_0402_16V7K
AA30 AG21

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
FBVDDQ_1 PEX_IOVDD_1
DIS@ CG57

DIS@ CG58

DIS@ CG48

DIS@ CG59

DIS@ CG49

DIS@ CG60
1 1 1 1 1 1 AB27 AG22
AB33 FBVDDQ_2 PEX_IOVDD_2 AG24
AC27 FBVDDQ_3 PEX_IOVDD_3 AH21
AD27 FBVDDQ_4 PEX_IOVDD_4 AH25
2 2 2 2 2 2 AE27 FBVDDQ_5 PEX_IOVDD_5 Under GPU Near GPU +1.05VGS
AF27 FBVDDQ_6
AG27 FBVDDQ_7 AG13
FBVDDQ_8 PEX_IOVDDQ_0

10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M
1U_0402_6.3V6K

1U_0402_6.3V6K
B13 AG15

4.7U_0603_6.3V6K
FBVDDQ_9 PEX_IOVDDQ_1

DIS@ CG61

DIS@ CG62

DIS@ CG63

DIS@ CG64

DIS@ CG65

DIS@ CG66

DIS@ CG67
Under GPU B19 AG16 1 1 1 1 1 1 1
E13 FBVDDQ_11 PEX_IOVDDQ_2 AG18
E19 FBVDDQ_12 PEX_IOVDDQ_3 AG25
FBVDDQ_14 PEX_IOVDDQ_4
1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
H10 AH15
4.7U_0603_6.3V6K

4.7U_0603_6.3V6K

FBVDDQ_15 PEX_IOVDDQ_5 2 2 2 2 2 2 2
DIS@ CG68

DIS@ CG69

DIS@ CG70

DIS@ CG71

DIS@ CG72

DIS@ CG73
1 1 1 1 1 1 H11 AH18
H12 FBVDDQ_16 PEX_IOVDDQ_6 AH26
H13 FBVDDQ_17 PEX_IOVDDQ_7 AH27
H14 FBVDDQ_18 PEX_IOVDDQ_8 AJ27
2 2 2 2 2 2 H18 FBVDDQ_19 PEX_IOVDDQ_9 AK27
H19 FBVDDQ_22 PEX_IOVDDQ_10 AL27
H20 FBVDDQ_23 PEX_IOVDDQ_11 AM28

POWER
H21 FBVDDQ_24 PEX_IOVDDQ_12 AN28
Near GPU H22 FBVDDQ_25 PEX_IOVDDQ_13
H23 FBVDDQ_26 +3VGS_AON
H24 FBVDDQ_27 Near GPU
330U 2V D2 LESR9M EEFSX H1.9

FBVDDQ_28
10U_0603_6.3V6M

10U_0603_6.3V6M

22U_0805_6.3V6M

22U_0805_6.3V6M

N14P_GB4-128 H8 AH12
DG-6246_V04 FBVDDQ_29 PEX_PLL_HVDD
DIS@ CG76

DIS@ CG77

DIS@ CG78

DIS@ CG79

1U_0402_6.3V6K
H9

4.7U_0603_6.3V6K

4.7U_0603_6.3V6K
C
1 1 1 1 FBVDDQ_30
@ CG74

DIS@ CG80

DIS@ CG81

DIS@ CG82
L27 1 2 DIS@ C
1 FBVDDQ_31 1 1 1
SGA20331E10

M27 CG75 0.1U_0402_16V7K

+ N27 FBVDDQ_32 AG12
2 2 2 2 P27 FBVDDQ_33 PEX_SVDD_3V3
R27 FBVDDQ_34 @ 1 2 2 2 2
2 T27 FBVDDQ_35 CG83 0.1U_0402_16V7K
T30 FBVDDQ_36 AG26
T33 FBVDDQ_37 PEX_PLLVDD
Y27 FBVDDQ_38
FBVDDQ_43 +1.05VGS
J8 Under GPU Near GPU
3V3_AON K8
3V3_AON

0.1U_0402_16V7K

1U_0402_6.3V6K
L8

4.7U_0603_6.3V6K
3V3_MAIN

DIS@ CG84

DIS@ CG85

DIS@ CG86
B16 M8 1 1 1
E16 FBVDDQ_AON 3V3_MAIN
H15 FBVDDQ_AON
H16 FBVDDQ_AON
V27 FBVDDQ_AON AH8 2 2 2
W27 FBVDDQ_AON IFPAB_PLLVDD AJ8
W30 FBVDDQ_AON IFPAB_RSET
W33 FBVDDQ_AON AG8
FBVDDQ_AON IFPA_IOVDD AG9
IFPB_IOVDD

AF7 Under GPU (one per pin) Near GPU +3VGS_AON

+1.35VGS IFPC_PLLVDD AF8
IFPC_RSET

0.1U_0402_16V7K
FB_VDDQ_SENSE

0.1U_0402_16V7K

1U_0402_6.3V6K
2 1 F1 AF6

4.7U_0603_6.3V6K
@
FB_VDDQ_SENSE IFPC_IOVDD

DIS@ CG87

DIS@ CG88

DIS@ CG89

DIS@ CG90
RG36 10_0402_5% 1 1 1 1
2 @ 1 FB_GND_SENSE F2 AG7
+1.35VGS RG37 10_0402_5% FB_GND_SENSE IFPD_PLLVDD AN2
B NC_AN2 2 2 2 2 B
2 DIS@ 1 FB_CAL_PD_VDDQ J27 AG6
RG38 40.2_0402_1% FB_CAL_PD_VDDQ IFPD_IOVDD

2 DIS@ 1 FB_CAL_PU_GND H27 AB8

RG39 42.2_0402_1% FB_CAL_PU_GND IFPEF_PLVDD AD6
IFPEF_RSET
Under GPU (one per pin) Near GPU +3VGS_MAIN
2 DIS@ 1 FB_CAL_TERM_GND H25 AC7
RG40 51.1_0402_1% FB_CAL_TERM_GND IFPE_IOVDD AC8
IFPF_IOVDD

0.1U_0402_16V7K

0.1U_0402_16V7K

1U_0402_6.3V6K

4.7U_0603_6.3V6K
DIS@ CG91

DIS@ CG92

DIS@ CG93

DIS@ CG94
Place near balls 1 1 1 1

N15P-GT_BGA908 2 2 2 2
@

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (4/5) POWER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 42 of 63
5 4 3 2 1
 5 4 3 2 1

UG1F

Part 6 of 7
A2 D2
AA17 GND_0 GND_100 D31
+VGA_CORE UG1G +VGA_CORE AA18 GND_1 GND_101 D33
AA20 GND_2 GND_102 E10
AA22 GND_3 GND_103 E22
Part 7 of 7 V17 AB12 GND_4 GND_104 E25
D AA12 VDD_56 V18 AB14 GND_5 GND_105 E5 D
AA14 VDD_0 VDD_57 V20 AB16 GND_6 GND_106 E7
AA16 VDD_1 VDD_58 V22 AB19 GND_7 GND_107 F28
AA19 VDD_2 VDD_59 W12 AB2 GND_8 GND_108 F7
AA21 VDD_3 VDD_60 W14 AB21 GND_9 GND_109 G10
AA23 VDD_4 VDD_61 W16 A33 GND_10 GND_110 G13
AB13 VDD_5 VDD_62 W19 AB23 GND_11 GND_111 G16
AB15 VDD_6 VDD_63 W21 AB28 GND_12 GND_112 G19
AB17 VDD_7 VDD_64 W23 AB30 GND_13 GND_113 G2
AB18 VDD_8 VDD_65 Y13 AB32 GND_14 GND_114 G22
AB20 VDD_9 VDD_66 Y15 AB5 GND_15 GND_115 G25
AB22 VDD_10 VDD_67 Y17 AB7 GND_16 GND_116 G28
AC12 VDD_11 VDD_68 Y18 AC13 GND_17 GND_117 G3
AC14 VDD_12 VDD_69 Y20 AC15 GND_18 GND_118 G30
AC16 VDD_13 VDD_70 Y22 AC17 GND_19 GND_119 G32
AC19 VDD_14 VDD_71 AC18 GND_20 GND_120 G33
AC21 VDD_15 AA13 GND_21 GND_121 G5
AC23 VDD_16 U1 AC20 GND_22 GND_122 G7
M12 VDD_17 XVDD_1 U2 AC22 GND_23 GND_123 K2
M14 VDD_18 XVDD_2 U3 AE2 GND_24 GND_124 K28
M16 VDD_19 XVDD_3 U4 AE28 GND_25 GND_125 K30

POWER
M19 VDD_20 XVDD_4 U5 AE30 GND_26 GND_126 K32
M21 VDD_21 XVDD_5 U6 AE32 GND_27 GND_127 K33
M23 VDD_22 XVDD_6 U7 AE33 GND_28 GND_128 K5
N13 VDD_23 XVDD_7 U8 AE5 GND_29 GND_129 K7
N15 VDD_24 XVDD_8 AE7 GND_30 GND_130 M13
N17 VDD_25 AH10 GND_31 GND_131 M15
N18 VDD_26 V1 AA15 GND_32 GND_132 M17
N20 VDD_27 XVDD_9 V2 AH13 GND_33 GND_133 M18
N22 VDD_28 XVDD_10 V3 AH16 GND_34 GND_134 M20
P12 VDD_29 XVDD_11 V4 AH19 GND_35 GND_135 M22
P14 VDD_30 XVDD_12 V5 AH2 GND_36 GND_136 N12
C P16 VDD_31 XVDD_13 V6 AH22 GND_37 GND_137 N14 C
P19 VDD_32 XVDD_14 V7 AH24 GND_38 GND_138 N16
P21 VDD_33 XVDD_15 V8 AH28 GND_39 GND_139 N19
P23 VDD_34 XVDD_16 AH29 GND_40 GND_140 N2
R13 VDD_35 AH30 GND_41 GND_141 N21
R15 VDD_36 W2 AH32 GND_42 GND_142 N23
R17 VDD_37 XVDD_17 W3 AH33 GND_43 GND_143 N28

GND
R18 VDD_38 XVDD_18 W4 AH5 GND_44 GND_144 N30
R20 VDD_39 XVDD_19 W5 AH7 GND_45 GND_145 N32
R22 VDD_40 XVDD_20 W7 AJ7 GND_46 GND_146 N33
T12 VDD_41 XVDD_21 W8 AK10 GND_47 GND_147 N5
T14 VDD_42 XVDD_22 AK7 GND_48 GND_148 N7
T16 VDD_43 AL12 GND_49 GND_149 P13
T19 VDD_44 Y1 AL14 GND_50 GND_150 P15
T21 VDD_45 NC_Y1 Y2 AL15 GND_51 GND_151 P17
T23 VDD_46 NC_Y2 Y3 AL17 GND_52 GND_152 P18
U13 VDD_47 NC_Y3 Y4 AL18 GND_53 GND_153 P20
U15 VDD_48 XVDD_23 Y5 AL2 GND_54 GND_154 P22
U17 VDD_49 XVDD_24 Y6 AL20 GND_55 GND_155 R12
U18 VDD_50 XVDD_25 Y7 AL21 GND_56 GND_156 R14
U20 VDD_51 XVDD_26 Y8 AL23 GND_57 GND_157 R16
U22 VDD_52 XVDD_27 AL24 GND_58 GND_158 R19
V13 VDD_53 AL26 GND_59 GND_159 R21
V15 VDD_54 AA1 AL28 GND_60 GND_160 R23
VDD_55 NC_AA1 AA2 AL30 GND_61 GND_161 T13
NC_AA2 AA3 AL32 GND_62 GND_162 T15
NC_AA3 AA4 AL33 GND_63 GND_163 T17
NC_AA4 AA5 AL5 GND_64 GND_164 T18
NC_AA5 AA6 AM13 GND_65 GND_165 T2
NC_AA6 AA7 AM16 GND_66 GND_166 T20
NC_AA7 AA8 AM19 GND_67 GND_167 T22
NC_AA8 AM22 GND_68 GND_168 AG11
B AM25 GND_69 GND_169 T28 B
AN1 GND_70 GND_170 T32
AN10 GND_71 GND_171 T5
N15P-GT_BGA908 AN13 GND_72 GND_172 T7
AN16 GND_73 GND_173 U12
@ GND_74 GND_174
AN19 U14
AN22 GND_75 GND_175 U16
AN25 GND_76 GND_176 U19
AN30 GND_77 GND_177 U21
AN34 GND_78 GND_178 U23
AN4 GND_79 GND_179 V12
AN7 GND_80 GND_180 V14
AP2 GND_81 GND_181 V16
AP33 GND_82 GND_182 V19
B1 GND_83 GND_183 V21
B10 GND_84 GND_184 V23
B22 GND_85 GND_185 W13
B25 GND_86 GND_186 W15
B28 GND_87 GND_187 W17
B31 GND_88 GND_188 W18
B34 GND_89 GND_189 W20
B4 GND_90 GND_190 W22
B7 GND_91 GND_191 W28
C10 GND_92 GND_192 Y12
C13 GND_93 GND_193 Y14
C19 GND_94 GND_194 Y16
C22 GND_95 GND_195 Y19
C25 GND_96 GND_196 Y21
C28 GND_97 GND_197 Y23
C7 GND_98 GND_198 AH11
GND_99 GND_199 C16
GND_OPT W32
A GND_OPT A

N15P-GT_BGA908
@

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX (5/5) POWER/ GND
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 43 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Lower 32 bits [31..0]

UGV2 @
UGV1 @
+VREFC_UGV1 M8 E3 MDA4
DQMA[3..0] +VREFC_UGV1 M8 E3 MDA12 +VREFD_UGV1 H1 VREFCA DQ0 F7 MDA1
<41> DQMA[3..0] +VREFD_UGV1 H1 VREFCA DQ0 F7 MDA9 VREFDQ DQ1 F2 MDA5
CMDA[31..0] VREFDQ DQ1 F2 MDA13 CMDA9 N3 DQ2 F8 MDA0
<41,45> CMDA[31..0] CMDA9 N3 DQ2 F8 MDA8 CMDA11 P7 A0 DQ3 H3 MDA6
DQSA[3..0] CMDA11 P7 A0 DQ3 H3 MDA14 CMDA8 P3 A1 DQ4 H8 MDA3
D <41> DQSA[3..0] CMDA8 P3 A1 DQ4 H8 MDA10 CMDA25 N2 A2 DQ5 G2 MDA7 D
DQSA#[3..0] CMDA25 N2 A2 DQ5 G2 MDA15 CMDA10 P8 A3 DQ6 H7 MDA2
<41> DQSA#[3..0] CMDA10 P8 A3 DQ6 H7 MDA11 CMDA24 P2 A4 DQ7
MDA[31..0] CMDA24 P2 A4 DQ7 CMDA22 R8 A5
<41> MDA[31..0] CMDA22 R8 A5 CMDA7 R2 A6 D7 MDA18
CMDA7 R2 A6 D7 MDA26 CMDA21 T8 A7 DQ8 C3 MDA20
CMDA21 T8 A7 DQ8 C3 MDA28 CMDA6 R3 A8 DQ9 C8 MDA16
CMDA6 R3 A8 DQ9 C8 MDA24 CMDA29 L7 A9 DQ10 C2 MDA21
CMDA29 L7 A9 DQ10 C2 MDA29 CMDA23 R7 A10/AP DQ11 A7 MDA17
CMDA23 R7 A10/AP DQ11 A7 MDA25 CMDA28 N7 A11 DQ12 A2 MDA22
CMDA28 N7 A11 DQ12 A2 MDA30 CMDA20 T3 A12/BC# DQ13 B8 MDA19
CMDA20 T3 A12/BC# DQ13 B8 MDA27 CMDA4 T7 A13 DQ14 A3 MDA23
CMDA4 T7 A13 DQ14 A3 MDA31 CMDA14 M7 A14 DQ15
CMDA14 M7 A14 DQ15 A15/NC +1.35VGS
A15/NC +1.35VGS 1.35V
1.35V CMDA12 M2 B2
BA0 VDD

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
CMDA12 M2 B2 CMDA27 N8 D9
BA0 VDD BA1 VDD

DIS@ CGV4

DIS@ CGV5

DIS@ CGV6
0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
CMDA27 N8 D9 CMDA26 M3 G7 1 1 1
BA1 VDD BA2 VDD

DIS@ CGV1

DIS@ CGV2

DIS@ CGV3
Place close to Vram CMDA26 M3 G7 1 1 1 K2
BA2 VDD K2 VDD K8
CLKA0 VDD K8 VDD N1
VDD N1 CLKA0 J7 VDD N9 2 2 2
VDD CK VDD PLACE 0.1uF CAPS CLOSEST
1

CLKA0 J7 N9 2 2 2 CLKA0# K7 R1
<41> CLKA0
CLKA0# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST CK# VDD R9 TO THE MEMORY DEVICES
RGV1
162_0402_1%
<41> CLKA0# CK# VDD R9 TO THE MEMORY DEVICES VDD
DIS@ VDD CMDA3 K9
CMDA3 K9 J9 CKE0 A1
PLACE LARGER CAPACITORS
PLACE LARGER CAPACITORS SLIGHTLY FARTHER AWAY
2

CLKA0# J9 CKE0 A1 CMDA2 K1 CKE1/NC VDDQ A8

CMDA2 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY J1 ODT0 VDDQ C1
J1 ODT0 VDDQ C1 CMDA0 L2 ODT1/NC VDDQ C9
CMDA0 L2 ODT1/NC VDDQ C9 L1 CS0# VDDQ D2
L1 CS0# VDDQ D2 CS1#/NC VDDQ E9 +1.35VGS
C CS1#/NC VDDQ E9 +1.35VGS VDDQ F1 C
VDDQ F1 CMDA30 J3 VDDQ H2
VDDQ RAS# VDDQ 1.35V
CMDA30 J3 H2 1.35V CMDA15 K3 H9
CMDA15 K3 RAS# VDDQ H9 CMDA13 L3 CAS# VDDQ
CAS# VDDQ WE#

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CMDA13 L3
WE#

10U_0603_6.3V6M

DIS@ CGV15

DIS@ CGV16

DIS@ CGV17

DIS@ CGV18

DIS@ CGV19

DIS@ CGV20

DIS@ CGV21

DIS@ CGV22
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
A9 1 1 1 1 1 1 1 1
VSS

DIS@ CGV7

DIS@ CGV8

DIS@ CGV9

DIS@ CGV10

DIS@ CGV11

DIS@ CGV12

DIS@ CGV13

DIS@ CGV14
A9 1 1 1 1 1 1 1 1 DQSA0 F3 B3
DQSA1 F3 VSS B3 DQSA2 C7 LDQS VSS E1
DQSA3 C7 LDQS VSS E1 UDQS VSS G8
UDQS VSS G8 VSS J2 2 2 2 2 2 2 2 2
VSS J2 2 2 2 2 2 2 2 2 DQSA#0 G3 VSS J8
DQSA#1 G3 VSS J8 DQSA#2 B7 LDQS# VSS M1
DQSA#3 B7 LDQS# VSS M1 UDQS# VSS M9
UDQS# VSS M9 VSS P1
VSS P1 DQMA0 E7 VSS P9
DQMA1 E7 VSS P9 DQMA2 D3 LDM VSS T1
DQMA3 D3 LDM VSS T1 UDM VSS T9
UDM VSS T9 VSS
VSS
CMDA5 T2 B1
CMDA5 T2 B1 RESET# VSSQ B9
RESET# VSSQ B9 VSSQ D1
VSSQ D1 VSSQ D8
VSSQ D8 RGV2 1 DIS@ 2 243_0402_1% L8 VSSQ E2
RGV3 1 DIS@ 2 243_0402_1% L8 VSSQ E2 ZQ0 VSSQ E8
ZQ0 VSSQ E8 L9 VSSQ F9
L9 VSSQ F9 ZQ1/NC VSSQ G1
ZQ1/NC VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3L
SDRAM DDR3L H5TC4G63AFR-11C_FBGA96
B H5TC4G63AFR-11C_FBGA96 B

+1.35VGS
+1.35VGS
1
1

RGV5
RGV4 1.33K_0402_1%
1.33K_0402_1% DIS@
DIS@
2

+VREFD_UGV1
2

+VREFC_UGV1
A15 is not required for any x16
1

1
device, even up to 4Gb density.
1

1 RGV7 CGV24
RGV6 CGV23 1.33K_0402_1% 0.01U_0402_25V7K
1.33K_0402_1% 0.01U_0402_25V7K DIS@ DIS@
DIS@ DIS@ 2 A15 is only needed if we support
2

2
x8 configurations, and only at
2

A 4Gb. A

Security Classification
2015/04/13
Compal Secret Data
2018/04/13 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3_A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 44 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition A - Upper 32 bits [63..32]

UGV3 @ UGV4 @
DQMA[7..4]
<41> DQMA[7..4] +VREFC_UGV3 M8 E3 MDA41 +VREFC_UGV3 M8 E3 MDA33
CMDA[31..0] +VREFD_UGV3 H1 VREFCA DQ0 F7 MDA45 +VREFD_UGV3 H1 VREFCA DQ0 F7 MDA36
<41,44> CMDA[31..0] VREFDQ DQ1 F2 MDA43 VREFDQ DQ1 F2 MDA34
DQSA[7..4] CMDA9 N3 DQ2 F8 MDA44 CMDA9 N3 DQ2 F8 MDA39
D <41> DQSA[7..4] CMDA11 P7 A0 DQ3 H3 MDA40 CMDA11 P7 A0 DQ3 H3 MDA35 D
DQSA#[7..4] CMDA8 P3 A1 DQ4 H8 MDA46 CMDA8 P3 A1 DQ4 H8 MDA38
<41> DQSA#[7..4] CMDA25 N2 A2 DQ5 G2 MDA42 CMDA25 N2 A2 DQ5 G2 MDA32
MDA[63..32] CMDA10 P8 A3 DQ6 H7 MDA47 CMDA10 P8 A3 DQ6 H7 MDA37
<41> MDA[63..32] CMDA24 P2 A4 DQ7 CMDA24 P2 A4 DQ7
CMDA22 R8 A5 CMDA22 R8 A5
CMDA7 R2 A6 D7 MDA50 CMDA7 R2 A6 D7 MDA58
CMDA21 T8 A7 DQ8 C3 MDA52 CMDA21 T8 A7 DQ8 C3 MDA60
CMDA6 R3 A8 DQ9 C8 MDA48 CMDA6 R3 A8 DQ9 C8 MDA56
CMDA29 L7 A9 DQ10 C2 MDA53 CMDA29 L7 A9 DQ10 C2 MDA62
CMDA23 R7 A10/AP DQ11 A7 MDA49 CMDA23 R7 A10/AP DQ11 A7 MDA57
CMDA28 N7 A11 DQ12 A2 MDA54 CMDA28 N7 A11 DQ12 A2 MDA63
CMDA20 T3 A12/BC# DQ13 B8 MDA51 CMDA20 T3 A12/BC# DQ13 B8 MDA59
CMDA4 T7 A13 DQ14 A3 MDA55 CMDA4 T7 A13 DQ14 A3 MDA61
CMDA14 M7 A14 DQ15 CMDA14 M7 A14 DQ15
A15/NC +1.35VGS A15/NC +1.35VGS
1.35V 1.35V
CMDA12 M2 B2 CMDA12 M2 B2
BA0 VDD BA0 VDD

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
Place close to Vram CMDA27 N8 D9 CMDA27 N8 D9
BA1 VDD BA1 VDD

DIS@ CGV25

DIS@ CGV26

DIS@ CGV27

DIS@ CGV28

DIS@ CGV29

DIS@ CGV30
CMDA26 M3 G7 1 1 1 CMDA26 M3 G7 1 1 1
BA2 VDD K2 BA2 VDD K2
CLKA1 VDD K8 VDD K8
VDD N1 VDD N1
VDD VDD
1

CLKA1 J7 N9 2 2 2 CLKA1 J7 N9 2 2 2
<41> CLKA1
CLKA1# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST CLKA1# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST
RGV8
162_0402_1%
<41> CLKA1# CK# VDD R9 TO THE MEMORY DEVICES CK# VDD R9 TO THE MEMORY DEVICES
DIS@ VDD VDD
CMDA19 K9 CMDA19 K9
PLACE LARGER CAPACITORS PLACE LARGER CAPACITORS
2

CLKA1# J9 CKE0 A1 J9 CKE0 A1

CMDA18 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY CMDA18 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY
J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
CMDA16 L2 ODT1/NC VDDQ C9 CMDA16 L2 ODT1/NC VDDQ C9
C L1 CS0# VDDQ D2 L1 CS0# VDDQ D2 C
CS1#/NC VDDQ E9 +1.35VGS CS1#/NC VDDQ E9 +1.35VGS
VDDQ F1 VDDQ F1
CMDA30 J3 VDDQ H2 CMDA30 J3 VDDQ H2
RAS# VDDQ 1.35V RAS# VDDQ 1.35V
CMDA15 K3 H9 CMDA15 K3 H9
CMDA13 L3 CAS# VDDQ CMDA13 L3 CAS# VDDQ
WE# WE#

10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DIS@ CGV31

DIS@ CGV32

DIS@ CGV33

DIS@ CGV34

DIS@ CGV35

DIS@ CGV36

DIS@ CGV37

DIS@ CGV38

DIS@ CGV39

DIS@ CGV40

DIS@ CGV41

DIS@ CGV42

DIS@ CGV43

DIS@ CGV44

DIS@ CGV45

DIS@ CGV46
A9 1 1 1 1 1 1 1 1 A9 1 1 1 1 1 1 1 1
DQSA5 F3 VSS B3 DQSA4 F3 VSS B3
DQSA6 C7 LDQS VSS E1 DQSA7 C7 LDQS VSS E1
UDQS VSS G8 UDQS VSS G8
VSS J2 2 2 2 2 2 2 2 2 VSS J2 2 2 2 2 2 2 2 2
DQSA#5 G3 VSS J8 DQSA#4 G3 VSS J8
DQSA#6 B7 LDQS# VSS M1 DQSA#7 B7 LDQS# VSS M1
UDQS# VSS M9 UDQS# VSS M9
VSS P1 VSS P1
DQMA5 E7 VSS P9 DQMA4 E7 VSS P9
DQMA6 D3 LDM VSS T1 DQMA7 D3 LDM VSS T1
UDM VSS T9 UDM VSS T9
VSS VSS

CMDA5 T2 B1 CMDA5 T2 B1
RESET# VSSQ B9 RESET# VSSQ B9
VSSQ D1 VSSQ D1
VSSQ D8 VSSQ D8
RGV9 1 DIS@ 2 243_0402_1% L8 VSSQ E2 RGV101 DIS@ 2 243_0402_1% L8 VSSQ E2
ZQ0 VSSQ E8 ZQ0 VSSQ E8
L9 VSSQ F9 L9 VSSQ F9
ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
B SDRAM DDR3L SDRAM DDR3L B
H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96

+1.35VGS +1.35VGS
1

RGV11 RGV12
1.33K_0402_1% 1.33K_0402_1%
DIS@ DIS@
2

+VREFC_UGV3 +VREFD_UGV3
1

RGV13
1
CGV47 RGV14
1
CGV48
A15 is not required for any x16
1.33K_0402_1% 0.01U_0402_25V7K 1.33K_0402_1% 0.01U_0402_25V7K device, even up to 4Gb density.
DIS@ DIS@ DIS@ DIS@
2 2
A15 is only needed if we support
2

A
x8 configurations, and only at A
4Gb.

Security Classification
2015/04/13
Compal Secret Data
2018/04/13 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3_A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 45 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Lower 32 bits [31..0]

DQMC[3..0]
<41> DQMC[3..0]
UGV6 @
CMDC[31..0] UGV5 @
<41,47> CMDC[31..0] +VREFC_UGV5 M8 E3 MDC0
DQSC[3..0] +VREFC_UGV5 M8 E3 MDC15 +VREFD_UGV5 H1 VREFCA DQ0 F7 MDC3
<41> DQSC[3..0] +VREFD_UGV5 H1 VREFCA DQ0 F7 MDC13 VREFDQ DQ1 F2 MDC2
DQSC#[3..0] VREFDQ DQ1 F2 MDC12 CMDC9 N3 DQ2 F8 MDC1
<41> DQSC#[3..0] CMDC9 N3 DQ2 F8 MDC14 CMDC11 P7 A0 DQ3 H3 MDC7
MDC[31..0] CMDC11 P7 A0 DQ3 H3 MDC9 CMDC8 P3 A1 DQ4 H8 MDC5
D <41> MDC[31..0] CMDC8 P3 A1 DQ4 H8 MDC10 CMDC25 N2 A2 DQ5 G2 MDC4 D
CMDC25 N2 A2 DQ5 G2 MDC11 CMDC10 P8 A3 DQ6 H7 MDC6
CMDC10 P8 A3 DQ6 H7 MDC8 CMDC24 P2 A4 DQ7
CMDC24 P2 A4 DQ7 CMDC22 R8 A5
CMDC22 R8 A5 CMDC7 R2 A6 D7 MDC25
CMDC7 R2 A6 D7 MDC18 CMDC21 T8 A7 DQ8 C3 MDC30
CMDC21 T8 A7 DQ8 C3 MDC20 CMDC6 R3 A8 DQ9 C8 MDC27
CMDC6 R3 A8 DQ9 C8 MDC16 CMDC29 L7 A9 DQ10 C2 MDC29
CMDC29 L7 A9 DQ10 C2 MDC21 CMDC23 R7 A10/AP DQ11 A7 MDC26
CMDC23 R7 A10/AP DQ11 A7 MDC17 CMDC28 N7 A11 DQ12 A2 MDC28
CMDC28 N7 A11 DQ12 A2 MDC22 CMDC20 T3 A12/BC# DQ13 B8 MDC24
CMDC20 T3 A12/BC# DQ13 B8 MDC19 CMDC4 T7 A13 DQ14 A3 MDC31
CMDC4 T7 A13 DQ14 A3 MDC23 CMDC14 M7 A14 DQ15
CMDC14 M7 A14 DQ15 A15/NC +1.35VGS
A15/NC +1.35VGS 1.35V
1.35V CMDC12 M2 B2
BA0 VDD

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
CMDC12 M2 B2 CMDC27 N8 D9
BA0 VDD BA1 VDD

DIS@ CGV52

DIS@ CGV53

DIS@ CGV54
0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
CMDC27 N8 D9 CMDC26 M3 G7 1 1 1
BA1 VDD BA2 VDD

DIS@ CGV49

DIS@ CGV50

DIS@ CGV51
Place close to Vram CMDC26 M3 G7 1 1 1 K2
BA2 VDD K2 VDD K8
CLKC0 VDD K8 VDD N1
VDD N1 CLKC0 J7 VDD N9 2 2 2
VDD CK VDD PLACE 0.1uF CAPS CLOSEST
1

CLKC0 J7 N9 2 2 2 CLKC0# K7 R1
<41> CLKC0
CLKC0# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST CK# VDD R9 TO THE MEMORY DEVICES
RGV15
162_0402_1%
<41> CLKC0# CK# VDD R9 TO THE MEMORY DEVICES VDD
DIS@ VDD CMDC3 K9
CMDC3 K9 J9 CKE0 A1
PLACE LARGER CAPACITORS
PLACE LARGER CAPACITORS SLIGHTLY FARTHER AWAY
2

CLKC0# J9 CKE0 A1 CMDC2 K1 CKE1/NC VDDQ A8

CMDC2 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY J1 ODT0 VDDQ C1
J1 ODT0 VDDQ C1 CMDC0 L2 ODT1/NC VDDQ C9
CMDC0 L2 ODT1/NC VDDQ C9 L1 CS0# VDDQ D2
L1 CS0# VDDQ D2 CS1#/NC VDDQ E9 +1.35VGS
C CS1#/NC VDDQ E9 +1.35VGS VDDQ F1 C
VDDQ F1 CMDC30 J3 VDDQ H2
VDDQ RAS# VDDQ 1.35V
CMDC30 J3 H2 1.35V CMDC15 K3 H9
CMDC15 K3 RAS# VDDQ H9 CMDC13 L3 CAS# VDDQ
CAS# VDDQ WE#

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
CMDC13 L3
WE#

10U_0603_6.3V6M

DIS@ CGV63

DIS@ CGV64

DIS@ CGV65

DIS@ CGV66

DIS@ CGV67

DIS@ CGV68

DIS@ CGV69

DIS@ CGV70
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
A9 1 1 1 1 1 1 1 1
VSS

DIS@ CGV55

DIS@ CGV56

DIS@ CGV57

DIS@ CGV58

DIS@ CGV59

DIS@ CGV60

DIS@ CGV61

DIS@ CGV62
A9 1 1 1 1 1 1 1 1 DQSC0 F3 B3
DQSC1 F3 VSS B3 DQSC3 C7 LDQS VSS E1
DQSC2 C7 LDQS VSS E1 UDQS VSS G8
UDQS VSS G8 VSS J2 2 2 2 2 2 2 2 2
VSS J2 2 2 2 2 2 2 2 2 DQSC#0 G3 VSS J8
DQSC#1 G3 VSS J8 DQSC#3 B7 LDQS# VSS M1
DQSC#2 B7 LDQS# VSS M1 UDQS# VSS M9
UDQS# VSS M9 VSS P1
VSS P1 DQMC0 E7 VSS P9
DQMC1 E7 VSS P9 DQMC3 D3 LDM VSS T1
DQMC2 D3 LDM VSS T1 UDM VSS T9
UDM VSS T9 VSS
VSS
CMDC5 T2 B1
CMDC5 T2 B1 RESET# VSSQ B9
RESET# VSSQ B9 VSSQ D1
VSSQ D1 VSSQ D8
VSSQ D8 RGV161 DIS@ 2 243_0402_1% L8 VSSQ E2
RGV171 DIS@ 2 243_0402_1% L8 VSSQ E2 ZQ0 VSSQ E8
ZQ0 VSSQ E8 L9 VSSQ F9
L9 VSSQ F9 ZQ1/NC VSSQ G1
ZQ1/NC VSSQ G1 VSSQ G9
VSSQ G9 VSSQ
VSSQ 96-BALL
96-BALL SDRAM DDR3L
SDRAM DDR3L H5TC4G63AFR-11C_FBGA96
B H5TC4G63AFR-11C_FBGA96 B

+1.35VGS +1.35VGS
1

RGV18 RGV19
1.33K_0402_1% 1.33K_0402_1%
DIS@ DIS@
2

+VREFC_UGV5 +VREFD_UGV5
1

1 1
RGV20 CGV71 RGV21 CGV72
1.33K_0402_1% 0.01U_0402_25V7K 1.33K_0402_1% 0.01U_0402_25V7K
DIS@ DIS@ DIS@ DIS@ A15 is not required for any x16
2 2
device, even up to 4Gb density.
2

A15 is only needed if we support

x8 configurations, and only at
A 4Gb. A

Security Classification
2015/04/13
Compal Secret Data
2018/04/13 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3_A Lower
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 46 of 63
5 4 3 2 1
 5 4 3 2 1

Memory Partition C - Upper 32 bits [63..32]

DQMC[7..4]
<41> DQMC[7..4]
UGV7 @ UGV8 @
CMDC[31..0]
<41,46> CMDC[31..0] +VREFC_UGV7 M8 E3 MDC47 +VREFC_UGV7 M8 E3 MDC32
DQSC[7..4] +VREFD_UGV7 H1 VREFCA DQ0 F7 MDC45 +VREFD_UGV7 H1 VREFCA DQ0 F7 MDC35
<41> DQSC[7..4] VREFDQ DQ1 F2 MDC46 VREFDQ DQ1 F2 MDC33
DQSC#[7..4] CMDC9 N3 DQ2 F8 MDC44 CMDC9 N3 DQ2 F8 MDC34
D <41> DQSC#[7..4] CMDC11 P7 A0 DQ3 H3 MDC42 CMDC11 P7 A0 DQ3 H3 MDC37 D
MDC[63..32] CMDC8 P3 A1 DQ4 H8 MDC40 CMDC8 P3 A1 DQ4 H8 MDC39
<41> MDC[63..32] CMDC25 N2 A2 DQ5 G2 MDC41 CMDC25 N2 A2 DQ5 G2 MDC36
CMDC10 P8 A3 DQ6 H7 MDC43 CMDC10 P8 A3 DQ6 H7 MDC38
CMDC24 P2 A4 DQ7 CMDC24 P2 A4 DQ7
CMDC22 R8 A5 CMDC22 R8 A5
CMDC7 R2 A6 D7 MDC54 CMDC7 R2 A6 D7 MDC61
CMDC21 T8 A7 DQ8 C3 MDC49 CMDC21 T8 A7 DQ8 C3 MDC59
CMDC6 R3 A8 DQ9 C8 MDC55 CMDC6 R3 A8 DQ9 C8 MDC63
CMDC29 L7 A9 DQ10 C2 MDC50 CMDC29 L7 A9 DQ10 C2 MDC57
CMDC23 R7 A10/AP DQ11 A7 MDC52 CMDC23 R7 A10/AP DQ11 A7 MDC60
CMDC28 N7 A11 DQ12 A2 MDC48 CMDC28 N7 A11 DQ12 A2 MDC56
CMDC20 T3 A12/BC# DQ13 B8 MDC53 CMDC20 T3 A12/BC# DQ13 B8 MDC62
CMDC4 T7 A13 DQ14 A3 MDC51 CMDC4 T7 A13 DQ14 A3 MDC58
CMDC14 M7 A14 DQ15 CMDC14 M7 A14 DQ15
A15/NC +1.35VGS A15/NC +1.35VGS
1.35V 1.35V
CMDC12 M2 B2 CMDC12 M2 B2
BA0 VDD BA0 VDD

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K
Place close to Vram CMDC27 N8 D9 CMDC27 N8 D9
BA1 VDD BA1 VDD

DIS@ CGV73

DIS@ CGV74

DIS@ CGV75

DIS@ CGV76

DIS@ CGV77

DIS@ CGV78
CMDC26 M3 G7 1 1 1 CMDC26 M3 G7 1 1 1
BA2 VDD K2 BA2 VDD K2
CLKC1 VDD K8 VDD K8
VDD N1 VDD N1
VDD VDD
1

CLKC1 J7 N9 2 2 2 CLKC1 J7 N9 2 2 2
<41> CLKC1
CLKC1# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST CLKC1# K7 CK VDD R1
PLACE 0.1uF CAPS CLOSEST
RGV22
162_0402_1%
<41> CLKC1# CK# VDD R9 TO THE MEMORY DEVICES CK# VDD R9 TO THE MEMORY DEVICES
DIS@ VDD VDD
CMDC19 K9 CMDC19 K9
PLACE LARGER CAPACITORS PLACE LARGER CAPACITORS
2

CLKC1# J9 CKE0 A1 J9 CKE0 A1

CMDC18 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY CMDC18 K1 CKE1/NC VDDQ A8 SLIGHTLY FARTHER AWAY
J1 ODT0 VDDQ C1 J1 ODT0 VDDQ C1
CMDC16 L2 ODT1/NC VDDQ C9 CMDC16 L2 ODT1/NC VDDQ C9
C L1 CS0# VDDQ D2 L1 CS0# VDDQ D2 C
CS1#/NC VDDQ E9 +1.35VGS CS1#/NC VDDQ E9 +1.35VGS
VDDQ F1 VDDQ F1
CMDC30 J3 VDDQ H2 CMDC30 J3 VDDQ H2
RAS# VDDQ 1.35V RAS# VDDQ 1.35V
CMDC15 K3 H9 CMDC15 K3 H9
CMDC13 L3 CAS# VDDQ CMDC13 L3 CAS# VDDQ
WE# WE#

10U_0603_6.3V6M

10U_0603_6.3V6M
0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

0.1U_0402_10V7K

1U_0402_6.3V6K

1U_0402_6.3V6K

1U_0402_6.3V6K
DIS@ CGV79

DIS@ CGV80

DIS@ CGV81

DIS@ CGV82

DIS@ CGV83

DIS@ CGV84

DIS@ CGV85

DIS@ CGV86

DIS@ CGV87

DIS@ CGV88

DIS@ CGV89

DIS@ CGV90

DIS@ CGV91

DIS@ CGV92

DIS@ CGV93

DIS@ CGV94
A9 1 1 1 1 1 1 1 1 A9 1 1 1 1 1 1 1 1
DQSC5 F3 VSS B3 DQSC4 F3 VSS B3
DQSC6 C7 LDQS VSS E1 DQSC7 C7 LDQS VSS E1
UDQS VSS G8 UDQS VSS G8
VSS J2 2 2 2 2 2 2 2 2 VSS J2 2 2 2 2 2 2 2 2
DQSC#5 G3 VSS J8 DQSC#4 G3 VSS J8
DQSC#6 B7 LDQS# VSS M1 DQSC#7 B7 LDQS# VSS M1
UDQS# VSS M9 UDQS# VSS M9
VSS P1 VSS P1
DQMC5 E7 VSS P9 DQMC4 E7 VSS P9
DQMC6 D3 LDM VSS T1 DQMC7 D3 LDM VSS T1
UDM VSS T9 UDM VSS T9
VSS VSS

CMDC5 T2 B1 CMDC5 T2 B1
RESET# VSSQ B9 RESET# VSSQ B9
VSSQ D1 VSSQ D1
VSSQ D8 VSSQ D8
RGV231 DIS@ 2 243_0402_1% L8 VSSQ E2 RGV241 DIS@ 2 243_0402_1% L8 VSSQ E2
ZQ0 VSSQ E8 ZQ0 VSSQ E8
L9 VSSQ F9 L9 VSSQ F9
ZQ1/NC VSSQ G1 ZQ1/NC VSSQ G1
VSSQ G9 VSSQ G9
VSSQ VSSQ
96-BALL 96-BALL
B SDRAM DDR3L SDRAM DDR3L B
H5TC4G63AFR-11C_FBGA96 H5TC4G63AFR-11C_FBGA96

+1.35VGS +1.35VGS
1

RGV25 RGV26
1.33K_0402_1% 1.33K_0402_1%
DIS@ DIS@
2

+VREFC_UGV7 +VREFD_UGV7
1

RGV27
1
CGV95 RGV28
1
CGV96
A15 is not required for any x16
1.33K_0402_1% 0.01U_0402_25V7K 1.33K_0402_1% 0.01U_0402_25V7K device, even up to 4Gb density.
DIS@ DIS@ DIS@ DIS@
2 2
A15 is only needed if we support
2

A
x8 configurations, and only at A
4Gb.

Security Classification
2015/04/13
Compal Secret Data
2018/04/13 Title
Compal Electronics, Inc.
Issued Date Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VRAM_DDR3_A Upper
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom LA-C501P 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 47 of 63
5 4 3 2 1
 5 4 3 2 1

2014-10-01:NV Review +1.35V_VDDQ +1.35VGS

For Power consumption Use +3VGS_MAIN as control signal for
Measurement +1.05VGS and +VGACORE to meet power
sequence requirement. Q27 DIS@
AON6504_POWERDFN56-8-5

+3VS +3VS_D
1
2
1
CGV99
+3VS_DGPU for GC6 reserved.

2
JPV1 5 3 0.1U_0402_16V7K +3VS_D
1 2 @ R480
1 2 2 +19VB 470_0402_5%

1U_0402_6.3V6K
JUMP_43X39 V0.3 1
DIS@

CGV98 DIS@
JP@ 1 R529DIS@

1
+1.05VS +1.05VS_D VRAM_1.35VS_GATE 1 2

4.7U_0603_6.3V6K
RG70 C780 180K_0402_5% +3VGS_MAIN

3
1 2 DIS@ 2
1
N16S@ 2 R484 Q29A UG5

0.033U_0402_25V7K
0_0805_5% C781 DIS@ 820K_0402_5% Q29B 1 14
DIS@ 2 1.35V_PWR_EN# 5 2N7002KDWH_SOT363-6 2 VIN1 VOUT1 13
VIN1 VOUT1 1
2 2N7002KDWH_SOT363-6 DIS@ +5VALW CGV104

2
D DIS@ DGPU_MAIN_EN 3 12 1 2 @ 0.1U_0402_16V7K D
9/19:NV add delay. <39> DGPU_MAIN_EN

4
+5VALW ON1 CT1 CGV103 DIS@
4 11 1000P_0402_50V7K 2
1 2 VBIAS GND
DGPU_PWR_EN

1U_0402_6.3V6K
100K_0402_5% R485 1 5 10 1 2 @
<9> DGPU_PWR_EN ON2 CT2

CGV107
DIS@ CGV105
6 9 3300P_0402_50V7K +3VGS_AON
VIN2 VOUT2

1
D

DIS@
7 8
1.35VGS_PWR_EN 2 DIS@ 2 +3VS_D VIN2 VOUT2
<39> 1.35VGS_PWR_EN
G 15 1
Q33 GPAD CGV109
S

3
2N7002_SOT23-3 EM5209VF DFN 14P 0.1U_0402_16V7K
+1.05VS_D UG4 +1.05VGS DGPU_PWR_EN 1 @ 2 DIS@
SA00007PM00
RG52 10K_0402_5% 2
1 7 DIS@
VIN VOUT 1
1 +3VGS_MAIN RG53 2 8 CGV106 9/19:NV review
VIN VOUT

CGV108 N16S@
1U_0402_6.3V6K
5.1K_0402_5% N16S@ 0.1U_0402_16V7K
1 2 3 6 1 2 N16S@
+5VALW ON CT 2

1U_0402_6.3V6K
CG100 N16S@
N16S@ CGV102
2 1000P_0402_50V7K
1
4
VBIAS 5
GND

1U_0402_6.3V6K
CGV101 N16S@
1 9
2 GND

SA00006U600
2 AOZ1336_DFN8_2X2
N16S@

PIR Item 15 GPU VDDQ and VRAM Shared with DDR3

C C

B B

+3VL_EC
2

<39> DGPU_PEX_RST#
RG67
A 10K_0402_5% A
2
G

9/29: NV review.
1

3 1
<39,40> GPU_OVERT# DGPU_OVT# <33>
S

QG4 2N7002K_SOT23-3
DIS@

GPU side EC side

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
N15P-GX DC-DC
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 48 of 63
5 4 3 2 1
 5 4 3 2 1

ACDRV

+19VB
DC IN ACFET RBFET
D D

RT8243 +3VALWP Jumper +3VALW

SY8032ABC
+1.5VSP Jumper +1.5VS
Charger
BQ24735 SUSP#
EN
+5VALWP Jumper +5VALW
EC_ON
EN

BATDRV SY8003D
+1.35VP Jumper +1.35V_VDDQ
RT8207P +1.05VSP Jumper +1.05VS
VDDQ
Battery RBFET SYSON EN_VDDQ SUSP#
BATT S5_+1.35V EN
+0.675VSP +0.6V_0.675VS
Jumper
SUSP# VTT
EN_VTT
S3_+0.675V

C C

SY8003D DIS(N16P) only

+1.05VGSP Jumper +1.05VGS
+3VGS_MAIN
ISL95813
+VCC_CORE EN

VR12.5_VR_ON
EN

RT8813A DIS only

+VGA_CORE
+3VGS_MAIN
EN

B B

A A

Security Classification Compal Secret Data

Compal Electronics, Inc.
Title
Issued Date
2014/10/09 Deciphered Date
2015/12/31
Power Block Diagram
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Re v
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.

LA-C501P 0.1
Date :
W ednesday, April 22, 2015 Sheet
49 of
61
5 4 3 2 1
 5 4 3 2 1

+19V_ADPIN +19V_VIN
EMI@ PL1
5A_Z120_25M_0805_2P
1 2
D D

@ PJP1 EMIVGA@ PL2

ACES_51483-00801-001 5A_Z120_25M_0805_2P
1 1 2
1 2 @ PR2
2 3 0_0402_5%

1000P_0402_50V7K
3 4 1 2 W hite_LED

100P_0402_50V8J

100P_0402_50V8J

1000P_0402_50V7K
4 5 <33> AC_LED#
5 6

1
ADP_SIGNAL

EMI@ PC1

EMI@ PC2

EMI@ PC3

EMI@ PC4
6 7

1
7 8

2
9 8 White_LED PR3
Amber_LED
10 GND 100K_0402_5%
GND

2
PR1
10K_0402_5%
ADP_SIGNAL 1 2 PR5
ADP_ID <33> 360_0402_1%
3

3
<33> BAT_CHG_LED 1 2 Amber_LED

100P_0402_50V8J

1000P_0402_50V7K
1

1
GLZ3.6B_LL34-2
L30ESD24VC3-2_SOT23-3

L30ESD24VC3-2_SOT23-3

1
10K_0402_5%
ESD@ PD1

ESD@ PD2

PR7

@ PD3

@ PC5

PC6
PR8
100K_0402_5%

2
2

2
1

C C

ADP_I <33,52>
2014-10-06:
+3VL_EC
Change EC Power Rail Name

1
PR25 PR26
16.2K_0402_1% 5.9K_0402_1%

2
VCIN0_PH <33> VCIN1_PH <33>

1
PH1 PR27
100K_0402_1%_NCP15W F104F03RC 10K_0402_1%

2
ECAGND <33>

VCIN0_PH set t i gn VCIN1_PH set t i ng

B Trigger point = 1V (92C) 90W B
Recovery point = 2.02V (56C) Act i ve : VCI N1_P H = 0. 799V( 123. 86 W
)
Resume : VCIN1_PH = 0.0.581V(90.07W)
65W
Act i ve : VCI N1_P H = 0. 599( 92. 86 W
)
Resume : VCIN1_PH = 0.419(64.96W)
45W
Act i ve : VCI N1_P H = 0. 414( 64. 18 W
)
Resume : VCIN1_PH = 0.289(44.8W)

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title
DC Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C501P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, April 22, 2015 Sheet 50 of 61
5 4 3 2 1
 5 4 3 2 1

+12.6V_BATT

+3V_LID

D D
@ PRB20

1
0_0402_5%
1 2 PR33 PR34
3.9K_0603_5% 3.9K_0603_5%
@ PJP2
ACES_50278-01001-001 PR22

2
1 100_0402_5%
1 2 EC_SMB_CK1_R 1 2 +3V_LID
2 3 EC_SMB_DA1_R EC_SMB_CK1 <32,33,52> +12.6V_BATT+ +12.6V_BATT
1 2 EMI@ PL3
3 4 EC_SMB_DA1 <32,33,52>
100_0402_5% 5A_Z120_25M_0805_2P
4 5 PR19 1 2
5 6
6 7

1
EMI@ PL4
7 8 B/I#_R 5A_Z120_25M_0805_2P
8 9 1 2 PR31

DMN65D8LDW-7_SOT363-6
9 10 200K_0402_5%
10 11

3
EMI@ PC11

2
GND 12

1
EMI@ PC10 0.01U_0402_25V7K
GND

1
1000P_0402_50V7K

PQ307B
100_0402_5%

2
5

2
PR30

4
DMN65D8LDW-7_SOT363-6
6
PR29

2
100K_0402_5%
1 2

PQ307A
+3VL 2
+3VL

PR32
1M_0402_5%
B/I# <33>

1
2

2
C C
@

2
@ESD@ PD7 @ESD@ PD6
1

L30ESD24VC3-2_SOT23-3 L30ESD24VC3-2_SOT23-3

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title
BATT Conn
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C501P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, April 22, 2015 Sheet 51 of 61
5 4 3 2 1
 A B C D

1
D
2 @ PQB2
G 2N7002KW_SOT323-3
S

3
@ PRB1 @ PRB2
1 2 1 2

1M_0402_5% 3M_0402_5%
1 1

+19V_VIN P1 P2 +19VB
PQB1 PQB3 PRB3 EMI@ PLB1 PQB4
MDU1512RH_POWERDFN56-8-5 SI7716ADN-T1-GE3 1N POWERPAK1212-8 0.01_1206_1% 1.2UH_2.6A_+-30%_4X4X2_F SI7716ADN-T1-GE3 1N POWERPAK1212-8
1 1 1 4 1 2 +19VB_CHG 1
2 2 2

2200P_0402_50V7K
5 3 3 5 2 3 5 3

10U_0805_25V6K

10U_0805_25V6K
0.1U_0402_25V6

@EMI@ PCB4

PCB5

PCB6
68P_0402_50V8J

82P_0402_50V8J
1

1
@RF@ PCB31

@RF@ PCB32

0.01U_0402_50V7K
1
+19V_VIN
2200P_0402_50V7K

PCB2
4

4
1

1
PCB1

PCB7
2

2
1 2
2
2

2
3

2
PCB3
0.1U_0402_25V6 PRB4
ACDRV1_CHG 4.12K_0603_1%

0.1U_0402_25V6
PDB1 BATDRV_CHG 1 2 BATDRV_CHG_R

0.1U_0402_25V6

PCB9
BAS40CW_SOT323-3

1
PCB8
PCB10

10
0.047U_0402_25V7K

2
1 2 5 4

D1
S2 D1

10_1206_1%
PRB5

1
6 3

2.2_0603_5%
S2 D1

PRB6
PDB2
RB751V-40_SOD323-2 7 2 PRB7
S2 D1

D2/S1
0_0603_5%

2
PCB11 8 1 UG_CHG_R 2 1 UG_CHG

2
1U_0603_25V6K G2 G1
1 2
4.12K_0603_1%

4.12K_0603_1%

9
REGN_CHG
1

2
PQB5 +12.6V_BATT 2

VCC_CHG
PRB8

PRB9

BST_CHG
UG_CHG
PCB12 AON7934_DFN3X3A8-10

LX_CHG
1U_0603_25V6K PLB2 PRB10
1 2 4.7UH_5.5A_20%_7X7X3_M 0.01_1206_1%
LX_CHG 1 2 CHG 1 4
2

@EMI@ PRB11
2 3

4.7_1206_5%

RB551V-30_SOD323-2
20

19

18

17

16

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K

10U_0805_25V6K
CSON1
CSOP1

1
BTST
PHASE

HIDRV
VCC

REGN

PCB13

PCB14

@ PCB23

@ PCB24
1

1
PDB3
21
PAD

0.1U_0402_25V6

0.1U_0402_25V6
1 SNB_CHG 2
ACN_CHG 1 15 LG_CHG

2
ACN LODRV

PCB15

PCB16

2
1

1
ACP_CHG 2 14

680P_0603_50V8J
PRB12
ACP GND

@EMI@ PCB17
PUB01 0_0603_1%

2
BQ24735RGRR_QFN20_3P5X3P5 1 2 CSOP1
CMSRC_CHG 3 13 SRP_CHG
CMSRC SRP

2
PRB13 PCB18 PCB23 , PCB24
ACDRV_CHG 4 12 SRN_CHG 0_0603_5% 0.1U_0603_16V7K Place at battery

2
PRB14 ACDRV SRN 1 2 CSON1 connector
10K_0402_1%
1 2 5 11 BATDRV_CHG
+3VL ACOK BATDRV

ACDET

IOUT

SDA

SCL

ILIM
[26,37] ACIN
6

10
ACDET_CHG

ILIM_CHG
+19VB
IOUT_CHG

3 3

PRB15
357K_0402_1% +3VL
+19V_VIN 1 2

68P_0402_50V8J

68P_0402_50V8J

68P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J

82P_0402_50V8J
0.01U_0402_25V7K

1
100K_0402_1%

@RF@ PCB25

@RF@ PCB26

@RF@ PCB27

@RF@ PCB28

@RF@ PCB29

@RF@ PCB30
1
422K_0402_1%

PRB17

PCB19
1

1
PRB16

2
2
2
2

Vin Dectector
EC_SMB_CK1 [26,33,38]
Min. Typ Max.
0.1U_0402_25V6

66.5K_0402_1%

H-->L 17.23V
1
PCB20

PRB18
1

L-->H 17.63V EC_SMB_DA1 [26,33,38]

@ PRB19
2

0_0402_5%
2

1 2
ILIM and external DPM ADP_I [26,37]
1

3.61A PCB21 @ PCB22

100P_0402_50V8J 0.1U_0402_10V7K
2

4
Please locate the RC 4

Near EC chip
2011-02-22

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
CHARGER
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Sheet 52 of 61
A C D
 A B C D

PR302
90.9K_0402_1%
1 2

PR303
56K_0402_1%
1
1 2 1

PR304
@ PC302 97.6K_0402_1%
100P_0402_50V8J 1 2
1 2
PR305
30K_0402_1%
+19VB +19VB_3/5V
EMI@ PL301 PR301 1 2
5A_Z120_25M_0805_2P 14K_0402_1%
1 2 1 2 +19VB_3/5V

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
PR307

@EMI@ PC318
PR306 19.1K_0402_1%

1
PC303

PC304
1 2

10U_0805_25V6K

10U_0805_25V6K
20K_0402_1%
+3VALW 1 2

1
PC307

PC308
2

ENTRIP_3V

ENTRIP_5V
1

TON_35V

2
FB_3V

FB_5V
PR318
10K_0402_1%

PQ301

2
AON7934_DFN3X3A8-10 PQ302

10

1
AON7934_DFN3X3A8-10

10
4 5

D1

FB2

ENTRIP2

ENTRIP1

FB1
TON
D1 S2 <8,27> SPOK
21 5 4

D1
3 6 6 PAD S2 D1
D1 S2 PC305 PR309 PGOOD 20 6 3
2 7 0.1U_0402_10V7K 2.2_0402_1% BYP1 PR310 PC306 S2 D1
D1 S2 2 BST_3V_R 1 2 BST_3V

D2/S1
1 7 2.2_0402_1% 0.1U_0402_10V7K 7 2
UG_3V 1 LG_3V BOOT2 BST_5V 1 2 BST_5V_R 1 S2 D1

D2/S1
8 19 2
2 G1 G2 BOOT1 LG_5V 8 1 UG_5V 2

9 UG_3V 8 G2 G1
PL303 UGATE2 18 UG_5V

9
3.3UH_6.3A_20%_7X7X3_M UGATE1 PL302
1 2 LX_3V 9 2.2UH_7.8A_20%_7X7X3_M
+3VALWP PHASE2 17 LX_5V 1 2
PHASE1 +5VALWP
1

@EMI@ PR311
4.7_1206_5%

1
LG_3V

@EMI@ PR312
10

4.7_1206_5%
LGATE2 16 LG_5V

ENLDO
LGATE1

LDO5

LDO3
ENM
VIN
1
SNUB_3V 2

SNUB_5V 2
+ PC316 PU301

11

12

13

14

15
RT8243AZQW_WQFN20_3X3 + PC317
150U_D2_6.3VM_R17M
150U_D2_6.3VM_R17M
2

+5VLP

+3VLP
680P_0603_50V8J

2
@EMI@ PC311

680P_0603_50V8J
PR313
1

+3VLP

@EMI@ PC312
330K_0402_1%

1
1 2 @ PJ301
+19VB_3/5V JUMP_43X39
2

100K_0402_1%
1 2

1U_0603_10V6K
0.1U_0603_25V7K
+3VL

2
1 2

1
1

1
PC313

PR314

@ PC314
(100mA,40mils ,Via NO.= 2)
+3VALWP +5VALWP

1
+3VL PC310

2
4.7U_0603_10V6K

2
82P_0402_50V8J

82P_0402_50V8J

68P_0402_50V8J

82P_0402_50V8J

PR315
0.1U_0402_25V6

0.1U_0402_25V6
1

1
@RF@ PC320

ESD@ PC321

@RF@ PC322

@RF@ PC323

@RF@ PC324

ESD@ PC325

2.2K_0402_1%
3
1 2 3

<33> EC_ON +5VLP

2

@ PR316 @ PJ304
0_0402_5% JUMP_43X39
1 2 1 2
1 2 +5VL
<33> MAINPWON

4.7U_0603_6.3V6K

402K_0402_1%
(100mA,40mils ,Via NO.= 2)

1
1

1
PC315

PR317
PC309
4.7U_0603_10V6K
2

2
3VALWP 2
Fsw : 455kHz
ITDC : 5.6A
Ipeak : 7A
Iocp: 8.4A @ PJ302
1 2
OVP : 113%~120% +3VALWP 1 2 +3VALW
JUMP_43X118

5VALWP @ PJ303
1 2
Fsw : 390kHz +5VALWP 1 2 +5VALW
ITDC : 6.4A JUMP_43X118
Ipeak : 8A
Iocp: 9.6A
4 OVP : 113%~120% 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
3VALW/5VALW
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Sheet 53 of 61
A C D
 5 4 3 2 1

Pin19 need pull separate from +1.35VP.

EMI@ PLM1
+19VB 5A_Z120_25M_0805_2P
If you have +1.35V and +0.675V sequence question, 0.675Volt +/- 5%
1 2 +19VB_DDR you can change from +1.35VP to +1.35VS. TDC 0.7A

2200P_0402_50V7K

10U_0805_25V6K

10U_0805_25V6K
Peak Current 1A

0.1U_0402_25V6
D D

1
@EMI@ PCM1

EMI@ PCM2

PCM3

PCM4
2

2
PQM1 N16P@ PQM2
AON7934_DFN3X3A8-10 AON7934_DFN3X3A8-10

10

10
PCM7 PRM1
4 5 4 5 0.1U_0603_25V7K 2.2_0603_5%

D1

D1
D1 S2 D1 S2 1 2 BST_DDR_R 1 2 BST_DDR
3
D1 S2
6 3
D1 S2
6 +1.35VP
2 7 2 7
D1 S2 D1 S2 UG_DDR +0.675VSP

D2/S1

D2/S1
UG_DDR1 8 LG_DDR UG_DDR1 8 LG_DDR
G1 G2 G1 G2
LX_DDR

10U_0603_6.3V6M

10U_0603_6.3V6M
9

1
PCM5

PCM6
PLM2

16

17

18

19

20
1UH_11A_20%_7X7X3_M

2
1 2

VLDOIN
PHASE

UGATE

BOOT

VTT
+1.35VP PAD
21

1
LG_DDR 15 1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
@EMI@ PRM3 N16P@ PRM2 LGATE VTTGND
1

1
PCM9

PCM10

PCM11

PCM12

PCM13

PCM14
4.7_1206_5% 6.2K_0402_1%
14 2

2
1SNB_DDR
UMA@ PRM2 PGND VTTSNS
2

C N16S@ PRM2 7.15K_0402_1% C

7.15K_0402_1% 1 2 CS_DDR 13 PUM01 3
PCM8 CS RT8207PGQW _W QFN20_3X3 GND
1U_0402_10V6K
@EMI@ PCM17 1 2 VDDP_DDR 12 4 VTTREF_DDR
680P_0402_50V7K PRM4 VDDP VTTREF

2
5.1_0603_5%
1 2 VDD_DDR 11 5
+5VALW VDD VDDQ +1.35VP

1
PGOOD
PCM15
+5VALW

TON
1
0.033U_0402_16V7K

FB
S5

S3

2
PCM16 1 2
1U_0402_10V6K

10

6
@ PJM1 +1.35V_VDDQ PRM5
+1.35VP 1 2 +1.35V_VDDQ 5.1_0603_5%
1 2

EN_DDR

EN_0.675VSP
TON_DDR
JUMP_43X118 PRM6
@ PJM2 8.06K_0402_1%
1
1 2
2 PRM7 FB_DDR 1 2 +1.35VP
470K_0402_1%
82P_0402_50V8J

68P_0402_50V8J
1

1 +19VB_DDR 1 2
@RF@ PCM20

@RF@ PCM21

JUMP_43X118

1
@ PJM3 @ PRM9
2

1 2 0_0402_5% PRM8
+0.675VSP 1 2 +0.6V_0.675VS 1 2 10K_0402_1%
<36,39> SYSON
JUMP_43X39

2
1
@ PCM18
0.1U_0402_10V7K
B B

2
Switching Frequency:540kHz
@ PRM10
Ipeak(UMA) : 6.5A 0_0402_5%
Iocp(UMA) : 8A 1 2
Ipeak(VGA) : 11A <36,39,44> SUSP#
Iocp(VGA) : 13A

1
OVP : 113%~120% @ PCM19
VFB=0.75V, Vout=1.3545V 0.1U_0402_10V7K

2
MOSFET: 3x3 DFN
H/S Rds(on): 12.4mohm(Typ), 15.8mohm(Max)
Idsm: 13A@Ta=25C, 7.8A@Ta=70C Mode Level +0.675VSP VTTREF_1.35V
S5 L off off
L/S Rds(on): 9.4mohm(Typ), 11.6mohm(Max) S3 L off on
Idsm: 15A@Ta=25C, 9A@Ta=70C S0 H on on
A
Choke: 7x7x3 Note: S3 - sleep ; S5 - power off A

Rdc=6.7mohm(Typ), 7.4mohm(Max)

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/12/31 Title
2014/10/09 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.35V/0.675VS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 54 of 61
5 4 3 2 1
 5 4 3 2 1

D @EMI@ PRH11 @EMI@ PCH16 D

4.7_0603_5% 680P_0402_50V7K
1 2SNB_1.05V1 2
PUH1
SY8003ADFC_DFN8_2X2
+1.05VSP +1.05VS
@ PJH2 4 5 PLH2 @ PJH1
JUMP_43X79 PGND NC 1UH_2.8A_30%_4X4X2_F JUMP_43X79
1 2 +3VB_1.05V 3 6 LX_1.05V 1 2 1 2
+3VALW 1 2 IN LX 1 2

22U_0603_6.3V6M
EN_1.05V
+3VS 1 2 2 7

22P_0402_50V8J
PG EN

1
10K_0402_5%

PCH14

PCH15
15K_0402_1%

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
PRH13 FB_1.05V 1 8

PCH17

PRH10

PCH18
FB SGND 9

2
PGND
1.05V_VS_PG_PWR
2

2
2
2014-10-03:
Remove"+" for the signal name from
"+1.05V_VS_PG_PWR" to "1.05V_VS_PG_PWR"

20K_0402_1%
PRH8
PRH12
0_0402_5%
1 2
<33,37,54,58> SUSP#

2
3A continuous
3.5A current limit

1
PRH9 @ PCH19
C 1M_0402_5% 0.1U_0402_16V7K C

2
2
B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title
1.05V
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C501P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, April 22, 2015 Sheet 55 of 61
5 4 3 2 1
 5 4 3 2 1

Module model information:

ISL95813_V1A for IC module H-side MOS: MDV1525URH L-side MOS: MDU1511RH Choke: 0.15UH (Size:7*7*3)
ISL95813_V1B for SW module Rds(on): Rds(on): Rdc=0.66mohm +-7%
<10.1mohm@Vgs=10V <2.4mohm@Vgs=10V Heat Rating Current=36A
<14.0mohm@Vgs=4.5V <3.3mohm@Vgs=4.5V
Id :24A@Vgs=10V Id :100A@Vgs=10V
ITDC=10A
ICCMAX=32A
OCP=38A
D Fsw=700kHz D
Follow intel guideline

+1.05VS_VCCST PRZ1
130_0402_1%
1 2

PCZ1 PRZ2
1U_0402_6.3V6K 54.9_0402_1%
1 2 1 2
EMI@ PLZ01
+19VB_CPU 5A_Z120_25M_0805_2P +19VB
1 2

Note: <11> VR_SVID_DAT @EMI@ PLZ3

VR_SVID_ALRT# 5A_Z120_25M_0805_2P
+19VB_CPU 1 2
Pull high on HW side

33U_D2_25VM_R60M

33U_25V_NC_6.3X4.5

33U_25V_NC_6.3X4.5
<11> VR_SVID_ALRT#

2200P_0402_50V7K
2.2U_0402_25V6M
1 1 1

10U_0805_25V6K

10U_0805_25V6K

68P_0402_50V8J

0.1U_0402_25V6
1

1
+ + +

@RF@ PCZ23

@RF@ PCZ24

@ PCZ81

@ PCZ22
PCZ2

PCZ3

@EMI@ PCZ4

EMI@ PCZ5

PCZ6
<11> VR_SVID_CLK Note:
PRZ3 PRZ3=90.9K
90.9K_0402_1%
=>ICCMAX=33A

VR_SVID_ALRT#

2
1 2 2 2 2

VR_SVID_DAT
Fsw=700kHz

VR_SVID_CLK

PRGM1_CPU
<11> VR12.5_VR_ON
ECO mode

5
@ PRZ22 PRZ4

MDV1525URH_PDFN33-8-5
+1.05VS_VCCST 1.5K_0402_1% 1.5K_0402_1%
1 2 1 2
PRZ5
0_0603_5%

21

20

19

18

17
<11> VGATE PUZ1 1 2 4
C C

PQZ1
SCLK

SDA
PAD

ALERT#

PRGM1
PCZ7 VR12.5_VR_ON 1 16 LG_CPU

3
2
1
1000P_0402_50V7K VR_ON LGATE PLZ2
1 2 0.15UH_29A_+-20%_7X7X4_M
2 15 LX_CPU 1 4
PRZ6 PGOOD PHASE +VCC_CORE

4.7_1206_5%
2 3

@EMI@ PRZ8
110K_0402_1%

1
1 2 IMON_CPU 3 14 UG_CPU
Note: IMON UGATE

5
VR_HOT# Pull high on HW side PRZ7 PCZ8
ISL95813HRZ-T_QFN20_3X4 2.2_0603_5% 0.22U_0603_16V7K

PK632BA_PDFN8-5
VR_HOT# 4 13 BST_CPU
1 2BST_CPU_R1 2
<33> VR_HOT# VR_HOT# BOOT
PHZ1

2
47P_0402_50V8J

PQZ3
470K_0402_5%_B25/50 4700K PRZ10
NTC_CPU

680P_0603_50V8J
1 2 1 2 5 12 4
NTC VCC +5VS
1
PCZ9

@EMI@ PCZ10
1
3.83K_0402_1%
PRZ11 COMP_CPU 6 11 PRGM2_CPU
2

COMP PRGM2

1
27.4K_0402_1% ISUMN

ISUMP

3
2
1

2
1 2 PCZ11
RTN

124K_0402_1%
0.1U_0402_25V6
FB

2
1
PRZ12
Over temperature protection:
7

10
6800P_0402_25V7K 3.16K_0402_1%

ISUMN_CPU_R
ISUMP_CPU_R
OTP Setting: 100C active
Pin5 (NTC) voltage <0.88V, Protect change to AON6794
1
PRZ13

(SB000017Q00)

2
Pin5 (NTC) voltage >0.92v, recovery FB_CPU
33P_0402_50V8J

ISUMN_CPU

ISUMP_CPU

Note:
PRZ12=124K
1

PCZ12

=>Slew rate=53mV/us
10_0402_1%
2K_0402_1%

Vboot = 1.7V
2

PRZ15

PRZ9
2

@ PRZ14

3.65K_0603_1%
1

1.27K_0402_1%

1 2
PCZ13

4.99M_0402_1%

B @ B
1
PRZ16
2

1
@ PRZ17
390P_0402_50V7K

RC Match PRZ18
1
330P_0402_50V7K

4.32K_0402_1%
2
1

1
PCZ14

1
PRZ19
2

2
@ PCZ15

Droop PCZ16 PCZ17 11K_0402_1%

2

@ 0.01U_0402_25V7K 0.1U_0402_16V4Z
2

1
2
OCP Setting PHZ2
10K_0402_5%_B25/50 4250K
<11> VCCSENSE
PRZ20

2
@ PCZ18 280_0402_1%
330P_0402_50V7K 1 2
0.082U_0402_16V7K

1 2
@ PCZ19
1

@ PCZ21 @ PRZ21
PCZ20 4700P_0402_25V7K 1.5K_0402_1%
2

0.01U_0402_50V7K 1 2 1 2
1 2

<13> VSSSENSE

A A
Local sense put on HW site

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
VCC_CORE
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P for CN30
Date: Wednesday, April 22, 2015 Sheet 56 of 61
5 4 3 2 1
 5 4 3 2 1

D D

+VCC_CORE
BDW-U 15W

220U_D2 SX_2VY_R9M
1
+
220uF X 1

PCZ42
22uF X7
2 2.2uF X1
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

2.2U_0402_10V6M
2

2
PCZ69

PCZ68

PCZ67

PCZ66

PCZ64

PCZ62

PCZ61

PCZ70
1

1
C C
22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M

22U_0603_6.3V6M
2

2
PCZ57

PCZ56

@ PCZ60

@ PCZ59

@ PCZ58
1

@ @

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PROCESSOR DECOUPLING
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501Pfor CN30
Date: Sheet 57 of 61
5 4 3 2 1
 A B C D

PC1509 @EMI@ PR1508 @EMI@ PC1507

22U_0603_6.3V6M 4.7_0603_5% 680P_0402_50V7K
1 2 SNB_1.5V 1 2
1 2

PU1501
1 @ PJ1501 SY8032ABC_SOT23-6 PL1502 1

JUMP_43X79 1UH_2.8A_30%_4X4X2_F
+3VALW 1 2 +3VB_1.5V 4 3 LX_1.5V 1 2
1 2 IN LX +1.5VSP
5 2

30.1K_0402_1%

68P_0402_50V8J
PG GND

22U_0603_6.3V6M

22U_0603_6.3V6M
1

1
6 1

PR1510

PC1511

PC1512

PC1508
@ PR1511 FB EN
0_0402_5%

2
1 2 +1.5VSP_ON
<33,37,54,55> SUSP#

2
FB_1.5V

0.1U_0402_16V7K
1

1M_0402_1%

1
@ PR1509

@ PC1510

1
20K_0402_1%
PR1507
2
2
@ PJ1502

2
JUMP_43X79
1 2
+1.5VSP 1 2 +1.5VS

continuous 2.5A

2 2

3 3

4 4

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title
1.5VS
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS LA-C501P 0.1
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: W ednesday, April 22, 2015 Sheet 58 of 61
A B C D
 5 4 3 2 1

H-side MOS: AON6992 L-side MOS: AOS6992 Choke: 0.22UH (Size:7*7*3)

Rds(on): Rds(on): Rdc=0.98mohm +-5%
4.3mohm@Vgs=10V 2mohm@Vgs=10V Heat Rating Current=28A
5.2mohm@Vgs=4.5V 2.2mohm@Vgs=4.5V
Id :32A@Tc=100C Id :66A@Tc=100C

D D

@VGA@ PRV1 +19VB

1K_0402_5%
1 2 +3VGS_AON EMIVGA@ PLV1
+19VB_VGA 5A_Z120_25M_0805_2P
VGA@ PRV2 1 2
0_0402_5%
1 2 NVVDD_PWM_VID <39> EMIVGA@ PLV4
5A_Z120_25M_0805_2P
VGA@ PRV26 1 2

1
10K_0402_5%

2200P_0402_50V7K

33U_D2_25VM_R60M

33U_D2_25VM_R60M
1
VGA@ PCV1 Rref1 1 2

10U_0805_25V6K

10U_0805_25V6K
+3VGS_AON 1 1

EMIVGA@ PCV3

VGA@ PCV4

VGA@ PCV6
1U_0402_6.3V6K

1
+ +

VGA@ PCV2
VGA@ PRV3 VGA@ PRV6

N16P@ PCV11
20K +-1% 0402 0_0402_5% VGA@ PRV10
1 2 NVVDD_PSI <39> 0_0603_5%

2
UG1_VGA 1 2 UG1_VGA_R 2 2
VGA@ PRV4 VGA@ PRV5 @VGA@ PRV28
2K +-1% 0402 20K +-1% 0402 10K_0402_5%
1 2 1 2 1 2
Rboot Rrefadj @VGA@ PRV27 VGA@ PRV7 VGA@ PCV5
1K_0402_5% 2.2_0603_5% 0.22U_0603_25V7K

1
1 2 BST1_VGA 1 2 BST1_VGA_R 1 2
+3VGS_AON
VGA@ PCV8

2
@VGA@ PCV7 2700P 50V K X7R 0402 VGA@ PRV9

2
0.01U_0402_16V7K C 0_0402_5%

G1

D1

G1

D1
AON6992 2N DFN5X6D

AON6992 2N DFN5X6D
1 2 1 2 +3VGS_MAIN VGA@ PLV2 +VGA_CORE
0.22UH_24A_+-20%_7X7X4_M

GPU_FBRTN
LX1_VGA LX1_VGA 7 LX1_VGA

GPU_VID
Rref2 7 1 2
D2/S1 D2/S1

VGA@ PQV1

N16P@ PQV2
@VGA@

1
VGA@ PRV8 VGA@ PRV11 PCV9 @EMIVGA@
18K +-1% 0402 0_0402_5% 0.1U_0402_25V6 PRV14

G2

G2
S2

S2

S2

S2

S2

S2
1 1

330U_D1_2VY_R9M

330U_D1_2VY_R9M
2
1 2 1 2

GPU_REFADJ
Reserve Location 4.7_1206_5%

BST1_VGA
+ +

VGA@ PCV12

VGA@ PCV10
6

3
UG1_VGA
GPU_PSI

GPU_EN

1SNB1_VGA 2
LG1_VGA
2014-09-24: Change VGA_Core Enable Net Name
2 2
2014-10-01:Change VGA_Croe Enable pin from

1
C DGPU_MAIN_EN to +3VGS_MAIN Power Rail C
N16S@ PRV15
9.76K_0402_1%
N16P@ PRV15 @EMIVGA@

1
8.2K_0402_1% Rocset PCV15

2
VGA@ PRV13 680P_0603_50V7K

UGATE1

BOOT1
VID

PSI

EN
REFADJ

2
432K_0402_1%
VGA@ PRV12 +19VB_VGA 1 2 Check OCP
100_0402_1% Rton GPU_REFIN 7 24 LX1_VGA
1 REFIN PHASE1
1 2
@VGA@ PCV14 GPU_VREF 8 23 LG1_VGA
0.01UF_0402_25V7K VREF LGATE1
VGA@ PRV16 2 GPU_TON 9 22
0_0402_5% TON GND/PWM3 +19VB_VGA
<40> VSSSENSE_VGA 1 2 GPU_FBRTN 10 VGA@ PUV1 21
RGND RT8813AGQW_WQFN24_4X4 PVCC
GPU_FB LG2_VGA

TALERT/ISEN2
11 20

2200P_0402_50V7K
VSNS LAGTE2
1

TSNS/ISEN3

10U_0805_25V6K

10U_0805_25V6K
VCC/ISNE1
VGA@ PCV16 GPU_COMP 12 19 LX2_VGA

EMIVGA@ PCV20

VGA@ PCV21

VGA@ PCV22
SS PHASE2

UGATE2

1
PGOOD
VGA@ PRV17 0.1U_0402_25V6 VGA@ PRV20

BOOT2
1
2

0_0402_5% 0_0603_5%
GND

1 2 @VGA@ PCV17 UG2_VGA 1 2 UG2_VGA_R

2
<40> VCCSENSE_VGA 0.01U_0402_16V7K
VGA@ Css 2
25

13

14

15

16

17

18
PRV18
100_0402_1% VGA@ PRV19 VGA@ PCV18
+VGA_CORE
1 2 2.2_0603_5% 0.22U_0603_25V7K
GPU_TSNS/ISEN3

GPU_DSBL/ISEN1

BST2_VGA 1 2 BST2_VGA_R 1 2
GPU_HOT#

2
GPU_VREF
BST2_VGA
UG2_VGA

G1

D1

G1

D1
AON6992 2N DFN5X6D

AON6992 2N DFN5X6D
VGA@ PLV3 +VGA_CORE
1

0.22UH_24A_+-20%_7X7X4_M
LX2_VGA 7 LX2_VGA 7 LX2_VGA 1 2
D2/S1 D2/S1

VGA@ PQV3

N16P@ PQV4
VGA@ PRV21

1
8.2K_0402_1%
@EMIVGA@

G2

G2
S2

S2

S2

S2

S2

S2
1 1

330U_D1_2VY_R9M

330U_D1_2VY_R9M
2

VGA@ PRV22 +3VGS_AON PRV23

B + + B
10K_0402_1% 4.7_1206_5%

VGA@ PCV25

N16P@ PCV13
6

3
1

1 2

2
1

LG2_VGA
VGA@ PHV1 VGA@ PCV23 DGPU_PWROK <39> 2 2

1SNB2_VGA
470K_0402_5%_TSM0B474J4702RE 1U_0402_6.3V6K
2
2

@EMIVGA@
VGA@ PRV25 VGA@ PRV24 +5VS PCV26
Operation phase PSI Voltage
Number setting 100K_0402_1% 2.2_0603_5% 680P_0603_50V7K

2
+3VS
1 2 1 2
1 phase with 0V to
1

DE M 0.8V VGA@
PCV27
1 phase with 1.2V to <33> GPU_HOT# 1U_0402_6.3V6K
2

CCM 1.8V
Active phase with 2.4V to
CCM 5.5V

1. VSNS Soft-Start time (Internal) is 0.7ms (PCV17 un-pop)

Tss=(Css*Vrefin)/Iss+2.3ms
=0.01U*0.9V/5uA+2.3ms=4.1ms (PCV17 pop) Switching Frequency : 353kHz
Ipeak(N16P-GT) : 70A
2. Switching frequency setting: Iocp(N16P-GT) : 83A
Fsw=(Vin-0.5)/(2*Vin*Rton*3.2p)=353Khz Ipeak(N16-S-GT) : 50A
Iocp(N16S-GT): 61A
3. Thermal monitoring:
(VGPU_VREF-VTSNS)/PRV21=VTSNS/Rth
A A

T_min T_typical T_max

PRV21=18.7K 99.16C 101.57C 103.94C

PRV21=13K 110.19C 112.75C 115.26C

Security Classification Compal Secret Data Compal Electronics, Inc.
Issued Date 2014/10/09 Deciphered Date 2015/12/31 Title
PRV21=8.2K 125.15C 127.91C 130.62C VGA_CORE
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 59 of 61
5 4 3 2 1
 4
3
2
1

A
A

2 1 2 1 2 1 2 1 2 1

N16P@ PCV67 VGA@ PCV51 VGA@ PCV82 VGA@ PCV72 VGA@ PCV59
4.7U_0603_6.3V6K 22U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 1U_0402_6.3V6K

2 1 2 1 2 1 2 1 2 1
+VGA_CORE

N16P@ PCV68 N16P@ PCV52 VGA@ PCV83 VGA@ PCV73 VGA@ PCV60
4.7U_0603_6.3V6K 22U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 1U_0402_6.3V6K

2 1 2 1 2 1 2 1 2 1

N16P@ PCV69 N16P@ PCV53 VGA@ PCV84 VGA@ PCV74 VGA@ PCV61
4.7U_0603_6.3V6K 22U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 1U_0402_6.3V6K

2 1 2 1 2 1 2 1 2 1

N16P@ PCV70 N16P@ PCV54 VGA@ PCV85 VGA@ PCV75 VGA@ PCV62
4.7U_0603_6.3V6K 22U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 1U_0402_6.3V6K

2 1 2 1 2 1 2 1 2 1

N16P@ PCV71 N16P@ PCV55 VGA@ PCV86 VGA@ PCV76 N16P@ PCV63

B
B

4.7U_0603_6.3V6K 22U_0603_6.3V6M 4.7U_0603_6.3V6M 4.7U_0603_6.3V6M 1U_0402_6.3V6K

2 1 2 1 2 1 2 1

@VGA@ PCV87 N16P@ PCV56 VGA@ PCV77 N16P@ PCV64

47U_0805_6.3V6M 22U_0603_6.3V6M 4.7U_0603_6.3V6M 1U_0402_6.3V6K

2 1 2 1 2 1 2 1

@VGA@ PCV88 N16P@ PCV57 VGA@ PCV78 N16P@ PCV65

47U_0805_6.3V6M 22U_0603_6.3V6M 4.7U_0603_6.3V6M 1U_0402_6.3V6K

2 1 2 1 2 1
2 1
@VGA@ PCV89 VGA@ PCV79 N16P@ PCV66
47U_0805_6.3V6M N16P@ PCV91 4.7U_0603_6.3V6M 1U_0402_6.3V6K
47U_0805_6.3V6M

Issued Date
2 1 2 1

@VGA@ PCV90 VGA@ PCV80

Security Classification
47U_0805_6.3V6M 4.7U_0603_6.3V6M

2 1 2 1

@VGA@ PCV58 VGA@ PCV81

47U_0805_6.3V6M 4.7U_0603_6.3V6M
NEAR GPU
UNDER GPU

C
C

2014/10/09
N16P-GT
N16S-GT

Compal Secret Data

Deciphered Date
1U 6.3V X5R 0402 (SE000000K80) X 8
1U 6.3V X5R 0402 (SE000000K80) X 4

MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
22U 6.3V X5R 0603 (SE00000M000) X 7
22U 6.3V X5R 0603 (SE00000M000) X 1
47U 6.3V X5R 0805 (SE00000PL00) X 1

4.7U 6.3V X5R 0603 (SE107475K80) X 5

2015/12/31
330U 2V LESR6M H1.9 (SGA00001Q80) X 4
330U 2V LESR6M H1.9 (SGA00001Q80) X 3

D
D

DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
4.7U 6.3V X5R 0603 H0.8 (SE107475M80) X 15
4.7U 6.3V X5R 0603 H0.8 (SE107475M80) X 15

B
Size
Title

Date:
Document Number

Wednesday, April 22, 2015

LA-C501P
E
E

Sheet
VGA CHIP DECOUPLING

60
Compal Electronics, Inc.

of
61
Rev
0.1
4
3
2
1
 5 4 3 2 1

D D

For Nvdia N16P-GT

N16P@ PCF05
22U_0603_6.3V6M @EMIN16P@ PRF01 @EMIN16P@ PCF02
1 2 4.7_0603_5% 680P_0402_50V7K
N16P@ PUF01 1 2SNB_1.05VGS 1 2
SY8003ADFC_DFN8_2X2
+1.05VGSP
4 5 N16P@ PLF01
@ PJF01 PGND NC 1UH_2.8A_30%_4X4X2_F
+3VALW 1
1 2
2 +3VB_1.05VGS 3
IN LX
6 LX_1.05VGS 1 2

1
2 7 EN_1.05VGS
JUMP_43X79 PG EN

1
N16P@ PRF03

N16P@ PCF06

N16P@ PCF03

N16P@ PCF04
15K_0402_1%

22P_0402_50V8J

22U_0603_6.3V6M

22U_0603_6.3V6M
1 8
FB SGND 9

2
PGND

2
C FB_1.05VGS C

N16P@ PRF02
20K_0402_1%
N16P@ PRF05
2K_0402_5%

2
+3VGS_MAIN 1 2

+1.05VGSP +1.05VGS

1
1M_0402_5%
N16P@ PCF01

N16P@ PRF04
1U_0402_16V6K
1
@ PJF02
1 2

2
1 2

2
JUMP_43X79

3A continuous
3.5A current limit

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/12/31 Title
2014/10/09 Deciphered Date
THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
1.05VGS
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 0.1
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. LA-C501P
Date: Wednesday, April 22, 2015 Sheet 61 of 61
5 4 3 2 1
 5
Version Change List ( P. I. R. List )
4 3
Page 1 2 1

Request
Item Page# Title Date Owner Issue Description Solution Description Rev.

D
1 D

C C

B B

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
PWR-PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number Rev
Custom 1.0
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC. <Doc>
Date: W ednesday, April 22, 2015 Sheet 62 of 63
5 4 3 2 1
 5 4 3 2 1

Version change list (P.I.R. List) Page 1 of 5 for HW

Item Fixed Issue Reason for change Rev. PG# Modify List Date Phase

1 ME request
0.2 P19 Change eDP Connector(JLCD1) for ME 12/15
D D

2 Screw Hole 0.2 P32 Change H20 from 3.0 mm to 3.3 mm 12/15

3 Sub USB Power Switch 0.2 P26 Change Power Switch US5 circuit 12/15

4 ME Flash Circuit 0.2 P6 Add ME FLASH Circuit 12/15

Audio GND Bridge circuit 0.2 P28 Add two Resistor for HP request 12/15
5

6 12/19
Add JUMP on JUSB1 and JUSB2 Power 0.2 P26 Add JUMP JPV5

7 ESD request 0.2 P34 Change Touch PAD Diode for ESD request 12/19

C 8 ESD request 0.2 P19 Reserve Touch Screen Diode for ESD 12/19 C

9 Change Camera and D-MIC Diode for 12/19

ESD request 0.2 P19 ESD request

10 Audio team Request 0.2 P28 Change JSPK2 Pin define 12/22

11 0.2 P31
Vendor Request P33 Change Subwoofer circuit 12/22

12 0.2 P35
Customer Request P33 Add Shipping Mode Circuit 12/22
P26 Reserve 68P and 82P on +3VALW and
13 RF Request 0.2 P32 +USB_VCC4 12/23

14 ESD request 0.2 P20 Change HDMI EMI Solution 12/23

B B
15 HW Modify 0.2 P48 Change N16X 1.35V and 1.05V solution 12/25

16 HW Modify 0.3 P48 Change N16X 1.35V and 1.05V solution 01/23

17 HW Modify 1.0 P32 Add DH5 for storage Mode 04/02

18 1.0 P31 Change Subwoofer circuit 04/02

Vendor Request
Change 0 ohm to short pad.
19 RC8,RC108,RC119,RC378, 04/13
HW Modify 1.0
RT19,RT37,RA32,RA34,
RA38,RA39,RA50,RA51,
RT17 RT18,RTS4

A A

Security Classification Compal Secret Data Compal Electronics, Inc.

Issued Date 2015/04/13 Deciphered Date 2018/04/13 Title

THIS SHEET OF ENGINEERING DRAWING IS THE PROPRIETARY PROPERTY OF COMPAL ELECTRONICS, INC. AND CONTAINS CONFIDENTIAL
HW PIR
AND TRADE SECRET INFORMATION. THIS SHEET MAY NOT BE TRANSFERED FROM THE CUSTODY OF THE COMPETENT DIVISION OF R&D Size Document Number R ev
DEPARTMENT EXCEPT AS AUTHORIZED BY COMPAL ELECTRONICS, INC. NEITHER THIS SHEET NOR THE INFORMATION IT CONTAINS Custom 1.0
MAY BE USED BY OR DISCLOSED TO ANY THIRD PARTY WITHOUT PRIOR WRITTEN CONSENT OF COMPAL ELECTRONICS, INC.
Date: Wednesday, April 22, 2015 Sheet 63 of 63
5 4 3 2 1