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Layout & Stick Diagrams

This document discusses CMOS VLSI design techniques including layout and stick diagrams. It covers defining transistors and wires using masks, design rules for layout, and estimating circuit area by counting wiring tracks. Standard cell design methodology and examples of basic gates like inverters and NAND gates are presented. Stick diagrams are introduced as a way to quickly plan layouts before detailed design. Estimating area involves multiplying the number of tracks by the track pitch.

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Jamius Siam
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515 views17 pages

Layout & Stick Diagrams

This document discusses CMOS VLSI design techniques including layout and stick diagrams. It covers defining transistors and wires using masks, design rules for layout, and estimating circuit area by counting wiring tracks. Standard cell design methodology and examples of basic gates like inverters and NAND gates are presented. Stick diagrams are introduced as a way to quickly plan layouts before detailed design. Estimating area involves multiplying the number of tracks by the track pitch.

Uploaded by

Jamius Siam
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Lecture 4:

Layout &
Stick
Diagrams
Inverter Top View
❑ Transistors and wires are defined by masks
❑ Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor


substrate tap well tap

0: Introduction CMOS VLSI Design 4th Ed. 2


Inverter Cross-section
❑ Substrate must be tied to GND and n-well to VDD
❑ Metal to lightly-doped semiconductor forms poor
connection called Shottky Diode
❑ Use heavily doped well and substrate contacts / taps
A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap

0: Introduction CMOS VLSI Design 4th Ed. 3


Gate Layout
❑ Layout can be very time consuming
– Design gates to fit together nicely
– Build a library of standard cells
❑ Standard cell design methodology
– VDD and GND should abut (standard height)
– Adjacent gates should satisfy design rules
– nMOS at bottom and pMOS at top
– All gates include well and substrate contacts

1: Circuits & Layout CMOS VLSI Design 4th Ed. 4


Simplified Design Rules
❑ Conservative rules to get you started

0: Introduction CMOS VLSI Design 4th Ed. 5


Example: Inverter

1: Circuits & Layout CMOS VLSI Design 4th Ed. 6


3-input NAND Gate
❑ Y pulls low if ALL inputs are 1
❑ Y pulls high if ANY input is 0

Y
A
B
C

0: Introduction CMOS VLSI Design 4th Ed. 7


Example: NAND3
❑ Horizontal N-diffusion and p-diffusion strips
❑ Vertical polysilicon gates
❑ Metal1 VDD rail at top
❑ Metal1 GND rail at bottom
❑ 32 l by 40 l

1: Circuits & Layout CMOS VLSI Design 4th Ed. 8


Example: NAND3

1: Circuits & Layout CMOS VLSI Design 4th Ed. 9


Stick Diagrams
❑ Stick diagrams help plan layout quickly
– Need not be to scale
– Draw with color pencils or dry-erase markers
VDD VDD
A A B C
metal1
c poly
ndiff
pdiff
Y
Y contact

GND GND
INV NAND3

1: Circuits & Layout CMOS VLSI Design 4th Ed. 10


Wiring Tracks
❑ A wiring track is the space required for a wire
– 4 l width, 4 l spacing from neighbor = 8 l pitch
❑ Transistors also consume one wiring track

1: Circuits & Layout CMOS VLSI Design 4th Ed. 11


Well spacing
❑ Wells must surround transistors by 6 l
– Implies 12 l between opposite transistor flavors
– Leaves room for one wire track

1: Circuits & Layout CMOS VLSI Design 4th Ed. 12


Area Estimation
❑ Estimate area by counting wiring tracks
– Multiply by 8 to express in l

40 l

32 l

1: Circuits & Layout CMOS VLSI Design 4th Ed. 13


Example: O3AI
❑ Y = ( A+ B + C) D

A
B
C D
Y
D
A B C

1: Circuits & Layout CMOS VLSI Design 4th Ed. 14


Example: O3AI
❑ Sketch a stick diagram for O3AI and estimate area
–
Y = ( A+ B + C) D
VDD
A B C D

6 tracks =
48 l
Y

GND
5 tracks =
40 l

1: Circuits & Layout CMOS VLSI Design 4th Ed. 15


Example: NOR4

1: Circuits & Layout CMOS VLSI Design 4th Ed. 16


Example: 4x1 MUX
❑ 4x1 Nonrestoring MUX

1: Circuits & Layout CMOS VLSI Design 4th Ed. 17

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