DIGITAL ELECTRONICS CS IT 205 HEMANT MENARIA 09828404410

DE multiplexer

Demultiplexer is a combinational circuit has single input, ‘n’ selection lines and maximum of 2n outputs.
The input will be connected to one of these outputs based on the values of selection lines.

Since there are ‘n’ selection lines, there will be 2n possible combinations of zeros and ones. So, each
combination can select only one output. De-Multiplexer is also called as De-Mux.

1x4 De-Multiplexer

1x4 De-Multiplexer has one input I, two selection lines, s1 & s0 and four outputs Y3, Y2, Y1 &Y0. The block
diagram of 1x4 De-Multiplexer is shown in the following figure.

The single input ‘I’ will be connected to one of the four outputs, Y3 to Y0 based on the values of selection
lines s1 & s0. The Truth table of 1x4 De-Multiplexer is shown below.

Selection Inputs Outputs

S1 S0 Y3 Y2 Y1 Y0

0 0 0 0 0 I

0 1 0 0 I 0

1 0 0 I 0 0

1 1 I 0 0 0

From the above Truth table, we can directly write the Boolean functions for each output as
DIGITAL ELECTRONICS CS IT 205 HEMANT MENARIA 09828404410
Y3=s0s1I

Y2=s1s0′I

Y1=s1′s0I

Y0=s1′s0′I

We can implement these Boolean functions using Inverters & 3-input AND gates. The circuit diagram of
1x4 De-Multiplexer is shown in the following figure.

We can easily understand the operation of the above circuit. Similarly, you can implement 1x8 De-
Multiplexer and 1x16 De-Multiplexer by following the same procedure.
DIGITAL ELECTRONICS CS IT 205 HEMANT MENARIA 09828404410

1-to-8 Demultiplexer
The below figure shows the block diagram of a 1-to-8 demultiplexer that
consists of single input D, three select inputs S2, S1 and S0 and eight outputs
from Y0 to Y7.

It is also called as 3-to-8 demultiplexer due to three select input lines. It

distributes one input line to one of 8 output lines depending on the
combination of select inputs.

The truth table for this type of demultiplexer is shown below. The input D is
connected with one of the eight outputs from Y0 to Y7 based on the select
lines S2, S1 and S0.

For example, if S2S1S0=000, then the input D is connected to the output Y0

and so on.
DIGITAL ELECTRONICS CS IT 205 HEMANT MENARIA 09828404410

From this truth table, the Boolean expressions for all the outputs can be
written as follows.

From these obtained equations, the logic diagram of this demultiplexer can be
implemented by using eight AND gates and three NOT gates as shown in
below figure. The different combinations of the select lines , select one AND
gate at given time , such that data input will appear at a particular output.
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What is Demultiplexer
Demultiplexer is a combinational circuit that accepts multiplexed data and
distributes over multiple output lines. In other words, the function of
Demultiplexer is the inverse of the multiplexing operation. Similar
to Multiplexer, the output depends on the control input.
The control input or the ‘select’ input decides which output line is connected
to the input. Let us consider 1:4 Demultiplexer as shown in Fig.1 below
where: D is the input, S0 and S1 are the control inputs, I0, I1, I2, I3 are the 4
output lines and the data is transmitted to one of the four outputs.
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Fig. 1 – Schematic Diagram of 1:4 Demux

Possible Outcomes
If S1S0 = 00, then I0 output of Demultiplexer receive the input data.
If S1S0 = 01, then output I1 receives the input data.
If S1S0 = 10, then input data is distributed to I2.
If S1S0 = 11, then output I3 receives the input data.
Hence, the logic equations for the outputs are:
 I0 = S’1 S’0 D
 I1 = S’1 S0 D
 I2 = S1 S’0 D
 I 3 = S1 S 0 D
Types of Demultiplexer
There are several types of Demultiplexers and few basic ones are listed as
follows:

 1:2 Demultiplexer
 1:4 Demultiplexer
 1:8 Demultiplexer
 1:16 Demultiplexer

1:2 Demultiplexer
The 1:2 Demux consists of 1 data input, 1 control bit and 2 output bits.
I0 and I1 are the two output bits, S is the control bit or the select bit and D is
the input bit.
Fig (2) illustrates the block diagram and circuit diagram of 1:2 Demux.
DIGITAL ELECTRONICS CS IT 205 HEMANT MENARIA 09828404410

Fig. 2 – (a) Block Diagram of 1:2 Demux (b) Circuit Diagram of 1:2 Demux using Logic
Gates
1:4 Demultiplexer
The 1:4 Demux consists of 1 data input bit, 2 control bits and 4 output bits.
D is the input bit, I0, I1, I2, I3 are the four output bits and S0 and S1 are the
control bits.
Fig (3) illustrates the block diagram and circuit diagram of 1:4 Demux.
DIGITAL ELECTRONICS CS IT 205 HEMANT MENARIA 09828404410
Fig. 3 – (a) Block Diagram of 1:4 Demux (b) Circuit Diagram of 1:4 Demux using Logic
Gates
1:8 Demultiplexer
The 1:8 Demux consists of 1 data input bit, 3 control bits and 8 output bits.
I0, I1, I2, I3, I4, I5, I6, I7 are the eight output bits, S0, S1 and S2 are the control
bits and input D.
Fig (4) illustrates the block diagram and circuit diagram of 1:8 Demux.

Fig. 4 – (a) Block Diagram of 1:8 Demux (b) Circuit Diagram of 1:8 Demux using Logic
Gates
1:16 Demultiplexer
The 1:16 Demux consists of 1 data input bit, 4 control bits and 16 output
bits. I0, I1, I2, I3, I4, I5, I6, I7, I8, I9, I10, I11, I12, I13, I14, I15 are the sixteen output bits,
S0, S1, S2 and S3 are the control bits and D is the input bit.
Fig (5) illustrates the block diagram and circuit diagram of 1:16 Demux.
DIGITAL ELECTRONICS CS IT 205 HEMANT MENARIA 09828404410

Fig. 5 – (a) Block Diagram of 1:16 Demux (b) Circuit Diagram of 1:16 Demux using Logic
Gates
Cascading of Demultiplexers
Cascading refers to a process where large Demuxes can be designed and
implemented using smaller Demuxes.

Example: 1:8 Demux can be designed using two 1:4 Demuxes and similarly
1:16 Demuxes can be designed using one 1:2 Demux and two 1:8
Demultiplexers as shown in the figure.
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TRUTH TABLE 1 TO 16 DEMUX

D s0 s1 s2 s3 I0 I1 I2 I3 I4 I5 I6 I7 I8 I9 I10 I11 I12 I13 I14 I15

D 0 0 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D 0 0 0 1 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0 0
D 0 0 1 0 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0 0
D 0 0 1 1 0 0 D 0 0 0 0 0 0 0 0 0 0 0 0
D 0 1 0 0 0 0 0 0 D 0 0 0 0 0 0 0 0 0 0 0
D 0 1 0 1 0 0 0 0 0 D 0 0 0 0 0 0 0 0 0 0
D 0 1 1 0 0 0 0 0 0 0 D 0 0 0 0 0 0 0 0 0
D 0 1 1 1 0 0 0 0 0 0 0 D 0 0 0 0 0 0 0 0
D 1 0 0 0 0 0 0 0 0 0 0 0 D 0 0 0 0 0 0 0
D 1 0 0 1 0 0 0 0 0 0 0 0 0 D 0 0 0 0 0 0
D 1 0 1 0 0 0 0 0 0 0 0 0 0 0 D 0 0 0 0 0
D 1 0 1 1 0 0 0 0 0 0 0 0 0 0 0 D 0 0 0 0
D 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D 0 0 0
D 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 D 0 0
D 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D 0
D 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D