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Unit 1

VHDL is a hardware description language used to model digital systems. It can be used to synthesize, simulate, validate and test digital circuits. There are three main modeling styles in VHDL - dataflow, behavioral, and structural. Dataflow models use concurrent signal assignments, behavioral models use sequential statements, and structural models describe a design as interconnected components. An entity declares inputs, outputs, and ports. Architecture defines the design. There are standard data types like integers, logic vectors and operators for modeling digital logic.

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59 views

Unit 1

VHDL is a hardware description language used to model digital systems. It can be used to synthesize, simulate, validate and test digital circuits. There are three main modeling styles in VHDL - dataflow, behavioral, and structural. Dataflow models use concurrent signal assignments, behavioral models use sequential statements, and structural models describe a design as interconnected components. An entity declares inputs, outputs, and ports. Architecture defines the design. There are standard data types like integers, logic vectors and operators for modeling digital logic.

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Tarun Singhal
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Various Uses Of Vhdl

The VHDL language can be used for several goals like -


 To synthesize digital circuits.
 To verify and validate digital designs.
 To generate test vectors to test circuits.
 To simulate circuits.
IEEE Standard Libraries Available In Vhdl
 std_logic_1164.
 numeric_std.
 numeric_bit.
 std_logic_arith.
 std_logic_unsigned.
VHDL stands for very high-speed integrated circuit hardware description language. It is a
programming language used to model a digital system by dataflow, behavioral and structural
style of modeling. This language was first introduced in 1981 for the department of Defense
(DoD) under the VHSIC program.
Describing a Design
In VHDL an entity is used to describe a hardware module. An entity can be described using,
 Entity declaration
 Architecture
 Configuration
 Package declaration
 Package body

Entity Declaration

It defines the names, input output signals and modes of a hardware module.
Syntax –
entity entity_name is
Port declaration;
end entity_name;
An entity declaration should start with ‘entity’ and end with ‘end’ keywords. The direction
will be input, output or inout.
In Port can be read

Out Port can be written

Inout Port can be read and written

Buffer Port can be read and written, it can have only one source.

Architecture −

Architecture can be described using structural, dataflow, behavioral or mixed style.

Syntax –
architecture architecture_name of entity_name
architecture_declarative_part;

begin
Statements;
Data Types And Operators In Vhdl
VHDL Data Types
VHDL has a set of standard data types (predefined / built-in). It is also possible to
have user defined data types and subtypes.
Some of the predefined data types in VHDL are: BIT, BOOLEAN and INTEGER.
The STD_LOGIC and STD_LOGIC_VECTOR data types are not built-in VHDL data
types, but are defined in the standard logic 1164 package of the IEEE library therefore
need to include this library in VHDL code.
The BIT data type can only have the value 0 or 1. When assigning a value of 0 or 1 to
a BIT in VHDL code, the 0 or 1 must be enclosed in single quotes: '0' or '1'.
BIT_VECTOR
The BIT_VECTOR data type is the vector version of the BIT type consisting of two
or more bits. Each bit in a BIT_VECTOR can only have the value 0 or 1.
When assigning a value to a BIT_VECTOR, the value must be enclosed in double
quotes, e.g. "1011" and the number of bits in the value must match the size of the
BIT_VECTOR.
STD_LOGIC
The STD_LOGIC data type can have the value X, 0, 1 or Z. There are other values
that this data type can have, but the other values are not synthesizable – i.e. they
cannot be used in VHDL code that will be implemented on a CPLD or FPGA.
These values have the following meanings:
 X – unknown
 0 – logic 0
 1 – logic 1
 Z – high impedance (open circuit) / tristate buffer
When assigning a value to a STD_LOGIC data type, the value must be enclosed in
single quotes: 'X', '0', '1' or 'Z'.
STD_LOGIC_VECTOR
The vector version of the STD_LOGIC data type. Each bit in the set of bits that make
up the vector can have the value X, 0, 1 or Z.
When assigning a value to a STD_LOGIC_VECTOR type, the value must be
enclosed in double quotes, e.g. "1010", "ZZZZ" or "ZZ001". The number of bits in
the value must match the size of the STD_LOGIC_VECTOR.
VHDL Operators
Some of the VHDL operators are listed below. Not all operators can operate on all
data types. Operators will be explained as they are used in this course.
Logical Operators
NOT, AND, NAND, OR, NOR, XOR and XNOR.
Arithmetic Operators
 + addition
 - subtraction
 * multiplication
 / division
 ABS absolute value
 MOD modulus
 REM remainder
 ** exponent
Comparison Operators
 = equal to
 /= not equal to
 < less than
 > greater than
 <= less than or equal to
 >= greater than or equal to
Shift Operators
 sll – shift left logical
 srl – shift right logical
 sla – shift left arithmetic
 sra – shift right arithmetic
 rol – rotate left
 ror – rotate right

Modeling used in VHDL


There are three type of modeling used:
Data Flow Modeling
In this modeling style, the flow of data through the entity is expressed using concurrent
(parallel) signal. The concurrent statements in VHDL are WHEN and GENERATE.
Besides them, assignments using only operators (AND, NOT, +, *, sll, etc.) can also be
used to construct code.
Finally, a special kind of assignment, called BLOCK, can also be employed in this kind
of code.
In concurrent code, the following can be used −
 Operators
 The WHEN statement (WHEN/ELSE or WITH/SELECT/WHEN);
 The GENERATE statement;
 The BLOCK statement
Behavioral Modeling
In this modeling style, the behavior of an entity as set of statements is executed
sequentially in the specified order. Only statements placed inside a PROCESS,
FUNCTION, or PROCEDURE are sequential.
PROCESSES, FUNCTIONS, and PROCEDURES are the only sections of code that are
executed sequentially.
However, as a whole, any of these blocks is still concurrent with any other statements
placed outside it.
One important aspect of behavior code is that it is not limited to sequential logic. Indeed,
with it, we can build sequential circuits as well as combinational circuits.
The behavior statements are IF, WAIT, CASE, and LOOP. VARIABLES are also
restricted and they are supposed to be used in sequential code only. VARIABLE can
never be global, so its value cannot be passed out directly.
Structural Modeling
In this modeling, an entity is described as a set of interconnected components. A
component instantiation statement is a concurrent statement. Therefore, the order of these
statements is not important. The structural style of modeling describes only an
interconnection of components (viewed as black boxes), without implying any behavior
of the components themselves nor of the entity that they collectively represent.
In Structural modeling, architecture body is composed of two parts − the declarative part
(before the keyword begin) and the statement part (after the keyword begin).
Delays In VHDL

1. Delta delay - In VHDL simulations, all signal assignments occur with some infinitesimal
delay, known as delta delay. VHDL uses the concept of delta delay to keep track of processes
that should occur at a given time step,but are actually evaluated in different machine cycles
.A delta delay is a unit of time as far as the simulator hardware is concerned, but in the
simulation itself time has no advance. Technically, delta delay is of no measurable unit, but
from a hardware design perspective one should think of delta delay as being the smallest time
unit one could measure, such as a femto second(fs).

2. Inertial delay - The inertial delay causes the pulses less than specified delay to get
suppressed & will not propogate these pulses to change the output. The inertial delay model
is specified by adding an after clause to the signal assignment statement. Inertial delay is
basically a default delay, i.e it's a component delay.

3. Transport delay - Tranport delay adds the propogation delay to the signal. The transport
delay model just delays the change in the output by the time specified in the after clause.
Transport delay basically represents a wire delay.

Acknowledgement: https://www.tutorialspoint.com/

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