“BLUE BOX” POWER ELECTRONICS CONTROL MODULES FOR

LABORATORY-BASED EDUCATION

R. S. BALOG, J. W. KIMBALL, Z. SORCHINI, P. T. KREIN,

AND P. L. CHAPMAN

CEME-TR-2004-02
June 2004

Grainger Center for Electric Machinery and Electromechanics

Department of Electrical and Computer Engineering
University of Illinois at Urbana/Champaign
Urbana, Illinois 61801
 UILU-ENG-2004-2504

“BLUE BOX” POWER ELECTRONICS CONTROL MODULES FOR

LABORATORY-BASED EDUCATION

R. S. BALOG, J. W. KIMBALL, Z. SORCHINI, P. T. KREIN,

AND P. L. CHAPMAN

CEME-TR-2004-02
June 2004

Grainger Center for Electric Machinery and Electromechanics

Department of Electrical and Computer Engineering
University of Illinois at Urbana/Champaign
Urbana, Illinois 61801
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 FORWARD

This technical report is a collection of design documents detailing the design and
fabrication of “blue box” power electronics control modules used in the power electronics
and machines laboratories at the University of Illinois at Urbana-Champaign.

The study of modern energy conversion draws upon a broad range of knowledge and
often requires a fair amount of experience. This suggests that laboratory instruction
should be an integral component of a power electronics and electric machines curriculum.
However, before a single watt can be processed in a realistic way, the student must
understand not only the operation of converter topologies but also more advanced
concepts such as control theory, gate drive isolation, layout issues, and other critical
issues. In a “blue box” approach, these details are pre-built into convenient modules but
not hidden from the students inside a “black box.”

The design details, schematics, and bill of materials for second-generation “blue box”
modules are described in the following design documents for a triple SCR control box, a
dual-MOSFET control box with independently isolated FET devices, a high quality
PWM inverter built with discrete components, and a small discrete brushless dc drive
system.

Please note that due to recent administration changes at the University of Illinois at
Urbana-Champaign some of the course numbers referred to in this report may be subject
to change.

Financial support for the “blue box” projects was provided by the Grainger Center for
Electric Machinery and Electromechanics. In-kind support was provided by the
University of Illinois at Urbana-Champaign Department of Electrical and Computer
Engineering.

Professor P. T. Krein,
Professor P. L. Chapman,
Jonathan W. Kimball,
Robert S. Balog,
Zakdy Sorchini
June 2004
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 Table of Contents

SCR BOX
Design Document
Schematics
PCB Artwork
Software
Mechanical Drawings
Bill of Materials

FET BOX
Design Document
Schematics
PCB Artwork
Mechanical Drawings
Bill of Materials

PWM Inverter
Design Document
Schematics
PCB Artwork
Mechanical Drawings
Bill of Materials

Brushless DC Motor (BLDC)

Design Document
Schematics
PCB Artwork
Mechanical Drawings
Bill of Materials
(This page intentionally left blank)
 Grainger Center for Electric Machinery and Electromechanics
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
1406 W. Green St.
Urbana, IL 61801

Design Document
SCR Box 2003

Reference: DD00001
Issue: 001
Status: Issued
Author: Jonathan Kimball/Zakdy Sorchini
Principal Investigator: P. T. Krein
Created: September 14, 2004
\\ece-powernts2\ece power design archives\documents\design documents\dd00001-000 scr box 2003.doc

Abstract:
From May through September 2003, new SCR boxes were designed and constructed to replace
existing boxes used in ECE469, Power Electronics Laboratory. The old boxes were fully analog
and required frequent calibration in order to perform properly. The new boxes use digital timing
and have a host of new features to enable their use in advanced experiments, both for teaching and
research use.

Copyright © Jonathan Kimball, Zakdy Sorchini, and Philip T. Krein 2004. All Rights Reserved.
May be duplicated for educational use only so long as this notice remains intact.
Work performed at the University of Illinois at Urbana-Champaign.
 SCR Box 2003
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Document Revision History
Issue Date Comments
000 02/12/04 Released after revision and review.
001 9/15/04 Integrated contents of DOC00001-000 (test procedure)

Contents

1. Introduction ......................................................................................................... 3
1.1 Scope ..................................................................................................................................... 3
1.2 Definitions............................................................................................................................... 3
1.3 References ............................................................................................................................. 3
2. Core Timing Design ............................................................................................ 4
2.1 Microcontroller Timing............................................................................................................ 4
2.1.1 Delay Information ..............................................................................................................4
2.1.2 Counter Loading................................................................................................................4
2.2 CPLD Timing .......................................................................................................................... 4
3. Power Circuit Design .......................................................................................... 6
3.1 Power Supply ......................................................................................................................... 6
3.2 Trigger Generation ................................................................................................................. 6
3.2.1 Internal Trigger.................................................................................................................. 6
3.2.2 External Trigger................................................................................................................. 6
3.2.3 Coordination...................................................................................................................... 7
3.3 SCR Gate Firing..................................................................................................................... 7
3.4 SCRs ...................................................................................................................................... 7
4. User Interface ..................................................................................................... 8
4.1 Timing Control ........................................................................................................................ 8
4.2 Operational Control ................................................................................................................ 8
4.3 Power Connections ................................................................................................................ 8
4.4 Internal Jumpers .................................................................................................................... 8
5. Enclosure Design.............................................................................................. 10

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1. Introduction
This project provides advanced SCR systems capable of being used in a multitude of projects.
Jonathan Kimball is the project manager, mechanical designer, and power designer. Zakdy
Sorchini is the digital and analog designer and the software engineer. Construction assistance was
provided by Yongxiang Chen, the ECE Electronics Shop, and the ECE Machine Shop.

1.1 Scope
The primary end use of the boxes is for ECE369 use. Therefore, it must be rugged and reliable in
an undergraduate lab setting. It must also be easy to debug and repair.
In addition, it is desirable to provide advanced capabilities used in a research setting. This includes
operation from an external trigger ranging 50-400 Hz, and either time-based or PLL-based angle
determination.
The box contains three SCRs, for phases A, B, and C.

1.2 Definitions
Master delay: time or pulse count from rising edge of master trigger to the initiation of phase A
firing.
Phase-to-phase delay: time or pulse count from the initiation of phase A firing to initiation of phase
B firing, and from initiation of phase B to initiation of phase C.

1.3 References
Schematics: SK0009 rev 1 and SK0010 rev 3
Layouts: PB0009 rev A and PB0010 rev B
Drawings: PJ0004 rev B

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2. Core Timing Design

A digital timing design provides more flexibility and allows repeatability of experiments, since
specific delay numbers can be dialed.
The principle behind timing is very simple: the main trigger signal (generated from the internal or
external trigger circuit) starts the process by enabling a counter which counts up to the specified
delay and then activates a “done” signal and also enables the next counter. In the actual design the
timing process is regulated by a microcontroller PIC16F72 from Microchip and a XC9572 CPLD
from Xilinx. Most of the timing circuit is implemented in the CPLD.

2.1 Microcontroller Timing

The microcontroller is used to obtain the delay (master and phase-to-phase) information from the
user via the encoder interface and load the counters when it is safe to do so.

2.1.1 Delay Information

To obtain the delay information from the encoder input, the µC is assumed to be fast enough to be
able to scan the encoder inputs to detect any change. Each cycle the µC reads the encoder value
along with the MASTER/PHASE switch state to modify the proper register. A brute force
approach is used to update the delay register, namely, the encoder value is compared to a previous
value and the appropriate action is taken (i.e., increase or decrease the register). The code assumes
that the encoder will not jump more than one state between reads; if that happens, no register is
actually modified.
Additionally, there is a calibration delay DIP switch, SW1, which allows an extra delay to be added
to the master delay. The µC is also responsible for reading this value and adding it to the master
delay.

2.1.2 Counter Loading

The delay values are loaded into the corresponding counters after they reached the zero count and
are inactive. When a counter is done, it triggers an interrupt on the µC, which then loads that same
counter with the proper value.

2.2 CPLD Timing

Once the counters are loaded, they are ready for the timing sequence. Internally, a flip-flop is
activated when the positive edge of the trigger signal occurs, which starts the counting process and
signals a “count in progress” state for the Master Delay counter. When the count reaches zero, the
flip-flop is deactivated and the next stage’s flip-flop is activated, which starts a similar process.
The same occurs for the third stage.
As mentioned in the previous section, the µC responds to the “counter done” event via an interrupt
process. The µC then enables a pulsing signal that is fed into the CPLD, one for each
corresponding counter. These three signals along with the “count in progress” signals are used in
an AND array to generate the SCR pulses for each phase. Additionally, a global Master Enable
signal ANDs with the SCR pulses for a global enabling capability.

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The CPLD timing implementation also covers a trigger signal deglitching circuit, which is able to
remove false positive edges from the trigger signal. False edges are generated by the load circuit
when turning on an SCR, or when commutating current. These are primarily observed on the
external trigger circuit, since the internal trigger stage lies behind the power transformer of the box.
The circuit uses a flip-flop to disable subsequent triggering which is reset before the next true edge
comes in.

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3. Power Circuit Design

The power circuit consists of four main parts: power supply, internal and external trigger
generation, SCR gate firing, and the actual SCRs.

3.1 Power Supply

The power supply is a simple linear supply derived from a 120V:12V center-tapped transformer,
shown on page 7 of SK0010. Each half of the secondary is half-wave rectified, to yield an
approximately 17V DC source. Linear regulators, an LM7812 and an LM7805, are used to derive
voltages used in the rest of the circuit. The 12V supply is only used by the SCR gate firing circuits,
but also serves as the source for the LM7805. The 5V supply is used for the remainder of the
circuitry. There are additionally resistors separating digital and analog supplies.
The total current required by the circuitry is approximately 1 A. This results in high power
dissipation in the linear regulators. Clip-on heat sinks are used, Wakefield 574502B03300 with the
mounting tabs clipped (Digi-Key HS220-ND). These are sufficient to keep case temperatures
below 85°C in a closed box in a 22°C ambient under all load conditions up to 10 ADC from a 208
VAC source.

3.2 Trigger Generation

3.2.1 Internal Trigger

There are two trigger circuits. The first is derived from the power supply transformer. It is used in
the teaching laboratory. The circuit is located primarily on page 10 of SK0010, fed from the power
supply on page 7. The capacitor shown, combined with the parasitic inductance and resistance of
the transformer, filters out any noise on the line. U10, a 2.5V reference, is used to move the zero
crossing circuit away from ground. This is necessary because of the single-supply topology
chosen. A small amount of positive feedback is necessary due to the slow nature of the power feed
(60 Hz).

3.2.2 External Trigger

The external trigger is derived from a 12-120 VAC source. For example, the laboratory benches
include a 25 VAC line-to-neutral single- or three-phase source, which can be fed into the external
trigger. For more sophisticated experiments, if line-to-neutral voltages are less than 120, they can
be used directly; otherwise, a simple transformer can be used to derive an appropriate voltage.
The external trigger source may be at any potential with respect to ground, so full isolation is
needed. For simplicity of the power supply, the necessary power is derived from the external
trigger source itself. It requires approximately 20 mA. This is shown at the upper left of page 11
of SK0010. The TIP47, 1N4744, and R32 combine to make a rudimentary linear regulator. It is
fed from half-wave rectified voltage via D15. There is no capacitance at the input, because that
would require the linear regulator to continuously drop a high voltage. Instead, the rectifier
capacitance is located after the linear regulator. The result is significant ripple in “+V”, but the
remainder of the circuit is tolerant to the ripple.

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The zero crossing circuit is essentially identical to the internal trigger circuit. To keep current
consumption down, some values are changed. An RLC filter was found to be necessary to prevent
glitches on the trigger signal when using the 25 VAC line-to-neutral source for both triggering and
load. This reduced line notching enough that the glitches could be handled in software.
Unfortunately, the filtering adds delay, on the order of 100 µs. For each box, the delay is measured
and recorded.
To complete the isolation, an optocoupler is used, shown at the bottom of page 10 of SK0010.

3.2.3 Coordination
There are two switches and a jumper involved in complete coordination of the internal and external
trigger. First, there is a jumper to invert the nominal internal trigger, in case of an error in wiring,
etc., J5 on page 7 of SK0010. Next, there is a switch connected to J7 on page 10 to choose internal
or external triggering. Finally, there is a switch connected to J8 on page 10 to give true or inverted
operation.
Typical operation in the teaching lab is to derive the power from (plug the box into) phase A of the
source that you are controlling. J5 is in the “NORM” position, J7 is in the “INTERNAL” position,
and J8 is in the “TRUE” position. For two-box experiments, such as for a full bridge rectifier, one
box would have J8 in the “INVERTED” position.

3.3 SCR Gate Firing

There are three gate firing circuits for the three phases, shown on pages 2-4 of SK0010. References
to follow are for phase A on page 2.
R8 sets the gate current. The voltage across the primary of T2 is given by the gate-cathode drop
plus a small drop in R4, plus a diode drop in D1. The source is a regulated 12V. R8 is chosen as
100 Ω to set the current at approximately 100 mA, assuming all of the drops on the secondary add
up to 2 V.
D9 is a flyback diode and D6 provides flux reset. Values are chosen so that the flux always resets
after every pulse, even for worst-case on-time. The transformer is a Coilcraft SD250-1. R1 and C1
form a gate snubber, possibly unnecessary but always advisable.

3.4 SCRs
The chosen SCRs are International Rectifier 10RIA40 stud-mount non-isolated devices. All three
are mounted to a single heat sink, Wakefield 403K. Isolation is achieved with thermal washers.
Additionally, there are O-rings on the studs to guarantee separation between the stud and the heat
sink.
The SCRs have been tested using a 208V three-phase source in a mid-point rectifier with a resistive
load up to 10 ADC. They have also been tested with RL loads and capacitive loads from lower
voltages. The highest case temperature seen is 56°C in a 22°C ambient with the box closed. It is
anticipated that even higher currents are possible without stressing the SCRs.

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4. User Interface
Any piece of equipment is useless without a good user interface. Most of our inputs as well as the
display are on the front panel of the box. The external trigger and the internal/external switch are
on the back, putting them out of sight (and hopefully out of mind) for the novice user.

4.1 Timing Control

There are two displays integrated on PB0012. The display was originally calibrated in pulses, but
now displays in milliseconds, in increments of 5 ms. Each display unit is a four-digit seven-
segment LED. They are labeled “master” and “phase” for master delay and phase-to-phase delay.
The user input for fully digital operation is an encoder. We chose a Grayhill 62A11-02-050S
optical encoder for reliability; it includes mechanical detents for tactile feedback. For long delay
times, incrementing in 5 ms steps would be interminably slow, so a coarse/fine switch is available.
In coarse mode, increments are 100 ms. Another switch determines whether the user is adjusting
the master or phase-to-phase delay.
For some applications, an analog input is desired. This allows the construction of a closed-loop
system. A switch determines whether the master delay derives digitally or from the analog input.
The analog input is a BNC with a 50 ohm termination and protection. The input range is 0 to 5 V,
which corresponds to a delay range of 0 to 20.47 ms.

4.2 Operational Control

At power-up, delays are all set to minimum (0.005 ms for master, 0.300 ms for phase-to-phase)
delay. To give the user the opportunity to adjust delays prior to energizing the power circuit, an
enable switch is available.
Standard operation fires the A phase SCR some delay time after the master trigger goes high. In
some applications, such as the negative half of a bridge rectifier, the user may desire to fire after
the master trigger goes low. A “TRUE/INVERTED” switch is available for this operation.
Advanced users may desire external triggering. The switch towards the bottom of the back panel is
an internal/external switch. The master trigger goes high when the voltage on the orange post goes
positive with respect to the blue post.
There is a power switch on the back panel. Power derives from a standard IEC320 cord via a 250
mA standard fuse. Power is indicated by an LED on the front panel, which is powered from 5V.

4.3 Power Connections

The SCR anodes and cathodes are on the front panel via binding posts. Each is rated for 15 A.
Orange is the anode, for a weak “positive” connotation.

4.4 Internal Jumpers

A jumper, J5, is provided to invert the main internal trigger. This may be necessary depending on
how the rest of the box is wired. So far, we have not needed to invert.

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A jumper, JP2, is provided to switch from the microcontroller-derived clock to a PLL-derived

clock. This can be used for other frequencies besides 60 Hz. For proper operation of the PLL,
another jumper, JP1, is provided to set the nominal center frequency of the oscillator. The high
range is for 400 Hz, the low range is for 50/60 Hz, and the middle range is for other frequencies in-
between. Note that in PLL operation, the displayed delay will be 0.005x the number of pulses, with
4096 pulses per cycle.

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5. Enclosure Design
The enclosure is a modified Hammond 1458E5. We chose ASA 61 Grey for the top and bottom,
and stayed with the standard Contempra Gray (more like beige) front and black back. This type of
box was chosen to be consistent with the 2002 version of the FET box.
The enclosure was designed in Autodesk Inventor. PDFs of the machining prints are available, as
well as the source Inventor files, under PJ0004 rev B.
The front panel was silk-screened black. At the time the order was submitted, we planned to have
the display in pulses. We later decided to display milliseconds to reduce confusion. The ECE
Machine Shop painted over the text indicating the readout type.
Looking back, the box is really just a little too small for the system. It would have been better to
have another inch in height and in width, although depth would not have helped much. The
1458E5 gave us the best possible solution for a standard box. The height is dictated mainly by the
SCR heat sink assembly, but also by the display board and binding posts on the front panel. The
width is dominated by the SCR heat sink assembly plus the power outlet and switch. Another inch
in width would have greatly simplified the assembly of the power input.

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6. Test Procedure

6.1 Preface
This test procedure was meant to be as generic as possible, but a couple of issues specific to the
Power Lab at the University of Illinois could not be made generic enough:
y It is assumed that a 120 VAC three-phase set (standard plug) is available to power
equipment and is synchronized to whatever three-phase source is used in the experiments.
y Some steps require the use of a 25 VAC (line to neutral) three-phase source. Transformer
implementation of this source should have a Y-connected secondary at a low enough
potential to be safe for testing, but high enough to be able to power the external trigger
circuitry. Refer to 3.2.2 for the proper ratings.

6.2 Introduction
The added complexity of the new SCR Boxes requires a systematic test procedure. This section
allows any user to verify operation of the box, either after initial assembly or for troubleshooting.
Individual subsections cover testing of the different subsystems of the SCR Box. For reference, a
diagram of the front panel is shown in Figure 1.

Figure 1. SCR Box front panel diagram.

The trigger source selector switch is located on the back panel. The position TOWARDS the
external trigger banana post connectors is for external triggering. Similarly the position AWAY
from the connectors is for internal triggering. The orange terminal is positive relative to the blue
terminal.

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All measurements, unless otherwise stated, are referenced to ground. Ground test points available
are TP12, TP14, TP21, TP22 and TP23. Analog ground is TP18. The isolated ground for the
external trigger input is TP44. As a reference, Figure 2 shows a diagram of the main board to aid
in locating individual parts or test points.

Figure 2. SCR Box control PCB diagram.

6.3 Known Issues

y Noise is injected to the digital bus line from the serial clock within the interface cable that
connects the main PCB to the display PCB. This problem will manifest itself as random
firing of the SCRs, and seems to be more sensitive as the master delay is increased. A
workaround is to use a custom interface cable that shields the lines and uses an overall shield.
The particular grounding scheme (on each side or both sides) did not seem to make any
difference, but in general it was observed that this solution minimizes the problem.

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y The accuracy of the delays is limited (± 5 µs) by the uncertainty created from the lack of
synchronism between the high frequency clock derived from the microcontroller and the
trigger signal derived form the internal or external trigger circuit. Although the high
frequency clock derived from the PLL section is synchronized to the trigger signal, the
resolution of the PLL itself (since it is working as a frequency multiplier) also gives a
comparable uncertainty. Reduction of the multiplier (current implementation uses a 212
multiplier) should minimize this uncertainty.
y When using the external trigger, noise in the input voltage (particularly spikes) can alter the
zero crossing detection or introduce false triggering. A passive filter is used to minimize the
effect of this noise. This has the effect of introducing a delay (about 100 µs) in the trigger
signal. Noise spikes are particularly troublesome and are typically created by current
commutation. Therefore, the trigger logic is designed to remove false triggers once the
trigger sequence is already in progress. Essentially the zero crossing detection is disabled
during particular periods in time when a true zero cross cannot occur.

6.4 Converter Operation

This section covers the tests that do not require opening the SCR Box for access to internal signals.
It should be used to verify normal operation of the box. Typical failures for this section are missed
phases at the output (SCR not fired or bad internal connection), no output (problem with
True/Inverted switch or with trigger circuit), improper phasing or wrong delay observed (mixed
internal SCR connections, problem with True/Inverted switch or misconfiguration of the internal
calibration delay).
1. Connect the power cable of the box to the phase A power outlet.
2. Connect phase A (typically from the 25 VAC source) to the external trigger. The phase wire
should be connected to the orange connector and the neutral to the blue connector.
3. Power up the SCR Box. The main power LED should light up and the displays should read
0.005 for the Master delay and 0.300 for the Phase-to-Phase delay. If the box does not
power up or the displays do not light up, verify operation of the power distribution.
Sometimes, the displays might power up with all segments illuminated. Turning the box
off and on should correct the issue; if not, there is a problem with the display.
4. Set the Phase-to-Phase delay to 5.555 ms (the nominal value for 60 Hz operation).
5. Implement a half-bridge controlled rectifier as shown in Figure 3, using the 25 VAC source
(the 3-phase transformer set). Connect the differential (scope) probe across the load
resistor. Setting the scope’s trigger to AC line will help displaying the waveforms.

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Figure 3. Half-bridge controlled rectifier with resistive load.

6. Set the trigger switch to Internal.

7. Verify operation of the (trigger) Enable switch. Enabled will show a waveform similar to
what is shown in Figure 4. Disabled will make the output of the converter zero.
8. With the Master delay control set to digital, vary the master delay from 0.005 ms to about 9
ms using BOTH the coarse and fine control to verify their operation. The output should
look like the sequence shown in Figure 4. If the waveform does not resemble the ones
shown in the figure, verify operation of the trigger stage.
9. Set the trigger switch to External.
10. Verify operation by repeating steps 7 and 8. The waveforms should be almost the same.
11. Connect a function generator to the BNC connector for analog control. Set the function
generator for a sine wave of 1 Hz between 0 and 2 V.
12. Set the Master Delay Source to Analog (use any trigger source). This will modulate the
delay by the sine wave. The modulation should be close to 100 % (i.e., the delay should go
from about 0 ms to 9 ms giving 100 % to 0 % output voltage). The modulation process in a
slow time scale should look like what is shown in Figure 5. If the output is not modulated,
then verify the analog input circuit (User Interface Section).

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(a) 0.005 ms (b) 4 ms

(c) 6 ms (d) 8 ms
Figure 4. Converter output for different Master delays.

13. Verify operation of the True/Inverted switch. Reverse the connections on the external
trigger input and set the switch to Inverted. Operation should be the same as in step 8,
since the reversal of the external trigger connections is cancelled by inverting the trigger.
14. If no faults are found, the box is functioning properly; terminate the test.

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Figure 5. Output voltage modulation.

6.5 Power Distribution

1. Connect the power cable to any electrical outlet and power up the box. Verify that the
Power LED lights up and that the LED digits light up (they should light up as 0.005 for the
Master delay and 0.300 for the Phase-to-Phase delay).
2. Verify that ac power is available. Connect at TP8 and at TP7; and verify that the readings
are equal and around 14 VRMS. If no voltage is present, check the fuse on the power
receptacle.
3. Verify the dc power voltages. TP24 should be unregulated 16 V, TP25 should be 12 V
nominal, TP26 should be 5 V nominal, and TP28 with respect to TP18 should be 5V
nominal.
4. Verify dc power to the display board mounted on the front panel. If the voltages on the
main board are correct and the displays light up as 0.005 and 0.300, then power is ok.
Otherwise, verify that pin 6 on the display board is 5 V nominal. Alternatively, the
terminals toward the inside of the board on R1 or C1 can be verified.

6.6 Trigger System

1. Make sure that the calibration delay (SW1) is set to zero (all jumpers inactive). The
inactive position (as marked in the board) is AWAY from the front panel.
2. Follow the procedure in Part 1 to prepare the box for normal converter operation. Monitor
the output voltage with the differential probe.
3. Verify the operation of the microcontroller. Check TP29 for the high frequency clock at a
nominal 200 kHz (NOT 50 % duty ratio). If this signal is not present then the
microcontroller is not operating properly.
4. Verify the internal trigger circuit.
a. Verify that TP38 is fixed at 2.5 V nominal (voltage reference).
b. Verify that TP27 is a square wave at nominal 50 % duty ratio and in phase with the
voltage powering the box (typically phase A).

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5. Verify the external trigger circuit. Use the differential probe when verifying signals on the
isolated side.
a. Using the isolated ground (TP44), verify that TP43 is approximately 13 V
unregulated dc.
b. Verify that TP42 is 5 V nominal (zener regulated).
c. Verify that TP37 is a square wave at nominal 50 % duty ratio and in phase with the
external trigger input voltage.
d. Verify that TP36 shows LOGICAL inversion of the previous signal (the signals
will have different amplitudes). This is on the output side of the optical isolator, so
a regular probe can be used.
6. Verify TP35, the main trigger signal going into the CPLD. This is the trigger signal
according to the trigger source selector and the True/Inverted switch. Verify all
combinations of both switches (no change should be observed between internal and
external triggering). Keep the signal in the scope as a reference.
7. Verify TP33, the high frequency clock going into the CPLD; it should be the same as
TP29. Make sure that JP2 is closed to gate the high frequency clock coming from the
microcontroller.
8. Verify the master counter enable signal, EN_MC (TP15, active low). Move the signal with
signal by changing the Master delay. The falling edge should be in synch with the raising
edge of the trigger signal. The raising edge should move as the Master delay is varied.
Refer to Figure 6 (Ch1 – Trigger, Ch2 – EN_MC, Ch3 – EN_PPC1, Ch4 – EN_PPC2).
9. Verify the phase-to-phase counter 1 signal, EN_PPC1 (TP16, active low). The whole
signal should move as the Master delay is changed. The raising edge should move as the
Phase-to-Phase delay is varied. Refer to Figure 6.
10. Verify the phase-to-phase counter 2 signal, EN_PPC2 (TP20, active low). The whole
signal should move as the Master delay is changed. Both edges will move as the Phase-to-
Phase delay is changed. Refer to Figure 6.

(a) Master delay 2 ms, Phase-to-Phase delay 2 ms (b) Master delay 2 ms, Phase-to-Phase delay 6 ms

SCR Box 2003 Status : Issued

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 SCR Box 2003
Design Document Issue 001 DD00001

(c) Master delay 6 ms, Phase-to-Phase delay 2 ms (d) Master delay 6 ms, Phase-to-Phase delay 6 ms
Figure 6. Timing sequence for different delays.

11. Set the Phase-to-Phase delay to 5.555 ms (nominal for 60 Hz operation) and enable SCR
firing.
12. Verify the gate control signals for the SCRs, TP19 (SCR A), TP17 (SCR B) and TP18
(SCR C). They should be pulse trains that start with the raising edge of the corresponding
enable signal (SCR A – EN_MC, SCR B – EN_PPC1 and SCR C – EN_PPC2) and end
with the falling edge of the next one. Figure 7 shows the sequence to be expected for
Phase A, for Master delays of 1 ms and 6 ms. Ch1 is the trigger signal; Ch2 is EN_MC,
Ch3 is EN_PPC1; Ch4 is the SCR A control signal; and Ref1 is the output voltage
waveform. Notice that the first pulse of the SCR control signal is wider.

(a) 2 ms (b) 6 ms
Figure 7. Phase A trigger sequence for different Master delays.

6.7 Gate Drives

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 SCR Box 2003
Design Document Issue 001 DD00001

1. From 6.6, SCR control signals should have been verified. These are the pulses that are fed
to the gate drives.
2. Verify the voltage on the primary side of the pulse transformer for SCR A (TP9). It should
be at 12 V at rest and pulse between 0 V and 28 V when active. If flux is completely reset
during pulsing, the signal goes back to 12 V.
3. Connect the differential probe across TP1 and TP2, the secondary side of the transformer.
This is the voltage applied to the gate of the SCR. The secondary voltage should mimic the
primary voltage. Figure 8 shows the gating process for a small Master delay. Ch1 is the
trigger signal, Ch2 is the control signal, Ch3 is the primary side voltage and Ch4 is the
voltage applied to the gate of the SCR.
4. Repeat the previous step for SCRs B and C primary side (TP10 and TP11) and the
corresponding secondary voltage (TP3, TP4 and TP5, TP6).

Figure 8. Gate drive A operation for a small Master delay.

6.8 PLL Section

The SCR Box includes a PLL section as a second source of high frequency pulses that feed the
counters in the delay process. By synchronizing to the trigger signal (internal or external) the delay
is in degrees as opposed to absolute time. Therefore, a fixed delay can be achieved (i.e., delay
angle α) independently of the frequency of the power source. A multiplier of 212 is used, thus
giving a resolution of approximately 0.088° per step.
The high frequency clock generated by the circuit has to be manually selected (JP2) to be used in
the trigger circuit.
1. Make sure that the frequency range of the circuit is correct. Typically it will use the low
frequency range (i.e., both jumpers in JP1 closed) for 60 Hz operation.
2. Verify the signal in TP31. This should be in synch with whatever the trigger signal is (i.e.,
Internal/External, True/Inverted). If it is not (assorted notches on the signal jumping
around), then the frequency range might not be correct.

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 SCR Box 2003
Design Document Issue 001 DD00001

3. Verify the signal in TP32. This is the high frequency clock generated by the circuit and
should be nominally 212 times the input frequency (245.7 kHz for 60 Hz input).

6.9 User Interface Section

This section covers the analog input and the encoder logic. The analog input has a 50 Ω input
impedance, so the source driving this input should not be soft. The outputs of the encoder are open
collector, so pull-up resistors are used.
1. Verify TP41 and TP39 for proper operation of the encoder. They should be square
waveforms that follow a repetitive pattern as the encoder is moved (every four steps the
sequence will repeat). Figure 9 shows the sequencing of the encoder outputs as the
encoder is moved eight steps (two cycles); each step corresponds to a particular logic
combination of the encoder outputs (Ch1 – TP41, Ch2 – TP39). If no signal is present,
there is probably no power feeding the encoder.

Figure 9. Encoder outputs for a two cycle movement of the encoder.

2. For the analog input, if no control of the Master delay is achievable, one of the input
protection diodes might be damaged or reversed.
3. Verify the physical integrity of the MTA-100 connectors. During assembly it was
observed that a significant number of connectors were not crimped correctly and therefore
bad connection to the header resulted. Also, sometimes the switches on the front panel
might fail.

SCR Box 2003 Status : Issued

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 Power Switch AC Input (120 VAC)

To J1
Power Anode A
To J6
A
Coarse/Fine
To J11 Cathode A
Master/Interphase To J2 Anode B
To J13
B
Encoder for Adjustment
To J3 Cathode B
Digital/Analog SCR Box Main Board Anode C
To J15
C
To J4
Analog Input To J12 Cathode C

To J8 To J7 Internal/External Switch
True/Inverted
Ext Orange
To J14 To J10
Enable
Ext Blue

To J16

Connection Diagram
Display PCB SCR Box
Jonathan Kimball
University of Illinois at Urbana-Champaign
Rev B of 17 September 2004
 VCC

VCC
R1
56k

J1 U1
6

12

12
5 1 DIN DOUT 24

9
8
6

9
8
6
4 U2 U3
3 18 ISET DIG0 2
2 DIG1 11
1 13 CLK DIG2 6
DIG3 7
12 3

11
7
4
2
1
10
5
3

11
7
4
2
1
10
5
3
MTA100-6 LOAD DIG4
DIG5 10
DIG6 5
DIG7 8
VCC
SEGA 14
SEGB 16
SEGC 20
+ C2 23
10u C1 SEGD
SEGE 21
0.1u 15
SEGF
SEGG 17
SEGDP 22

MAX7219

Copyright 2003 by Jonathan Kimball and Zakdy Sorchini.

All Rights Reserved. May be duplicated for educational
use only so long as this notice remains intact.
Work performed at the University of Illinois at Urbana-Champaign.

Title
SCR Box Display PCB

Size Document Number Rev

A SK0009 1

Date: Friday, October 03, 2003 Sheet 1 of 1

 5 4 3 2 1

D D

MICRO_C USER_IO

POWER_SUPPLY
EN_SR EN_SR
ZERO_CROSS EN_AD EN_AD
+12V EN_DISP EN_DISP

WINDING WINDING SCK SCK

SDO SDO
TRIG SDI SDI
POWER_SUPPLY
AD_CTRL AD_CTRL
ZERO_CROSS
C C
GATE_A MASTER_ENABLE
GATE_B
GATE_C
USER_IO
HF_CK_UC LD_MC GATE_DRIVES
LD_PPC1 TIMING
LD_PPC2
+12V
EN_MC SCK
EN_PPC1 SDO
EN_PPC2 SCR_A SCR_A
GATE_A SCR_B SCR_B
GATE_B SCR_C SCR_C
MICRO_C GATE_C
GATE_DRIVES
LD_MC
LD_PPC1
B LD_PPC2 B

EN_MC
EN_PPC1
JP2 EN_PPC2
PLL
HF_CK
1 2
TRIG HF_CK 3 4 TRIG

TP33 MASTER_ENABLE
PLL
JUMPER2
TIMING

A A
Copyright 2003 by Jonathan Kimball, Zakdy Sorchini, and Philip T. Krein.
All Rights Reserved. May be duplicated for educational Title
use only so long as this notice remains intact. SCR Box Control Board
Work performed at the University of Illinois at Urbana-Champaign.
Size Document Number Rev
A SK0010 3

Date: Friday, October 03, 2003 Sheet 1 of 11

5 4 3 2 1
 5 4 3 2 1

+12V
D D

R8
100 1W

TP1

D6
D1 R4
1N4744A SCR_A_G
T2
C 1 10 C
J2
1N4148 10 R1 1
C1 2
1k00 0.1uF
5 6

D9 SD250-1 SCR_A_K MTA100-2

1N4148

TP9 TP2

C6
0.1uF

R12 Q1
B B
SCR_A 2N7000

330

A A

Title
SCR Box Control Board

Size Document Number Rev

A SK0010 3

Date: Friday, October 03, 2003 Sheet 2 of 11

5 4 3 2 1
 5 4 3 2 1

+12V
D D

R9
100 1W

TP3

D7
D2 R5
1N4744A SCR_B_G
T3
C 1 10 C
J3
1N4148 10 R2 1
C2 2
1k00 0.1uF
5 6

D10 SD250-1 SCR_B_K MTA100-2

1N4148

TP10 TP4

C7
0.1uF

R13 Q2
B B
SCR_B 2N7000

330

A A

Title
SCR Box Control Board

Size Document Number Rev

A SK0010 3

Date: Friday, October 03, 2003 Sheet 3 of 11

5 4 3 2 1
 5 4 3 2 1

+12V
D D

R10
100 1W

TP5

D8
D3 R6
1N4744A SCR_C_G
T4
C 1 10 C
J4
1N4148 10 R3 1
C3 2
1k00 0.1uF
5 6

D11 SD250-1 SCR_C_K MTA100-2

1N4148

TP11 TP6

C8
0.1uF

R11 Q3
B B
SCR_C 2N7000

330

A A

Title
SCR Box Control Board

Size Document Number Rev

A SK0010 3

Date: Friday, October 03, 2003 Sheet 4 of 11

5 4 3 2 1
 5 4 3 2 1

D D

VCC
U3
1 /MCLR RB0 21 EN_MC
RB1 22 GATE_A
RB2 23 GATE_B
EN_SR 2 RA0 RB3 24 GATE_C
EN_AD 3 RA1 RB4 25
EN_DISP 4 RA2 RB5 26
C
LD_MC 5 RA3 RB6 27 EN_PPC1 C
6 RA4 RB7 28 EN_PPC2
LD_PPC1 7 RA5
RC0 11
C17 10pF 12
RC1
RC2 13 HF_CK_UC
9 OSC1 RC3/SCK 14 SCK
Y1 15
RC4/SDI SDI
C18 10pF 16MHz 10 16
OSC2 RC5/SDO SDO
RC6 17 AD_CTRL
RC7 18 LD_PPC2

PIC16F72

VCC TP29
B B

C15 C14
TP14 0.1uF 0.1uF

A A

Title
SCR Box Control Board

Size Document Number Rev

A SK0010 3

Date: Friday, October 03, 2003 Sheet 5 of 11

5 4 3 2 1
 5 4 3 2 1

D D

TP31

R23

U4 10

R18 R15 10 3 10
TRIG COMPIN DEMOD OUT
221k 5 2
R20 33k2 INH PHCOMP I OUT U7
14 SIGIN PHCOMP II OUT 13
9 VCOIN PHPULSE 1
C
VCOOUT 4 10 CLK Q1 9 C
6 C1A Q2 7
+ C13 7 R22 VCC 11 6
4.7uF C1B 10 RST Q3
11 R1 Q4 5
12 R2 16 VCC Q5 3
R17 AVCC 15 2
ZENER Q6
4

VSS
22k1 Q7
16 VDD Q8 13
JP1 12
Q9
14

8
74HC4046B Q10
1 2 Q11 15
3 4 HF_CK Q12 1

C20 C22 AVCC

68pF C26 100pF 74HC4040
250pF
TP32 VCC
C16
B These capacitors will set the oscillator frequency 0.1uF B
by the total capacitance between IC pins.
C25
00 - High Frequency 0.1uF
01 - Mid Frequency 1
10 - Mid Frequency 2
11 - Low Frequency

A A

Title
SCR Box Control Board

Size Document Number Rev

A SK0010 3

Date: Friday, October 03, 2003 Sheet 6 of 11

5 4 3 2 1
 5 4 3 2 1

TP8

VCC AVCC
D TP26 TP28 D
TP25 +12V

TP24 D13 D12

1N4002 1N4002
T1
SW "Side-Winder" D5 U1 U2
R16
5 1 IN OUT 3 1 IN OUT 3
1
+ C5 + C9 + C10 10
J1 1N4002 470uF 100uF C11 100uF C12
1

LM7812C/TO220 LM7805C/TO220 0.1uF R14 0.1uF

C 3 6 C
2 MOV1
1 V130LA10A 7
10
2

D4 TP12
MTA156-3 4 TP21 TP18
8

1N4002
R7 VCC
J5

Zerohm NORM 1
TP7 2 R19
INV 3
C4 330
J6
B B
JUMPER3 1
2
Do Not Stuff

MTA100-2
WINDING

NOTES:

J1 comes from IEC320 plug via switch and fuse.

J1 pin 2 is earth ground for safety.
AVCC used by 12-bit A/D converter and PLL chip.
A May replace resistors R14 and R16 with inductors for added noise separation. A
J6 pin 1 is anode, pin 2 is cathode for indicator LED.
Title
SCR Box Control Board

Size Document Number Rev

A SK0010 3

Date: Friday, October 03, 2003 Sheet 7 of 11

5 4 3 2 1
 5 4 3 2 1

MASTER_ENABLE

HF_CK

D SCK D

SCR_A
VCC

SCR_B

C33
0.1uF SCR_C

TP19

44
43
42
41
40
U9

6
5
4
3
2
1
GCK2
GCK1
4
3
2
1
44
43
GTS1
VCCINT
GTS2
GATE_A TP17
7 GCK3 GSR 39
GATE_B 8 8 38 38
C 9 9 37 37 C
10 36 TP13
GND 36
GATE_C 11 11 35 35
12 34 VCC
12 34
13 13 33 33
14 14 VCCIO 32
15 TDI GND 31
TP20 16 30
TMS TDO C19
17 TCK 29 29
0.1uF

VCCINT

GND
EN_PPC2

18
19
20

22

24
25
26
27
28
TP16

18
19
20
21
22
23
24
25
26
27
28
XC9572_PC44
EN_PPC1
TP15
B B

EN_MC

SDO

LD_MC

LD_PPC1

LD_PPC2

TRIG
VCC

A A

TP23 TP22 Title

C23 SCR Box Control Board
0.1uF
Size Document Number Rev
A SK0010 3

Date: Friday, October 03, 2003 Sheet 8 of 11

5 4 3 2 1
 5 4 3 2 1

TO DISPLAY BOARD VCC VCC

J16 R33

1
6 10K x9
5 SDO
SCK SDO
4
3 EN_DISP
2 CALIBRATION DELAY DIP SWITCH U12
D D
1
SW1 10 9
SDI Q7
7

2
3
4
5
6
7
8
9
10
MTA100-6 Q7
11 D0
12 D1
AVCC 13 VCC
EN_AD D2
14 D3
3 D4
4 D5
D14 5 C32
U11 D6

8
6 0.1uF
1N5819 SCK D7
1 7

VCC
TP40 /CS CLK SCK
SCK 2 CLK
ANIN 2 6 SDI VCC
GND
CH0 DOUT SDO R31 NOT_EN_SR
3 CH1 DIN 5 15 CKE

1
10K x9 EN_SR 1
D17 MCP3202 PL
4

C SW DIP-12 C
1N5819 74HC165

COARSE/FINE SWITCH
ANALOG INPUT U8
J11

2
3
4
5
6
7
8
9
10
J12 1 AD_CTRL 14 9 SDI
ANIN MASTER_ENABLE SDI QH' SDI
AVCC 2
1 15 A
2 R42 R40 R39 1k00 1
100 100 C35 MTA100-2 B
2 C
0.1uF + C31 3 VCC
MTA100-2 10uF C30 J13 D
4 E
0.1uF 1 5 F
2 6 G
VCC 7 C28
H 0.1uF
ENCODER INPUT MTA100-2 12
B ACTUALLY 6 MASTER/PHASE SWITCH SCK RCLK B
11 SRCLK
PIN CABLE
R35 R34 10
J9 10k0 10k0 EN_SR OE
EN_SR 13 SH/PL
10
9 74HC14 U6E
8 VCC TP41 74HC589
7 74HC14 U6D 11 10 NOT_EN_SR
6 VCC
5 9 8 ENC_A
4
3
2 74HC14 U6F C27
1 TP39 0.1uF
13 12 ENC_B

RIBBON10
A A

ENABLE SCR FIRING J14 DIGITAL / ANALOG CONTROL J15 Title

MASTER_ENABLE 1 AD_CTRL 1 SCR Box Control Board
MASTER_ENABLE AD_CTRL
2 2
Size Document Number Rev
A SK0010 3
MTA100-2 MTA100-2
Date: Friday, October 03, 2003 Sheet 9 of 11
5 4 3 2 1
 5 4 3 2 1

R25
WINDING
This circuit uses internal power supply as zero cross source (12V CT transformer).
R24 C?? is on rev B of PB0010 as rework.
22k1
VCC
R26
1k00 1M00
D D

C?? R21 VCC

2.2uF U5 10k0 U6A

8
5
R27
1k00 2 +
7 1 2 \INT C21
3 - 0.1uF
R29 TP30
VCC TP27

4
1
6
LM311 74HC14
C24
22k1 0.1uF
TP34 TP35

R30
C 1k00 U6B C

\INT
TRIG
3 4
\EXT

TP38
74HC14
2

3
2
1

3
2
1
U10
C29
LM385-2.5/TO92 0.1uF
J7 J8
3

MTA100-3 MTA100-3

VCC
B B

ISO1
R36 R28
2 8 1k00 U6C
+V
1k50 7
6 5 6 \EXT
ZEROX 3
TP36
74HC14
C34
5

HCPL2611 0.1uF

A A
This circuit uses an external 12-120VAC
for reference. See next page. Title
SCR Box Control Board

Size Document Number Rev

A SK0010 3

Date: Friday, October 03, 2003 Sheet 10 of 11

5 4 3 2 1
 5 4 3 2 1

This circuit self-powers from a 12-120VAC

source and generates a reference pulse. R41
TP43
D D
D15 Q5 1M00
TIP47
+V
+V

1N4004
R32 ZEROX
+ C38 R37
100uF
10k0
27k3 U13

8
5
R38 2 + Q4
D16 7 2N7000
100
1N4744 3 -
TP37

4
1
6
LM311
C
J10 C
2
1 C37 C36
0.1uF 0.01uF

MTA156-2 ISO_GND
L1 R??
TP44

22mH 560

R45

+V 47k5 1/2W R?? is on rev B of the PB0010 as rework.

C41
Do Not Stuff C40
R47 0.1uF 200V
B B
4k75 R43
1k00

TP42

R44
1k00
D18 C39
0.1uF
1N4733

R46
47k5
A A

Title
ISO_GND SCR Box Control Board

Size Document Number Rev

A SK0010 3

Date: Friday, October 03, 2003 Sheet 11 of 11

5 4 3 2 1
 SW0000_B
;*******************************************************************************************
;
; SCR Box - Microcontroller code
;
; This program implements all routines for the SCR Box microcontroller.
; Tasks include reading delay information, displaying delay information,
; calculating delays and output gating signals for the SCR drivers.
;
; Coded by:
; Zakdy Sorchini
;
; Target:
; PIC16F72 - MAKE SURE TO SET PROPER CONFIGURATION BITS: Oscillator HS
;
; NOTES:
; 1. Since Interrupt code uses SPI transfer, ALL transfers in Main loop must disable
; interrupts for proper operation.
; 2. Seems like when making a CALL to a subroutine, interrupts are affected (not serviced?)
; Changed the code to just use explicit code and not a CALL for the BIN2BCD
conversion.
;
; Revision History:
;
; Version B - 8/05/2003: Changed time base. Display in milliseconds.
; Changed BIN2BCD from subroutines
to explicit code.
; Changed implementation of
interrupt code.
; Version A - 7/30/2003: Initial code for the SCR Box.
;
;********************************************************************************************

;********************************************************************************************
; PIN ASSIGMENT TABLE
;
; RA0 - Shift Register Enable
; RA1 - A/D Enable
; RA2 - Display Driver Enable
; RA3 - Load Master Counter
; RA4 - Free
; RA5 - Load Phase-to-Phase Counter 1
; RB0 - Master Counter done input
; RB1 - Gate A
; RB2 - Gate B
; RB3 - Gate C
; RB4 - Free
; RB5 - Free
; RB6 - Phase-to-Phase Counter 1 done input
; RB7 - Phase-to-Phase Counter 2 done input
; RC0 - Free
; RC1 - Free
; RC2 - HF Clock - PWM module
; RC3 - Serial Clock
; RC4 - Serial Data In
; RC5 - Serial Data Out
; RC6 - Digital/Analog Master Delay input
; RC7 - Load Phase-to-Phase Counter 2
;
;********************************************************************************************
#include "P16F72.inc"
#define OPTION 0x81
#define SDO 5
#define SCK 3
#define RBPU 7
#define LED_RATE .5 ; Display update rate
#define STAT_H 0x20 ; SCR box status register HIGH
byte
#define STAT_L 0x21 ; SCR box status register LOW
byte
#define NUM_H 0x22 ; High part of number for
Bin-BCD
#define NUM_L 0x23 ; Low part of number for Bin-BCD
#define ONES 0x24 ; BCD result
Page 1
 SW0000_B
#define TENS 0x25 ; BCD result
#define HUND 0x26 ; BCD result
#define THOU 0x27 ; BCD result
#define TENK 0x28 ; BCD result
#define AD_0_L 0x29 ; Low part of A/D channel 0
#define AD_0_H 0x2a ; High part of A/D channel 0
#define AD_1_L 0x2b ; Low part of A/D channel 1
#define AD_1_H 0x2c ; High part of A/D channel 1
#define STAT_H_OLD 0x2d ; Old status
#define STAT_L_OLD 0x2e ; Old status
#define M_DELAY_H 0x2f ; Master delay
#define M_DELAY_L 0x30 ; Master delay
#define PP_DELAY_H 0x31 ; Phase-to-phase delay
#define PP_DELAY_L 0x32 ; Phase-to-phase delay
#define TEMP 0x33 ; Temp. register
#define AD_COUNT 0x34 ; Count for A/D update
#define PORTB_OLD 0x35 ; Old PORTB value to determine what pin caused
; interrupt on change
#define TEMP_INT 0x36 ; Temp register for interrupt routine
#define TEMP_CNT 0x37 ; Temp register for interrupt routine (for counters)
#define FLAG 0x38 ; Flag for Timer 0
#define GATE 0x39 ; Mask for Gate signal
#define M_DELAY_H_PLD 0x3a ; These are the actual registers used
for transfer to the CPLD
#define M_DELAY_L_PLD 0x3b ; they are carefully updatedmto ensure
the limits are enforced
#define PP_DELAY_H_PLD 0x3c ; and is safe to use them all the time
#define PP_DELAY_L_PLD 0x3d
#define LED_UPDATE 0x3e ; Display update register
#define LED_UPDATE_L 0x3f ; Display update register, low part
#define W_TEMP 0x70 ; Temp W for interrupts
#define STATUS_TEMP 0x71 ; Temp STATUS for interrupts
; NOTE:
Previous two registers MUST be defined
;
accross all banks
;********************************************************************************************
; STATUS WORD DEFINITION
;
; STAT_H
; Bits 7-6: Encoder
; Bit 5: Master/Phase-to-phase
; Bit 4: Coarse/Fine
; Bits 3-0: Calibration Delay bits 11-8
; STAT_L
; Bits 7-0: Calibration Delay bits 7-0
;
;********************************************************************************************

;********************************************************************************************
; RESET VECTOR
;********************************************************************************************
org 00h
goto MAIN
;********************************************************************************************
; INTERRUPT CODE
;
; The ISR will load the counters when it is safe to do so, basically when the counter has
; been disabled by the triggering process.
;
; Note that this code will use the SPI interface. Special care has to be taken to ensure
; that if the interrupt occurs during SPI use in main loop, proper status will be preserved.
; Perhaps the best thing to do is just disable interrupts while processing the SPI transfer.
; This assumes that the interrupt code is, therefore, not time critical.
;
; Also note that there is a minimum Phase-to-Phase delay enforced by this code.
;********************************************************************************************
INTER
org 04h
; PUSH implementation
movwf W_TEMP
Page 2
 SW0000_B
swapf STATUS,W
movwf STATUS_TEMP
bcf STATUS,RP0 ; switch to Bank 0 - IMPORTANT
;Code starts here
btfsc INTCON,TMR0IF ; check if timer 0 interrupt
call TMR0_INT ; goto timer 0 interrupt
btfsc INTCON,INTF ; check if external interrupt
call EXT_INT ; goto external interrupt
btfsc INTCON,RBIF ; check if PORTB interrupt
call PORTB_INT ; goto PORTB interrupt
; POP implementation
POP
swapf STATUS_TEMP,W
movwf STATUS ; note that swapping nibbles is only
done
; to avoid changing
STATUS
swapf W_TEMP,f
swapf W_TEMP,W
retfie
PORTB_INT
movlw 0xff ; waste some time - needed when pp-delay
is set to 180 degrees
movwf TEMP_INT ; since both pins will change state at
the same time
PB_LOOP
decfsz TEMP_INT,f
goto PB_LOOP
movf PORTB,W ; end mismatch condition
bcf INTCON,RBIF ; clear interrupt flag
movwf TEMP_INT ; save port value
xorwf PORTB_OLD,f ; xor old value with new value
btfsc PORTB_OLD,7
call RB7_CHG ; pin changed call code
btfsc PORTB_OLD,6
call RB6_CHG ; pin changed call code
movf TEMP_INT,W
movwf PORTB_OLD ; update old value of port
; check to see if the port changed again
btfss INTCON,RBIF
return
goto PORTB_INT
EXT_INT
bsf GATE,1 ; enable gate A pulses
bcf GATE,3 ; disable gate C pulses
bcf INTCON,INTF ; clear interrupt flag
movf M_DELAY_H_PLD,W
movwf TEMP_CNT
movf STAT_H,W
andlw 0x0f
addwf TEMP_CNT,f ; calibration + master delay high part
movf M_DELAY_L_PLD,W
addwf STAT_L,W ; calibration + master delay low part
movf TEMP_CNT,W ; prepare to send to shift register
btfsc STATUS,0 ; used to test for overflow
incf TEMP_CNT,W ; overflow occured, increment high part
call READ
movf M_DELAY_L_PLD,W
addwf STAT_L,W ; calibration + master delay low part
call READ
bcf PORTA,3
bsf PORTA,3 ; strobe pin to load Master counter
return
TMR0_INT
bcf INTCON,TMR0IF ; clear interrupt flag
comf FLAG,f ; toggle flag
movlw .225
movwf TMR0 ; load timer
; Gate signals
movf FLAG,W
andwf GATE,W
movwf PORTB
return
Page 3
 SW0000_B
RB7_CHG
btfss TEMP_INT,7
return ; pin is low, do nothing
bcf GATE,2 ; disable gate B pulses
bsf GATE,3 ; enable gate C pulses
movf PP_DELAY_H_PLD,W
call READ
movf PP_DELAY_L_PLD,W
call READ
bcf PORTC,7
bsf PORTC,7 ; strobe pin to load PP counter 2
return
RB6_CHG
btfss TEMP_INT,6
return ; pin is low, do nothing
bcf GATE,1 ; disable gate A pulses
bsf GATE,2 ; enable gate B pulses
movf PP_DELAY_H_PLD,W
call READ
movf PP_DELAY_L_PLD,W
call READ
bcf PORTA,5
bsf PORTA,5 ; strobe pin to load PP counter 1
return
;********************************************************************************************
; MAIN PROGRAM
;********************************************************************************************
MAIN
; Setup PORTA
clrf PORTA ; clear output data latches
bsf STATUS,RP0 ; switch to bank 1
movlw 0x06
movwf ADCON1 ; configure pins as digital pins
movlw B'00010000'
movwf TRISA ; set RA4 as input, all others to
outputs
bcf STATUS,RP0 ; switch to bank 0
bcf PORTA,0 ; chip select for shift register
is active high
; (register will
parallel load when disabled)
bsf PORTA,1 ; chip select for A/D is active
low
bcf PORTA,2 ; load for display driver is
active high
bsf PORTA,3 ; load for Master Counter is
active low
bsf PORTA,5 ; load for PP Counter 1 is
active low
; Setup PORTB
clrf PORTB ; clear output data latches
bsf STATUS,RP0 ; switch to bank 1
movlw B'11000001'
movwf TRISB ; RB0 input, RB1-5 outputs, RB6-7 inputs
bcf STATUS,RP0 ; switch to bank 0
bsf PORTB,1 ; allow SCR triggering
bsf PORTB,2 ; allow SCR triggering
bsf PORTB,3 ; allow SCR triggering
; Setup PORTC
clrf PORTB ; clear output data latches
bsf STATUS,RP0 ; switch to bank 1
movlw B'01010000'
movwf TRISC ; RC6, RC4 inputs, all others outputs
bcf STATUS,RP0 ; switch to bank 0
bsf PORTC,7 ; load for PP Counter 2 is
active low
; Setup SPI port
bsf SSPCON,SSPEN ; enable synchronous serial port
bcf SSPCON,SSPM0 ; set as SPI master with clock = Fosc/4
Page 4
 SW0000_B
bcf SSPCON,SSPM1
bcf SSPCON,SSPM2
bcf SSPCON,SSPM3
bsf SSPCON,CKP ; clock polarity - idle state is
high
bsf STATUS,RP0 ; switch to bank 1
bcf TRISC,SDO ; SDO must be set as output
bcf TRISC,SCK ; SCK must be set as output
bcf SSPSTAT,SMP ; sample data at middle of data
out
bcf SSPSTAT,CKE ; clock edge - data xmit on
rising edge of SCK
bcf STATUS,RP0 ; switch to bank 0
bcf PORTC,SDO ; set SDO to 0
; Setup PWM module
bsf STATUS,RP0 ; switch to bank 1
movlw .19
movwf PR2 ; set the PWM period (freq =
200kHz for 16MHz Xtal)
bcf STATUS,RP0 ; switch to bank 0
movlw B'00000101'
movwf CCPR1L ; set the PWM duty cycle to 50%
bsf STATUS,RP0 ; switch to bank 1
bcf TRISC,2 ; set CCP1 pin as an output
bcf STATUS,RP0 ; switch to bank 0
movlw B'00000100'
movwf T2CON ; enable Timer 2
movlw B'00001100'
movwf CCP1CON ; set PWM mode
; Configure LED driver
movlw 0x09
call READ
movlw 0xff
call READ
bsf PORTA,2
bcf PORTA,2 ;set decode mode
movlw 0x0a
call READ
movlw 0x0f
call READ
bsf PORTA,2
bcf PORTA,2 ;set intensity to max
movlw 0x0b
call READ
movlw 0x07
call READ
bsf PORTA,2
bcf PORTA,2 ;set scan limit (scan all
digits)
movlw 0x0c
call READ
movlw 0x01
call READ
bsf PORTA,2
bcf PORTA,2 ;set shutdown to normal
; Setup Timer 0
bsf STATUS,RP0 ; switch to bank 1
bcf OPTION,T0CS ; set as timer operation
bcf STATUS,RP0 ; switch to bank 0
clrf TMR0 ; reset timer register
; Setup Interrupts
bsf STATUS,RP0 ; switch to bank 1
bsf OPTION,INTEDG ; positive edge triggered external
interrupt
bcf STATUS,RP0 ; switch to bank 0
bsf INTCON,INTE ; enable external interrupt
bsf INTCON,RBIE ; enable PORTB interrupt on change
bsf INTCON,TMR0IE ; enable Timer 0 interrupt
bsf INTCON,GIE ; enable interrupts
; Init some registers
clrf M_DELAY_H
Page 5
 SW0000_B
clrf PP_DELAY_H
clrf GATE
call READ_SR ; read shift register to initialize STAT
; word - basically will
make STAT_OLD=STAT
movlw .1
movwf M_DELAY_L ; start with 1 in Master delay (steps,
not time)
movlw .60
movwf PP_DELAY_L ; start with 60 in P-P delay (steps, not
time)
movlw LED_RATE
movwf LED_UPDATE ; initialize display update register

; Start main loop

LOOP
; Decipher encoder - see if need to increase or decrease delay
; Basically a brute force approach - just test the reasonable combinations
; Assumes that scanning of the encoder is fast enough
call READ_SR ; read shift register
movf STAT_H,W ; assemble word to see how to update
delays
movwf TEMP
rrf TEMP,f ; rotate right and place result
in TEMP
rrf TEMP,W ; rotate right and place result
in W
andlw B'00110000' ; clear bits
movwf TEMP ; save byte
movf STAT_H_OLD,W
andlw B'11000000' ; clear bits
iorwf TEMP,f ; OR to form final byte store in TEMP
movf TEMP,W
sublw B'00010000'
btfsc STATUS,2 ; check zero flag
goto INCREASE
movf TEMP,W
sublw B'00100000'
btfsc STATUS,2 ; check zero flag
goto DECREASE
movf TEMP,W
sublw B'01110000'
btfsc STATUS,2 ; check zero flag
goto INCREASE
movf TEMP,W
sublw B'01000000'
btfsc STATUS,2 ; check zero flag
goto DECREASE
movf TEMP,W
sublw B'11100000'
btfsc STATUS,2 ; check zero flag
goto INCREASE
movf TEMP,W
sublw B'11010000'
btfsc STATUS,2 ; check zero flag
goto DECREASE
movf TEMP,W
sublw B'10000000'
btfsc STATUS,2 ; check zero flag
goto INCREASE
movf TEMP,W
sublw B'10110000'
btfsc STATUS,2 ; check zero flag
goto DECREASE
goto DO_NEXT
DECREASE
movlw 1 ; if bit 4 clear then dec fine
btfsc STAT_H,4
movlw .20 ; if bit 4 set then dec coarse
btfss STAT_H,5 ; if bit 5 set then dec master
goto DEC_P_TO_P
subwf M_DELAY_L,f ; decrement
btfsc STATUS,0 ; skip if no borrow
Page 6
 SW0000_B
goto DO_NEXT
decf M_DELAY_H,f ; borrow occurred decrement high part
btfss M_DELAY_H,7
goto DO_NEXT
clrf M_DELAY_H
clrf M_DELAY_L
goto DO_NEXT
DEC_P_TO_P
subwf PP_DELAY_L,f ; decrement p-to-p delay
btfsc STATUS,0 ; skip if no borrow
goto DO_NEXT
decf PP_DELAY_H,f ; borrow occurred dec high part
btfss PP_DELAY_H,7
goto DO_NEXT
clrf PP_DELAY_H
clrf PP_DELAY_L
goto DO_NEXT
INCREASE
movlw 1 ; if bit 4 clear then inc fine
btfsc STAT_H,4
movlw .20 ; if bit 4 set then inc coarse
btfss STAT_H,5 ; if bit 5 set then inc master
goto INC_P_TO_P
addwf M_DELAY_L,f ; increment
btfss STATUS,0 ; skip if no carry
goto DO_NEXT
incf M_DELAY_H,f ; carry occurred increment high part
btfss M_DELAY_H,4 ; test if delay > 4095
goto DO_NEXT
movlw B'00001111'
movwf M_DELAY_H
movlw 0xff
movwf M_DELAY_L ; reset delay to 4095
goto DO_NEXT
INC_P_TO_P
addwf PP_DELAY_L,f ; decrement
btfss STATUS,0 ; skip if no carry
goto DO_NEXT
incf PP_DELAY_H,f ; carry occurred increment high part
btfss PP_DELAY_H,4 ; test if delay > 4095
goto DO_NEXT
movlw B'00001111'
movwf PP_DELAY_H
movlw 0xff
movwf PP_DELAY_L ; reset delay to 4095
goto DO_NEXT
DO_NEXT
; Now check if need A/D data. If so, get value.
btfsc PORTC,6 ; check Analog/Digital control bit
goto DO_NEXT_2 ; if digital, just skip (already have
delays)
call READ_AD ; read A/D
movf AD_0_H,W
movwf M_DELAY_H
movf AD_0_L,W
movwf M_DELAY_L ; replace the delay values with the ones
; obtained from the A/D
DO_NEXT_2
; Until now delays are enforced to the max limit, now check the min limit
movf M_DELAY_H,f
btfss STATUS,2
goto DO_NEXT_3 ; high part is not zero, so ok
movf M_DELAY_L,f
btfsc STATUS,2
incf M_DELAY_L,f ; delay was zero, so set to 1 again
DO_NEXT_3
movf PP_DELAY_H,f
btfss STATUS,2
goto DO_NEXT_4 ; high part is not zero, so ok
movlw .60
subwf PP_DELAY_L,W
movlw .60
btfss STATUS,0 ; check if result is positive or zero
movwf PP_DELAY_L ; result was negative, so reset to 20
Page 7
 SW0000_B
DO_NEXT_4
bcf INTCON,GIE ; disable interrupts - this is done to safely update the
delay values
movf M_DELAY_H,W ; move proper value to the register used
to load the counter
movwf M_DELAY_H_PLD
movf M_DELAY_L,W ; move proper value to the register used
to load the counter
movwf M_DELAY_L_PLD
movf PP_DELAY_H,W ; move proper value to the register used
to load the counter
movwf PP_DELAY_H_PLD
movf PP_DELAY_L,W ; move proper value to the register used
to load the counter
movwf PP_DELAY_L_PLD
bsf INTCON,GIE ; enable interrupts
; Check to see if time to update LED displays
btfsc PORTC,6 ; check Analog/Digital control bit
goto DO_NEXT_5 ; if digital, just skip (fast update
rate)
decf LED_UPDATE_L,f ; decrement update register low part
btfss STATUS,2
goto DO_NEXT_6
decf LED_UPDATE,f ; decrement update register
btfss STATUS,2
goto DO_NEXT_6 ; not time to update,
loop
movlw LED_RATE ; time to update
movwf LED_UPDATE ; reload the update register
DO_NEXT_5
; Convert Master delay and display it
movf M_DELAY_H,W
movwf NUM_H
movf M_DELAY_L,W
movwf NUM_L
; Convert the value to BCD result is in TENK, THOU, HUND, TENS, ONES
; Notice that this cannot be in a subroutine (CALL) since interrupt timing is affected
movf NUM_H,W ; multiply high part by 5
addwf NUM_H,f
addwf NUM_H,f
addwf NUM_H,f
addwf NUM_H,f
movf NUM_L,W ; multiply low part by 5 and check for
overflow
addwf NUM_L,f
btfsc STATUS,0
incf NUM_H,f
addwf NUM_L,f
btfsc STATUS,0
incf NUM_H,f
addwf NUM_L,f
btfsc STATUS,0
incf NUM_H,f
addwf NUM_L,f
btfsc STATUS,0
incf NUM_H,f
; so up to here we have the number of pulses times five, therefore we have a microsecond
; representation of the delay
swapf NUM_H,w
andlw 0x0f
addlw 0xf0
movwf THOU
addwf THOU,f
addlw 0xe2
movwf HUND
addlw 0x32
movwf ONES
movf NUM_H,w
andlw 0x0f
addwf HUND,f
addwf HUND,f
addwf ONES,f
addlw 0xe9
movwf TENS
Page 8
 SW0000_B
addwf TENS,f
addwf TENS,f
swapf NUM_L,w
andlw 0x0f
addwf TENS,f
addwf ONES,f
rlf TENS,f
rlf ONES,f
comf ONES,f
rlf ONES,f
movf NUM_L,w
andlw 0x0f
addwf ONES,f
rlf THOU,f
movlw 0x07
movwf TENK
movlw 0x0a
Lb1_M:
addwf ONES,f
decf TENS,f
btfss 3,0
goto Lb1_M
Lb2_M:
addwf TENS,f
decf HUND,f
btfss 3,0
goto Lb2_M
Lb3_M:
addwf HUND,f
decf THOU,f
btfss 3,0
goto Lb3_M
Lb4_M:
addwf THOU,f
decf TENK,f
btfss 3,0
goto Lb4_M
movf TENK,W ; move register to activate Zero flag
btfss STATUS,2
goto DISP_SHIFT_M
bsf THOU,7
goto DISP_FINAL_M
DISP_SHIFT_M
movf TENS,W
movwf ONES
movf HUND,W
movwf TENS
movf THOU,W
movwf HUND
movf TENK,W
movwf THOU
bsf HUND,7
DISP_FINAL_M
movlw 0x05 ; refers to the left display
movwf TEMP ; (start at digit 5)
call DISPLAY

DO_NEXT_6
; Convert P-P delay and display it
movf PP_DELAY_H,W
movwf NUM_H
movf PP_DELAY_L,W
movwf NUM_L
; Convert the value to BCD result is in TENK, THOU, HUND, TENS, ONES
; Notice that this cannot be in a subroutine (CALL) since interrupt timing is affected
movf NUM_H,W ; multiply high part by 5
addwf NUM_H,f
Page 9
 SW0000_B
addwf NUM_H,f
addwf NUM_H,f
addwf NUM_H,f
movf NUM_L,W ; multiply low part by 5 and check for
overflow
addwf NUM_L,f
btfsc STATUS,0
incf NUM_H,f
addwf NUM_L,f
btfsc STATUS,0
incf NUM_H,f
addwf NUM_L,f
btfsc STATUS,0
incf NUM_H,f
addwf NUM_L,f
btfsc STATUS,0
incf NUM_H,f
; so up to here we have the number of pulses times five, therefore we have a microsecond
; representation of the delay
swapf NUM_H,w
andlw 0x0f
addlw 0xf0
movwf THOU
addwf THOU,f
addlw 0xe2
movwf HUND
addlw 0x32
movwf ONES
movf NUM_H,w
andlw 0x0f
addwf HUND,f
addwf HUND,f
addwf ONES,f
addlw 0xe9
movwf TENS
addwf TENS,f
addwf TENS,f
swapf NUM_L,w
andlw 0x0f
addwf TENS,f
addwf ONES,f
rlf TENS,f
rlf ONES,f
comf ONES,f
rlf ONES,f
movf NUM_L,w
andlw 0x0f
addwf ONES,f
rlf THOU,f
movlw 0x07
movwf TENK
movlw 0x0a
Lb1_PP:
addwf ONES,f
decf TENS,f
btfss 3,0
goto Lb1_PP
Lb2_PP:
addwf TENS,f
decf HUND,f
btfss 3,0
goto Lb2_PP
Lb3_PP:
addwf HUND,f
decf THOU,f
btfss 3,0
goto Lb3_PP
Lb4_PP:
addwf THOU,f
decf TENK,f
Page 10
 SW0000_B
btfss 3,0
goto Lb4_PP
movf TENK,W ; move register to activate Zero flag
btfss STATUS,2
goto DISP_SHIFT_PP
bsf THOU,7
goto DISP_FINAL_PP
DISP_SHIFT_PP
movf TENS,W
movwf ONES
movf HUND,W
movwf TENS
movf THOU,W
movwf HUND
movf TENK,W
movwf THOU
bsf HUND,7
DISP_FINAL_PP
movlw 0x01 ; refers to the right display
movwf TEMP ; (start at digit 1)
call DISPLAY

goto LOOP
;********************************************************************************************
; Read shift register subroutine
;********************************************************************************************
READ_SR
bcf INTCON,GIE ; disable interrupts
movf STAT_L,W
movwf STAT_L_OLD
movf STAT_H,W
movwf STAT_H_OLD ; save old status word
bsf PORTA,0
bcf PORTA,0 ; strobe chip select pin to load new
data
bsf PORTA,0 ; now put register in shift mode
call READ
movwf STAT_H
call READ
movwf STAT_L ; read STATUS value and save
bcf PORTA,0 ; disable shift register
bsf INTCON,GIE ; enable interrupts
return
;********************************************************************************************
; Read from SPI device subroutine
;
; Note: This code is critical regarding interrupts. If not disabled, an interrupt during
; an execution of a transfer will have unpredictable results
;********************************************************************************************
READ
movwf SSPBUF ; write to serial buffer (assume value
in W)
bsf STATUS,RP0 ; switch to bank 1
WAIT btfss SSPSTAT,BF ; wait until receive buffer is full
goto WAIT
bcf STATUS,RP0 ; switch to bank 0
movf SSPBUF,W ; read buffer (to clear BF flag)
; read value is returned
in W
return
;********************************************************************************************
; Read A/D subroutine
;********************************************************************************************
READ_AD
bcf INTCON,GIE ; disable interrupts
bcf PORTA,1 ; select A/D
movlw 0x01
call READ ; send start bit
Page 11
 SW0000_B
movlw B'10100000' ; select channel 0
call READ
movwf AD_0_H ; receive high byte
call READ
movwf AD_0_L ; receive low byte
bsf PORTA,1 ; deselect A/D
movlw B'00001111'
andwf AD_0_H,f ; clear upper bits channel 0
bsf INTCON,GIE ; enable interrupts
return
;********************************************************************************************
; DISPLAY VALUE SUBROUTINE
;
; This subroutine makes 4 SPI transfers. Perhaps this is too much wait time for interrupts
; so just enable interrupts between transfers to reduce waiting time for an interrupt.
;********************************************************************************************
DISPLAY
bcf INTCON,GIE ; disable interrupts
movf TEMP,W ; temp has the starting digit
incf TEMP,f
call READ ; send digit byte
movf THOU,W
call READ ; send data byte
bsf PORTA,2
bcf PORTA,2 ; write thousands
bsf INTCON,GIE ; enable interrupts
movf TEMP,W
incf TEMP,f
bcf INTCON,GIE ; disable interrupts
call READ ; send digit byte
movf HUND,W
call READ ; send data byte
bsf PORTA,2
bcf PORTA,2 ; write hundreds
bsf INTCON,GIE ; enable interrupts
movf TEMP,W
incf TEMP,f
bcf INTCON,GIE ; disable interrupts
call READ ; send digit byte
movf TENS,W
call READ ; send data byte
bsf PORTA,2
bcf PORTA,2 ; write tenths
bsf INTCON,GIE ; enable interrupts
movf TEMP,W
incf TEMP,f
bcf INTCON,GIE ; disable interrupts
call READ ; send digit byte
movf ONES,W
call READ ; send data byte
bsf PORTA,2
bcf PORTA,2 ; write units
bsf INTCON,GIE ; enable interrupts
return
end

Page 12
 README
SCR Box Microcontroller code.
Intended for the Microchip MPLAB IDE.
See SW0001 for the CPLD code (schematic).
Known Issues:

1. Code implemented as subroutines and the actual CALL implementation seems to

affect Interrupt handling. Changed to
explicit code to avoid the problem.

Project File: SW0000_B.mcp

Main File: SW0000_B.asm
To compile, open the Project file. Make sure program the Configuration Bits;
Oscillator
should be set to HS and Watchdog Timer to OFF.

The microcontroller is used to do the following tasks:

1. Read configuration data (calibration delay, analog/digital control,
Master/P-P encoder, coarse/fine encoder, etc.)
2. Read encoder and update the delay values (read the A/D if necessary).
3. Generate the HF clock for the time-based design.
4. Generate the SCR triggering clock.
5. Display the Master and P-P Delay values (send data to LED driver).
Implies conversion of binary data to BCD values.
6. Load the delay counters (send data to timing CPLD).
7. Create gating signals for SCR triggering.

************************************************************************************
********
NOTE: The operation of the uC is dependent on the actual implementation of the
Timing block.
See SW0001 for the CPLD implementation
************************************************************************************
********
The software uses the PWM module (HF clock), a Timer (SCR triggering clock) and
Interrupts
(Gate signals) and a Main Loop.

The Main Loop essentially reads the configuration data, and updates the delay values
and displays them.

The Timer is also used in Interrupt mode and is nominally a 10 us period clock.
This clock is not fixed because it has a lower priority and can be interrupted.

Interrupts check for the status of the counters and determines the appropriate time
to load the counters with updated values.
The gating signals are such that when the corresponding counter is done, the SCR
will automatically see a trigger pulse. After a response time, the uC is able to
respond to that even and starts the pulsing process for the SCR trigger. In this
sense the first SCR trigger pulse will be longer than any subsequent pulse, but will
be at the desired time (within timing precision).
Interrupt processing is disabled whenever an SPI transfer is made in the main loop,
because the Interrupt code makes use of SPI transfers. Although this makes the
Interrupt processing not instantaneuos, so far it has been observed to work
satisfactorily.

An interaction between Interrupt processing and subroutines was observed. It was

evident when a large number was displayed, which meant the Binary to BCD code was
Page 1
 README
taking extra time to finish which affected the timing process (i.e., SCRs
misfiring).

Page 2
 1 2 3 4 5 6 7 8
SR16CE
SERIAL_IN SLI counter_13 AND2B1
VCC
DATA(15:0) DATA(12:0) FDP TRIG_EDGE
Q[15:0] DATA(12:0) TC
INV
PRE FD
CE LD_MC LOAD
D Q
SCK C CE D Q
CLR
A HF_CK CLK A
INT_TRIG
C
HF_CK
GND C

GND

counter_12
DATA(11:0) FDP
DATA(11:0) TC
INV
PRE
LD_PPC1 LOAD
D Q
See the notes for a design explanation CE

CLK
C
GND

TRIG INT_TRIG
B counter_12 B
DATA(11:0) TC
FDP AND2B1
VCC
INV
PRE
LD_PPC2 LOAD FDC
D Q
CE
INH_TRIG
D Q
CLK
C
GND
C
CLR
AND2B1
EN_MC

EN_PPC1

EN_PPC2

SCR_A
GATE_A EN_MC AND3
AND3B2 AND2
EN_PPC1

EN_PPC2
C SCR_B OR2B1
C
GATE_B
AND3B2 AND2

EN_MC

SCR_C
GATE_C
EN_PPC2 AND3B1 AND2
EN_PPC1

EN_MC
MASTER_EN

CPLD EN_MC

EN_PPC1
AND2B1
EN_PPC2 FD
Implementation INH_TRIG EN_PPC2
D D Q D
TRIG_EDGE
AND5
Top Level HF_CK
C

OR2

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

VCC

flipflop
SET T_OUT
DATA(11:0)
T_IN
A DATA(0) A
D

LOAD AND2B1 LOAD

INV
CLK
CLK

Down Counter implementation

flipflop
FD SET T_OUT
Note that the counter RESET sets all FFs to 1
CE D Q T_IN
DATA(1)
D

C LOAD

CLK

flipflop
SET T_OUT

T_IN
DATA(2)
D

LOAD

CLK
FD
D Q

B flipflop B
C
INV
SET T_OUT

T_IN
DATA(3)
D

LOAD
This FF is used to extend and synch. the auto reset pulse of the counter
CLK

TC
INV

This is critical, otherwise the reset pulse is too small and the implementation had trouble with it
flipflop
SET T_OUT
flipflop Seems like by locking the pins, the pulse was missed
SET T_OUT
T_IN
DATA(4) T_IN
D
DATA(11)
D
LOAD

LOAD
CLK
CLK

flipflop
flipflop SET T_OUT

SET T_OUT T_IN

DATA(10)
T_IN D
C DATA(5) C
D LOAD

LOAD CLK

CLK

flipflop
SET T_OUT
flipflop
T_IN
SET T_OUT
DATA(9)
D
T_IN
DATA(6) LOAD
D

CLK
LOAD Counter 12
CLK

flipflop Implementation
flipflop SET T_OUT

SET T_OUT T_IN

DATA(8)
T_IN D
DATA(7)
D LOAD

LOAD CLK

CLK

D D

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

VCC

flipflop
SET T_OUT
DATA(12:0)
T_IN
A DATA(0) A
D

LOAD AND2B1 LOAD

INV
CLK
CLK

Down Counter implementation

flipflop
FD SET T_OUT
Note that the counter RESET sets all FFs to 1
CE D Q T_IN
DATA(1)
D

C LOAD

CLK

flipflop
SET T_OUT

T_IN
DATA(2)
D

LOAD

CLK
FD
D Q

B flipflop B
C
INV
SET T_OUT

T_IN
DATA(3) flipflop
D
SET T_OUT
LOAD
This FF is used to extend and synch. the auto reset pulse of the counter
T_IN
CLK
DATA(12)
D

LOAD
TC
INV
CLK

This is critical, otherwise the reset pulse is too small and the implementation had trouble with it
flipflop
SET T_OUT
flipflop Seems like by locking the pins, the pulse was missed
SET T_OUT
T_IN
DATA(4) T_IN
D
DATA(11)
D
LOAD

LOAD
CLK
CLK

flipflop
flipflop SET T_OUT

SET T_OUT T_IN

DATA(10)
T_IN D
C DATA(5) C
D LOAD

LOAD CLK

CLK

flipflop
SET T_OUT
flipflop
T_IN
SET T_OUT
DATA(9)
D
T_IN
DATA(6) LOAD
D

CLK
LOAD Counter 13
CLK

flipflop Implementation
flipflop SET T_OUT

SET T_OUT T_IN

DATA(8)
T_IN D
DATA(7)
D LOAD

LOAD CLK

CLK

D D

1 2 3 4 5 6 7 8
 1 2 3 4 5 6 7 8

A A

SET

XOR2

FDP
M2_1 T_IN
D0 PRE
O
T_OUT
D Q
D1
D AND2B1
S0
C This gate generates the enable (T) signal for the next stage of the counter
LOAD

B B
CLK
OR2

The FF is optimized to work in a down counter situation

C C

Custom FlipFlop
Implementation

D D

1 2 3 4 5 6 7 8
 README.txt
SCR Box CPLD code (schematic).
Intended for the Xilinx ISE.
See SW0000 for the Microcontroller code.
Known Issues:

1. The Trigger de-glitching implementation limits the range of the Main and
Phase-to-Phase counters.

Project File: Timing.npl

Main Files: Timing.sch - Main Schematic
FlipFlop.sch, FlipFlop.sym - Custom FlipFlop
Counter_12.sch, Counter_12.sym - Custom Down Counter 12 bits
Counter_13.sch, Counter_13.sym - Custom Down Counter 13 bits
Pin_Ass.ucf - CPLD Pin assigment

To compile, open the Project file. Select the timing (timing.sch) in the
module view window (it is an element under xc9572-15pc44 - XST VHDL). In the
process view window run Synthesize, Implement Design and Generate Programming
File.

***********************
*
* Main Schematic:
*
************************

A serial-to-parallel shift register is used to interface the CPLD with the uC.
This transfers the value to be loaded into a particular counter (Master,
Phaset-to-Phase 1 or Phase-to-Phase 2). An external signal (LD_MC, LD_PPC1,
LD_PPC2) coming from the uC will load the counter with the value placed on the
register. Notice that the uC is responsible to load the counters at the
correct times.

The main trigger signal (i.e., the AC zero crossing) is deglitched first
before going into the trigger input of the main circuit. Deglitching is
required since noise on the AC signal creates additional transitions on the
TRIG signal (in particular when using the External Trigger of the SCR Box) and
is implemented in the following way:

- In the initial state, a positive edge on TRIG will pass directly to the
internal trigger circuit.
- This same edge enables the Inhibit Trigger FF. Any subsequent edges on TRIG
will not be seen in INT_TRIG. A combination of the Counter enabled signals
(EN_MC, EN_PPC1, EN_PPC2) can disable the signal that activates the FF. This
combination follows from a timing diagrams that shows that if the enable
signals are in that particular state, no trigger inhibit is required.
- The Inhibit Trigger FF is reset to it's normal state under anu of the
following conditions:
1. The enable signals are in the inactive state, triggering is
inhibited and a positive edge in TRIG is detected.
This just means that the Timming process is inactive but triggering
is inhibited, therefore the trigger process
cannot start. This is not a normal operating state, but occurs
when powering up the SCR Box.
2. A positive edge on EN_PPC2 is detected (i.e., PPC2 returns to it's
inactive state).
Once a positive edge on INT_TRIG is detected, the trigger process stars and
follows the following steps:
1. The EN_MC FF is reset (set to zero). This enables the Master Counter (MC).
2. When MC is done, generates a signal that sets the EN_MC FF. This therefore
disables the counting process on MC. At the same time a positive edge happens
Page 1
 README.txt
on EN_MC which resets the EN_PPC1 FF.
3. EN_PPC1 being low enables PPC1.
4. PPC1 is done and sets the EN_PPC1 FF and sets the EN_PPC2 FF.
5. EN_PPC2 being low enables PPC2.
6. PPC2 is done and sets the EN_PPC2 FF.

Notice that under normal 3 phase operation two counters can be active at the
same time since INT_TRIG occurs asynchronously.

The design also implements the SCR trigger pulses. When EN_MC goes HIGH and
while EN_PPC1 stays low the gating pulses coming from the uC are transfered
directly to the SCR A gate drive and similarly for the other SCRs, except that
SCR C requires EN_PPC2 HIGH and EN_PPC1 HIGH.
The gating pulses are such that whenever the counter is done, the SCR will
automatically fire and then, when the uC is able to respond to the event,
pulsing will occur.
Notice that the pulse trains for SCR firing generated by the circuit do not
overlap.
***************************************
*
* Counter_12 and Counter_13 Schematics
*
***************************************
Both schematics implement the same circuit in 12 and 13 bits respectively. 13
bits are required since the Calibration Delay is added to the Master Delay and
this is the value loaded into the Master Counter.

The counters are simply Presetable down counters with enable and an auto reset
(all ones) when the count goes to all zeros. A counter done signal is the
output of the counter. The autoreset feature uses an extra FF to extend and
synchronize the reset pulse. This was required to avoid violating timing
constraints of the CPLD.
The counters use custom T type FFs.

***************************
*
* FlipFlop Schematic:
*
***************************
The FF can be asynch. cleared and asynch. loaded. Asynch. loading is
implemented by the MUX. Otherwise it operates as a T FF. The FF contains
logic that allows cascading of FFs to implement a down counter. Basically the
output will be HIGH if the FF is LOW and the cascading input is HIGH.

******************************************************************************
**************
NOTE: The operation of the CPLD is dependent on the actual implementation of
the Microcontroller
interrupt handling and Gating pulse generation.
See SW0000 for the uC implementation
******************************************************************************
**************

Page 2
 PJ0004 Rev B
SCR Boxes for ECE469

Drawing Description PDF EPS

DR0001 Heat Sink, Wakefield 403K pdf

DR0004 SCR and Heat Sink Assembly pdf

DR0005 Back Panel for box pdf

DR0006 Box assembly with heat sink and boards pdf

DR0016 Bottom plate of box pdf

DR0019 Silkscreen for Front of Box pdf eps

DR0020 Front Panel of Box pdf

 2 1

n.375

1.000
B B

.000

1.000

NOTE: HORIZONTAL DIMENSIONS ARE

REFERENCE. HOLES ARE ON THE CENTERLINE.
2.375

.000

2.375
DE-BURR ALL HOLES, FRONT AND BACK SIDES.

DRAWN
Jonathan Kimball 7/29/2003 University of Illinois at Urbana-Champaign
CHECKED
Zakdy Sorchini 7/29/2003 TITLE
A QA A

MFG
Heat Sink, Wakefield 403K
APPROVED
SIZE DWG NO REV

A PJ0004-DR0001 B
SCALE
SHEET 1 OF 1
2 1
 4 3 2 1

D D

SCR, 10RIA40

Thermal Washer
C C

O-ring

O-ring

Heat Sink

Thermal Washer

B B
Steel Washer

1/4-28 Nut

DRAWN
Jonathan Kimball 7/29/2003 University of Illinois at Urbana-Champaign
CHECKED
Yongxiang Chen 9/5/2003 TITLE
A QA A

COPYRIGHT 2003 BY JONATHAN KIMBALL. ALL RIGHTS MFG

RESERVED. MAY BE DUPLICATED FOR EDUCATIONAL
SCR and Heat Sink Assembly
USE ONLY SO LONG AS THIS NOTICE REMAINS INTACT. APPROVED
SIZE DWG NO REV

C PJ0004-DR0004 B
SCALE
SHEET 1 OF 1
4 3 2 1
 4 3 2 1

D D

1.000
1.125

2.375

4.000

5.250
5.375

5.823
6.003
6.208

6.688

7.063
7.243
.000

2.438 .000

.500
R.125

1.250
1.000
1.572

.500
C 2.072 C

.000
2.692

3.312

A
n.250
n.150 4.000
n.213 2 PLCS
4 PLCS 4.375
SEE NOTE 1

.328
7.938

3.500

1.750

.875

.000
.250

B R.164 B

DETAIL A
NOTES: SCALE 2 : 1

1. Install PEM S-832-2-ZI or equivalent protruding near side at locations shown.

2. Vent pattern is symmetric top to bottom.

3. Corners on smaller rectangular opening must be square.

4. After machining, paint standard black. Material: standard .062 aluminum.

DRAWN
Jonathan Kimball 6/10/2003 University of Illinois at Urbana-Champaign
CHECKED
Rob Balog 7/7/2003 TITLE
A QA A
MFG
Back Panel of box
APPROVED
SIZE DWG NO REV

C PJ0004-DR0005 B
SCALE
SHEET 1 OF 1
4 3 2 1
 4 3 2 1

7.250

.750

.000
D D

8.750

2X n.166 THRU
2 PLCS

7.070

C C

NOTES:

1. Install PEM SO-632-16-ZI or equivalent protruding

B far side where shown. B

2. After machining operations, paint ASA 61 Grey.

1.570
3. Material: standard steel.
4X n.213 THRU
4 PLCS 4. This drawing shows additional machining to bottom
SEE NOTE 1
only. Top of box to be standard machining, painted to
match.
.000

COPYRIGHT 2003 BY JONATHAN KIMBALL. ALL RIGHTS DRAWN

RESERVED. MAY BE DUPLICATED FOR EDUCATIONAL USE Jonathan Kimball 6/18/2003 University of Illinois at Urbana-Champaign
ONLY SO LONG AS THIS NOTICE REMAINS INTACT. CHECKED
Rob Balog 7/7/2003 TITLE
A QA A
MFG
Bottom Plate for Box
APPROVED
SIZE DWG NO REV

C PJ0004-DR0016 B
SCALE
SHEET 1 OF 1
4 3 2 1
 4 3 2 1

1.000

1.950

3.075

4.200

4.665
4.869

6.931
7.115
.000
D D

.000 .000

.444
.624

1.250 1.256
1.350 1.444
n.250 n.375
6 PLCS
R.063 2.256
n.213
2.575
A 4 PLCS 2.624

3.000
B SEE NOTE 1
C C
3.125

3.875
4.125

NOTES:

1. INSTALL PEM BSO-632-10-ZI OR EQUIVALENT

.000

1.250

1.750

2.600

3.000

4.150

5.400

6.650
PROTRUDING FAR SIDE AT LOCATIONS SHOWN.

2. AFTER MACHINING OPERATIONS, PAINT

B CONTEMPRA GREY. B

3. ON RECTANGULAR OPENINGS, MAX RADIUS IS

R.195 .250 SHOWN, RIGHT ANGLES ALLOWED.

4. MATERIAL: STANDARD .062 ALUMINUM.

.328
.355

DRAWN
R.164
Jonathan Kimball 7/7/2003 University of Illinois at Urbana-Champaign
CHECKED
Rob Balog 7/7/2003 TITLE
A DETAIL B QA A
DETAIL A SCALE 4 : 1 MFG
SCALE 4 : 1 6 PLCS Front Panel of Box
APPROVED
SIZE DWG NO REV

C PJ0004-DR0020 A
SCALE
SHEET 1 OF 1
4 3 2 1
SCR Box Enclosure Revised: Thursday, September 4, 2003

University of Illinois at Urbana-Champaign

1406 W. Green St.
Urbana, IL 61801

Bill Of Materials September 30,2003 3:21:41 pm

Item Quantity Description Mfg Mfg PN Cost Ea Ext Cost

1 1 Enclosure, customized Hammond 1458E5* $ 58.61 $ 58.61

2 1 Power Inlet, IEC320 Qualtek 719W-00/04 (689-3524) $ 1.87 $ 1.87
3 1 Fuse, 5x20mm, 250mA Bussmann GDB 250MA $ 1.43 $ 1.43
4 1 Power Switch, Rocker Carling RA911-VB-B-1-V (683-0114) $ 0.95 $ 0.95
5 4 Binding post, blue EF Johnson 111-0110-00 $ 0.40 $ 1.60
6 4 Binding post, orange EF Johnson 111-0106-00 $ 1.99 $ 7.96
7 6 Toggle switch, SPDT Alcoswitch MTA-106D $ 2.35 $ 14.10
8 1 LED, green Agilent HLMP3507 $ 0.23 $ 0.23
9 1 Snap mount for T-1-3/4 LED Agilent HLMP0103 $ 0.15 $ 0.15
10 1 Optical encoder with detents Grayhill 62A11-01-050S (GH3048-ND) $ 33.88 $ 33.88
11 1 Knob for 1/4" shaft Alcoswitch PKG-50B-1/4 $ 0.92 $ 0.92
12 1 BNC, panel mount Amphenol 31-221 $ 0.98 $ 0.98
13 1 Heat sink, custom drilled Wakefield 403K* (58F505) $ 12.28 $ 12.28
14 6 O-rings for 1/4" stud, Buna-N -008 McMaster-Carr 9452K16 $ 0.02 $ 0.14
15 6 Thermal pad, DO-5 Wakefield 175-6-510P (46F7886) $ 0.50 $ 3.00
16 3 SCR, 10RIA40 International Rectifier 10RIA40 (09F5025) $ 11.00 $ 33.00
17 4 Mounting feet Smith 2192 $ 0.15 $ 0.60
18 12 6-32 x 1/4" pan head screw $ 0.15 $ 1.80
19 2 6-32 Nuts $ 0.10 $ 0.20
20 4 8-32 x 3/8" pan head screw $ 0.10 $ 0.40
21 2 4-40 x 1/2" flat head screw $ 0.10 $ 0.20
22 2 4-40 Nuts with integral lock washers $ 0.10 $ 0.20
23 1 PB0009 Rev A Advanced Circuits Custom $ 33.00 $ 33.00
Item Quantity Description Mfg Mfg PN Cost Ea Ext Cost

24 1 PB0010 Rev B Advanced Circuits Custom $ 33.00 $ 33.00

Total $ 240.50
SCR Box Display Board Revised: Thursday, June 26, 2003
SK0009 Revision: 1

University of Illinois at Urbana-Champaign

1406 W. Green St.
Urbana, IL 61801

Bill Of Materials June 26,2003 8:35:06

Item Quantity Reference Part Mfg Mfg PN Cost Ea Ext Cost

1 1 C1 0.1u Kemet C322C104K5R5CA $ 0.15 $ 0.15

2 1 C2 10u Panasonic ECA-1HM100 $ 0.20 $ 0.20
3 1 J1 MTA100-6 AMP 640456-6 (571-6404566) $ 0.15 $ 0.15
4 1 R1 56k $ 0.00 $ 0.00
5 1 U1 MAX7219 Maxim MAX7219CNG (34C4018) $ 10.81 $ 10.81
6 2 U2,U3 LED_7S_4 Lumex LDQ-N516RI (67-1450-ND) $ 7.40 $ 14.80
7 1 U1 socket 24-PIN NARROW IC SOCKET MILL-MAX 110-13-324-41-001 (575-113324) $ 1.06 $ 1.06

Total $ 27.17
SCR Box Control Board Revised: Thursday, September 25, 2003
SK0010 Revision: 3

University of Illinois at Urbana-Champaign

1406 W. Green St.
Urbana, IL 61801

Bill Of Materials September 30,2003 9:53:28

Item Quantity Reference Part Mfg Mfg PN Cost Ea Ext Cost

1 1 C?? 2.2uF Kemet C330C225M5U5CA (24C0241) $ 0.70 $ 0.70

2 26 C1,C2,C3,C6,C7,C8,C11, 0.1uF Kemet C322C104K5R5CA $ 0.15 $ 3.90
C12,C14,C15,C16,C19,C21,
C23,C24,C25,C27,C28,C29,
C30,C32,C33,C34,C35,C37,
C39
3 1 C4 Do Not Stuff $ - $ -
4 1 C5 470uF Panasonic ECA-1JM471 (P5196-ND) $ 1.22 $ 1.22
5 3 C9,C10,C38 100uF Panasonic ECA-1HM101 (P5182-ND) $ 0.29 $ 0.87
6 1 C13 4.7uF Sprague 199D475X0035CA1 $ 0.26 $ 0.26
7 2 C18,C17 10pF BC Components K100J15C0GF5TL2 (BC1001CT-ND) $ 0.11 $ 0.22
8 1 C20 68pF BC Components K681J15C0GF5TL2 (BC1023CT-ND) $ 0.16 $ 0.16
9 1 C22 100pF BC Components K101J15C0GF5TL2 (BC1013CT-ND) $ 0.11 $ 0.11
10 1 C26 250pF BC Components K221J15C0GF5TL2 (BC1017CT-ND) $ 0.12 $ 0.12
11 1 C31 10uF Panasonic ECA-1HM100 (P5178-ND) $ 0.20 $ 0.20
12 1 C36 0.01uF Vishay Sprague 1C20Z5U103M050B $ 0.10 $ 0.10
13 1 C40 0.1uF 200V Kemet C330C104K2R5CA (95F4961) $ 0.96 $ 0.96
14 1 C41 Do Not Stuff Kemet $ - $ -
15 6 D1,D2,D3,D9,D10,D11 1N4148 IR 1N4148 $ 0.10 $ 0.60
16 4 D4,D5,D12,D13 1N4002 ON 1N4002 $ 0.15 $ 0.60
17 3 D6,D7,D8 1N4744A ON 1N4744A $ 0.18 $ 0.54
18 2 D17,D14 1N5819 $ 0.38 $ 0.76
19 1 D15 1N4004 ON 1N4004 $ 0.10 $ 0.10
Item Quantity Reference Part Mfg Mfg PN Cost Ea Ext Cost

20 1 D16 1N4744 $ 0.18 $ 0.18

21 1 D18 1N4733 $ 0.15 $ 0.15
22 1 ISO1 HCPL2611 Agilent HCPL-2611 (06F5452) $ 1.36 $ 1.36
23 2 JP2,JP1 JUMPER2 FCI 54102-S08-02 (22C2546) $ 0.13 $ 0.26
24 1 J1 MTA156-3 AMP 640445-3 (571-6404453) $ 0.10 $ 0.10
25 9 J2,J3,J4,J6,J11,J12,J13, MTA100-2 AMP 640456-2 (571-6404562) $ 0.08 $ 0.72
J14,J15 $ -
26 1 J5 JUMPER3 Molex 22-28-4030 (WM6403-ND) $ 0.32 $ 0.32
27 2 J8,J7 MTA100-3 AMP 640456-3 (571-6404563) $ 0.11 $ 0.22
28 1 J9 RIBBON10 3M 3793-6002 $ 1.21 $ 1.21
29 1 J10 MTA156-2 AMP 640445-2 (571-6404452) $ 0.10 $ 0.10
30 1 J16 MTA100-6 AMP 640456-6 (571-6404566) $ 0.15 $ 0.15
31 1 L1 22mH C&D Technologies 22R226 (98B8554) $ 0.86 $ 0.86
32 1 MOV1 V130LA10A Intersil V130LA10A $ 0.23 $ 0.23
33 4 Q1,Q2,Q3,Q4 2N7000 Fairchild 2N7000 (2N7000FS-ND) $ 0.29 $ 1.16
34 1 Q5 TIP47 ON Semi TIP47 (08F8952) $ 0.69 $ 0.69
35 1 R?? 560 $ 0.00 $ 0.00
36 10 R1,R2,R3,R26,R27,R28,R30, 1k00 $ 0.00 $ 0.01
R39,R43,R44
37 8 R4,R5,R6,R14,R15,R16,R22, 10 $ 0.00 $ 0.01
R23
38 1 R7 Zerohm $ 0.00 $ 0.00
39 3 R8,R9,R10 100 1W Xicon 29SJ901-100 $ 0.48 $ 1.44
40 4 R11,R12,R13,R19 330 $ 0.00 $ 0.00
41 3 R17,R25,R29 22k1 $ 0.00 $ 0.00
42 1 R18 221k $ 0.00 $ 0.00
43 1 R20 33k2 $ 0.00 $ 0.00
44 4 R21,R34,R35,R37 10k0 $ 0.00 $ 0.00
45 2 R24,R41 1M00 $ 0.00 $ 0.00
46 2 R33,R31 10K x9 Bourns 4310R-101-103 (4310R-1-103-ND) $ 0.65 $ 1.30
47 1 R32 27k3 $ 0.00 $ 0.00
48 1 R36 1k50 $ 0.00 $ 0.00
49 3 R38,R40,R42 100 $ 0.00 $ 0.00
50 1 R45 47k5 1/2W Xicon $ 0.15 $ 0.15
Item Quantity Reference Part Mfg Mfg PN Cost Ea Ext Cost

51 1 R46 47k5 $ 0.00 $ 0.00

52 1 R47 4k75 $ 0.00 $ 0.00
53 1 SW1 SW DIP-12 Grayhill 76SB12 (GH1202-ND) $ 1.62 $ 1.62
54 44 TP1,TP2,TP3,TP4,TP5,TP6, T POINT A Keystone 501x (52F7287-91) for different colors $ 0.17 $ 7.63
TP7,TP8,TP9,TP10,TP11,
TP12,TP13,TP14,TP15,TP16,
TP17,TP18,TP19,TP20,TP21,
TP22,TP23,TP24,TP25,TP26,
TP27,TP28,TP29,TP30,TP31,
TP32,TP33,TP34,TP35,TP36,
TP37,TP38,TP39,TP40,TP41,
TP42,TP43,TP44
55 1 T1 SW "Side-Winder" Stancor SW-524 (44F2126) $ 9.19 $ 9.19
56 3 T2,T3,T4 SD250-1 Coilcraft SD250-1 $ 6.35 $ 19.05
57 1 U1 LM7812C/TO220 ON MC7812CT $ 0.58 $ 0.58
58 1 U2 LM7805C/TO220 ON MC7805CT $ 0.28 $ 0.28
59 1 U3 PIC16F72 Microchip PIC16F72-I/SP-ND $ 3.45 $ 3.45
60 1 U4 74HC4046B TI CD74HC4046AE (296-9208-5-ND) $ 0.50 $ 0.50
61 1 U5 LM311 National LM311N $ 0.31 $ 0.31
62 1 U6 74HC14 $ 0.47 $ 0.47
63 1 U7 74HC4040 TI SN74HC4040N (296-8324-5-ND) $ 0.48 $ 0.48
64 1 U8 74HC589 Fairchild MM74HC589N (512-MM74HC589N) $ 0.92 $ 0.92
65 1 U9 XC9572_PC44 Xilinx XC9572-15PC44C (122-1171-ND) $ 5.53 $ 5.53
66 1 U10 LM385-2.5/TO92 ON Semi LM385-2.5 (06F9438) $ 0.55 $ 0.55
67 1 U11 MCP3202 Microchip MCP3202-CI/P-ND $ 3.15 $ 3.15
68 1 U12 74HC165 Fairchild MM74HC165N (512-MM74HC165N) $ 0.47 $ 0.47
69 1 U13 LM311 National LM311N $ 0.31 $ 0.31
70 1 Y1 16MHz ECS ECS-160-20-4 (X176-ND) $ 0.40 $ 0.40
or ECS-160-20-1 (520-HCA1600-20)

Total $ 76.96
Cost of One Box

System Level Components $ 240.50

PB0009 Components $ 27.17
PB0010 Components $ 76.96

Total $ 344.63
 Grainger Center for Electric Machinery and Electromechanics
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
1406 W. Green St.
Urbana, IL 61801

Design Document
FET Control Box Redesign 2002

Reference: DD00003
Issue: 001
Status: Issued
Author: Robert S. Balog
Principal Investigator: P.T. Krein
Created: September 15, 2004
w:\documents\design documents\dd00003-001 fet box 2003.doc

Abstract:
The power FET Control box is designed for general instructional and research laboratory use. It
incorporates two electrically independent FET devices and control logic to achieve three switching
modes whereby the two FETs can be made to switch with identical switching functions,
complementary with dead-time switching functions, and alternating switching functions. A
multitude of dc-dc, dc-ac, and ac-ac converters can be realized by using either one FET Control
Box or ganging two FET Control Boxes in a master-slave configuration.

Copyright © Robert S. Balog and Philip T. Krein 2004. All Rights Reserved.
May be duplicated for educational use only so long as this notice remains intact.
Work performed at the University of Illinois at Urbana-Champaign
 FET Control Box Redesign 2002
Design Document Issue 001 DD00003
Document Revision History
Issue Date Comments
000 3/4/2004 Released after revision and review
001 9/15/2004 Added troubled shooting section

Contents

1. Introduction ......................................................................................................... 4
1.1 Scope ..................................................................................................................................... 4
1.2 Definitions............................................................................................................................... 4
1.3 References ............................................................................................................................. 4
2. Specification ....................................................................................................... 5
3. User Interface ..................................................................................................... 7
3.1 Back Panel ............................................................................................................................. 7
3.2 Front Panel............................................................................................................................. 7
4. Theory of Operation ............................................................................................ 8
4.1 Power Supply ......................................................................................................................... 8
4.2 Internal Generation of Switching Function ............................................................................. 8
4.3 Dead-Time and switching function control logic..................................................................... 9
4.4 Power Output Stage............................................................................................................... 9
5. Assembly Instructions ....................................................................................... 10
5.1 Rear panel wire harness make-ready ..................................................................................10
5.1.1 AC Power Wire Harness Assembly make-ready ............................................................10
5.1.2 DC Power wire harness assembly make-ready..............................................................10
5.2 Front Panel Wire Harness make-ready................................................................................10
5.2.1 Freq switch assembly (SPDT switch) .............................................................................10
5.2.2 M/S switch (SPDT switch)...............................................................................................10
5.2.3 Mode switch (DP3T) .......................................................................................................11
5.2.4 Duty ratio POT (Multi-turn pot)........................................................................................11
5.2.5 Frequency POT (Single-turn pot)....................................................................................11
5.2.6 BNC jacks (Qnt=2) ..........................................................................................................11
5.2.7 Green LED ......................................................................................................................11
5.3 Back Panel Assembly ..........................................................................................................11
5.4 Front Panel Assembly ..........................................................................................................12
5.5 Bottom Assembly .................................................................................................................13
5.6 PCB Make-Ready ................................................................................................................14
5.6.1 U13 heat-sink ..................................................................................................................14

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5.6.2 Heatsink ground wire ......................................................................................................14
5.6.3 L2, L3 snubber inductor ..................................................................................................14
5.6.4 L1 inductor ......................................................................................................................14
5.6.5 T2 flyback inductor ..........................................................................................................15
5.6.6 Heat-sink with power diodes and FETs ..........................................................................16
5.7 PCB assembly......................................................................................................................19
5.8 Final Assembly.....................................................................................................................22
6. FET Control Box Assembly Electrical Testing................................................... 27
6.1 Power supply (requires a test ac harness)...........................................................................27
6.2 PWM section (requires a front panel) ..................................................................................28
6.2.1 Procedure........................................................................................................................28
6.2.2 Trouble Shooting Guide ..................................................................................................28
6.3 Final test...............................................................................................................................29
6.3.1 Procedure........................................................................................................................29
6.3.2 Trouble Shooting Guide ..................................................................................................30
7. Verification of Operation: “Calibration” ............................................................. 31
8. PCB Bill of Materials ......................................................................................... 32

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1. Introduction
This project provides advanced Power MOSFET systems capable of being used in a plurality of
projects. Robert S. Balog was the project manager as well as performed all of the mechanical and
electrical design. Jonathan Kimball provided helpful insight as well as a design review forum.
Professor Philip T. Krein provided overall guidance. Construction assistance was provided by
Andrew Niemerg (BSEE '02), Brian Raczkowski (BSEE '03), and Nathan Brown (BSEE '04), the
ECE Electronics Shop and the ECE Machine Shop.

1.1 Scope
The primary end use of the FET boxes is for ECE469 use. Therefore, it must be rugged and
reliable in an undergraduate lab setting. It must also be easy to debug and repair.

In addition, it is desirable to provide advanced performance sufficient for use in a research setting.

The box contains two electrically independent and isolated pairs of Power MOSFETs and Power
Diodes and the control logic to internally generate three switching modes based on PWM control.

1.2 Definitions
BOM: Bill of Material. The parts list that contains part numbers and reference designators.
Control Mode: The two electrically independent FET devices can be made to switch in one of
three modes – 1) identically, 2) complementary with dead time, 3) alternately.
Master / Slave: Two or more FET boxes can be connected such that one acts as the master clock
and the rest act as slaves. In this manner bridge topologies can be achieved.
Switching function: The signal that governs the frequency and duty ratio of switching. The FET
boxes have an internal PWM generator, or they can be supplied with an external switching
function.

1.3 References
Schematics: SK0003 Rev 4
PCB Layout: PB0003 Rev C
Drawings: PJ0008 Rev A

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2. Specification
POWER SUPPLY:
1. Grounded AC line cord with universal IEC style (computer) receptacle with integrate fuse
and an ac power switch.
2. External DC input power jack 0.100” barrel jack.
3. OFF-line isolated switching power supply using a flyback design and galvanically isolated
step-down transformer.
4. Power ON indicator (LED) on secondary of flyback converter.
5. 180 kHz switching frequency.
6. Pot core flyback inductor to limit EMI
7. Three flyback secondary circuits: two FET gate drive circuits and a control circuit.
8. Each gate drive supply is electrically isolated.
9. Control circuit referenced to earth ground for safety.

POWER SEMICONDUCTORS:
• Power diode (MUR3040PT) and FET (IRFP360) with lossy snubber designed for 200V, 10A.

POWER SEMICONDUCTOR CONNECTIONS:

• Multi-hookup binding posts with 0.750” center layout.

CONTROL INPUTS: (BNC jacks)

• D input for direct modulation of q(t). Example: PWM generation.
• q(t) w/ switch (DPDT):
int: ouput q(t) to BNC as master control
ext: input q(t) from BNC as slave control
• Switch to select mode for FET 2 (DPTT):
1. q(t)
2. invert q(t) with dead time (internal adjustment via multi-turn pot)
3. Alternate FET 1 and FET 2 for push-pull
• ESD protection: series resistance and zener clamp.

CONTROLS:
• Duty Ratio:
• Multi-turn precision POT
• 5% to 95% range.
• Frequency:
• Single turn POT with indicator.
• 1 kHz to 300 kHz in two ranges

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CONSTRUCTION:
• PCB based design
• Front panel mounted controls and connections
• Rear panel ac line cord, dc aux input, fuse, power switch.

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3. User Interface
The user interfaces for the FET Control Box resides on the front and rear panels. The rear panel
contains the ac and dc supply connections and power switch. The front panel contains the
uncommitted FET and Diode connections and controls and inputs for the switching function.

3.1 Back Panel

The back panel contains the AC input and fuse, the DC input, and the power switch. The FET
Control Box accepts 120V AC via a standard IEC style line cord. The AC inlet has an integral fuse
and spare fuse holder. The power switch turns off the AC power. Alternatively, a 12 VDC source
can be used. Polarity is +12 on the “tip” and ground reference common on the “ring.” The power
switch has no effect when using the DC input.

Figure 1: Rear Panel

3.2 Front Panel

The front panel contains the frequency and duty ratio controls for the FET Control Box, external
control input and outputs, the source and drain terminals for each of the FETs, and the anode and
cathode terminals for each of the auxiliary diodes. The two FETs and two auxiliary diodes are
completely isolated for configuration in a wide variety of topologies. There is a switch for
selecting the switching functions for the two FETs. Another switch selects between the internally
generated switching function and an externally supplied switching function. For internal switching
function operation, “int,” the Frequency and Duty Ratio knob set their respective parameters and
the q(t) BNC jack operates as an output. A second BNC, D, allows the user to override the Duty
Ratio control knob with an external signal. For externally generated switching function, “ext,” the
q(t) BNC is the input for a TTL compatible signal. The green LED indicates that the internal
power supply of the FET Control Box is operating.

Figure 2: Front Panel

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4. Theory of Operation

4.1 Power Supply

The FET box is designed to be powered primarily from a 120 Vac earth grounded main connection.
A fuse and power switch are located on the rear panel and act to prevent high voltage from
reaching the PCB. The input front end of the power supply is shown on page 1 “Input Rectifier” of
the schematic.
A step-down transformer (T1) with center-tapped secondary is used to achieve galvanic isolation.
A MOV (MOV1) across the primary and necked down traces on the PCB offer protection and
clamping in the case of a line voltage transient.
The secondary circuit of the transformer is earth grounded thru a ferrite bead. The ferrite bead (L1)
is necessary to prevent common mode noise coupled to the chassis ground via the FETs and
grounded heatsinks from coupling into the control circuit. A half-bridge rectifier (D2,D3) and
capacitors (C1,C2,C40) provide a dc bus voltage. A linear regulator (U13) provides tightly
regulated 12V for the power supply PWM ic.
Page 2 of the schematic “Isolated Flyback Power Supply” contains the control and power stages for
the flyback converter. The PWM ic (U2) operates in open loop mode with frequency set by C12
and R4 and duty ratio set by trim pot R19. A gate driver ic (U3) provide low impedance current
drive for the flyback FET (Q1). The snubber circuit is not entirely necessary as the ratings of the
FET are more than adequate to maintain a safe operating area (SOA).
The flyback inductor (T2) is wound on a P3622 bobbin and a P36/22 pot core with one gapped and
one ungapped 3B7 ferrite piece. Two secondary circuits provide the isolated 12V nominal voltage
for the gate drive of each power FET. The actual voltage is set to about 14V with no power FET
current and drops to about 12V with high switching frequency or large drain currents on the power
FET devices. A linear regulator provides 5V from the unregulated 7V winding for the logic ics.

4.2 Internal Generation of Switching Function

Another PWM ic (U4) operates open loop to generate a primary PWM signal used to derive the
switching function for each of the power FETs as shown on page 3 “FET Drive PWM Circuit” of
the schematic. The front panel mounted “Duty Ratio” control (R8) adjusts the duty ratio while
pront panel mounted “Frequency” control (R11) adjusts the oscillator frequency. The duty ratio
control is trimmed at high and low end to minimize dead-travel by R7 and R10. The frequency
range selector switch (S2) switches a second capacitor (C20) in parallel with the primary timing
capacitor (C19).
The dual outputs of the PWM ic open collector and wire-or’ed together with a pull-up resistor. The
PWM signal is buffered by U14 before the front panel mounted BNC (J4). A series resistor (R28)
provides current limiting in the event of a short circuit on the BNC or elsewhere external to the
control box.
The PWM ic can be synchronized externally by providing a TTL compatible signal on the q(t)
BNC (J4) and selecting “ext” on the front panel mounted switch (S1). An external duty ratio can
be programmed via the “D” front panel mounted BNC (J3) connector. The external signal is setup
with an inverting function so that a higher signal at “D” will drive a lower duty ratio. This enable
easy feedback connection without an external inverting op-amp.

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4.3 Dead-Time and switching function control logic

The switching function for each power FET is derived by the logic circuit on page 4 “Deadtime
Circuit w/ Second FET Logic” in the schematic. The front panel mounted switch (S3) selects the
switching function for each of the power FETs. Dead time is generated for the “complement with
deadtime” configuration by R12 and C23. Nominal deadtime is set for 150nS. It is critical that the
correct family of logic be used (U6) because of the different threshold voltage levels inherent
between TTL and CMOS. Use only the logic families called out on the BOM.
The isolated gate drive is provided by the circuit on page 5 of the schematic. Speed-up capacitors
C32 and C33 help increase the switching speeds of Q2 and Q4. U8 and U10 prvide optical
isolation. Low impedance gate drive is provided from each isoltaled gate drive voltage buss by U9
and U11.

4.4 Power Output Stage

The main power devices (M1, M2, D13,D14,D15,D16) are mounted on heatsinks using electrically
isolating material. Speed-up capacitors C52, C53 help with commutation. Gate-source resistors
R26,R27 help to prevent dv/dt turn on via the miller capacitance. Due to the wide operating range
of the FET control box, the snubber is not optimized but instead designed to protect the FET under
worste case conditions to maintain operation within the SOA.

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5. Assembly Instructions

5.1 Rear panel wire harness make-ready

NOTE: Observe pin numbers on MTA connectors begin with #1 on right and increase to the left. All
assemblies use stranded wire.

5.1.1 AC Power Wire Harness Assembly make-ready

Terminal Wire MTA 156 (3 pos)
Neutral 6.75″ white #18 AWG for Neutral #1
Earth GND 7″ green #18 AWG for GND #2
Hot 8.25″ black #18 AWG for Hot #3

Over the wire harness, add 4″ of 0.25″ dia. clear heat shrink tubing centered between the ends. Crimp 90O
fast-on “flag” connectors on other ends of the harness. Use a vise to crimp.

One (1) 4″ black #18 AWG wire with 90O fast-on “flag” connectors on both ends.

5.1.2 DC Power wire harness assembly make-ready

Barrel connector Terminal Wire MTA 156 (3 pos)
Ring (GND) 3.75″ white #18 AWG #1
Tip (POWER) 3.75″ black #18 AWG #2

5.2 Front Panel Wire Harness make-ready

NOTE: Observe pin numbers on MTA connectors begin with #1 on right and increase to the left. All
assemblies use stranded wire. First solder wires to terminals, and then cut all wires to same length and
crimp into connector. Twist all wires within a harness together.

5.2.1 Freq switch assembly (SPDT switch)

Terminal Wire MTA 100 (2 pos)
On 5″ orange #24 AWG #1
Center 5″ purple #24 AWG #2
On No Connect No Connect

5.2.2 M/S switch (SPDT switch)

Terminal Wire MTA 100 (3 pos)
On 4″ yellow #24 AWG #1
Center 4″ purple #24 AWG #2
On 4″ orange #24 AWG #3

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5.2.3 Mode switch (DP3T)

Mode switch has three rows of four terminals. ⇒ one color per row, three colors.
Terminal Wire Flying leads
Bottom row 2″ yellow #24 tinned
Middle row 2.5″ purple #24 tinned
Top row 3″ orange #24 tinned

5.2.4 Duty ratio POT (Multi-turn pot)

Terminal Wire MTA 100 (3 pos)
#1 6″ yellow #24 AWG #1
#2 wiper (center) 6″ purple #24 AWG #2
#3 6″ orange #24 AWG #3

5.2.5 Frequency POT (Single-turn pot)

Terminal Wire MTA 100 (2 pos)
#1 No Connect No Connect
#2 wiper (center) 4″ purple #24 AWG #2
#3 4″ orange #24 AWG #1

5.2.6 BNC jacks (Qnt=2)

Terminal Wire
Center 2″ red #24 AWG
Ring 2″ black #24 AWG
Tin ends of wires and twist together.

5.2.7 Green LED

Terminal Wire MTA 100 (2 pos)
Anode (longer lead) 6″ #24 AWG red wire #1
Cathode (shorter lead) 6″ #24 AWG black wire #2

Cut LED leads to approx 0.75″ keeping the anode longer. Solder wires to LED, staggering solder
joint. Slide 1″ of 3/32″ clear heat shrink each wire all the way to the LED body. Shrink with
heatgun. Slide 1″ of 3/16″ clear heat shrink around both leads and shrink with heatgun.

5.3 Back Panel Assembly

NOTE: Use tools called out in instructions. Do-not use adjustable wrenches as they slip and may
mar the finish. Use only parts called out in the BOM – no substitutions.

1. Wipe all metal surfaces with rag and Windex to remove any grease or residue before assembly.
2. Insert AC switch by pressing firmly into panel as shown in Figure 3.
3. Insert AC inlet. Secure with two (2) 6-32 x ⅜″ flat head Phillips head screw with 6-32 backing
nuts as shown in Figure 3 and Figure 4. Tighten with appropriate size screwdriver and 5/16”
wrench to hold nut. (slot heads ok if Phillips not available)
4. Install one (1) 250mA fuse into fuse holder and one (1) into spare holder.
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5. Insert DC coaxial barrel jack with a backing nut and a front nut. Adjust so jack sits flush on
panel as shown in Figure 3. Use ¼” washer as a spacer on inside panel if needed as shown in
Figure 4. Tighten using a ⅜″ wrench.

AC
Switch
DC inlet
AC inlet

Figure 3: Back Panel Assembly - outside

Figure 4: Back Panel Assembly – inside

5.4 Front Panel Assembly

NOTE: All devices mount flush to front of panel. Adjust rear nut to achieve proper mounting
depth. When given the choice, use the thinner nuts on the output of the panel and the thicker ones
for the inside (hidden).

1. Wipe all metal surfaces with rag and Windex to remove any grease or residue before assembly.
2. Install binding posts in correct color order. Tighten nut with ⅜″ wrench.
3. Install BNC jacks with solder washer, star washer, then nut on inside of panel. Tighten with a
7/16” wrench.

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4. Install M/S and freq selector switches. Be sure to orient in straight up/down manner. Use a front
nut and back nut with star washer and round washer to flush mount the switch to the front of the
panel. Star washer goes against panel, then round washer followed by nut. Reverse the locator
notch on the round washer since no hole exists for it. Frequency selector switch (S2) mounts with
yellow wire up. M/S switch (S1) mounts with orange wire up. Tighten using ⅜″ wrench and
channel lock pliers to hold switch body in vertical orientation.
5. Install pots. Use a front nut and back nut with star washer to flush mount the shaft threads to the
front of the panel. Tighten using ½” wrench.
6. Turn the pot shafts fully CCW. Install knobs for pots with screws at 10 o’clock and 2 o’clock.
Tighten with 0.050” allen wrench. Freq knob indicator should point to 7 o’clock when fully
CCW and 5 o’clock when fully clockwise. Duty ratio knob is without indicator line.
7. Place retaining ring over LED and push past LED. Insert LED holder from the front of panel.
Push LED into holder from rear of panel. Push holder and LED to front, compressing ear-tabs so
that the retainer ring can slide on. Hold retainer from back and push LED holder from front until
flush with panel and assembly is tight.

Figure 5: Front Panel Assembly - inside

5.5 Bottom Assembly

1. Wipe all metal surfaces with rag and Windex to remove any grease or residue before assembly.
2. Attach rubber feet (4) with 6-32 x ¼″ Phillips pan head screws to the 6-32 x 3/8″ stand-offs on
the inside of box. Do not over tighten.
3. Attach the fifth 6-32 x 3/8″ stand-off to the bottom enclosure with a 6-32 x ¼″ Phillips pan head
screw. Use a ¼″ hex nut driver to hold the standoff while tightening.

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5.6 PCB Make-Ready

5.6.1 U13 heat-sink

Wipe all metal surfaces with rag and Windex to remove any grease or residue before assembly.
Attached heat-sink to U13 with 6-32x¼″ Phillips pan head screw and 6-32 using a 5/16” socket
driver.

5.6.2 Heatsink ground wire

8.00″ green #18 AWG for M1 heatsink
10.00″ green #18 AWG for M2 heatsink
Strip and tin one end using solder pot, crimp #8 ring terminal to other.

5.6.3 L2, L3 snubber inductor

3.00″ #14 AWG magnetic wire
Cut magnetic wire to length. Remove 0.25” of varnish from both ends of wire. Pass wire through
ferrite bead and align at mid-point. Bend each wire under ferrite bead as shown in Figure 6. Tin
ends of wire using a solder pot to ensure uniform coating.

Figure 6: 1 turn ferrite bead for snubber inductor

5.6.4 L1 inductor
Put 11 turns of #16 AWG magnetic wire on a L1 ferrite inductor. Strip insulation ½” from end and
tin using solder pot.

Figure 7: L1 inductor

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5.6.5 T2 flyback inductor

The flyback inductor consists of a total of four (4) electrically isolated windings placed on a pinned
36/22 pot core bobbin as per Table 1. Pins are numbered consistent with DIP package. All
windings MUST be wound in counter-clockwise as viewed from above starting with the dot-
winding as in Figure 8.

1. Wind Isolated-A and Isolated-B simultaneously by using two spools of wire.

2. Use yellow polyester tape to separate the two windings.
3. Solder to pins.
4. Wind Control winding.
5. Tape using yellow polyester tape.
6. Solder to pins.
7. Wind primary coil.
8. Tape using yellow polyester tape.
9. Solder to pins.
10. Test for continuity of each coil and for shorts between coils.

Table 1: Flyback inductor windings

Winding Order Wire # of turns Nominal Inductance Pins on bobbin (dot-
first)
1) Isolated-A #24 AWG magnetic 38 577µH 2-5
wire
1) Isolated-B #24 AWG magnetic 38 577µH 3-6
wire
2) Control #24 AWG magnetic 29 336µH 9-10
wire
3) Primary #24 AWG magnetic 50 1000µH 8-11
wire

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12 11 10 9 8 7 12 11 10 9 8 7 12 11 10 9 8 7

tape tape tape

1 2 3 4 5 6 1 2 3 4 5 6 1 2 3 4 5 6
a b c
6 5 4 3 2 1 6 5 4 3 2 1 6 5 4 3 2 1

tape tape tape

7 8 9 10 11 12 7 8 9 10 11 12 7 8 9 10 11 12
d e f
Figure 8: Winding direction and taping (viewed from the top)

5.6.6 Heat-sink with power diodes and FETs

1. Wipe all metal surfaces with rag and Windex to remove any grease or residue before assembly.
Pay particular attention to the flat back of the heatsink.
2. Use the heatsink assembly fixture shown in Figure 9. Note that the left and right side heatsinks
are mirror images. Only one heatsink can be assembled at a time. Orient the heatsink assembly
fixture with the writing in the normal orientation (shown in Figure 9)

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Figure 9: Heatsink assembly fixture

3. Cut plastic shoulder washer to fit thickness of metal tab on D13, D14.
4. Insert M1 face down in the slot labeled FET on the Left side.
5. Insert D13 and D14 face down in the slot labeled Diode on the Left side.
6. Cover the tab of M1, D13, and D14 with thermal isolation pads, aligning the hole in the pad with
the hole in the device. Do NOT use thermal grease.
7. Slide the Left heatsink into the fixture with the end-side hole facing to the left. Use the alignment
pins on the fixture to properly locate the heatsink.
8. Flip the fixture and heatsink over. Attach M1, D13 and D14 to the heatsink using fasteners and
shoulder washers specified in Table 2. Hand-tighten.

Table 2: Heatsink assembly fasteners

Part Fastener Shoulder washer
M1, M2 4-40x½” Phillips pan head Un-modified
D13, D14, D15, D16 4-40x⅜” Phillips pan head Cut to size

9. Remove the heatsink from the fixture.

10. Verify no electrical shorts exist to heatsink: use a multi-meter in continuity mode to check for
shorts between each pin of M1, D13, D14 and the heatsink. If a short exists, remove the screw
for that device, Repeat the assembly of that part using the fixture. Note the position of the
thermal pad. Check again for shorts.
11. Attach the ground wire to the heatsink as per Table 3 using a star washer and 6-32x⅜” Phillips
pan head screw.

Table 3: Heatsink ground wire

Heatsink Wire
Left 8.00″ green #18 AWG for M1 heatsink
Right 10.00″ green #18 AWG for M2 heatsink

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12. Repeat assembly steps 3 through 11for Right heatsink.

13. Fully assembled heatsinks are shown in Figure 10 and Figure 11.

8” wire

Figure 10: Left side heatsink

10” wire

Figure 11: Right side heatsink

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5.7 PCB assembly

1. Insert IC sockets only (no chips).
2. Insert and solder IC sockets with a fine tip iron.
3. Insert and solder 1µF and 0.1µF capacitors as in Figure 12.

Figure 12: Sockets, 1µF and 0.1µF capacitors

4. Insert and solder test points.
5. Insert and solder ¼W resistors. Bend leads at 0.400”.
6. Insert and solder Q2 and Q4.
7. Insert and solder pot R7, R10.
8. Insert and solder R19.
9. DO NOT insert R1, R2, or C31.
10. Insert remaining capacitors.
11. R16, R18 bend leads at 0.700”
12. Bend D1-D12, D18-D22 diodes at 0.400”.
13. Insert and solder MTA headers.
14. 1W and 2W resistors placed as “hairpins” per Figure 13 and Figure 14.
15. Insert a 0.300” jumper at location 171 near M1.
16. Insert the fuse into the fuse holders before inserting the holder into the PCB. This helps retain the
fuse holder during soldering.
17. Solder L2 and L3 onto PCB ensuring that the ferrite stands above the PCB for air circulation.
18. Insert and solder L1.
19. Insert heatsink and U13 assembly into PCB. Solder heatsink pins BEFORE TO-220 pins.
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Figure 13: Hairpin 2W resistors

Figure 14: Orientation of Hairpin resistors

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20. Secure the transformer (T1) to the PCB with the long 4-40 screws inserted from the bottom so
that the nut is on the transformer and the head against the PCB.
21. Assemble the flyback inductor (T2) as in Figure 15 with the ungapped (no marking) 36/22 pot
core half on the bottom, then the pinned bobbin, followed by the gapped (with markings) core
piece. Secure the flyback inductor (T2) with the nylon screw inserted from the bottom of the
PCB and a nylon washer. Hand tighten with a 11/32” nut driver. Solder pins after tightening
screw.

Gapped peice un- gapped peice

(with writing) (no writing)

Figure 15: Flyback transformer mounting to PCB

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 FET Control Box Redesign 2002
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5.8 Final Assembly

1. Ensure that PCB has been tested according to 6.1 Power supply and 6.2 PWM section
2. Solder all wires from front panel assembly to PCB according to Table 4, Table 5, Figure 16, and
Figure 17.
NOTE: Wire to binding posts is 16 AWG.
NOTE: For placement of panel wires to the PCB, assume a top view with writing right side
up.
NOTE: Left and Right cluster of binding posts NOT identical.
Table 4: Front Panel BNC connection
BNC terminal Wire PCB pad
Center Red Top
Ring Black Bottom

Table 5: Front panel binding post connection

Binding post PCB pad wire
Blue Top right A cut to 3.25” strip ¼” ea. end Side, tin one end
Black Bottom right K cut to 2.25” strip ¼” ea. end Side, tin one end
Red Top left D cut to 3.25” strip ¼” ea. end Side, tin one end
Black Bottom left S cut to 2.25” strip ¼” ea. end Side, tin one end

Figure 16: Solder wires from PCB to binding posts

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 FET Control Box Redesign 2002
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Figure 17: Inside of front panel fully assembled

3. Use solder jig to hold pieces together as shown in Figure 18. NOTE: JIG holds everything
upside down. Position right heatsink subassemblies on left side with green wire pointing to back.
As shown in Figure 19. Position left heatsink subassemblies on right side with green wire
pointing to back as shown in Figure 20.

Figure 18: Heatsink assembly fixture

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 FET Control Box Redesign 2002
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Figure 19: Heatsink assembly fixture - left side

Figure 20: Heatsink assembly fixture -right side

4. Turn PCB upside down and aligned with power component pins.
5. Lower the PCB to rest on the stand-off locator pins as in Figure 21 (NOTE: front panel not shown
for illustration purposes).

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 FET Control Box Redesign 2002
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6. Ensure that the PCB fully seated and resting on the stand-off pins for proper alignment. Solder
the power devices to the PCB. Trim off leads.
7. Inserted the green ground wires from the heatsinks HS1 and HS2 from the bottom of the PCB and
solder from the top.

Figure 21: Heatsink assembly fixture with PCB

8. Turn a bottom enclosure piece upside down and place over PCB-heatsink assembly.
9. Attach the heatsinks to the bottom enclosure with 4-40x⅜” (4) Phillips pan head screw.
10. Remove assembly from fixture.
11. Attached PCB to stand-offs using 6-32x3/16” (5) Phillips pan head screws. Hand tighten only.
12. Attach front panel to bottom enclosure using 6-32 screws provided with enclosure.
13. Attached rear panel to bottom enclosure using 6-32 screws provided with enclosure.
14. Attach all wire harness from front and rear panel as shown in Figure 22.

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 FET Control Box Redesign 2002
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Figure 22: Rear panel wire harness

15. Attach top enclosure piece using 6-32 screws provided with enclosure.
16. Test as per section 6.3.

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 FET Control Box Redesign 2002
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6. FET Control Box Assembly Electrical Testing

NOTE: All ICs initially removed from sockets. Always use the variac to ramp up the ac voltage –
never switch on 120V directly.

6.1 Power supply (requires a test ac harness)

1. With U2 and U3 removed from socket, connect 120V thru a variac to the PCB via J2 using test ac
harness shown in Figure 23. Slowly increase AC voltage via variac to 120Vac . If at any point
the input ac line current exceeds 125mA, turn off the power. Measure voltage at TP14 (Vrect)
with respect to TP16 (ckt com). It should be 19V – 20 Vdc.

Figure 23: Ac test harness

2. Verify TP15 (VCC) is at 12Vdc ± 0.010 V with respect to TP16.
3. Turn off AC power. Insert IC U2.
4. Adjust R19 to approximately mid-point (10 turn pot , clockwise lowers voltage).
5. Ramp up AC voltage. Verify that pin2 of U3 is a square wave, has frequency of 180kHz ±
10kHz. Adjust R19 for an approximately 50% duty ratio (wiper voltage will be about 3V).
6. Turn off AC power. Insert IC U3.
7. Ramp up AC voltage. Measure voltages across D9 (TP9 to anode ) and D10 (TP10 to anode).
Adjust R19 such that these voltages are about 13.5Vdc ± 0.050 V. (final duty ratio ~55%, record
the actual value with the PCB serial number)
8. Measure voltage at TP12. It should be 5Vdc ± 0.010 V.
9. Verify that “Power” LED on the front panel turns on.
10. Turn off AC power.

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 FET Control Box Redesign 2002
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6.2 PWM section (requires a front panel)

6.2.1 Procedure
1. Insert U4.
2. Attach R8 (duty ratio), R11 (frequency), and S2 (freq sel) from the front panel. Adjust pot R7
and pot R10 to approximately the mid-point. Position S2 (freq sel) in the up or “high” position.
3. Connect Oscilloscope to the lead of R6 by the silk screen (toward front of box). Turn on AC
power. Verify that the Duty Ratio and Freq knobs work for both freq ranges (high and low).
4. Turn off AC power.
5. Insert U5, U6, U7, U8, U9, U10, U11, U14. OBSERVE ORIENTATION!
6. Connect Oscilloscope probes (2) from TP17 to the top pad of M1 and from TP18 to the bottom
pad of M2. Adjust freq and duty ratio control knobs to about mid-point.
7. Put Mode switch into up position [q,q]. Ensure that both pins have exactly the same signal.
8. Put Mode switch into middle position [q,q’]. Ensure that both pins have complementary signals.
Verify dead-time between two signals (both stay low for time.)
9. Put Mode switch into down position [Alt q, Alt q]. Ensure that both the signals alternate with half
the frequency.
10. Set the Mode switch in the “up” position [q,q], and the frequency select switch to “high” and the
freq knob full CCW. Adjust the Duty ratio trim potentiometers as per Table 6.

Table 6: Duty Ratio trim

Position of Duty ratio knob Adjust
CW R10 to minimize dead travel
CCW R7 to minimize dead travel

6.2.2 Trouble Shooting Guide

Symptom Correction
Vgs of M1, M2 not identical when
Verify Q2 and Q4 part number and insertion orientation.
MODE is [q,q]
Check proper placement of U8, U9 and U10, U11 for each
No signal on Vgs as either M1 or M2
FET respectively.
Verify proper logic family is used for dead-time circuit U5 and
U6.
No dead-time for one or both switching
Excessive propagation delay through the opto-couplers will
transitions when MODE is [q,q’]
require a larger time-constant in the dead-time control
logic.
Vgs of M1, M2 not alternating when
Verify U7 part number and insertion orientation.
MODE is [Alt q, Alt q]

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 FET Control Box Redesign 2002
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6.3 Final test

6.3.1 Procedure
1. Connect a buck converter shown in Figure 24 to each FET.

D S

20V Twist wires 47µF K

DC Tantalum 300µΗ
FET Rload
Supply close to 470µF
Control Box A
box

Figure 24: Buck converter test circuit

2. Wire the tantalum capacitor or equivalent quality low ESR electrolytic as close to the banana
posts as possible and to make the connection between the FET source terminal and the diode
cathode terminal as short as possible. Observe polarity and voltage ratings of the tantalum
capacitor. The positive lead is connected to the DRAIN banana jack. Twist the leads of the
supply wires to minimize inductance.
3. Use a 3.6Ω, 38W or equivalent load resistor. Set the input voltage to 20V and current limit to
4A. Set duty ratio to 50% and a frequency of approximately 30kHz.
4. Connect an oscilloscope probe across the diode and another across the load resistor. Attach a
clamp style current probe to the wire connecting the source banana jack to the inductor. Observe
current polarity.
5. Switch on power to the FET Control Box. Verify expected results shown in Table 7 and
waveforms as shown in Figure 25. Verify that the diode voltage is in-phase with the q(t) signal
and dips negative while q(t) is low. The output voltage is “ac” coupled and is in-phase with the
inductor current. The inductor current is rising for positive diode voltage and falling for negative
diode voltage. All traces are stable and do not jitter or jump.
6. Increase the current limit to 6A. Sweep the frequency and duty ratio to verify operation. Check
both “high” and “low” frequency ranges.

Table 7: Typical operation of buck converter test circuit

VIN 20V
IIN 1.2A – 1.5A
VOUT1 DC: 8.8V – 9.9V
AC: 20mV – 50mV2
Duty Ratio 47% – 53%
Frequency 28kHz – 32 kHz
1
Measured with a multi-meter at the load
2
Actual ac component will vary depending on ESR of output capacitor

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 FET Control Box Redesign 2002
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q(t)

Diode
Voltage

Inductor
current
(dashed)

Output
Voltage

Figure 25: Buck Converter typical waveforms

6.3.2 Trouble Shooting Guide

Symptom Correction
Duty Ratio control changes signal at q(t)
but has no effect on output voltage.
Check FET for possible short
The output voltage is approximately
the supply voltage.
Converter is likely running in discontinuous current mode.
The inductor makes a popping or Verify if the inductor current drops to zero for any portion
hissing sound of the switching period. If so, increase the switching
frequency to elliminate the condition.

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 FET Control Box Redesign 2002
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7. Verification of Operation: “Calibration”

1. Use a multi-meter with diode checking capability. Connect the positive lead of the meter to the
Source “S” banana jack of the left FET and the negative lead of the meter to the Drain “D”
banana jack and verify approximately 0.5V. Reverse the multi-meter leads and verify an “open”
condition. If a short exists in either configuration, then the FET is likely short circuited. Replace
the FET.
2. Repeat for the right FET.
3. Verify that the front panel “POWER” led lights when the power switch is turned on. If not, open
the top cover and perform the steps in section 6.1.
4. Connect a BNC cable from the q(t) jack to an oscilloscope. Set the Mode switch in the “up”
position [q,q], and the frequency select switch to “high” and the freq knob full CCW. Verify that
the switching frequency is approximately 26kHz. Sweep the Duty Ratio control knob through the
entire range of motion and observe the duty ratio of q(t). Verify that there is no appreciable
“dead-travel”. If a problem exists, open the top cover and perform the steps in section 6.2.
5. Set the frequency range selection to “low” and the frequency control knob to CCW. Verify that
the frequency is less than 1kHz. Turn the Duty Ratio Control knob to CCW and verify that
minimum duty ratio is achieved. Turn the Duty Ratio Control knob to CW and verify that
maximum duty ratio is achieved.
6. Repeat for frequency range selection to “low” and the frequency control knob to CW.
7. Repeat for frequency range selection to “high” and the frequency control knob to CCW.
8. Repeat for frequency range selection to “high” and the frequency control knob to CCW.

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 FET Control Box Redesign 2002
Design Document Issue 001 DD00003

8. PCB Bill of Materials

Quantity Reference Part
1 C1 1000uF, 63V
11 C2,C6,C7,C9,C14,C16,C30,C35,C37,C39,C56 1uF
3 C3,C4,C5 470uF
27 C8,C10,C11,C15,C17,C18, C21,C22,C24,C26,C34,
C36,C38,C40,C41,C42,C43,C44,C45,C46,C47,C48,
C49,C50,C51,C54,C55 0.1uF
1 C12 1500 pF
3 C13,C25,C27 22uF Tant
3 C19,C32,C33 1000 pF
1 C20 0.047uF
1 C23 500pF
2 C29,C28 0.001uF, HV
2 C52,C53 1000pF
3 D1,D2,D3 1N4004
1 D4 1N4733
1 D5 1N4742
7 D6,D7,D8,D12,D15,D18,D22 MUR160
2 D9,D10 1N4744
2 D21,D20 1N4747
2 F1,F2 10A Fast Blow
1 J1 2 POS MTA156
1 J2 3 POS MTA156
1 L1 FT50-43
2 L2,L3 1Turn FT50B-43
1 MOV1 V130LA10A
1 Q1 IRF540
2 Q2,Q4 2N3904
6 R3,R6,R12,R26,R27,R32 1k
1 R4 5.1k
1 R5 330, 1/4W
2 R10,R7 5k POT
1 R9 2k
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 FET Control Box Redesign 2002
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2 R14,R13 680
7 R15,R17,R23,R24,R25,R29,R30 330, 2W
2 R16,R18 10, 1/2W
1 R19 10k POT
1 R20 27k, 1/4W
2 R22,R21 1.5k
1 R28 47
1 R31 10, 1/4W
3 R33,R34,R35 4.7, 1W
1 TP9 - TP18 WHITE Test-Point
1 T1 SW-524
1 T2 P36-22 – custom transformer
1 U1 MC7805C / TO220
2 U4,U2 SG3526
1 U3 MIC4423
1 U5 SN74LS08
1 U6 SN74HC14
1 U7 SN74LS175
2 U8,U10 HP2211
3 U9,U11,U14 MIC4420
1 U13 MC7812C / TO220

FET Control Box Redesign 2002 Status : Issued

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 5 4 3 2 1

D D

D1 1N4004
J1 1DC in
PWR

2
D20
1N4747
C C

Vrect TP14 TP15 VCC

Isolated AC U13
D2 MC7812C/TO220
5 P1 Vrect 1 IN OUT 3

GND
N 1
1N4004
J2

2
1

3 6
2 MOV1
1 V130LA10A 7 C1 C2 C40 C30
1000uF, 63V 1uF 0.1uF 1uF
2

From fuse H 4 D3
& switch 8 P2
B B
Earth GND T1 1N4004
SW-524

L1 FT50-43

Con1 HS1

Con2 HS2
A University of Illinois at Urbana-Champaign A

Title
Input Rectifier
Size Document Number Rev
Copyright 2003 by Robert Balog. All Rights Reserved. May be duplicated A SK0003 4
for educational use only so long as this notice remains intact.
Date: Tuesday, November 18, 2003 Sheet 1 of 6
5 4 3 2 1
 5 4 3 2 1

TP9
VCC Iso M1

D6 R33
T2
C7 P3622 +12V A
1uF 5 MUR160 4.7, 1W
D D
C8 D9
0.1uF 1N4744
R1 C34 C35 C3 R23 15V
6.8k 2 0.1uF 1uF 470uF 330, 2W
C9 C10 18 17
1uF 0.1uF VREF VCC Ckt Com A
1 5 TP10
EA+ RST Iso M2
2 EA- SHDN 8
R19 R2 D7 R34
10k POT 3.0k
gate +12V B
3 COMP VC 14
4 CSS 6 MUR160 4.7, 1W
D10
C11 7 1N4744
0.1uF CS+ C36 C37 C4 R24 15V
6 CS- SYNC 12
3 0.1uF 1uF 470uF 330, 2W
OUTA 13 Ckt Com B
C 10 CT OUTB 16 C
9 TP11 TP12
RT Vrect Iso_CTRL U1 5V 5V
11 RDT D8 R35 MC7805C
GND 15
C12 R4 1 3

GND
1500 pF 5.1k IN OUT
U2 8 10 MUR160 4.7, 1W
180kHz fswitch SG3526

2
C38 C39 C5
NOTES: D21 0.1uF 1uF 470uF R25 C6
1N4751 11 9 330, 2W 1uF
C12 & R4 set frequency 30V
R1 & R2 set duty ratio - DO NOT PLACE if R19 placed C56
1uF
D22
MUR160

B B
VCC

VCC R20 27k, 1/4W

C13
22uF Tant C41 C42
0.1uF 0.1uF D18 MUR160
5V R3
1K TP13
6

q(t) flyback
C31
R5 R31 10, 1/4W
GND VS

0.01uF
330, 1/4W 2 7 Q1
INA OUTA IRF540
gate 4 5
INB OUTB R32
1

1k
3

D11 U3 Inverting Driver

A MIC4423 TP16 University of Illinois at Urbana-Champaign A
PWR ON Ckt Com
Front Panel Dedicated ckt com return Title
Power Isolated Flyback Power Supply
2

Indicator
Size Document Number Rev
Copyright 2003 by Robert Balog. All Rights Reserved. May be duplicated A SK0003 4
for educational use only so long as this notice remains intact.
Date: Tuesday, November 18, 2003 Sheet 2 of 6
5 4 3 2 1
 5 4 3 2 1

VCC

J3
D D
BNC
Duty panel 1
jack C14 C15
1uF 0.1uF

2
D D5
1N4742
12V U4
SG3526 5V

18 VREF VCC 17
5V
q
1 5 R6
EA+ RST 1K
2 EA- SHDN 8
min
C16 C17 R7 duty
C54 C55
1uF 0.1uF 5k POT 3 14 q
COMP VC 0.1uF 0.1uF
C C18 4 U14 C
0.1uF CSS MIC4420

8
1
7 CS+
1

6 12

GND VS
GND VS
CS- SYNC
2 IN OUT 6
R8 2 13 7
Duty Ratio OUTA OUT
10 CT OUTB 16
Panel Mounted 9
Duty Ratio C19 RT
11
3

4
5
1000 pF RDT
GND 15
R9 R28
S2 2k 47
max Freq Sel
R10 duty
5k POT Freq range
1

select
R11 buffered qout
C20 Freq
B Panel Mounted B
0.047uF
Frequency S1
1
2 q ext 1 J4
2

3 BNC

2
M/S panel jack
D4 and switch
1N4733
5.1V

NOTES:
C19,C20 & R9,R11 set frequency
R8 Panel Mount duty ratio adjust
R10 trim max duty ratio
R7 trim min duty ratio, CW increases
A University of Illinois at Urbana-Champaign A

Title
FET Drive PWM Circuit
Size Document Number Rev
Copyright 2003 by Robert Balog. All Rights Reserved. May be duplicated A SK0003 4
for educational use only so long as this notice remains intact.
Date: Tuesday, November 18, 2003 Sheet 3 of 6
5 4 3 2 1
 5 4 3 2 1

5V
D D

14 U6F
C21
13 12 0.1uF

14
7
74HC14AN 12
11 Q1 deadtime
13
U5D
74LS08

q_buffered
5V

C 14 U6B R12 7 U6C 14 U6E C

1K
3 4 5 6 11 10

C22 7 14 7 S3
0.1uF 74HC14AN C23 74HC14AN 74HC14AN Mode
150pF
14 U6A 1
2 q1
q 1 2 3

7
7 4
74HC14AN 10 5
8 Q2 deadtime 6
9
U5C 7
5V 74LS08 8 q2

14
B
9 B
16

C43 10
U7 5 11
0.1uF
1 6 Q1 alt 12
R
9 4
C1 U5B
74LS08
14

2
4 1D 3
7 2
5 6 3 Q2 alt
10 1
12 11 U5A
15 74LS08
14

13 14
8

A 74LS175 University of Illinois at Urbana-Champaign A

NOTE: R12 (1k) and C23 (150pf) result in 150nS deadtime Title
Deadtime Circuit w/ Second FET Logic
Size Document Number Rev
Copyright 2003 by Robert Balog. All Rights Reserved. May be duplicated A SK0003 4
for educational use only so long as this notice remains intact.
Date: Tuesday, November 18, 2003 Sheet 4 of 6
5 4 3 2 1
 5 4 3 2 1

5V
+12V A
D D
R13 U8
680 2211 U9
MIC4420

8
1
VCC 8
2

GND VS
GND VS
Anode
OUT 7 2 IN OUT 6 q1_drive
3 Cathode OUT 7
5 C24
R21 GND 0.1uF

3
1.5k

4
5
2 Q2 C25 C44 C45 C46 C47
q1 2N3904 22uF Tant 0.1uF 0.1uF 0.1uF 0.1uF
1 Ckt Com A

C32
C 1000 pF C

5V
+12V B

R14 U10
680 2211 U11
MIC4420

8
1
B VCC 8 B
2

GND VS
GND VS
Anode
OUT 7 2 IN OUT 6 q2_drive
3 Cathode OUT 7
R22 5 C26
1.5k GND 0.1uF
Q4
q2

4
5
2N3904 C27 C48 C49 C50 C51
22uF Tant 0.1uF 0.1uF 0.1uF 0.1uF
Ckt Com B
C33
1000 pF

C32, C33 Speed up switching of Q2, Q4

A University of Illinois at Urbana-Champaign A

Title
FET 1 and FET 2 Isolated Gate Drive
Size Document Number Rev
Copyright 2003 by Robert Balog. All Rights Reserved. May be duplicated A SK0003 4
for educational use only so long as this notice remains intact.
Date: Tuesday, November 18, 2003 Sheet 5 of 6
5 4 3 2 1
 5 4 3 2 1

RCD - Turn On snubber

F1
2 1 TP1
D1
10A Fast Blow

D D

L2 TP2
1Turn FT50B-43 R29 R15 K
330, 2W 330, 2W K1 Tab = Cathod (K)
D12 MUR160

2
D13
C52 1000pF Tab = Drain
MUR3040PT
TP17
G1

3
2

Tab = Cathod (K)

2
R16 10, 1/2W M1 D14 A1
C28
1 IRF360 MUR3040PT TP3
q1_drive 0.001uF, HV
C A C
3

3
R26
1K
Ckt Com A
TP4
S1
F2
2 1 TP5
D2
10A Fast Blow

B B
L3 TP6
1Turn FT50B-43 R30 R17 K Tab = Cathod (K)
330, 2W 330, 2W K2
D15 MUR160

2
D16
Tab = Drain
C53 1000pF TP18 MUR3040PT
G2

3
2

Tab = Cathod (K)

2

R18 10, 1/2W M2 D17 A2

C29
1 IRF360 MUR3040PT TP7
q2_drive 0.001uF, HV
A
R27
3

1k
A University of Illinois at Urbana-Champaign A
Ckt Com B
Title
TP8 Power Output Section
S2
Size Document Number Rev
Copyright 2003 by Robert Balog. All Rights Reserved. May be duplicated A SK0003 4
for educational use only so long as this notice remains intact.
Date: Tuesday, November 18, 2003 Sheet 6 of 6
5 4 3 2 1
 PJ0008 Rev History
FET Box for ECE 469

NOTE: This project pre-dates the current documentation system and does not comply with the current documentation
standards.

Drawing Description REV DWG DXF IPT IAM IPN IDV IDW PDF EMS VSD

DR0001 PCB Assembly fixture base-plate A ipt idw pdf

DR0002 PCB Assembly fixture boss A ipt idw pdf

DR0003 5/8" Rubber mounting boot A ipt idw pdf

DR0004 PCB Assembly fixture assembly A ipt idw pdf

DR0005 Enclosure Top and Bottom Shell E pdf vsd

Enclosure Assembly Front Cut-

DR0006 E pdf vsd
Away

DR0007 Enclosure Front and Rear Panel B pdf vsd

DR0008 Heatsink E pdf vsd

file://W:\Drawings\PJ0008\REV%20A\index.htm 9/15/2004
 4 3 2 1

D D
12.000 0.375 typ. stock

1.000 1.000

1.000 1.000

6-32 UNC
4 PLCS
TAP THRU

C C

n0.251REAM 5 PLCS
SPOT FACE 0.375 DIA TO UNIFORM DEPTH

5.050 `0.002

10.000

1.175 `0.002
B B

4.050 `0.002 1.000

2.475
7.674 `0.002

1.000

1.000
1.000
DRAWN
RSB 3/22/2004
A CHECKED University of Illinois at Urbana-Champaign A
J. KIMBALL 9/15/2004
2.163 QA
Aluminum TITLE
MFG
All tolerances +/- 0.010 unless otherwise specified
APPROVED FET BOX PCB Final Assembly Fixture

SIZE DWG NO REV

C PJ0008-DR0005 A
SCALE
SHEET 1 OF 1
4 3 2 1
 2 1

B B

n0.250 -
+ 0.000 0.078 typ.
0.003
60° n0.313

n0.135 `0.003
10-32 UNFx0.500 0.125 0.300

3.375 `0.003

DRAWN
RSB 3/22/2004
A CHECKED University of Illinois at Urbana-Champaign A
J. KIMBALL
QA
TITLE
Stainless Steel MFG
All tolerances +/- 0.010 unless otherwise noted
APPROVED FET Box PCB Final Assembly Fixture Stand-off

SIZE DWG NO REV

A PJ0008-DR0007 A
SCALE
SHEET 1 OF 1
2 1
 2 1

B B

n.625
.200
R.125
n.250

n.125

.375

DRAWN
Jonathan Kimball 9/15/2004 University of Illinois
CHECKED
R.S. Balog 9/15/2004 TITLE
A QA A

MFG
5/8" Rubber Mounting Foot
APPROVED
SIZE DWG NO REV

A PJ0008-DR0003 A
SCALE
SHEET 1 OF 1
2 1
 4 3 2 1

D D

C C

B B

DRAWN
Jonathan Kimball 9/15/2004 University of Illinois
CHECKED
R.S. Balog 9/15/2004 TITLE
A QA A
MFG
PCB Assembly Fixture Assembly
APPROVED
SIZE DWG NO REV

C PJ0008-DR0004 A
SCALE
SHEET 1 OF 1
4 3 2 1
 10.000 NOM outside

SPEC: A- Dimensions taken from OUTSIDE of box

B- All drawings shown from a TOP side VIEW
0.780
C- 20 gauge steel top and bottom - Custom Painted "Gulf Blue"
0.468
D- Standard Gray aluminum back and front panels - blank
0.156

0.950
1.500
ea.

0.400

RSB
REVIEWED
FET CONTROL BOX ENCLOSURE - Based on Hammond 1458 Series Enclosure

PR0008-DR0005 FETBOX ENCLOSURE REV E.VSD

8.000
NOM
outside 5.300 0.400

7/7/2003
LAST REVISED
0.400

REVISION

E
8/27/2002
DRAWING NO

INITIAL DATE
ROBERT S. BALOG
1.250 0.936 0.936

1:1
DRAWN BY

SCALE
TITLE
FRONT TOP Piece
 10.000 NOM outside

SPEC: A- Dimensions taken from OUTSIDE of box

B- All drawings shown from a TOP side VIEW
0.780 C- 20 gauge steel top and bottom - Custom Painted "Gulf Blue"
0.468
D- Standard Gray aluminum back and front panels - blank
0.156

0.950
1.500
ea.

0.400

RSB
REVIEWED
FET CONTROL BOX ENCLOSURE - Based on Hammond 1458 Series Enclosure

PR0008-DR0005 FETBOX ENCLOSURE REV E.VSD

8.000
NOM
outside 5.300 0.400

7/7/2003
LAST REVISED
0.400

REVISION

E
8/27/2002
DRAWING NO

INITIAL DATE
ROBERT S. BALOG
1.250 0.936 0.936

1:1
DRAWN BY

SCALE
TITLE
FRONT TOP Piece
 10.000 NOM outside
9.900 NOM inside

SPEC: A- Dimensions taken from OUTSIDE of box

0.227 0.227
B- All drawings shown from a TOP side VIEW
0.780 C- 20 gauge steel top and bottom - Custom Painted "Gulf Blue"
0.468
D- Standard Gray aluminum back and front panels - blank
0.156
0.156

1.500
ea.

0.400

RSB
REVIEWED
FET CONTROL BOX ENCLOSURE - Based on Hammond 1458 Series Enclosure

PR0008-DR0005 FETBOX ENCLOSURE REV E.VSD

8.000
NOM 5.050 Ø 0.113 x4
outside 5.300

7/7/2003
LAST REVISED
0.400

2.108

REVISION

E
1.175
0.942

8/27/2002
DRAWING NO

INITIAL DATE
Ø 0.140 x5
4.050

ROBERT S. BALOG
7.674
0.325 0.325
1.250 1.475

1:1
DRAWN BY
1.163

SCALE
TITLE
FRONT BOTTOM Piece
 10.000 NOM outside
9.900 NOM inside

SPEC: A- Dimensions taken from OUTSIDE of box

0.227 0.227
B- All drawings shown from a TOP side VIEW
0.780 C- 20 gauge steel top and bottom - Custom Painted "Gulf Blue"
0.468
D- Standard Gray aluminum back and front panels - blank
0.156
0.156

1.500
ea.

0.400

RSB
REVIEWED
FET CONTROL BOX ENCLOSURE - Based on Hammond 1458 Series Enclosure

PR0008-DR0005 FETBOX ENCLOSURE REV E.VSD

8.000
NOM 5.050 Ø 0.113 x4
outside 5.300

7/7/2003
LAST REVISED
0.400

2.108

REVISION

E
1.175
0.942

8/27/2002
DRAWING NO

INITIAL DATE
Ø 0.140 x5
4.050

ROBERT S. BALOG
7.674
0.325 0.325
1.250 1.475

1:1
DRAWN BY
1.163

SCALE
TITLE
FRONT BOTTOM Piece
 10.000 NOM outside
9.900 NOM inside

0.938 0.938
0.888 8.125 0.888

SPEC: A- Dimensions taken from OUTSIDE of box

0.227 0.227
B- All drawings shown from a TOP side VIEW
1.250 0.780 0.225
C- 20 gauge steel top and bottom - Custom Painted "Gulf Blue"
0.468
D- Standard Gray aluminum back and front panels - blank
0.156 0.226
0.156
0.225 0.225

1.500
ea.

0.400

RSB
REVIEWED
FET CONTROL BOX ENCLOSURE - Based on Hammond 1458 Series Enclosure

PR0008-DR0005 FETBOX ENCLOSURE REV E.VSD

8.000
NOM 5.500 5.050 Ø 0.113 x4
outside 5.300

7/7/2003
LAST REVISED
0.400

2.108

REVISION

E
1.175
0.942

8/27/2002
DRAWING NO

INITIAL DATE
0.225 0.225
Ø 0.140 x5
4.050

ROBERT S. BALOG
7.674
0.325 0.325
1.250
4.275
1.475

1:1
DRAWN BY
1.163

SCALE
TITLE
FRONT BOTTOM Piece
 TOP Piece

3.800

4.000
nom outside

1.240

0.439 0.375

0.870 0.227 BOTTOM Piece 0.227 0.870

1.163 7.674
10.000 nom outside

TITLE

FET CONTROL BOX ENCLOSURE - Hammond 1458 Enclosure

DRAWN BY FULL FILENAME

ROBERT S. BALOG PJ0008-DR0006 FETBOX ENCLOSURE REV E.VSD

SCALE INITIAL DATE REVISION LAST REVISED REVIEWED

1:1 8/27/2002 E 7/7/2003 RSB

 9.875
0.630 0.630
4.000
0.750
0.750 3.000 3.000
1.781
0.781 1.125

Ø 0.250
Ø 0.375
Ø 0.375
Ø 0.250

1.375 Bananna
1.000 Jack
Double D
Ø 0.313
3.910

1.000 Ø 0.375 Ø 0.375

BNC BNC
D D

Ø 0.250 Ø 0.250

0.500 0.500

1.500 2.250

TITLE

FET BOX BACK PANEL - Hammond 1458 Enclosure

DRAWN BY FULL FILENAME

ROBERT S. BALOG PJ0008-DR0007 FRONT AND REAR PANEL REV B.VSD

SCALE INITIAL DATE REV LAST REVISED
1:1 7/24/2002 B 7/28/2002
 FET Control Box
Power High University of Illinois
Urbana - Champaign

Low
Frequency Duty Ratio
D D
S S

int q
FET 1 q(t) D q' FET 2
ext alternate

TITLE

FET BOX BACK PANEL - Hammond 1458 Enclosure

DRAWN BY FULL FILENAME

ROBERT S. BALOG PJ0008-DR0007 FRONT AND REAR PANEL REV B.VSD

SCALE INITIAL DATE REV LAST REVISED
1:1 7/24/2002 B 7/28/2002
 FET Control Box
Power High University of Illinois
Urbana - Champaign

Low
Frequency Duty Ratio
D D
S S

int q
FET 1 q(t) D q' FET 2
ext alternate

TITLE

FET BOX BACK PANEL - Hammond 1458 Enclosure

DRAWN BY FULL FILENAME

ROBERT S. BALOG PJ0008-DR0007 FRONT AND REAR PANEL REV B.VSD

SCALE INITIAL DATE REV LAST REVISED
1:1 7/24/2002 B 7/28/2002
 9.875
typ.
4.238
2.158
1.986
0.823

0.505

1.330

1.955
1.100
1.434
Ø 0.313

3.910 0.525
typ.
1.250
Clearance for 6-32
x2
1.090

TITLE
FET BOX BACK PANEL - Hammond 1458 Enclosure
DRAWN BY DRAWING NO

ROBERT S. BALOG PR008-DR0007 FRONT AND REAR PANEL REV B.VSD

SCALE INITIAL DATE REVISION LAST REVISED REVIEWED

1:1 7/24/2002 B 7/28/2002 RSB

OFF
120 Volts
AC
ON
12 Volts
DC

FUSE
+12 V DC

250V 250mA
GDB - 250

TITLE
FET BOX BACK PANEL - Hammond 1458 Enclosure
DRAWN BY DRAWING NO

ROBERT S. BALOG PR008-DR0007 FRONT AND REAR PANEL REV B.VSD

SCALE INITIAL DATE REVISION LAST REVISED REVIEWED

1:1 7/24/2002 B 7/28/2002 RSB

120 Volts
AC
12 Volts
DC

+12 V DC

250V 250mA
GDB - 250

TITLE
FET BOX BACK PANEL - Hammond 1458 Enclosure
DRAWN BY DRAWING NO

ROBERT S. BALOG PR008-DR0007 FRONT AND REAR PANEL REV B.VSD

SCALE INITIAL DATE REVISION LAST REVISED REVIEWED

1:1 7/24/2002 B 7/28/2002 RSB

 Front

Front
0.915 0.730 0.730 0.730 0.730 0.915

Thru Tap 6-32 spot face Thru Tap 6-32 spot face
3.800 3.800

RSB
REVIEWED
FET CONTROL BOX HEATSINK - Based on AAVID Thermalloy 622003B3800

PJ0008-DR0008 FETBOX HEATSINK REV E.VSD

2.000 2.000

10/8/2003
1.240 1.240 Thru Tap 4-40 x 3
Thru Tap 4-40 x 3

LAST REVISED
REVISION

E
0.500 2.333 0.500 2.333
1.167 1.167
Tap 4-40 3/8" min. thread depth x 2 Tap 4-40 3/8" min. thread dept x 2

FULL FILENAME

8/27/2002
INITIAL DATE
0.100

ROBERT S. BALOG

1:1
Left Side Right Side

DRAWN BY
Right and left side mirror images

SCALE
TITLE
NOTE: Fins are for illustration purposes only
and are not drawn accurately.
Description Part # Manuf Circuit Qnt ECE price Newark Allied $ per unit
Hardware
IEC power inlet with fuseholder 719W-00/04 Qualtek PWR 1 689-3524 $ 1.80
Fuseholder, 3AG, PCB MNT 354-101GY Littlefuse Control 2 44F851 $ 1.26
Snap-In Rocker RA911-VB-B-1-V Carlingswitch PWR 1 89F5553 683-0114 $ 1.25
4PDT switch 7411SYZQE C&K Control 1 21F671 676-3100 $ 17.68
SPDT switch, micro or miniature. 6A, 125VAC MTA-106D Alcoswitch Control 2 $ 2.99 61F1245 $ 7.70
120:12VAC 0.5A,PCB mount SW-524 Stancor PWR 1 44F2126 928-0123 $ 7.89
4-40 Screws - 1 3/8" 91793A119 McMaster PWR 2 $ 0.07 $ 0.14
4-40 Screws - 0.4" $ -
4-40 Screw Insulator - 1/8" 91145A129 McMaster PWR 6 $ 0.05 $ 0.32
4-40 Nuts 90257A005 McMaster PWR 2 $ 0.06 $ 0.11
6-32 x 3/8" hex spacer 4 $ 0.24 $ 0.96
6-32 x 1/4" phillips pan head screws 12 $ 0.10 $ 1.20
6-32 x 3/8" sloted flat machine screws 2 $ 0.10 $ 0.20
6-32 reg patern SS nuts 6 $ 0.05 $ 0.30
1/4" SS flat washer DC PWR IN 1 $ 0.15 $ 0.15
Nylon Insulating Washer - 0.125" 91145A129 McMaster PWR 2
0.1" center panel mnt coaxial PWR barrel jack. 712A Switchcraft PWR 1 $ 1.99 37F2993 932-9403 $ 2.47
0.1" center coaxial PWR barrel plug 760 Switchcraft PWR 1 $ 1.63 37F2995 932-0760 $ 2.52
Tordoid with 4 windings per spec MicoMetals PWR 1
Ferrite Bead FB-43-801 CWS Control 2 $ 0.03 $ 0.05
Binding Post - Red 111-0102-001 Johnson 1 528-0138 $ 1.97
Binding Post - Black 111-0103-001 Johnson 2 528-0139 $ 3.94
Binding Post - Blue 111-0110-001 Johnson 1 528-0144 $ 1.97
Rubber Feet B-323 GC/Waldom 4 $ 0.15 $ 0.60
BNC Jacks 31-221 Amphenol/AIM Control 2 39F075 510-8461 $ 3.90
Frequency Knob EH71-1C2S EHC Control 1 95F6988 904-7109 $ 2.69
Duty Ratio Knob EH71-1N2S EHC Control 1 95F6987 904-7108 $ 2.14
3 pos header 571-6404453 AMP PWR 1 $ 0.15 $ 0.15
3 pos housing 571-6404283 AMP PWR 1 $ 0.14 $ 0.14
2 pos header 571-6404452 AMP PWR 1 $ 0.10 $ 0.10
2 pos housing 571-6404282 AMP PWR 1 $ 0.20 $ 0.20
Metal-Oxide Varistor V130LA10A Littlefuse PWR 1 $ 0.72 $ 0.72
Fuse - 250mA, fast blow, 5mm x 20mm GDB - 250 Bussmann PWR 1 $ 1.33 46F084 740-5183 $ 2.10
Fuse - 15A, fast blow glass, 1/4" x 1.25" AGC - 15 Bussmann OUT 1 27F886 740-0202 $ 0.28

PCB 9.8"x5.5" 2sided, silk, LPI Advanced 1 $ 40.00 $ 40.00

Enclosure - painted blue & 1 panel silk scrn 1458K Hammond 1 $ 38.16 $ 38.16
Machine Shop Time 1 $ 60.00 $ 60.00
Description Part # Manuf Circuit Qnt ECE price Newark Allied $ per unit
Capacitors
1000uF 63V Electrolytic P6287-ND Panasonic PWR 2 $ 2.00 $ 4.00
470uF 25V Electolytic P6286-ND Panasonic PWR 3 $ 1.47 $ 4.41
1uF ceramic 2C20Z5U105M Sprague Control 6 $ 0.22 $ 1.32
0.1uF ceramic C322C104K5R5CA Kemet Control 10 $ 0.15 $ 1.50
0.01uF ceramic DD103 Sprague Control 1 $ 0.14 $ 0.14
0.001uF ceramic DD102 Sprague Control 3 $ 0.15 $ 0.45
0.047uF ceramic Kemet Control 1 $ 0.13 $ 0.13
22uF tantalum -20V Panasonic Control 3 $ 4.56 $ 13.68
150pF silver mica CD10FD151JO3 Cornell-Dublier Control 1 15f1364 862-3227 $ 0.95
1500pF silver mica CD19FD152JO3 Cornell-Dublier Control 1 15F1256 $ 3.14

Silicon
PWM IC SG3526 on-semi PWR/Control 2 568-0455 $ 5.00
Diode 1N4004 on-semi PWR 3 $ 0.10 09F3592 568-0144 $ 0.18
"digital" optocoupler HP2211 Agilent OUT 2 06F5428 787-4091 $ 5.24
600V 1A Ultrafast Rectifier MUR160 on-semi PWR 5 08F2048 568-2539 $ 2.15
MOSFET - IRF540 IRF540 IRF PWR 1 06F8274 273-5400 $ 0.90
Voltage Regulator - 5V LM7805CT Fairchild PWR 1 263-0135 $ 0.28
Logic - AND SN74LS08N on-semi Control 1 38C1108 568-2033 $ 0.29
Logic - Schmitt Trigger Hex Inverter SN74HC14AN on-semi Control 1 568-3901 $ 0.41
Logic - Flip Flop SN74LS175N TI Control 1 735-1686 $ 0.36
5.1V Zener 1N4733A on-semi Control 1 $ 0.13 95B4973 568-0013 $ 0.07
12V Zener 1N4742A on-semi Control 1 09F3911 568-0029 $ 0.14
15V Zener 1N4744A on-semi Control 2 09F3919 568-0033 $ 0.28
LED - Green + Snap connector HLMP-3507 PWR 1 $ 0.15 $ 0.15
Single input inverting FET driver MIC4423 Micrel OUT 1 83F5983 $ 2.10
Single input non-inverting FET driver MIC4420 Micrel OUT 2 83F5974 $ 3.28
POWER MOSFET - IRFP360 IRFP360 IRT OUT 2 06F8014 $ 24.40
MUR3040PT MUR3040PT on-semi OUT 4 08F2093 568-2562 $ 9.76

Resistors
2K 1/4W Control 1 $ 0.10 $ 0.10
10 1/4W Control 2 $ 0.10 $ 0.20
6.8K 1/4W Control 1 $ 0.10 $ 0.10
3.0K 1/4W Control 1 $ 0.10 $ 0.10
1K 1/4W Control 5 $ 0.10 $ 0.50
20K 1/4W Control 1 $ 0.10 $ 0.10
330 1/4W PWR 1 $ 0.10 $ 0.10
47 2W Control 1 296-0703 $ 1.70
330 2W Control 2 296-0712 $ 3.40
Description Part # Manuf Circuit Qnt ECE price Newark Allied $ per unit
5k 10 turn panel mount - Duty Ratio 73JA5K Control 1 01F3549 753-0238 $ 17.42
50K 1 turn panel mount - Frequency 3852A-282-503A Control 1 01F9200 754-5306 $ 9.44
Mounting Hardware - Nut M-2786 Control 1 10F1953 $ 0.32
Mounting Hardware - Washer B-13750 Control 1 10F1955 $ 0.76
Heat Sink Pad sp600-104 Bergquist OUT 6 BER109-ND $ 2.08

Total Cost $ 338.00

 Grainger Center for Electric Machinery and Electromechanics
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
1406 W. Green St.
Urbana, IL 61801

Design Document
Analog PWM Amplifier

Reference: DD00004
Issue: 000
Status: Issued
Author: Robert S. Balog
Principal Investigator: P.T. Krein
Created: September 14, 2004
w:\documents\design documents\dd00004-000 pwm amp.doc

Abstract:
The analog pulse width modulation amplifier was designed as an integrated “blue box” approach to
demonstrating the PWM process. With suitable component selection, the resulting PWM is of
sufficiently high quality to demonstrate not only motor drive applications but also audio
amplification. The design realizes the PWM discretely: a voltage controlled oscillator to generate
the ramp, a comparator, dead-time logic, and a full H bridge to drive the load. To simplify the gate
drive circuitry, each gate is driven directly from the input bus. In practice this limits the bus
voltage to the maximum Vgs of the FET – about 20V; sufficient to drive a small 8Ω speaker. Test
points are provided to allow investigation of every aspect of the PWM process including dead-time.

Copyright © Robert S. Balog and Philip T. Krein 2004. All Rights Reserved.
May be duplicated for educational use only so long as this notice remains intact.
Work performed at the University of Illinois at Urbana-Champaign
 Analog PWM Amplifier
Design Document Issue 000 DD00004
Document Revision History
Issue Date Comments
000 9/14/2004 Initial Release

Contents

1. Introduction ......................................................................................................... 3
1.1 Scope ..................................................................................................................................... 3
1.2 Definitions............................................................................................................................... 3
1.3 References ............................................................................................................................. 3
2. Specification ....................................................................................................... 4
3. Theory of Operation ............................................................................................ 4
3.1 Power Supply ......................................................................................................................... 4
3.2 Analog Input ........................................................................................................................... 4
3.3 Carrier and PWM Generation................................................................................................. 5
3.4 Dead-Time Circuit and Gate Drive......................................................................................... 5
3.5 Output Bridge ......................................................................................................................... 5
3.6 Low Pass Output Filter........................................................................................................... 5

Analog PWM Amplifier Status : Issued

Page 2 of 7 Printed 9/17/2004: 4:42:45 PM
 Analog PWM Amplifier
Design Document Issue 000 DD00004

1. Introduction
The analog pulse width modulation amplifier was designed as an integrated “blue box” approach to
demonstrating the PWM process. With suitable component selection, the resulting PWM is of
sufficiently high quality to demonstrate not only motor drive applications but also audio
amplification. The design realizes the PWM discretely: a voltage controlled oscillator to generate
the ramp, a comparator, dead-time logic, and a full H bridge to drive the load. To simplify the gate
drive circuitry, each gate is driven directly from the input bus. In practice this limits the bus
voltage to the maximum Vgs of the FET – about 20V; sufficient to drive a small 8Ω speaker. Test
points are provided to allow investigation of every aspect of the PWM process including dead-time.

1.1 Scope
The primary end use of the Analog PWM amplifier was for demonstration of a high quality PWM
process. The majority of the PWM integrated circuits commercially available to not make many of
the PWM process signals available to the user. Building the PWM process from discrete
components allows all signals at all phases of the PWM process to be examined.

1.2 Definitions
Dead-time: The time during which no switches in the H-bridge are gated on. The switches turn off
and on in a break before make configuration to prevent shorting out of the bus voltage.
H-Bridge: The output of the PWM process is a full H-bridge that connects the load to the bus in
either a positive polarity of a negative polarity. Depending on the switch configuration, the voltage
across the load becomes either +Vbus or –Vbus.
PWM – Pulse Width Modulation

1.3 References
Schematics: SK0002 Rev 3
PCB Layout: PB0003 Rev C

Analog PWM Amplifier Status : Issued

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 Analog PWM Amplifier
Design Document Issue 000 DD00004

2. Specification
Parameter Min. Max.
Supply voltage: 12V 20V
Analog input: -2V +2V
Switching frequency: ~10kHz >300kHz
Dead-time 200nS nom.
Low pass filer Second order response, 37.5kHz cut-off

3. Theory of Operation
Pulse width modulation, when used as the basis for an amplifier, is termed a “class D” or
sometimes “class S” circuit. The principle is that the switch duty ratios can be made to follow any
desired waveform, provided that switching is fast. The duty ratio signal can be recovered with a
simple low-pass filter.

3.1 Power Supply

The amplifier receives DC power through the 4 pin header J2. Pins are labeled as appropriate (see
schematic and PCB artwork). For general lab experimentation, the only externally required voltage
for the PWM AMP is VCC (and ground). Depending on the desired amplitude of the output, VCC
can be selected within the range of 12 < VCC < 20. Voltages less than 12V will not be enough to
power the ICs. Voltages above 20V will damage the FET driver ICs.

The PWM amplifier is designed both electrically and mechanically to interface with a small 12 V
open frame power supply. A piece of sheet steel connected to frame ground may be needed as a
Faraday shield between the PWM AMP and the power supply. Further, a solid ground connection
between the PWM AMP circuit common and the power supply frame ground is needed to minimize
noise.

Alternatively, any commonly available laboratory power supply can be substituted as the power
supply for instructional purposes. Two series linear regulators provide regulated 12V and 5V for
internal use within the amplifier circuit.

3.2 Analog Input

Analog input is supplied through the 3.5mm stereo headphone jack. Internally, the left and right
channels are summed into a mono signal. The attenuator POT R6 is a 50K linear variable resistor
that attenuates the applied input signal prior to the comparator. Note that there are no op-amps or
other circuit to provide gain in the traditional sense.

The input is ac coupled into the comparator stage through C2. R5 sets the dc bias (offset) on the
analog input and can be adjusted to compensate for any drift in the PWM amplifier to achieve a
50% output waveform for a 0V input. Turning R5 CW increases the DC bias.

Analog PWM Amplifier Status : Issued

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 Analog PWM Amplifier
Design Document Issue 000 DD00004

3.3 Carrier and PWM Generation

The PWM Amplifier process implements discretely conventional sine-triangle PWM techniques.
The triangle carrier function is generated by the LM566 VCO labeled U1 as seen on page 1 of the
schematic. The frequency of the triangle carrier is set by C1 and R3. Turning R3 CW (clock wise)
increases the frequency. R23 sets the peak to peak amplitude of the triangle function. Turning R23
CW increases the amplitude. General purpose comparator LM311 is used to create the PWM
waveform by comparing the modulating function (analog input) with the carrier function (triangle
waveform). The triangle carrier, modulating function, and resulting PWM are available via test
points on the PCB.

3.4 Dead-Time Circuit and Gate Drive

The PWM waveform resulting from the comparator stage is passed into the dead-time circuit
comprised of U3 and U4 as seen on page 2 of the schematic. The result is two gate drive signals
and their complement. These four gate drive signals ensure that one set of switches completely
turns off before another set turns on. This break before make feature ensures that both switches in
one leg of the H bridge output stage are not both on, eliminating the possibility for shoot-through
current and FET failure. The four gate signals are available on the orange test points TP4-TP7.

Soft-start circuitry (R15, C11, C22, C23) provides approximately a 200ms startup period to allow
the power supply to stabilize before the bridge is allowed to run.

3.5 Output Bridge

The output is a typical “H bridge” with four FET switches connected in a geometry that resembles
the letter H. Switches M1 and M4 operate as a one pair and M2 and M3 operate as the second pair.
When M1 and M4 are “ON” and M2 and M3 are “OFF”, positive voltage is imposed across the
load resulting in a current path in the positive direction. When M1 and M4 are “OFF” and M2 and
M3 are “ON”, negative voltage is imposed across the load and the current reversed polarity and
flows in the negative direction.. Thus the H bridge can supply both positive and negative output
voltages from a single supply.

The PWM Amplifier can be configured for half bridge operation by populating only M1 and M3
and placing jumper JMP1.

The gate voltages are driven directly from the bus voltage by Micrel MIC4424 low impedance gate
driver ICs. This arraignment simplifies the gate drive circuitry by eliminating the need for high-
side referenced gate signals. However, it imposes the constraint that the maximum bus voltage
cannot exceed the Vgs of the FET – typically about 20V.

3.6 Low Pass Output Filter

The output square wave from the bridge is low-pass filtered by L1, L2, C19, and C20. The
frequency response has a –3dB point at about 37.5 kHz and is characteristic of a 2 pole second
order filter. The calculated frequency response of the output filter is shown below. For carrier
frequencies above 100 kHz, the low pass filter should yield adequate performance and low standby
ripple current.

Analog PWM Amplifier Status : Issued

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 Analog PWM Amplifier
Design Document Issue 000 DD00004

Output Filter for Analog PWM AMP −6 −9

L := 20 × 10 C := 900⋅ 10
RLoad := 8
1
L⋅ C 4
f-3db = = 3.751 × 10
2π
RLoad

L 4
Full Bridge: KCL & KVL Equations = 6.366 × 10
2π
Vi − V1 V1 V1 − V2 V1 − V2 V2 ( )
V2 − −Vi
+ ( 1) + ( 2) Vout V1 − V2 ( 3)
j⋅ w⋅ L 1 RLoad RLoad 1 j⋅ w⋅ L
j ⋅ w⋅ C j ⋅ w⋅ C
Substitute (3) Substitute (3) Solve for V2

Vi − V1 V1 Vout Vout V2 ( )
V2 − −Vi V2 −Vout + V1
+ +
j⋅ w⋅ L 1 RLoad RLoad 1 j⋅ w⋅ L
j ⋅ w⋅ C j ⋅ w⋅ C

⎛ V ⋅ w⋅ L + i⋅ w2⋅ C⋅ R ⎞
Vout ⎝ out Load⋅ L⋅ Vout − i⋅ RLoad⋅ Vout + i⋅ RLoad⋅ Vi⎠
−2 V1 −i⋅
Vi 2
L⋅ C⋅ w −
2⋅ i⋅ w⋅ L
−1
( 2
RLoad⋅ w ⋅ C⋅ L − 1 )
RLoad

A ( w) := 20⋅ log⎡ ⎤ H( w) := 20⋅ log ⎡ ⎤

2 1
Half Ckt
⎢ 2 2⋅ j⋅ w⋅ L ⎥ transfer function
⎢ 2 2⋅ j ⋅ w⋅ L ⎥
⎢ 1 + ( j w) ⋅ L⋅ C + R ⎥ ⎢ 1 + ( j⋅ w) ⋅ L⋅ C + R ⎥
⎣ Load ⎦ ⎣ Load ⎦

arg ⎡ ⎤ arg ⎡ ⎤
180 2 180 1
AP ( w) := Half Ckt HP( w) :=
π ⎢ 2 2⋅ j ⋅ w⋅ L ⎥ transfer function π ⎢ 2 2⋅ j⋅ w⋅ L ⎥
⎢ 1 + ( j w) ⋅ L⋅ C + R ⎥ ⎢ 1 + ( j⋅ w) ⋅ L⋅ C + R ⎥
⎣ Load ⎦ ⎣ Load ⎦

Analog PWM Amplifier Status : Issued

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 Analog PWM Amplifier
Design Document Issue 000 DD00004

Frequency Response of Output Filter

10
5
0
5
10
15
20
Amplitude [dB]

25
30
35
40
45
50
55
60
65
70
3 4 5 6
10 100 1 .10 1 .10 1 .10 1 .10
Frequency [Hz]
Full Bridge
Half Bridge

Frequency Response of Output Filter

45

45
Phase [deg]

90

135

180

225

270
3 4 5 6
10 100 1 .10 1 .10 1 .10 1 .10
Frequency [Hz]
Full Bridge
Half Bridge

Analog PWM Amplifier Status : Issued

Page 7 of 7 Printed 9/17/2004: 4:42:45 PM
 5 4 3 2 1

12V

R1 12V
1K
12V
D D
R21

1
Freq Adjust R2 Volume Adjust 5k 3.5 mm PHONEJACK STEREO SW
1K Audio in (sums L+R into mono)
R4 C1 2 R3

3
1K 1000pF 20K POT

1
DC Bias MNT2
C2
R5 2 2

3
10K POT MNT1 R22
R7 C3 R6 5k J1
12V 4.7K C 2.2uF 50K POT

1
3
C4 R8
7
6
5
1000 pF 1 4.7K
VCC 8
GND_POWER
MOD
TCAP
TRES

C6 Place close
C 1uF Mono 12V to IC 12V C
R9
4.7K
C5 C7 TP3 Yellow
SQWOUT
TRWOUT

TP1 0.01uF R10

Orange 1 1K

1
5
6
8
U1 2uF Mono
LM566C 2 +
C24 7 PWM OUT
4
3

R11 100pF 3 -
R? U2
LM311

4
1
1

1
TP2
R12 R13 2 White
J2 10K 10K
B 4 R23 B
3 5V Place R9 and R11 close to LM311
10K POT
3

GND 2
VCC 1
Alternative to R11 and R12. Place
CON4 R23 to adjust amplitude of triangle
function. R11 not routed

C3 and C24 optional for noise immunity

C26 not routed

VCC_Supply
U8 12V
LM7812/TO
1 VIN VOUT 3 12V
A A
GND

C26 C25
10uF Tant .01uF Ceramic Title
Analog input and PWM Section
2

Size Document Number Rev

A SK0002 3

Date: Tuesday, September 14, 2004 Sheet 1 of 3

5 4 3 2 1
 5 4 3 2 1

C8, C9 not routed

5V Only 74HC14 must be used. Any

other series logic wil not work

D B D
C9
1uF Tant

14
Enable
14 U3F
1
PWM OUT 2 12 13 12 B*
13
7
U4A 74HC14

7
74LS11

5V 14 U3B R14 7 U3C 14 U3D

C 1K C
3 4 5 6 9 8 R14 and C10 set deadtime

C8 7 14 7
1uF Tant 74HC14 C10 74HC14
220pF 74HC14
14 U3A

1 2

7
74HC14 5V
14

14 U3E
3
4 6 11 10 A
5
7 R15
Enable U4B 74HC14
7

B
74LS11 1K B

14
A* 9
10 8 Enable
5V 11

5V U4C

7
74LS11
5V
U5
LM7805/TO C11 C22 C23
1 3 1uF Mono 1uF Mono 1uF Mono
12V VIN VOUT
GND

C13 C14
C12 10uF Tant .01uF Ceramic
47uF Tant
2

A A

Title
Dead Time Delay Logic

Size Document Number Rev

A SK0002 3

Date: Tuesday, September 14, 2004 Sheet 2 of 3

5 4 3 2 1
 5 4 3 2 1

U6 MIC4424 TP4
R17 10
2 7 M1 DRIVE

1 1
A INA OUTA
B* 4 INB OUTB 5 M2 DRIVE
VCC_Supply
6 R20 10
+VCC
3 -VCC TP6
C15
D D
47uF tant
Test Points
Non-inverting output T4, T5, T6, T7 Orange
driver chip

U7 MIC4424 TP7
R19 10
2 7 M4 DRIVE

1 1
A* INA OUTA
B 4 INB OUTB 5 M3 DRIVE
VCC_Supply
6 R18 10
+VCC
3 -VCC TP5 Outputs of Bridge are floating with respect to
C16 ground. But use differential voltage probes
2.2uF Mono

C VCC_Supply C
C15 and C16 placed close to U6, U7 Do Not place for Half
Bridge Operation

3
2

2
1 D1 C17 C D2 1
M1 DRIVE MBR360 MBR360 M2 DRIVE

M1 Red Red Black Black M2

IRF9530 IRF9530
2

2
TP8 TP10 TP11 TP9
L1 R16 L2

1
Rload
B B
M3 M4
2

2
IRF530 C19 C20 IRF530
D3 C C D4
MBR360 MBR360
Place jumper only 1 1
VCC_Supply for Half-Bridge M3 DRIVE M4 DRIVE
1

1
Operation
3

3
L1, L2, C17, C19, C20 values
based on LPF design
C18
47uF Tant
JMP1

VEE_Supply
C21
47uF Tant D1-D4 not routed due to space limits.
A A
Use body diode of FET
Jumper may be Title
VEE_Supply used in place Bridge Output and FET Drivers
of C21
Size Document Number Rev
A SK0002 3

Date: Tuesday, September 14, 2004 Sheet 3 of 3

5 4 3 2 1
Project: PWM Amplifier Quantity to Build: 1
Ref Des Description Part # Manuf Qnt

Documentation
Design Document DD00004 Issue 000 0
Schematic SK0002 Rev 3 0
PCB Layout PB0002 Rev B 0

Hardware
J1 3.5mm phone jack 1
J2 4 pos header mta156 571-6404453 AMP 1
J2* 4 pos housing mta156 571-6404283 AMP 1
U2*,U6*,U7* 8 PIN DIP socket 3
U3*,U4* 14 PIN DIP socket 2
TP1,TP4-TP7 Orange testpoints 5
TP2 White testpoint 5012 1
TP3 Yellow testpoint 1
TP8,TP10 Red testpoint 2
TP11 Black testpoint 1
PCB1 PCB 8.125"x5.5" 2sided, silk, LPI REV C Advanced 1

Magnetics
L1,L2 Powdered Iron toroidal core, 21 Turns T80-26 2

Capacitors
C1,C4 1000pFceramic 2
C2 2.2uF, 15V elect. 1
C3,C24 not placed 0
C5,C16 2.2uF Monolithic 2
C6,C11,C17,C19,C20,C22,C23 1uF ceramic 2C20Z5U105M Sprague 7
C7,C14,C25 0.01uF ceramic DD103 Sprague 3
C9,C8 1uF Tant 2
C10 220pFsilver mica or ceramic 1
C12,C15,C18 47uF 25V Tant 4
C13,C26 10uF 25V Tant 2
C21 Place a wire jumper 1

Silicon
M1,M2 P-Channel FET IRF9530 2
M3,M4 N-Channel FET IRF530 2
U1 Voltage Controlled Oscillator LM566C 1
U2 Comparator LM311 1
U3 Logic - Schmitt Trigger Hex Inverter 74HC14AN 1
U4 Logic - Triple input AND 74LS11 1
U5 +5V votlage regulator LM7805/TO 1
U6,U7 Dual non-inverting FET driver MIC4424 2
U8 +12V voltage regulator LM7812/TO 1

Resistors
R1,R2,R4,R10,R14,R15 1K 6
R3 20K precision multi-turn POT 1
R5,R23 10K precision multi-turn POT 2
R6 50K POT audio taper 1
R7,R8,R9 4.7K 3
R11 not placed 0
R12,R13 10K 2
R16 Rload via external wires 1
R17,R18,R19,R20 10, 1/4W 4
R21,R22 5k 2
 Grainger Center for Electric Machinery and Electromechanics
Department of Electrical and Computer Engineering
University of Illinois at Urbana-Champaign
1406 W. Green St.
Urbana, IL 61801

Design Document
BLDC Drive for ECE431

Reference: DD00002
Issue: 001
Status: Issued
Author: Jonathan Kimball
Principal Investigator: P.L. Chapman
Created: September 17, 2004
q:\documents\design documents\dd00002-001 bldc drive for ece431.doc

Abstract:
In 2003, drives and dynos were built to demonstrate brushless dc (BLDC) motors for ECE431
(Electric Machinery) laboratory experiments. They had a number of problems and were not very
rugged. A new system was designed in late 2003/early 2004 to replace them. The result is a
rugged drive capable of being used for a variety of experiments, and particularly convenient for use
with a rugged dynamometer composed of a BLDC motor coupled to a dc permanent-magnet motor.

Copyright © Jonathan Kimball, Dustin Kramer and Patrick L. Chapman 2004. All Rights Reserved.
May be duplicated for educational use only so long as this notice remains intact.
Work performed at the University of Illinois at Urbana-Champaign.
 BLDC Drive for ECE431
Design Document Issue 001 DD00002
Document Revision History
Issue Date Comments
000 07/15/2004 Initial Release.

Contents

1. Introduction ......................................................................................................... 3
1.1 Scope ..................................................................................................................................... 3
1.2 Definitions............................................................................................................................... 3
1.3 References ............................................................................................................................. 3
2. Control Design .................................................................................................... 4
2.1 Motor Signals ......................................................................................................................... 4
2.2 Start-Up .................................................................................................................................. 4
2.3 Protection ............................................................................................................................... 4
2.4 User Interface......................................................................................................................... 4
3. Power Design ..................................................................................................... 6
3.1 Gate Drive .............................................................................................................................. 6
3.2 Inverter Bridge........................................................................................................................ 6
3.3 Thermal Design...................................................................................................................... 6
4. Troubleshooting .................................................................................................. 7
4.1 Troubleshooting Flowchart..................................................................................................... 8

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 BLDC Drive for ECE431
Design Document Issue 001 DD00002

1. Introduction
This project involves a simple three-phase inverter capable of being used for a number of
experiments, with a primary emphasis on a BLDC dynamometer. The dynamometer was designed
by Scott McDonald and built in the ECE Machine Shop. The drive was designed entirely by
Jonathan Kimball. Boards were fabricated by Advanced Circuits; sheet metal was fabricated by
eMachineShop, finished by the ECE Machine Shop and silkscreened by the ECE Electronics Shop.
Final assembly was performed by Alicia Shepherd, Nathan Brown, and Yongxiang Chen.
Troubleshooting instructions were developed by Dustin Kramer.

1.1 Scope
The primary end use of the boxes is for ECE431 (formerly ECE333) use. Therefore, it must be
rugged and reliable in an undergraduate lab setting. It must also be easy to debug and repair.
In addition, it is desirable to provide capabilities for use outside the lab in demonstrations and
simple experiments. To that end, switching frequency should not be limited to commutation
frequency.
The inverter stage is composed of six IRFIZ48N MOSFETs.

1.2 Definitions
BLDC: brushless dc, a type of motor closely related to a permanent magnet synchronous machine.
The only difference is the way it is driven (square wave voltage vs. sine wave voltage).

1.3 References
Schematics: SK0014 rev 2
Layouts: PB0014 rev B
Drawings: PJ0005 rev B

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 BLDC Drive for ECE431
Design Document Issue 001 DD00002

2. Control Design

2.1 Motor Signals

The motor has “Hall effect” outputs spaced 120° electrically. The falling edge of a given Hall
signal is aligned to the peak of some line-to-neutral voltage. This is highly inconvenient, since
what is desired is alignment to line-to-line voltage.
There is an encoder as well. However, it is 500 pulses per revolution (500 ppr). This is not evenly
divisible by three, so it would not be convenient to use for commutation.
The decision was to accept the phase error and synchronize switching events to the Hall effects
directly. This means that the inverter output voltage leads the speed voltage by 30° electrical.
Some would argue that this is even preferable at high speeds to compensate for inductive effects.
Signals were found such that something we call “Hall U” corresponds to the low side of phase 1
being turned on.

2.2 Start-Up
The gate drive used is an IR2130 with the high sides powered by bootstrap. There was previously a
problem at start-up. In a switchmode converter, the low-side switch is always turned on eventually.
In a motor drive commutated by Hall tracks, there is no guarantee that the low-side switch will ever
turn on. To ensure that the bootstrap capacitors get charged, an enable switch was added.
For complete logic, see the schematic (SK0014 rev 2). Essentially, when the enable switch is off,
all three low-side switches are turned on. When the enable switch is on, the drive commutates
according to the Hall tracks.

2.3 Protection
The IR2130 has built-in overcurrent shutdown. To enable it, a 50 mΩ current sensing resistor was
used in the negative bus. The overcurrent threshold was set at 12 Apk, corresponding to 8.5 Arms,
a thermally safe current.
Both power inputs are diode protected. This prevents regeneration, but more importantly protects
against reverse polarity power.

2.4 User Interface

For convenience, some signals are brought out to the front panel through BNC jacks. The bus
current, as sensed by the overcurrent sensing resistor, is brought out. Scopes should be set on high
impedance, 10X probe, and then current will be read directly.
Also, the bus voltage is provided after the protection diode. Again, if the scope is set on high
impedance, 10X probe, the bus voltage will be read directly.
The three Hall effects are buffered and brought out to BNCs. This allows students to see the
relationship between switching and phase currents.

2.5 Use as a General Inverter

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 BLDC Drive for ECE431
Design Document Issue 001 DD00002

To use the drive as a generic inverter, it is necessary to provide PWM commands. J17 is a DB9
intended for connection to the BLDC motor in the dyno. Complete pin-out is given in the
schematic (SK0014 rev 2). Pins 1 and 2 are 5V and ground, respectively, available to run a small
external circuit. Pins 7, 8, and 9 are HALLW, HALLU, and HALLV, respectively. As stated
above, HALLU high → phase A is low, and similarly HALLV high → phase B low, HALLW high
→ phase C low.
There are no inherent frequency limitations, although the IR2130 inserts a deadtime of 2.5 µs. If
this is a problem, a drop-in replacement, IR2132, is available with a deadtime of 0.8 µs. These
drivers also have an inherent delay, see datasheet for complete details. Voltage is limited to the
rating of the bootstrap diodes (75 V), the rating of the MOSFETs (55 V), and the rating of the bus
capacitors (63 V). To avoid damaging overshoots, the bus voltage should not exceed 40 Vdc.

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 BLDC Drive for ECE431
Design Document Issue 001 DD00002

3. Power Design

3.1 Gate Drive

The gate drive is an IR2130. The circuit is very simple, straight from the data sheet. The biggest
detail is the bootstrap supply. The isolation diodes are 1N4148, which are fast but only rated to 75
V continuous.

3.2 Inverter Bridge

The inverter bridge is composed of six IRFIZ48N MOSFETs. These are 55 V, 16 mΩ MOSFETs
in a TO-220 Fullpak (fully isolated). Rated θJC is 3.6 °C/W. These represent a significant step
forward in the newer design; the previous version used FETs with approximately 6x the on-state
resistance.

3.3 Thermal Design

The best explanation for the failures of the previous version was inadequate thermal design. It was
thought that the motor only required a few hundred milliamps. In fact, the motor is rated 2.5 Arms.
In light of the higher current requirement, it is obvious that the MOSFETs require some sort of heat
sink.
The total power dissipation in the bridge is:

Rds( on ) + (1.37 I rms ) Rsense

2
Ptot = 3I rms
2
(1.1)

The 1.37 factor accounts for the rectifier action of the control scheme implemented. With the
devices used, the approximate power dissipation is:
Ptot = 0.142 I rms
2
(1.2)

The heat sink chosen is the same one used in the FET box (see DD00003, FET Box 2003), an
Aavid 62200 extrusion cut to 3.75”. Given natural convection, it can dissipate 10 W at a 35°C rise.
This calculates to an RMS current limit of 8.4 A, which has been implemented as a peak current
limit of 12 A. In this situation, the MOSFET junction temperature rise over the sink temperature is
only 2°C, so the current limit yields a steady-state junction temperature of approximately 60°C in
the laboratory, an extremely conservative figure.

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 BLDC Drive for ECE431
Design Document Issue 001 DD00002

4. Troubleshooting
Always complete a visual scan over the entire circuit and PCB to look for any visual signs of
damage. Look for overheated or burnt components; look for cracked solder joints and bad
connections. Check to make sure all snap mounts are securely fastened to PCB jacks.
The motor drive takes a 12V dc input to provide voltage to the numerous IC’s in the circuit.
VSOURCE in the schematic is 11.0V-12.0V dc, and VCC is a 5V dc supply to power logic IC’s
and LED’s. The 0-24V dc input is to provide voltage to the 3 phase output.
Proper motor drive operation will produce an output waveform like Fig. 1 using the differential
probe. BNC outputs U, V and W provide an output of the Hall Effect sensors located in the
Brushless DC motor. They should be square waves with their frequency proportional to the speed
of the motor.

Figure 1: Typical Voltage Waveform, measured with differential probe

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 BLDC Drive for ECE431
Design Document Issue 001 DD00002

4.1 Troubleshooting Flowchart

I. Motor Does Not Operate

1. Is the switch above the green enable LED in the up position?
Yes: Move to number 2
No: Move the switch in the up position and start with number 1.

2. Is a 12V dc supply present at the input terminals labeled 12V?

Yes: Move to number 3
No: Apply 12V dc to input terminals and start with number 1.

3. Is a 0-24 V dc supply present at the input terminals labeled 0-24 V?

Yes: Move to number 4
No: Apply 0-24V dc to input terminals and start with number 2.

II. Faulty Motor Drive Output Voltage. (See Figure 1)

4. Check TP5; is the voltage applied to the input terminals labeled 0-24 V present?
Yes: Move to number 5
No: Is the voltage applied to the input terminals labeled 0-24 V present at J10?
Yes: Check diode D5 (replace if faulty)
No: Check the input voltage.

5. Check TP6 is there a square wave with voltage amplitude approximately equal to the
input terminals labeled 0-24 V?
Yes: Move to number 6
No: Move to number 8

6. Check TP8 is there a square wave with voltage amplitude approximately equal to the
input terminals labeled 0-24 V?
Yes: Move to number 7
No: Move to number 9

7. Check TP10 is there a square wave with voltage amplitude approximately equal to the
input terminals labeled 0-24 V?
Yes: Check the Brushless DC Motor.
No: Move to number 10

8. Check TP1 and TP7 is there two out of phase square waves?
Yes: Is resistor R2 and/or R3 open?
Yes: Replace faulty resistor(s)
No: Check transistors Q1 and/or Q4 (replace if faulty)
No: Move to number 11

9. Check TP3 and TP9 is there two out of phase square waves?
Yes: Is resistor R4 and/or R5 open?
Yes: Replace faulty resistor(s)
No: Check transistors Q2 and/or Q5 (replace if faulty)

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 BLDC Drive for ECE431
Design Document Issue 001 DD00002

No: Move to number 12

10. Check TP4 and TP11 is there two out of phase square waves?
Yes: Is resistor R6 and/or R7 open?
Yes: Replace faulty resistor(s)
No: Check transistors Q3 and/or Q6 (replace if faulty)
No: Move to number 13.

11. Check pin 2 and pin 5 on IC U1; are pin 2 and pin 5 a pair of out of phase 5V square
waves?
Yes: Check the voltage between pin 1 and pin 12 on IC U1; is there
approximately 11V dc?
Yes: Replace IC U1.
No: Check diode D4.
No: Move to number 14

12. Check pin 3 and pin 6 on IC U1; are pin 2 and pin 5 a pair of out of phase 5V square
waves?
Yes: Check the voltage between pin 1 and pin 12 on IC U1; is there
approximately 11V dc?
Yes: Replace IC U1.
No: Check diode D4.
No: Move to number 15

13. Check pin 4 and pin 7 on IC U1; are pin 2 and pin 5 a pair of out of phase 5V square
waves?
Yes: Check the voltage between pin 1 and pin 12 on IC U1; is there
approximately 11V dc?
Yes: Replace IC U1.
No: Check diode D4.
No: Move to number 16

14. Check pin 5 on logic IC U4; is there a 5V square wave?

Yes: Is pin 6 on logic IC U4 at 0V?
Yes: Move to number 17
No: Check J14 and Switch above enable LED.
No: Check J17 and male connection from motor, (Hall Effect sensors may be
faulty)

15. Check pin 8 on logic IC U4; is there a 5V square wave?

Yes: Is pin 9 on logic IC U4 at 0V?
Yes: Move to number 17
No: Check J14 and Switch above enable LED.
No: Check J17 and male connection from motor, (Hall Effect sensors may be
faulty)

16. Check pin 11 on logic IC U4; is there a 5V square wave?

Yes: Is pin 12 on logic IC U4 at 0V?
Yes: Move to number 17

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 BLDC Drive for ECE431
Design Document Issue 001 DD00002

No: Check J14 and Switch above enable LED.

No: Check J17 and male connection from motor, (Hall Effect sensors may be
faulty)

17. Check the voltage between pins 14 and 7on logic IC’s U4 and U3; is there 5V for the
logic gates?
Yes: Check operation of logic gates in U4 and U3 (replace if faulty)
No: Move to number 18

18. Check TP17; is 5V dc present?

Yes: Check the foil runs to logic IC’s U4 and U3 pins 14 and 7
No: Check the following components:
Diode D6
IC U2
Diode D4

BLDC Drive for ECE431 Status : Issued

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 5 4 3 2 1

D1 1N4148 TP12

C2 C5
D2 1N4148 10u 0u1 TP13
D D

Vsource
C3 C6
D3 1N4148 10u 0u1 TP14
GATE COMMANDS (~XIN) ARE ACTIVE LOW TTL

U1 C4 C7
~HIN1 TP1 10u 0u1
1 28 R2 10
~HIN2 VCC VB1
2 ~HIN1 HO1 27 G1
~HIN3 3 ~HIN2 VS1 26 E1
4 25 TP3
~HIN3 NC R4 10
5 ~LIN1 VB2 24
~LIN1 6 ~LIN2 HO2 23 G2
7 ~LIN3 VS2 22 E2
8 21 TP4
~LIN2 ~FAULT NC R6 10
C 9 ITRIP VB3 20 C

~LIN3 10 CAO HO3 19 G3

C10 C8 11 18
0u1 10u CA- VS3 E3
~FLT 12 VSS NC 17
13 16 TP7
VS0 LO1 R3 10
IDC 14 LO3 LO2 15
TP9 G4
VCC IR2130 R5 10
R9
TP18 TP11 G5
10k0
R7 10
G6
R13
330
EMITTERS
J12 R8
J12 GOES TO RED LED 10k0
B (HLMP3301) IN SNAP MOUNT B
1 R10 R11
2 (PIN 1 = ANODE) TP15
NOMINAL CURRENT TRIP POINT IS 12A PEAK (8.5A RMS)

MTA100-2
49k9 10k0

D6
J9 PROVIDES 12V FOR GATE DRIVE PURPOSES Vsource
VCC
D4 U2
J9 1N4004 TP17
1 1 IN OUT 3
2 COPYRIGHT 2003 BY JONATHAN KIMBALL
ALL RIGHTS RESERVED
1N4004
MTA156-2 LM7805C/TO220
A A
C11 C12 C15
MTH1 10u 10u 0u1 Title
R18 TP2 BLDC Drive for ECE333
1
Size Document Number Rev
TP16 A SK0014 1
10 R16 BREAKS GROUND LOOP
Date: Thursday, December 18, 2003 Sheet 1 of 4
5 4 3 2 1
 5 4 3 2 1

U4A U3A
VCC 2
1 1 2
3
74HC02 74HC04
D D

1
R15 U3B U3C
4k7 x7 Bussed
3 4 5 6

74HC04 74HC04
J17 IS BOARD-MOUNT FEMALE DB9

8
7
6
5
4
3
2
AVAILABLE IN ELECTRONICS SHOP
CONNECTS TO MOTOR

J17
U4B U3D
1 5
2 4 9 8 ~HIN1
3 6
4 74HC02 74HC04
C 5 ~LIN1 C
6
7
8
9 U4C U3E
8
10 11 10 ~HIN2
DB9_FEMALE VCC 9
74HC02 74HC04
~LIN2

HALLU R12 U4D U3F

HALLV 330
HALLW 11
13 13 12 ~HIN3
12
74HC02 74HC04
B B
~LIN3

VCC
J15

1
2
3 C13 C14
4 0u1 0u1
J13 J15 FOR MONITORING PURPOSES (NOT USED AT THIS TIME)

MTA100-4 1
2 J13 GOES TO GREEN LED (HLMP3507) IN SNAP MOUNT (PIN 1 = ANODE)

J14
MTA100-2
A 1 A
2
3 Title
4 BLDC Drive for ECE333
J14 IS A DPDT WITH CONTACTS 1-2 AND 3-4.
PROVIDES ENABLE (OFF = ALL LOW SIDE ON, Size Document Number Rev
MTA100-4 ON = COMMUTATES BY HALL FEEDBACK) A SK0014 1

Date: Thursday, December 18, 2003 Sheet 2 of 4

5 4 3 2 1
 5 4 3 2 1

J10 PROVIDES 0-24V BUS SUPPLY

D5 PROVIDES REVERSE POLARITY PROTECTION

POSBUS

D TP5 D
POSBUS

Q1 Q2 Q3
1

IRFIZ48N/TO IRFIZ48N/TO IRFIZ48N/TO

D5 G1 G2 G3
myMBR1045 E1 E2 E3
TP6 J6 18AWG
3

RED 1
J10
TP8 TP10
C 1 J7 18AWG C
2 C1 C9 WHITE 1
470u 470u

MTA156-2 J5 18AWG
BLACK 1

Q4 Q5 Q6
IRFIZ48N/TO IRFIZ48N/TO IRFIZ48N/TO
G4 G5 G6
50m
R1

J1 18AWG J2 18AWG
B EMITTERS 1 1 B

18AWG J3 18AWG J4
1 1

R1 IS NON-STANDARD PART (TO-220 -> PINS 1 & 3)

A A
J1-J4 PROVIDE FOR 18AWG JUMPERS TO COMPLETE EMITTERS NET
Title
BLDC Drive for ECE333
J5-J7 PROVIDE FOR 18AWG FLYING LEADS TO MOTOR TERMINALS
Size Document Number Rev
A SK0014 1

Date: Thursday, December 18, 2003 Sheet 3 of 4

5 4 3 2 1
 5 4 3 2 1

Vsource

R20
10
U5
D R23 D

2 7 J16 GOES TO 5 BNC CONNECTORS

HALLU INA OUTA TERMINATE INTO 1 MEG
4 INB OUTB 5
51
6 VS J16
HALLV
R19
1
MIC4426 2
3
51 4
5
6

U6
R24
J11 MTA100-6
HALLW 2 INA OUTA 7 1
C 4 INB OUTB 5 C
18AWG
51
6 VS J8
1

MIC4426 18AWG
R14

IDC
IDC NET NOMINALLY 0.1*Ibus (1.0 ON 10X SCALE)
51

R16 R21 R17 R22 R25

POSBUS
B B
124 124 124 124 54R9

POSBUS PROVIDES VOLTAGE SENSING

AFTER PROTECTION DIODE
GAIN OF 0.1 (1.0 ON 10X SCALE)

C17 C16
0u1 0u1

A A

Title
BLDC Drive for ECE333

Size Document Number Rev

A SK0014 1

Date: Thursday, December 18, 2003 Sheet 4 of 4

5 4 3 2 1
 PJ0005 Rev B
BLDC Drive for ECE431

Drawing Description PDF

DR0006 Heat sink, Aavid 62200, drilled and tapped pdf
DR0011 Heat sink mounting bracket pdf
DR0012 U-shaped Enclosure Base pdf
DR0014 Enclosure Lid pdf
DR0019 Front Plate with Jacks, v2 pdf
DR0021 Enclosure, second design pdf
DR0023 Baseplate for fixture pdf
DR0024 Vertical plate for fixture pdf

Copyright © 2004 by Jonathan Kimball, Robert S. Balog, Zakdy Sorchini, and Philip T. Krein.

All Rights Reserved. May be duplicated for educational use only so long as this notice remains intact.

http://www.energy.ece.uiuc.edu/blueboxes/BLDC_drive/pj0005_b.htm 9/14/2004
 4 3 2 1

D D

C C

.000

.375
.375

.000

.000 .000 .000

1.060 1.060
NOTES:

6-32 UNC - 2B x .500 MACHINE 10 PARTS FROM SUPPLIED HEAT SINKS

4 PLCS 4-40 UNC - 2B x .500
7 PLCS MATERIAL SUPPLIED ANODIZED AND SMOOTH:
TAKE CARE TO MAINTAIN FINISH OF MOUNTING SURFACE
B B
DE-BURR AS NECESSARY TO MAINTAIN FLAT SURFACES
2.810 2.810
2.945 THREAD DEPTH SHOWN IS APPROXIMATE

PART IS SYMMETRIC
.000
.250

.750

1.250

1.750

2.250

2.750

3.250
3.500

DRAWN
Jonathan Kimball 12/9/2003 University of Illinois at Urbana-Champaign
CHECKED
Scott McDonald 12/9/2003 TITLE
A QA A
MFG
Scott McDonald 12/9/2003 Heat sink, drilled and tapped
APPROVED
Rob Balog 12/5/2003 SIZE DWG NO REV

C PJ0005-DR0006 A
SCALE
SHEET 1 OF 1
4 3 2 1
 2 1

Copyright (c) 2004 by Jonathan Kimball.

All Rights Reserved. May be duplicated for
educational purposes only.

B B

n.156
.500

.063
.500

R.079

.625

.000

.750

1.000

2.750

3.000

3.750
DRAWN
Jonathan Kimball 6/23/2004 University of Illinois at Urbana-Champaign
CHECKED
Zakdy Sorchini 6/23/2004 TITLE
A QA A

MFG
Heat Sink Mounting Bracket
APPROVED
SIZE DWG NO REV

A PJ0005-DR0011 B
SCALE
SHEET 1 OF 1
2 1
 4 3 2 1

D D

C C

4.624

.063

B B

Copyright (c) 2004 by Jonathan Kimball. DRAWN

All Rights Reserved. May be duplicated for Jonathan Kimball 6/23/2004 University of Illinois at Urbana-Champaign
educational purposes only. CHECKED
Zakdy Sorchini 6/23/2004 TITLE
A QA A
MFG
U-Shaped Enclosure Base
APPROVED
SIZE DWG NO REV

C PJ0005-DR0012 B
SCALE
SHEET 1 OF 2
4 3 2 1
 4 3 2 1

D D

11.767

12.330

12.517
3.000

3.942

4.359

4.509

4.884

7.634

8.009

8.159

8.575

9.517
.000

.750

5.050
4.800
C C
4.550

.250

3.500

2.000
2.000

.875

.250
1.500

B B
.250
.000
.000

.875

1.000

1.625

2.375

3.000

3.125

5.134

7.384

9.392

9.517

10.142

10.892

11.517

11.642
Copyright (c) 2004 by Jonathan Kimball.
All Rights Reserved. May be duplicated for
educational purposes only.
DRAWN
Jonathan Kimball 6/23/2004 University of Illinois at Urbana-Champaign
CHECKED
Zakdy Sorchini 6/23/2004 TITLE
A QA A
MFG
U-Shaped Enclosure Base
APPROVED
SIZE DWG NO REV

C PJ0005-DR0012 B
SCALE
SHEET 2 OF 2
4 3 2 1
 4 3 2 1

D D

4.750
.000

.000
.063
.313
.563
.000 .000

.687 .750
.750

C 1.563 C

n.188

3.563
3.750 3.750
3.813

4.925 4.925

B B

Copyright (c) 2004 by Jonathan Kimball.

All Rights Reserved. May be duplicated for
educational purposes only.

DRAWN
Jonathan Kimball 6/23/2004 University of Illinois at Urbana-Champaign
CHECKED
Zakdy Sorchini 6/23/2004 TITLE
A QA A
MFG
Enclosure Lid
APPROVED
SIZE DWG NO REV

C PJ0005-DR0014 B
SCALE
SHEET 1 OF 1
4 3 2 1
 4 3 2 1

D D

1.329

1.579

1.912

2.079

2.546

3.421

4.046

4.750
.000

.579

.662

.000 .000 .000

.500
.625
.625
1.000
C 1.125 C
1.250
.250

1.625
1.875
n.250 2.125
2.337
R.164 n.188
2.625
2.837
R.195 3.000
.355

3.437

3.875 3.875

B B

Copyright (c) 2004 by Jonathan Kimball.

All Rights Reserved. May be duplicated for
educational purposes only.

4.750

.063
.500

DRAWN
Jonathan Kimball 6/23/2004 University of Illinois at Urbana-Champaign
CHECKED
Zakdy Sorchini 6/23/2004 TITLE
A QA A
MFG
Front Plate with Jacks, v2
APPROVED
SIZE DWG NO REV

C PJ0005-DR0019 B
SCALE
SHEET 1 OF 1
4 3 2 1
 4 3 2 1

D D

5.150

6.000
.000

.850

.125

.250
6-32 UNC - 2B x .500
1.100

4.900

6.000
.000

C C

.000

.925

MATERIAL: 0.250 ALUMINUM

4X n.141 THRU FINISH NOT IMPORTANT
INTENDED USE: FIXTURE
(4) HOLES ON SURFACE CLEARANCE FOR #6
(2) HOLES ON EDGE TAPPED FOR 6-32, DEPTH APPROXIMATE

B B
3.325

6.000

DRAWN
Jonathan Kimball 1/15/2004 University of Illinois at Urbana-Champaign
CHECKED
Scott McDonald 1/15/2004 TITLE
A QA A
MFG
Scott McDonald 1/15/2004 Baseplate for fixture
APPROVED
Jonathan Kimball 1/15/2004 SIZE DWG NO REV

C PJ0005-DR0023 B
SCALE
SHEET 1 OF 1
4 3 2 1
 2 1

1.500

2.000

2.500

3.000

3.500

4.000

4.500

5.150

6.000
.000

.850
2.000
1.760
B B
4-40 UNC - 2B

.125
.000
MATERIAL: 0.062 ALUMINUM
2X n.141 THRU
FINISH NOT IMPORTANT
INTENDED USE: FIXTURE
LOWER HOLES ARE CLEARANCE FOR #6
UPPER HOLES TO BE DRILLED AND TAPPED
THROUGH FOR 4-40

DRAWN
Jonathan Kimball 1/15/2004 University of Illinois at Urbana-Champaign
CHECKED
Scott McDonald 2/4/2004 TITLE
A QA A

MFG
Scott McDonald 2/4/2004 Vertical plate for fixture
APPROVED
Jonathan Kimball 2/4/2004 SIZE DWG NO REV

A PJ0005-DR0024 B
SCALE
SHEET 1 OF 1
2 1
Bill of Materials for PB0014 rev B
ECE Stores refers to the ECE Storeroom in 66 Everitt Lab
Elex Shop refers to the Electronics Shop in 265 Everitt Lab

Item Quantity Description Source P/N

1 30 470u ECE Stores 470uF 63V electrolytic radial
2 90 10u ECE Stores
3 30 MTA156-2 ECE Stores
4 30 MTA100-2 ECE Stores
5 30 MTA100-4 ECE Stores
6 15 MTA100-6 ECE Stores
7 15 4k7 x7 Bussed ECE Stores 4308R-1-472-ND
8 135 0u1 Elex Shop
9 45 1N4148 Elex Shop
10 30 1N4004 Elex Shop
11 135 18AWG Elex Shop 1", .85"
12 15 DB9_FEMALE Elex Shop right angle PCB mount
13 120 10 Elex Shop
14 45 10k0 Elex Shop
15 15 49k9 Elex Shop
16 30 330 Elex Shop
17 60 51 Elex Shop
18 60 124 Elex Shop
19 15 54R9 Elex Shop
20 15 LM7805C/TO220 Elex Shop
21 15 74HC04 Elex Shop
22 15 74HC02 Elex Shop
23 270 T POINT A Newark 52F782x
24 90 IRFIZ48N/TO Newark 16F6432
25 30 MIC4426 Newark 83F5988
26 15 MBR1045 Newark 06F9822
27 15 50m Newark 02H2373
28 15 IR2130 Newark 06F8692