1.11 SHORT QUESTIONS AND ANSWERS 1.1 What is a microprocessor ? ‘A microprocessor is a program controlled semiconductor device (IC) which fetches, decodes and executes instructions. 1.2 What are the basic functional blocks of a microprocessor ? The basic functional blocks of a microprocessor are the ALU, an array of registers and control unit. 13 What is a bus ? A bus is a group of conducting lines that carries data, address and control signals. Scanned with CamScannerrE vag Micnoprocessons ANo Micnoconrnoutens LA Define bit, byte and word. : Jamentl storage unitor A digit of the binary number or code is called a bit. Also, the bit is the fundamental s computer memory. eae The 8-bit(8-digid) binary number oF code is called byte and 16-bit binary number a an (Some microprocessor manufacturers refer the basic data size operate ae ses LS State the relation between the number of address pins and physical m mons a The size ofthe binary number used fo adress the memory eee physical memory Pie. Ifa microprocessor has n-address pins then it can directly address wa memory locations that are directly addressed by the processor are called physical memory space.) 1.6 Why és data bus bidirectional? | ‘The microprocessor has to fetch (read the data from memory or input device fo processing and after processing it has to store (write) the data in memory or output device. Hence th s 1.7 Why is address bus unidirectional? sor toe The address is an identification number used by the microprocessor to identify or access a memory location or 10 device. It is an output signal from the processor. Hence the address bus is unidirectional. L8 State the difference between a CPU and an ALU. ‘The ALU is the unit that performs the arithmetic or logical operations. The CPU is the unit that includes ALU and the control unit. Apart from processing the data, the CPU controls the entire system functioning. Usually a microprocessor will be the CPU of a system and it is called the brain of the computer. 1.9 — What is tristate logic? Why is it needed in a microprocessor system? Intristate logic, three logic levels are used and they are high, low and high impedance state, The high and low are normal logic levels and high impedance state is an electrical open circuit condition, Ina microprocessor system all the peripheral/slave devices are connected to a common bus But communication (data transfer) takes place between the master (microprocessor) and one slave (peripheral) at any time instant. During this time instant all other devices should be isolated from the bus. Therefore, normally all the slaves (peripherals) will remain in high impedanee sate (ie. in electrical isolation). The master will selecta slave by sending the address and chip select Signal. When the slave is selected, it comes to normal logic and it communicates with the master 1.10 What is HMOS and HCMOS? HMOS refers to High density n-type Metal Oxide Silicon field microprocessors are fabricated using HMOS transistors. HEMOS is High density ntype Complementary Metal Oxide Silicon field effect transistors. tis alow Fong enionef HMOS. Fourth generation microprocessors are fabricated using HMOS transistos. 1.1 What are the drawbacks of first generation microprocessors? are first generation processors are fabricated using PMOS technology and it has drawbacks like ia Slow speed, provides low output currents and was not compatible with TTL logic levels. 12 Whatisa microcomputer? Explain the difference between a microprocessor and a microcomputer. A system designed using a microprocessor as its CPU is called a microcomputer. The term 1B Wy mbutet refers tothe whole system, whereas a microprocessor is the CPU of the sy: 1.13 What is the function of the ‘microprocessor in a system? t ieeimicroprocessor is the master inthe system which controls all the activities ofthe over it cneentan fess and control signals and fetches the instruction and data from memory. *ecules the instruction to take appropriate action, effect transistors. The third generation Scanned with CamScannerChapter 1 Intro DUCTION To MicroPRocessons — Ld LIS 116 117 118 119 1.20 121 1.22 List the sofa mi ui components of a microprocessor-based (single board microcomputer) system. ae roprocessor-ased system consists of a microprocessor as CPU, semiconductor memories and RAM, input device, output device and interfacing devices. Why is interfacing needed for 10 devi Oaerally 10 devices are slow devices. Therefore the speed of IO devices does ni eed of @ microprocessor: And so an interface is provided between system Pus What is the difference between CPU bus and system bus? un CPU bus has multiplexed lines but the system bus has separate lines for each si multiplexed CPU lines are demultiplexed by the CPU interface circuit to form the sy What is multiplexing and what is its advantage? Mai jexing is transferring different information at different well defined times through the ines. A group of such lines is called a multiplexed bus. The advantage of multiplexing fewer pins are required for microprocessors to communicate with the outside world. How are the address and data lines demultiplexed in 8085? The low order address and data lines of 8085 are demultiplexed D-Latch (74L.$373) and the ALE signal of 8085, as shown in Fig. QUIS. the beginning of every machine cycle, ALE is asserted high and then low. Also, the low byte of address is given out through AD, ~AD, lines. Since the ALE is connected to enable of latch, whenever ALE is asserted high and then low the addresses are latched into the output lines of the latch then the lines AD, - AD, are free for data transfer. yot match with the and 10 devices. ignal. (The em bus.) same is that using an external 8-bit ‘8085 (CPU) —a-A ALE rin Fig. Q1.18 : Demultiplexing of address and data lines in 8085 processor. What do you mean by 16 and 8-bit processors? Mention a few S-bit and 16-bit processors. Processors are classified into 8-bit or 16-bit depending on the basic data size handled by the ALU of the processor. 8-bit microprocessors : 8085, 280, Motorola 6800. 16-bit microprocessors : 8086, 28000, MC68000. What is the fabrication technology used for 8085A? The 8085A is fabricated using NMOS technology and 808SAH is fabricated using HMOS technology. What is the physical memory space in an 8085? The 8085 uses 16-bit address to access memory locations. Hence it can directly address 64k ‘memory locations (2'°= 65.536= 64k). Since 8085 has 8 data lines, it can read/write 8-data bits from ‘memory address. Therefore the physical memory space is 64 k x Ibyte = 64 kilobytes (64 kb). Wheat is ALE? ‘The ALE (Address Latch Enable) is a signal used to demultiplex the address and data lines using an external latch. It is used as enable signal for the external latch. Scanned with CamScanner1.42 Michopnocessons Avo Micnoconmotiens 4.23 Explain the function of 10/M in 8085, The 10/M is used to differentia asserted high, For memory tef ¢ memory necess and IO access. For IN and OUT instruction itis fence instructions itis asserted low. 1.24 How is the READY si " How is the READY signal used in a microprocessor system? ‘The READY is an input signal that can be used by slow peripherals to get extra time in order tg communicate with a 8085, The 8085 will work only when READY is tied to logic high. Whenever READY is tied to logic low, the 8085 will enter wait state. When the system has slow peripheray devices, additional hardware is provided in the system to make the READY input low during the required extra time while executing a machine eycle, so that the processor will remain in wait state during this extra time. 1.25 What is HOLD and HLDA? How is it used? The HOLD and HLDA signals“are used for the Direct Memory Access (DMA) type of data transfer. This type of data transfers are achieved by employing a DMA controller in the system, When DMA is required the DMA controller will place a high signal on the HOLD pin of the 8085, When the HOLD input is asserted high, the processor will enter a wait state and drive all its tristate pins to high impedance state and send an acknowledge signal to the DMA controller through an HLDA pin. Upon receiving the acknowledge signal, the DMA controller will take control of the bus and perform DMA transfer and at the end it asserts HOLD signal low. When HOLD is asserted Iow the processor will resume its execution. 1.26 Howare clock signals generated in an 8085 and what is the frequency of the internal clock? “The 8085 has the clock generation circuit on the chip but an external quartz crystal or LC circuitor tthe pins X, and X, in order to generate a clock signal, The 8085 RC circuit should be connected at clock generation circuit generates a clock whose frequency is double that of the internal clock. The generated clock is divided by two and then used as an internal clock. The maximum internal clock frequency of 80854 is 3.03 MHz. 1.27 What happens to a 8085 processor when it is resetted? When RESETIN pin is asserted low, the program counter, instruction register, interrupt mask bits and all internal registers are cleared/resetted. Also the RESET OUT signal is asserted high to lear/reset all the peripheral devices in the system, After a reset the content of the program counter will be 0000, and so the processor will start executing the program stored at 0000, 1.28 What are the operations performed by the ALU of an 8085? The operations performed by ALU of an 8085 are addition, subtraction, logical AND, OR, Exclusive~ OR, compare, complement, increment, decrement and lefUright shift. 1.29 Mention the names of various registers in an 8085 along with its size. Register ‘Size (bits) | __Register ‘Size (bits) [Accumulator (A) : 8 Stackpointer - 16 Temporary register - 8 Programcounter - 16 Instruction register - 8 General purpose register - 8 (B,C,D,E,H andL) 1.30 What is a flag? The flag is a flip flop used to store information about the status of the processor and the status of the instruction executed most recently. Scanned with CamScannerCharter 1_Inrropuction To Micnopnocessons 131 1.33 134 135 1.36 1.37 138 139 1.40 141 1.42 1.43 oe 149 List the flags of an S088. ‘There are five flags in an 8085, They are the sign Mug, zero flap, cany flag Show the bit positions of various flags in an 8085 flag register, ‘The bit positions of various Mags in the Mag register of 8O8S is shown in Pig, QLL32 ‘wixitinry coy tay, pruity Hayy and DvD DDD, Dp, ee — ; . = 20 Zew Fay st [ze at | [er cr AP“ Autilart Cony Pag cr Cany Hg Fig. Q1.32 : Bit positions of various flags in the flag register of 6085, What are the Hardware interrupts of an 8085? The hardware interrupts in an 8085 are TRAP, RST7.5, RST 6.5 and RSTS.5, Which interrupt has the highest priority in an 8085? What is the priority of other interrupts? TRAPhas the highest priority, followed by RST7.5, RST6.5, RST'S.5 and INTR. Define stack. Stack isa sequence of RAM memory locations defined by the programmer. What is a program counter? How is it useful in program execution? The program counter keeps track of program execution, To execute a program the starting address of the program is loaded in the program counter. The PC sends out an address to fetch a byte of instruction from memory and increment its content automatically. How the microprocessor is synchronized with peripherals ? ‘The timing and control unit synchronizes all the microprocessor operations with the clock and generates control signals necessary for communication between the microprocessor and the peripherals. What are the additional features in Z80, as compared to an 8085? The Z80 has separate pins for data and address. The Z80 provides more register, extra addressing ‘modes, a larger instruction set than 8085 and it has built-in logic to refresh dynamic RAM memories. The Z80 has an indexed addressing mode. What are shadow registers of Z80? Each register of Z80 has an alternate register. The set of alternate registers are called shadow registers. How are the control signals classified in Z80? ‘The control signals of Z80 are classified into bus control, CPU control and system control signals. Mist the register pairs of Z80. ‘The registers pairs of Z80 are BC, DE, HL, B'C’, D'E' and H'L'. List the flags of 280. ‘The Z80 has six flags: 1. Sign flag (S and $")* 4, Parity/Overflow flag (PIV and P'/V') 2, Zero flag (Zand Z') 5. Hall carry flag (H and H') 3. Cary fag (C and C’) 6, Subtract fag (N and N') What are the common features of 8085 and 280? ‘The common features of 8085 and Z80 are the following: 1. Both are fabricated sing NMOS technology and have 40 pins 2. Memory is atcessed by 2 16bit address and the IO device by an B-it addess, 3. The 8085 is software compatible with 280, Scanned with CamScannerCE ———_—E—————————&x« Charten t_ternoovction Ropnocessons 1 4 What are the modes in which 8086 can operate? and maximum (or The 8086 can operate i ie in two modes: minimums (or uniprocessor) mode 15S What is the data and address size in $086? ‘The 8086 , é p us SOS6 can operate on either 8-hit or 16-bit data. The 8086 us lemory and a l6-bit address to access 10 devices What is the difference between $086 and 8088. The external La bus in 8086 is 16-bit and that of 8088 is 8-bi vords but the BORK uecess memory isin bytes 1.57 Explain the function of MAO in 8086. zx ‘The signal M/IO is used to differentiate memory address and accessing memory locations M/IO is asserted high and when itis accessing I iis asserted low, 158 What are the hardware interrupts of 80862 Z The hardware interrupts of 8086 are [NTR and NMI. The INTR i NMI is non-maskable interrupt. 1.59 How isa clock signal generated in 8086? What isthe maximum internal clo = “The 8086 does not have an on-chip clock generation circuit. Hence the elock generator chip 8234 is used to generate the required clock. The frequency ofthe clock generated by 8284s thrice that of the internal clock frequency of 8086, The 8284 divides the generated clock by three and modifies the duty cycle to 33% and then supplies as the clock signal to 8086. The maximum internal clock frequency of 8086 is S MHz. 1.60 What is pipelined architecture? Inpipelined architecture the processor will have a number of ZF functional units ae overlapped. Each functional unit works 1.61 What are the functional units available in 8086 architecture? ZZ Toe Bus Interface Unit B1U) and Execution Unit (EU) are the vo functional units available in 8086 architecture. 1.62. List the segment registers of 8086. AZ The segment registers of 8086 are Code Segment (CS), Data Segment (DS), Stack Segment (SS) 1.63 cs a 20-bit address to wecess eq the 8086 access memory is 10 address, When the processor is |O-mapped devices is general maskable interruptand ick frequency of 8086? functional units and the execution time independently most of the time. and Extra Segment (ES)registers. What is the difference between a segment register and a general purpose register? ‘The segment registers are used to store the 16-bit segment base addresses of the four memory segments. The general purpose registers are used as the source or destination register during data transfer and computation, as pointers to memory and as counters. 1.64 What is queue? How queue is implemented in 8086? “A‘data structure which can be accessed on the basis of first-in first-out is called queue. The 8086 7 has six numbers of 8-bit FIFO registers, which are used as instruction queue. 1.65 Write the flags of 8086, The 8086 has nine Nags: 1. Canny Flag (CF) 4, Zero Flag (ZF) 7. Trace Flag (TF) (or Single step trap) 2. Pasty Flag (PF) 5. Sign Flag (SF) 8. Interupt Flag OF) 3. Auxiliary cary Flag (AF) 6. Overflow Flag (OF) 9. Direction Flag (OF) Scanned with CamScannerMicnopnocessons Ano MicnoconTotiey, 1 2.40 2.4 SHORT QUESTIONS AND ANSWERS 2.1 What is a microcontroller? ailable as IC and capable of perforng 22 24 25 26 27 ‘A microcontrollers a programmable semiconductor device av arithmetic and logical operations. What are the basic units of a microcontroller? “The basic units of a microcontroller are the ALU, a set of register 10 ports, memory, timing any aan pot unit, In addition some of the controllers may have MEFS, ADC and DAC. Mention few differences between a microprocessor ‘and a microcontroller? a) mieroracessor i concerod wit the rapid moverent ef cade ‘and data botween the extornal Memory ang yy whereas a microcotraller is concerned with he roid movement of code and data within the contro, sor will have few bit manipulating instructions, whereas @ mictot large number of tit general purpose systoms, whereas mic processor, ii) A microprocess« ‘manipulating instructions, ii) Microprocessors are generally used for designing designing dedicated application specific systems. List the features of an 8051 microcontroller? The features of an 8051 microcontroller are: bit controller operating on bit and byte operand controllers are usd fy ‘Provides separate code and data memory address space © 256 bytes internal RAM and 4kb internal ROM @ 64/60 kb external program memory address space ‘© 64 kb external data memory address space ‘e Four numbers of 8-bit parallel ports ‘e One number of programmable serial port ‘Two numbers of programmable timers © Five members of vectored interrupts List the alternate functions of the ports of an 8051 microcontroller. Port pins | _ Alternate signal Description = P00 AD7-ADO Multiplexed low byte address/data, P2.7-P2.0 AIS-A8 High byte address P37 RD External memory read control signal P36 WR External memory write control signal P35 TI External input to timer 1 P34 To External input to timer 0 P33 INTi External interrupt 1 P32 into Extemal interrupt 0 P34 BD Serial data output el i) Serial data input List the interrupts of an 8051 microcontroller. fe Le aceon has five interrupts and they are (in the order of higher to lower prot) ipt-0, Timer-0 interrupt, External interrupt-1, Timer-1 interrupt and Serial port interurt What are dedicated address pointers in an-8051? The 8051 hi i (DPTR), The PC fe secre address pointers: Program Counter (PC) and Data Poin for data, ess pointer for programs and DPTR is used as an address pois Scanned with CamScanner2.41 28 29 210 2 212 213 2d 21S -1ou To Michoconrnotuena What are SER? (ers of a microcontroller dedicated for fied/defined functions and ped as internal data SERs (Special Funct aoa ee Registers) are internal re f can be used foray oer fneton In piesa les the SFR emery fl or any other function. In microcontrollers, the SFRS are ms Y and can be accessed by direct addressing. What are register banks in an 8051? ee eae “ internal RAM locations of 8051 which can be Fnizsd as F000 sepia aa epee, The fs 32 bytes of internal RAM of 8051 are organizes “0 alter b ith each bank consisting of eight locations. At any one time, the ProvestO™ rk with only one register bank depending on the value of bits RSO and RSI inthe PSW register. What is PSW in an 8051? ie flag register of an 805 1 is called PSW (Program Status Word). The PSW lags and two register bank select bits. The math flags are carry, auxiliary carm+ Parity flag, The register bank select bits are RSO and RSI. How is stack implemented in an 8051? The 8051 supports a LIFO (Last-In-First-Out) stack and the stack can reside anywhere in the internal RAM, The 8051 has an bit Stack Pointer (SP) to indicat the top of stack. The stack <8 be accessed using PUSH and POP instructions. During PUSH, the SP is ‘automatically incremented by one and during POP, the SP is automatically decremented by one. What are the operating modes of the serial port of an 8051? ‘The operating modes of the serial port of an 8051 are mode-0, rmode-0, the serial port functions asa half duplex serial port at fixed baud rate and one data character is framed as 8 bits. In modes 1, 2 and 3, the serial port can function as full duplex serial port. In modes T and 3, the baud rate is variable and in mode-I, the baud rate is either 1/32 or 1/64 of oscillator frequency. In mode-1, one data character should be framed as 10 bits, and in modes 2 and 3, one data character is framed as 11 bits. How is the baud rate decided in modes 1 and 3 of serial transmission in an 8051? In serial transmission modes 1 and 3 of 8051, the baud rate depends on the SMOD bit of PCON register and the timer-1 overflow rate as shown below: S100 “The baud rate in mode I or 3 = 237 (in modes I and 3) used as general purpose consists of four math overflow and mode-I, mode-2 and mode-3. In x (Timer-I overflow rate) What are the operating modes of the timer of an 8051? “The operating modes of the timers of an 8051 are mode-0, mode-1, mode-2 and mode-3. In mode-O the timers will function as 13-bit timers and in mode-1 the timers will function 16-bit tt mode-2 the timers will function as 8-bit timers with auto reload feature. Timer-0 alone can work in mode-3 and in this mode the TLO will function as an 8-bit timer controller by standard timer-O control bits and THO will function as 8-bit timer controlled by timer-I control bits. List the features of an 8096 microcontroller. ‘The features of 8096 microcontroller are: ‘© 16-it controller operating on bit, byte and ward operands ‘© 16tit arithmetic operations including multiply and divide 256 bytes internal RAM and 8b internal RAM/EPROM Total address space of 64Kb organised either as one bank of 64Kb or two banks of 32 kb each i ADC Sechannol, 1 Scanned with CamScanner= Micnopnocessons Ano MIcRoconTRoLtens = PWM output ‘© One number of 16-bit timer, one number of 16-bit counter and four numbers of software timers © Serial port with own baud rate generation ‘© High speed input and output lines 2.16 What is power down RAM? FO, to FF, will 5 ‘1 : ss range u Will rece} Inan 8096 microcontroller, the 16 bytes of internal RAM in eae fs thr ea ‘down RAM ower through a separate pin called V,,,,. These memory fi 7 1 F on intained through a separate small batter because supply to these RAM locations can be mai 2 : mat backup supply so that the content of these RAM can be preserved during power failure conditions, 2.17 What are the functional blocks of RALU in an 8096? The functional blocks of RALU (Register ALU) of an 8096 micr: byte of PSW, Program Counter (PC), incrementer, loop counter, unit and stored constants. 2.18 What is Watchdog Timer (WDT)? The Watchdog Timer is a dedicated timer to take care of the controller during software malfunction, which is re will have facility for enabling or disabling the WDT. When the i Hi hardware reset, whenever it overflows. In order to avoid a reset during normal conditions, the software should take care of clearing the WDT well before it overflows. 2.19 Write a short note on the PWM generator of an 8096 controller? The 8096 controller has an internal PWM generator which can generate fixed frequency and variable duty cycle waveforms. The frequency is fixed at 15.625 kHz for a 12 MHz clock speed. Th duty cycle can be varied from 0% to 99.6% by writing an 8-bit value in the PWM register. 2.20 What are HSI and HSO lines? The High Speed Input (HSI) lines are input lines to an 8096 microcontroller that can be used t record external events and the time at which the event has occurred. The High Speed Output (HSO lines are output from microcontrollers through which the controller can generate time-based signal to initiate various programmable events like turning the ON/OFF a device, start/stop a process, et ocontroller are 17-bit ALU, high three temporary registers, delay system malfunction. It can be used to reset ferred to as "hanging". A microcontroller WDT is enabled, it will initiate a Scanned with CamScannercron Ser Or 8085 12 3.1 SHORT QUESTIONS AND ANSWERS JL Define mnemonics. The short-hand for crihing the instructions are called mne and form of des i ae F describing the instructi talted mnemonics. Th ‘en by the manufacturers of microprocessors and programmable devices: 4.2 What is processar cycle (machine eycle)? The processay sor cycle o ti Toetboutoen, ee machine cycle is the hasic external operation pe ction, the processor will run one or more machine cycles ina ye mnemonics are formed by the processor. particular order. 33 What is instruction eycte? instruction is hile executing an fF a number of The sequence of ‘quence of operations that a processor has to carry out consists of called instruction cy fa processor in jon cycle, Each in cycle of i « eet nstruction cycle of a processor in (1 What is fetch and execute cycle? In general, the instruction cycle of an instruction can be divided into fetch and execute cycles. The fetcheycle is excouted.to fechheoprode rom memory. The execute cycle sexeculese |? seo the instruction and to perform the work instructed by the instruction. “ 3.5. Listthe various machine eycles of 8085. : ‘The various machine cycles of 8085 are: (i) Opcode fetch cycle Gi) Memory read cycle (i) Memory write cycle {iv) 10 read cycle (uh 10 write cycle (vi) Interrupt acknowledge cycle ) Bus idle cycle 3,6 What is the need for a timing diagram? ‘The timing diagram provides information regarding the status of various signals, when a machine tial for a system designer, to select cycle is executed. The knowledge of timing diagram is essen matched peripheral devices like memories, latches, ports, ete» 10 form a microprocessor system. 3.7 What is T-state? ‘The Testa is the time period of the internal clock signal ofthe processor The time taken by the processor to execute a machine eycle is expressed in T-state. 48 How many machine eyeles constitute one instruction cycle in an 8085? les. Each instruction of the 8085 processor consists of one to five machine cyc! 3.9 Define opcode and operand. Opcode (Operation code) is the part Operand is a part of an instruction/di 3.10 What is opeode fetch cycle? uted to fetch the opcode of an instruction stored ‘The opcode fetch cycle is a machine cycle exec in memory, The first machine cycle of every instruction is the opcode fetch machine cycle. 3.11 What operation is performed during first T-state of every machine cycle in 8085? In 8085, during the first Tstate of every machine cycle, the low byte address is latehed into an external latch using ALE signal. sion/directive that identifies a specific: ‘operation. of an instruct cts. rective that represents a value on which the instruction a bein Scanned with CamScannera wae ait aus 36 37 318 3.19 3.20 3.21 3.22 3.23 Micnopnocessons An ——AEROPHOEESSORD AND Micriong,. 4 ho Ly sors? _ system designer to track the i Sry expansion (by providing sy ; Why are status slenaly provided in microproce “The status signals can be used by th processor, Also, iL can be used for me nternal operation, arate el of proatam and data, and selecting the banks using status signate), ee Memory Danis How dors the S088 processor differentiate memory accexs (read/write) ana 10 (readhwritey? ee, The memory access and 10 access is differ rentiated using IO/M signal . The 8085 pro, Operation and [O/M is asserted high, for 10 reat Wig sor output the 10 port address during an 10 recy, i asserts 10/M low, tor memory read/write operation, In which lines does the 8085 proc operation? When the processor executes an 10 read or write cycle, an 8-bit port address is se nt out the low order address bus and the high order address bus, This facility offers a Alexibility forge System designer, to use either low order address lines or hi igh order address lines for Addressnt Ports and generating chip select signals for 1O devices, ’ When does a 8085 processor check for an interrupt? In the second T-state of the last machine cycle of every instruction, the 8085 processor cheeky Whether an interrupt request is made or not What is interrupt acknowledge cycle? ‘The interrupt acknowledge cycle is a machine of the interrupt to get the address of the interru device, cle executed by an 8085 processor aft et Acceptance pt service routine in-order to service th © interrupig What will be the status of the processor during bus idle cycle? During bus idle cycle, the status signals S, and S, are both asserted low and data, addr address and cont Pins are driven to high impedance state. Also, the processor will not. sample the READY signal, How are the stow peripherals interfaced with an 8085 Processor? The slow peripherals require longer readAvrite time than allowed by the processor. Hence iy interface slow peripherals, an extra hardware should be designed, so that, it introduces the Tequired number of wait states in machine cycles between T, and T,. An alternate solution isto interface the slow peripherals using ports, When is the READY signal sampled by the processor? ‘The 8085 processor samples or checks th What are wait states? The T states introduced between T, a extra time for read/write operation) ar When will the 8085 processor enter The 8085 processor 1e READY signal at the second ‘T-state of every machine cycle. ind 7, of a machine cycle by the slow peripherals (#4 'e called wait states, wait state? will check the READY. signal at the second READY is tied low at this time, then it will The processor will come out of the wait st T-state of a machine cycle. Ifte H enter into the wait state (ie., after the second Tt) ‘te only when the READY is again made high. ‘What is the difference between wait state and bus idle condition? During bus idle condition, the tristated ping of the but during wait state they are in norma during the bus idle condition, but itis How many instructions are a Prosessor are driven to high impedance I states (either low or high). The READY #s not sa sampled during the Wait state. vailable in the 8085 instruction set? ists of 74 basic instructions and 246 total instructions. Scanned with CamScanneruspren3_Instnuerion Ser Or a0n5 3.59 jad What isthe instruction format ofan $085? The size of an 8085 instruction i: 3 . mis 1 to 3 bytes ning bytes are ci “nt, remaining bytes are cither data or address. The format of 8085 instructions a Bach instruction has one byte opcode. The ire shown below: One byte instruction Tesa3z10 76543210 Two byte instruction — : : opeode it dataadress ; 76543210 76543210 76543210 Three byte instruction: ‘opeade Low byte davadess] [rth byte datafakdess oe ped 3.25 What is addressing? Te method of specifying the data to be operated (operand) by the instruction is called addressing What are the addressing modes available in 8085? ‘The 8085 has the following five different modes of addressing: Immediate addressing i) Direct addressing ii) Register addressing iv) Register indirect addressing v) Implied addressing. 4327 Explain immediate addressing with an example. In immediate addressing mode, the data is specified in the instruction, itself. The data will be @ part of the program 3.26 instruction. Example : MVI_B, 3EH '- 3.28 What is direct addressing. Give an example. is directly specified inthe instruction, then the addressing mode is called direct addressing Move the data 3E, given in the instruction to B-register the address of the data i Example: LDA 1050H - Load the data avaible in memory location 1089, in accumulator. 3.29 Explain register addressing with an example. In register addressing mode, the instruction specifies the name of the register in which the data is available. Example : MOV A,B - Move the content ofthe Begister to theArepister. 4.30 Explain register indirect addressing with an example. Inregster indirect edressing mode, the instruction species the name of th register in whch the adress of the availble. Here, the data will be in the memory and the address wil bein the register pair ‘ofthe memory whose address is available in the HL pair is moved to the A-register. data is Example : MOV A, M - The content 431 What is implied or implicit addressing mode? ‘tthe instruction operates on a data. ‘available in the register is defined by the opcode, then the addressing mode is called an ‘nplied or implicit addressing mode. Example : CMA - Complement the content of the accumulator. Scanned with CamScanner3.60 3.32 3.33 3.35 3.36 3.37 3.38 3.39 3.40 341 3.42 MICROPROCESSORS OO CRO CONTROL, iy instruction? Give an example an What arethe functions performed by the data transfer insruction O07 exaote andar oti 0 Tho dato transfer instction can copy tho content of on register 1 aot “Ortog, merry ooo vores Example ; MOV B, C - The contont What are the functions performed by The functions pertrmed by atetc instructions ere Aton, S ded to accumulator 1 instructions? Give an example and explain What are the operations performed by logical The operations perormed by lice nections arvAND, OR, EXLUSIVE-OR, Complement, Compare and St iy Example: ANA D ~The confnt of he Deiter is logialyANDed wih he accumulator In which unitare the arithmetic and logical operations performed. Which unitis the destinayyy ofthe Ceregisar is moved (copied) (0 thoB-register ‘arithmetic instructions? Give an example and expiq,,, subtraction, Increment and Decrement. Example : ADD E - The content o the E-register Is a of the result. | “The arithmetic and logical operations are performed in ALU- After the operation, the result wily stored in the accumulator. Which group of instruction affects the flags? “The flags are altered after execution of the arithmetic and logical instructions. What are the arithmetic instructions that do not affect the flag? The 16-bit increment and decrement instructions (INX rp and DCX rp) will not affect any flag What are the flags affected by 8-bit increment and decrement instructions? Except carry, all other flags are affected by 8-bit increment and decrement instructions. What will be condition of the flags after logical AND and OR operations? ‘After logical AND operation, the carry flag is RESET (0), the auxiliary carry flag is SET (1) ang depending on the result of AND operation other flags are altered. ‘After logical OR operation, the carry flag and the auxiliary carry flag are RESET (0). Depending on the result of OR operation other flags are altered. List the instructions that affect only carry flag. The instructions that affect only carry flag are the following: omc RAR ste DAD ip RLC RAL RRC What is DAA ? DAA stands for Decimal Adjust Accumulator, After BCD addition, this instruction is executed, to get the result in BCD. When DAA instruction is executed, the content of the accumulator is altered or adjusted as explained below: , ‘ the sum ofthe lower rites exceeds 09, or auriary cary is set, a correction 06, (0110) is added tothe lower ne i) _! the sum of the upper nibbles exceeds 09, o cary is set, a correction 06, (0110) is added to the upper nb wee is DAD and what are the flags affected by this instruction? refers to Double Addition. This instruction is used to perform addition of two 16-bit da!2 Syntax : DAD rp Th vate gh 7a e content of register pair (rp) is added to the content of HL pair. After addition, the result! be in HL pair. The register pai camry flagis affect at can be BC, DE, HL, or SP. On execution ofthis instruction, oY Scanned with CamScanner i443 List the various instrnetinn aad BAS 3.46 347 348 349 3.50 351 352 he used to Ned t0 clear the accumulator ? ‘The accumutatr ¢ the fale "© following. instruction: 1. MVE A00, 2, SUBA 3. ANI 00, 4, XRAA What isthe similarity and difference p ™ i nee bet Similarity: Both suction se ENC sear compare acneon? ¢ alteres KF compatiso ¢ per fags are allered depending npn ihe eh me Peon hy surat wo datain ALU Ad Difference : After subtract instruction i the execution ofthe compare insinterny eu ‘uted, the resultis stored in the accumulator, but after the content of destination repivce “ot the result is discarded ( .¢., the subtract instruction alters conten of any registeror memoyy) nelson ba the compare insti will not alter the List the 10 instruction in an 8085, The 0 instruction of 8085 are WY adie and OUT add (@ The IN instruction is used to i input a de i ic data byte to the 10-mapped 4 ng wot ve {rom the 10-mapped dovica or port. The QUT instruction used to output State the differences between LDA and LDAX. The LDA instruction “ ae Seo sire addressing mode to load a data byte from the memory to the secu bat struction uses register indirect addressing for the same operation. ion the content of the memory locati ¢ is givenin the i i eal he ee ry location whose address is given in the instruction aed a a register pair contains the address of the memory location. The content of the memory location whose address is available in the register pair is moved to the accumulator. Explain DI and El. DI - Disable Interrupt, When this instruction is executed, all the interrupts except TRAP are disabled, When the interrupts are disabled, the processor will not accept or recognize the interrupt. EJ- Enable Interrupt. This instruction is used or executed to allow the interrupts after disabling. What is the function performed by SIM instruction? SIM-Set Interrupt Mask. The SIM instruction is used to mask the hardware interrupts RST 7.5, RST6.5 and RST 5.5. The execution of SIM instruction output the content of the accumulator to program interrupt mask bits and also used to output serial data on the SOD line. What is the function performed by RIM instruction? RIM- Read Interrupt Mask. The RIM instruction is used to check whether an interrupt is masked or not. It is also used to read data from the SID line. What will be the state of the processor after executing an HLT instruction? When the HLT instruction is executed, the processor suspends program execution and bus will bein idle state (.e., the processor keeps on executing bus idle cycle until a reset or interrupt). What is NOP? State its importance. The NOPis a dummy instruction, i neither achieves any result nor uffects any CPU register. This isused for producing software delay and reserve memory spaces fr future software modifications. What is PSW? jegister and accumulator together is called PSW. Flag PSW - Program Status Word. The flag a ! register is a low order register. The accumulator is a high order register, Scanned with CamScanner3. 62 353 354 3.56 3.57 3.58 3.60 3.61 3.62 Microprocessors ANo Microcontoy, >. er Explain RET instruction. RET - Return to main program. This instruction is placed at the end of the subroutine progr, order to return to the main program, When this instruction is executed, the top of the gant poped to the program counter. ki Explain the difference between the conditional and unconditional return instructions, Inaconditional return instruction, a flag condition is tested. If the flag condition is true, then ygram control returns to the main program. Ifthe flag condition is false, then the next instruc isexecuted. In unconditional return instruction, the program control returns to the matin progr irrespective of the condition of the flag. . State the difference between STA and STAX instructions. The STA instruction uses direct addressing mode, to store the c memory location, but the STAX instruction uses indirect addressing mode for the same operation, What will be the content of the SP (Stack Pointer) after execution of PUSH and POP instructions, be 02 less than the earlier value, ontent of the accumulator toa © Alter execution of PUSH instruction, the content of a stack pointer (SP) will © After execution of POP instruction, the content ofthe stack pointer (SP) will be 02 greater than the earlier vay, What is the difference between ADD and ADC: instruction? . The ADD instruction will not consider the value of the carry flag for addition, but the Apc instruction will consider the value of the carry flag (before executing this instruction) for addition, In ADC instruction, the content of the register or memory and the carry flag are added to the content of the accumulator. How is subtraction performed in an 8085? The 8085 processor performs 2's complement subtraction and after subtraction, it complements the carry flag. How can the result of subtract operation be interpreted? ‘© After subtract operation, if the carry flag is SET (1), then the result is negative and result will be in 2's complement form, © After subtract operation, if the carry flag is RESET (0), then the result is positive. What is the difference in 2’s complement subtraction and 8085 subtraction? In 2's complement subtraction, the result is positive, if the carry is equal to one(1) and negative, if the carry is equal to zero(0). But in 8085, the result is negative, if the carry is equal to one (1) and positive, if the carry is equal to (0). What is the difference between CALL and JUMP instruction? In CALL instruction, the address of the next instruction is pushed to the stack (i.e., stored in the stack memory) before transferring the program control to the call address. But in JUMP instruction, the address of the next instruction is not saved. What is the difference between conditional and unconditional branch instructions? In unconditional branch instructions, the program control is transferred to the branch address without checking any flag condition. But in conditional branch instructions, a flag condition is checked and only if the flag condition is true, the program control is transferred t the branch address, otherwise the next instruction is executed. Scanned with CamScannervv 4 4.14 SHORT QUESTIONS AND ANSWERS | 4.1 What is the size of an S086 inctruction? “The size of an 8086 instmiction is one to six bytes bil indicators. The second byte will specify the ad bytes will specify the immediate data or address. 4.2 Write the general format of S086 insruction? The general format of 8086 instruction is shown in Fig. 4.2. «The first byte consists of the opcode sing Idressing mode of the operands, The subse ht ey, e-5 Bytes} Ryte-2 Bytes 3 Byte-4 Bye Byte. 5 edsaaa10 Vesa id 765493210 76549410 76549210 765435, opeente fof] frog] ree [vm ] LL, hatispidats roaieprta, |], bata hivdon Fig. 04.2 : General format of 8086 instruction. 4.3 What is addressing? “The method of specifying the data to be operated (operand) by the instruction is called addres 44 What are the addressing modes available in 8086? The 8086 has the following 12 addressing modes: Based index addressing String addressing ‘i Repister addressing ii) Immediate addressing ii) Diroct addressing in) Direct 10 port addressing iw) Register indirect addressing x) Indirect 10 port addressing W) Based addressing xi) Relative addressing vi) Indexed addressing xii) Implied addressing 4.5 What is register addressing? Give an example, In register addressing, the instruction will specify the name of the register which holds the data to be operated ty ts instruction. Example : MOV CX, DX - The content of the DX-register is moved to the CX-registec 4.6 What is immediate addressing? Give an example. In immediate aatdressing mode, an 8-bit or 16-bit data is specified as part of the instruction. Example : MOV BX, OCASH - The 16-bit data (0CAS,) given in the instruction is moved to the BX-register 4.7 Explain direct addressing in 8086? {In direct addressing, an unsigned 16-bit displacement or signed 8-bit displacement will be specified in the insracon displacement is the effective address of the data, The 20-bit physical address of the data is computed by muitiping® content of the DS-repster by 16, and adding to the effective address. Example : MOV CL, (OF2AH] - The memory address is computed by muttiplying the content of the DS-register by’ 14,3 ‘adding the 16-bit dsplacement (OF2A,) given in the instruction. Then the content of the memory is moved to the C95 4.8 Explain register indirect addressing in 8086? In register indirect dressing, tho name of he register hich holds the effective address of the data willbe speed —_ Uh oset ‘used fo hold the effective address are BX, SI or DI. The 20-bit physical address of he Example if ‘lovee {ho conten ofthe S-regiser by 16, and adding ito the effective address. Zena Te mony tes cl gaia ty muting cote oS ete ating th content of th Otregister The content ofthe memory is moved fo the DX-register Scanned with CamScanneruw a all an 7) ay 4 iwsraverion Ser Or 8008 —— 4.85 in 8086, plain based adres atrssing the olfcto adarocs ofthe dat rte erate naa male adeno ea a ei ef the DS gist by 16, and add # to tho a ‘the 20-bit physical address of the data is calculated by multplying wr dt casted by muting be cone ve address. When BP holds the basa value, the 20-bit physical aes res mabe th font ofthe SS-regitor by 16, and adding othe effective adress. cample H [BP * » The effective addross is comput i ee ecto coiet of te BP register The 2. eae ed by adding the 16-bit displacement (0042, given acid ott fi ete sical address is obtained by multiplying tho content ofthe soregister bY 16, ing i to the efective address. The conten! cr ‘memory is moved tothe CX-ogistee xplain indexed addressing in 8086, the eff in ss toe, 7 pane ioe a La sae is specified as a sum of the index value and displacement. The ste vale. Tho 20-bi physica address of th the content bi Ds-egisler by 16,, and adding it to the effective address, a aoa example: Wak eee - me effective address is computed by sign extending tho B-bi displacement given in the fo 16-bit ar bee vi fo the content ofthe DI. The 20-bit physical address of memory is computed by multiplying the certental the DS register by 16, and ading othe effective edess. The content ofthe memory is moved theAX register hat is based indexed addressing? Give an example. Indssed indexed addressing, the effective address is specified as a sum of the base value, index value and displacement. ‘hebase value is stored in the ‘BX or BP and the index value is stored in the SI or Dl-register When BX holds the base value ofthe effective address, the: content afte 'DS-register is considered as a segment base address and when BP holds the base var, the content ofthe SS-registeris considered asthe segment base address. Te Zoi physical address is computed by multiplying the segment base address by 16, and adding tothe effective adress Example: MOV CX, [BP + D!+ O1AOH]- The effective address is computed by ading the contents ofthe BP-egister the iregster and the 16-bit displacement (0140) given in the instruction. The 20-bit physical adoress of the memory is ‘computed by multiplying ‘the content of the SS-register by 16,, and adding it to effective address, The content of the memory is moved to the CX-register Explain string addressing in 8086. 1n 8086, the string addressing is used by string instructions to address the source and destination opeanddata. In this mode, the SI-register is used to hold the effective address of the source data and the DI-register is used to hold the effective address of the destination. The memory address ofthe source is obtained by multiplying the content of the DS-register by 16,, and adding it to the effective address (content of SL-register). The memory address of the destination is obtained by ruliplying the content of the ES-register by 16,, and adding it to the effective address (content of Ditegister).After execution of the string instruction, the content of the SI and DI are incremented or decremented depending on the direction flag. How are 10 ports addressed in an 8086? ‘The 10 ports in an 8086-based system can be addressed either by direct addressing or by indirect addressing. In direct addressing, an 8-bit port address is directly specified in the instruction. In indirect addressing, a 16-bit port address is stored in the DX-register and the name of the register (OX) is specified in the instruction. What is relative addressing? lnrlatve ‘addressing, the effective address of @ program instruction is specified | sired displacement. Example: Jc OF 2H - ifthe cary flag is one, then a new effective address is calculated and loaded in the instruction Fos The new efectve address is oblained by sign extending the €-bit displacement (FZ) given inthe instruction and 24810 he content of th instruction pointe relative to the instruction pointer by an 8 Scanned with CamScanner ll4.16 417 418) 419 4.20 4.21 4.22 4.23 4.24 4.25 Mucnornocess0ns AND Micnocontng, N Wy 3d by the instruction, {1 impiodexdressing mod, tho instruction fsa wil speci th deta fo bo operated by Example : CLO - Clay Dirctonfg. Lis the data teansfer insects tha ffs the asim on BA set the flags are POPE : in tn 806, the da transfer nsrtonsafeeting the Mags are PO ae li is used to restore the previously stored status of the flag. iy y content of the fag register. List the instructions of an 8086 that affect only the carry flag. ‘The instructions that affect only the carry flag are CLC, CMC and STC. List the instructions of 8086 that affects direction flag. . ‘The instructions that affects direction flag are CLD, POPF and STD. List the instructions of 8086 that affects interrupt flag. ‘The instructions that i interrupt flag are CLI, INT, INTO, IRET, POPF and STI, What are the operations performed by data transfer instructions? ‘The operations performed by the data transfer instructions are: Copy the content of a register to another register. i) Copy the content of a registerisegment register to memory or vice versa. in an 8086. iii) Copy the content of the accumulator to the port or vice versa. jv) Exchange the content of two registers or repister and memory. v) Load an immediate operand to the register/memory.. vi) Load an effective address in the segment registers. What are the operations performed by arithmetic instructions? The operations performed by arithmetic instructions are: ’) Addition or subtraction ofthe binary, BCD or ASCII data Multiplication or division of signed or unsigned binary data Increment or decrement or comparison of binary data What are the operations performed by logical instructions? The operations performed by logical instructions are AND, OR, Exclusive-OR, complement, artnet: shift and logical shift What are the operations performed by string instructions? The operations performed by string instructions are: 1) Copy a bytelword of a string data from the data segment to the extra segment, 1 Compare the contents of two memory locaton or accumulator and a memory location, __ Load a bytelward of a sting data fom the memory to accumulator or vice-versa, List the string instructions of 8086. The string instructions of 8086 are RE 'PZ/REPE, REPNZ/REPNE, SW, CNB GHPSW. SCASB, SCASW, LODSB, LODSW, STOSB and STOSW oe be the content of the stack Pointer (SP) after a PUSH operation and after a POP. pert! | What wit, The-PUSH Operation will d ot the content ofthe SP will be fan me coe coment Of the SP by two and so after a PUSH | Scanned with CamScannerp 4 Insraucrion Str Or 8086 aa queen os the 10 instructions of 8086, 428 10 instretions of 8086 are: ) WA, adle8 i) OUT adr, A a INAIOX) 1 OUTIOXL a N instruction is used to load a byte/word ; Te Fm se 10 Sen hl fm eee eee ame OUT 1 Baplin the instruction LEA regl6, mem, 427 se instruction LEA is used (0 load the effective address of the memory operand to the register specified in the instruction. (i.e., this instruction will not load the content of the memory in the pepister but the calculated effective address of the memory data is loaded in the register) How can the low byte flag register be modified in 8086? ‘The low byte of flag register can be modified by moving an 8-bit data to the AH-register and then moving the content of the AH to a low byte flag register using SAHF instruction. How can the 16-bit flag register be modified in 8086? fn ‘Te steps involved in modifying the 16-bit flag register are avg sgjovk g2 3 4) Fist, move @ 16it data to a 16-it reise. i) Second, save the content of the register in the stack using the PUSH instruction, i) Finally, move the top of the stack tothe flag register using tho POP instruction How is subtraction performed in 8086 and how can the result be interpreted? ‘he 8086 processor performs 2's complement subtraction and after subtraction, the carry flag is complemented. Therefore, the result of subtraction can be interpreted as follows i) After subtraction if the cary flag is sete. CF ~ 1, then the result is negative and the result wil be in 2's ‘complement form. i) after subtraction ifthe carry log i cleaedteset (ie, CF = O, then the result is positive. What is the similarity and difference between subtract and compare instructions? Similarity + Both the subtraction and comparison are performed by subtracting two data in the ALU and the flags are altered depending upon the result Difference: After the subtract operation, the result is stored in the destination register/memory, but after the compare operation the result is discarded. That will be the status of flags after division and multiplication operations? The division and multiplication operation will modify all the six arithmetic flags (CF, AP, PF, ZF, SF and OF flags) but all these flags will be in an undefined state after the division and multiplication we 40 4 4a operations, 443 What is the difference between Compare and Test operations in 8086? Jn Compare operation, the content of the register or memory is subtracted from the content of auwiher register and the result is used to modify the flags. In Test operation, the content of the register or memory is bit by bit ANDed with the content another register and the result is used to modify the flags. |n both Compare and Test operations, the contents of the source and destination are not altered. What is the difference between arithmetic shift and logical shift? {a logical shift operation, zero is inserted in the shifted location (i-e., zero is inserted in the LSD Position for left shift and for right shift zero is inserted in the MSD position). eatihietc left shift operation is same as logical left shift whereas in arithmetic right shift mie the sign bit is copied into the shifted location, ie. afer every right shift the old value of ost Significant Digit) is copied into the current MSD location. 44 Scanned with CamScanner4.88 4.35 4.36 4.38 4.39 4.40 Mcnorrocessons ANO Mienocormna. ay What is the difference between shift and rotate operation? —— ; In shift operation either zero or one is inserted in the shifted location a in rotate oper, only the content of the register/memory with or without carry are rotated, (ie iM rotate operas” there is no insertion of extra bit in the shifted position.) "m What is near call and far call? same code segment memory in Which the» re stored in the i to calling a procedure stored in a differen, % te Near call refers to calling a procedu Far call refers program (or calling program)resides. segment memory than that of the main program. . While executing near call instructions, the content of the TP alone is pushed to the stack, yy, executing far call, the contents of the CS ‘and IP are pushed to the stack. le What is the difference between CALL and JUMP instruction? In CALL instruction, the address of the next instruction is pushed to stack (1.e., stored in the raemory) before traniferring the program conirol to the coll address. But in JUMP instructio address of the next instruction is not saved. What is the difference between conditional and program control is transferred to the branch addr ditional branch instructions, a flag condition ; the program control is transferred to the bans Stack the unconditional branch instructions? In unconditional branch instruction, the without checking any flag condition. But in cor checked and only if the flag condition is true, address, otherwise the next instruction is executed. What is near jump and far jump? In near jump, the program control is transferred to a new memory location in the same segmem modifying the content of the Instruction Pointer (IP). In far jump, the program control is transfers to a new memory location in another segment by modifying the content of the Instruction Poin; (IP) and Code Segment (CS) register. What is the difference between CALL and INT instruction? While executing CALL instruction only IP and CS are saved in the stack. But, while executing INT instruction IP, CS and flag register are saved in the stack. Scanned with CamScannera 4g SHORT QUESTIONS AND ANSWERS ats state in an 8031/8051 microcontroller ? BS The state is the basic time unit for discrete operation of the controller such as fetching an opcod executing an opcode, writing & data, etc. A machine cycle consists of six states and the timin of tip state is 2 oscillator clock periods 2 «a flow many machine cycles are needed to execute an instruction in an 8031/8051 controller ? 1 3/6051 miroconzller executes an instruction inoneofourmachine cycles. 53, How can the time taken to execute an instruction be estimated in an 8031/8051 controller ? ‘The time taken to execute an instruction by an 8031/8051 controller is obtained by multiplying the time to execute a machine cycle by the number of machine cycles of the instruction. The time to txecute amachine cycle is 12 clock periods. “_ Time to execute an instruction = Cx12xT=Cx 12x i where, C =Number of machine cycles of an instruction. T =Time period of crystal frequency in seconds. f =Crystal frequency in Hz. 54 What is the size of 8031/8051 instructions ? The size of 8031/8051 instructions is one to three bytes. The first byte is an opcode and the subsequent bytes are the address or data. 55 Listthe various machine cycles of an 8031/8051 controller. The various machine cycles of 8031/8051 microcontroller are: {Extra program memory fetch cycle. {Cater data memory read cycle. A batemal data memory write cycle. Per operation cycle. Scanned with CamScannerMicropnocessons AND Microcoy q ee CONTROL, a TE 5.6 How does an 80Sf microcontroller differentiate between external program memory M656, data memary access ? ead operations With external program memory. the controller can perform only read operations but with oxy, write operations. For reading ye? data memory. the controller can perform both read ary lennon ey memory, the controfler asserts BSEN as low. for ending data ernory he contro! erasers ¥ is WR as low. ow, and for writing data memory the controller assert . , 5.7 What are the addressing modes available in an 8051 controler ¢ The addressing modes available in the 8051 mic © lnmedinte addressing 9 Rogist ! © Direct addressing © Inpliod addressing © Register addressing fe Relative addressing 5.8 Explain register indirect addressing in an 8051. In ropister indirect addressing, the instruction specifies the name of the register in which tho address of thy ba ‘avoileble. The internal data RAM locations can be addressed indirectly through registers Rt and RO. The externaipy con be addressed indirectly through the PTR (Date pointer). u Example: MOV A,@RO - The content ofthe RAM location addressed by the RO is moved fo theA-register. 5.9 Explain relative addressing in an 8051. In relative addressing mode, the instruction specifies the address relative to theProgram Counter (PC), The igi, wil camry an olfset whose range is -128,, 0 +127,,, The offset is added to the PC to generate the 16-bit, Physicals, Examplo: JC ofset-f carry is one, then tha program control jumps fo an address obtained by adding te corey the PC and the offset value in the instruction. 5.10 How can the 8051 instructions be classified ? ‘The 8051 instructions can be classified into the following five groups: (i) Osta transfer instructions (i) Arithmetic instructions (i) Logical instructions (ivy Branching instructions {v) Boolean instructions 5.11 List the instructions of 8051 that affect all the flags of 8051. ‘The 8051 instructions that affects all the flags are ADD, ADDC, and SUBB. 5.12 List the instructions of 8051 that affect the overflow flag in 8051. The 8051 instructions that affect overflow flag are ADD, ADDC, DIV, MUL and SUBB. 5.13 List the instructions of 8051 that affect only the carry flag. ‘The 8051 instructions that affect only the carry flag are: ANL C,bit cpl RRC A ANL C,fbit MOV C.bit RLC A CONE ORL Cit SETBC cnc ORL Cit 5.4 List the instructions of 8051 that always clear the carry flag. The instructions that always clear the carry flag are: CLR C, DIV and MUL. 5. ic 5 : 15, What are the operations performed by the boolean variable instructions of an 8051? ‘The boolean variable i i a en it Ie instructions can clear or complement or move a particular bit of bitadd, RAMISER orc: " bitis set Cte ‘They can also transfer the program control to a new addressifa Scanned with CamScannerja SHORT QUESTIONS AND ANSWERS What is @ programmable peripheral device? ifs functions performed by a peripheral device can be altered or changed by a program instruction tten the peripheral device is a called programmable device. Usually programmable devices will have control registers. The device can be programmed by sending control word in the prescribed fomatto the control register. What is data transfer scheme and what are its types ? The data transfer scheme refers to the method of data transfer between the processor and the peripheral devices. The different types of data transfer schemes are shown below: Data Transfer u Programmed Data Transfer Direct Memory Access Synchronous Interrupt Driven Asynchronous Cycle Stealing Demand Transfer Block Transfer Scanned with CamScanner9.3 94 95 9.6 9.7 98 99 9.10 90 9.12 108 What is a synchronous data transfer scheme? In synchronous data transfer scheme, the processor does not check the readines, en issued for read/write operation, In th hep ration, In this seh request the device to get read! ‘and then read/write to the device immmcdistet me some synchronous schemes a small delay is allowed afler the request. What is an asynchronous data transfer scheme ? of the devi the processoy St alter the requ wit tn In asynchronous data transfer sche y ransfer scheme, first the processor sends a requ 2 ta tran ‘ a request (01 Mate operation, Then the processor keeps on polling the stalus of the device, Ore ready, the processor executes a data transfer instruction to complete the process What are the operating modes of an 8212 ? levies For ey, ce the device iy ‘The 8212 can be hardwired to work either as a latch or trista 2 ; ala state buffer. If mod then it will work as a latch and so it can be used as an output port. Iimode(MD) in it work as tristate buffer and so it can be used as an input port. pe What are the various internal devices of INTEL 8155? ‘The INTEL815Sisan IC consisting of static RAM. 10 pots andatimet The inter devices 256 bytes of static RAM, three numbers of programmable 10 ports and a 14-bit programmable fe = What are the internal devices of an 8255 ? = pe her en on teem opesingymdes! or ane What are the operating modes of port-A of an 8255? The port-A ofan 8255 can be programmed to workin any one fhe olling peng asa input or output port: Mode-0 : Simple IO port Mode-1 : Handshake IO port Mode-2 : Bidirectional 1O port What are the functions performed by port-C of an 8255? 1. Theport-C pins are used for handshake signals. 2. Port-C canbe used as an 8-it parallel 10 portinmade-0. 3, Itcan be used as two numbers of 4-bit parallel port in mode-0. 4. The individual pins of port-C can be set or reset for various control applications. What is a handshake port ? In ahandshake port, signals are exchanged between the IO de port and the processor for checking/informing various conditi Explain the working of a handshake input port. atl In handshake input operation, the input device will check whether ihe portis em en port is empty, then it will Toad the data to the port. When the port receives the’ a er te processor for read operation. Once the data has been. read by the processor 1 posse input device that it is empty. Now the input device can load another data to the Pt process is repeated. Explain the working of a handshake output port. wero 0 In handshake output operation, the processor will load a data (0 the pow. wat devi aly the data, it will inform the output device to collect the data. Once the Q ora Yond 3 data, the port will inform the processor that it is empty. Now the proces: to the port and the above process is repeated. Scanned with CamScanner Pins ted istiedlow. te, levice and the por or betveetOE ion of the device. ott?Guarten 9 PeniPvenat Devices Ano 13 How is DMA initiated? When the 10 device nee controller, The DM Aca DMA transfer, i will send a DMA request signal to the DMA receives HOLD reac an Hy turn send a HOLD request to the processor, When the processor trvction execution and gee “Rana ited pins to high impedance state at the end of current conttolle Will perform DM Amun Mow EMRE signal (0 the DMA controller, Now the DMA gtd What are the different types of DMA? The different types of DMA data t transfer (or Burst mode) DMA and Dey gS What is cycle stealing DMA? In cycle stealing DMA (or sin 8 gle transfer mode: ransfer in between ins (anode), the DMA controller wil loon DMA dana ntsttuction cycles (ic, in this mode the execution of bleetot ae ani sta transfer will take place alternatively. hep everishentinen 946 What is block and demand transfer mode DMA? In block transfer mode, the DMA controller will trans processor. After sometime another block of data ren In demand transfer mode, the DMA controller will co and then relieve the bus to the processor. usfer are cycle stealing gl ad anc gaits (or single transfer) DMA, Block fer a block of data and relieve the bus to ansferred by the DMA and so on. plete the entire data transfer at a stretch 317 What are the programmable registers of 8237? The programmable registers of 8237 are Base address regist n 3 sters, Base word Command register, Request register, Mode registers end Mask register ot ESET $18 What isthe first-last flip-flop? ‘The 8237 has an internal flip-flop called first-last flip-flop which takes care of reading/writing 16-bit information through 8-data lines. The first-last flip-flop selects the low or high byte during read/write operation of the address and count registers of channels. If first-last flip-flop is zero (ie. reset),then the low byte can be read/write. If it is one (ie., set), then the high byte can be read/write. After every read/write operation the first-last flip-flop automatically toggles. 919 What is the bit format used for sending asynchronous serial data? In asynchronous transmission, each data character has a bit which identifies its start and 1 or 2 bits which identifies its end. A typical bit format is shown in Fig. Q9.19. Always low Always high Fig.Q9.19 : Bit format used for sending asynchronous serial data. One character °20 What is baud rate ? The baud rate is the rate at which the serial data are transmitted. Baud rate is defined as (The time fora bit cell’ 10 some systems one bit cell has one data bit, then the baud rate and bits Per second are same, Scanned with CamScanner9.22 9.23 9.24 9.25 9.26 9.27 9.28 9.29 9.30 Micnopnacessons AND Micnocormo.teny What is RS-232C standard ? ccrial bus cons isting of by EIA (Electronics Industries Assoc aumof 25 signals. This bus signals are standar ray USA and adopted by TEEE. Usually the fig O signal: radars Fe remeron ite RS-292C serial buss usualy Sie using el it ra 25-pin connector. £ {9-pin connector oF oH oe a are el in RS-232€ serial communication standard? What voltage levels s 32C signals are, 15.V under load (-25-V on no load) der load (-+25-V on no load) een gic high) and ~12-V (logic low). Commonly used volt ic device ? How isthe RS-232C serial bus interfaced (0 a TTL logic device ? evels are not compatible with TTL logic levels. Hence forinterfaci s vers are used. The popularly used level convene The voltage levels for all RS-2 Logic low = -3-V 10 ~ Logic high = +3-V to +15-V uni ge levels are +12-V (lo RS-232C signal voltage I Tai Mevices to RS-232C serial bus, level convert are MC 1488 and MC 1489 or MAX 232, What is USART ? ‘ hronous or Asynchr hich can be programmed to perform Sync yachronous ser A ae vieication is called USART (Universal Synchronous Asynchronous Receiver ‘Transmitey, INTEL 8251 Ais an example of USART. What are the functions performed by INTEL 8251A? “The INTEL 8251A is used for converting parallel data to serial or vice versa, The data transmission or reception can be either asynchronous or synchronous. The 8251A can be used to interface MODEM and establish serial communication through MODEM over telephone lines, What are the control words of 8251A and what are its functions? ‘The control words of 8251A are mode word and command word. The mode word informs 825| about the baud rate, character length, parity and stop bits. The command word can be sent to enable the data transmission and/or reception. What are the information that can be obtained from the status word of 8251? The stats word can be read by the CPU to check the readiness of the transmitter or receiver and to check the character synchronization in synchronous reception. It also provides informatica regarding various errors in the data received. The various error conditions that can be checked from the status word are parity error, overrun error and framing error. What are the tasks involved in keyboard interface ? The task involved in keyboard interfacing are Sensin; i i k u 1g a key actuation, Debouncing the key a! Generating keycodes (Decoding the key). These tasks are performed by the software ihe Keyboard is} denied through ports and they are performed by hardware if the keyboard is interfced What is debouncing ? When ey 7 preted it bounces for a short time. If a key code is generated immediately “A hie See st ation, then the Processor will generate the same keycode a: numberof tines key gpicaly ounces for 10 to 20 milliseconds.) Hence the processor has to wait forth) Wang 10 sete before reading the keycode. This process is called keyboard debouett at is scanning in keyboard and what is scan time? ‘The process of sendin, actuation is called se the rows one by one hey 8 4 Zero to each row of a keyboard matrix and reading the colum i al "anning. The scan time is the time taken by the device/process" arting from first row and coming back to the first row again- Scanned with CamScanner dPeninenat Devices Ano cure no INTERFACING etana gat What is the disadvantage in keyboard interfacing using ports? 932 9.33 ad 935 936 937 $38 I tof the processor time is utilized speed/efficiency of the ‘The disadvantage in keyboard interfacing using in keyboard scanning and debe processor will be reduced, What is multiplexed display? What iv its advantage? The process of swi isplay des ‘one by one for a specified time interval is called multiplexed display. In mi ‘s tocight 7-segment LEDs are interfaced to provide multiplexed display. At any one time only one 7-segment LED is made to glow at a time. After a few milliseconds, the next 7-segment LED is made to glow and soon, Due to persistence of vision, it will appear as if the LEDs are glowing continuously, The advantage in multiplexed display is that the power requirement of the display devices is reduced to a very large extent. ing. As a result the computatio What is scanning in display and what is the scan time? Indisplay devices, the process of sending display codes to 7-segment LEDs to display the LEDs one by one is called scanning (or multiplexed display). The scan time is the time taken to display all the 7-segment LEDs one by one, starting from first LED and coming back to the first LED again. What is the disadvantage in 7-segment LED interfacing using ports? The disadvantage in using ports for 7-segment LED interfacing is that most of the processor time isutilized for display refreshing. What is the advantage in using INTEL 8279 for keyboard and display interfacing? When 8279 is used for keyboard and display interfacing, it takes care of all the task involved in keyboard scanning and display refreshing. Hence the processor is relieved from the task of keyboard scanning, debouncing, keycode generation and display refreshing, and so the processor time can be more efficiently used for computing. List the functions performed by 8279. The function performed by 8279 are: ‘Keyboard scanning © Key debouncing ‘« Informing the key entry to CPU ‘© Storing display codes © Keycode generation © Output display codes to LEDs © Display refreshing What is the maximum number of keycodes that can be generated by 8279? Inscanned keyboard mode, the maximum size of keyboard matrix array that can be interfaced to §279is 8 x 8, which consists of 64 keys. In addition, the 8279 has two control keys called shift and control. For each key press, an 8-bit code is generated and stored in the FIFO (keyboard RAM of 8279). The keycode consists of row and column number of the key in binary along with the status ofthe shift and control key. Hence with 64 contact keys, shift and control key, a maximum of 256 keycodes can be generated by the 8279. What are the programmable display features of 8279 ? The 8279 can be used for interfacing LEDs or 7 segment LEDs. In decoded scan, 4 numbers of 7-segment LEDs can be interfaced and in encoded scan, a maximum of 16 numbers of 7-segment LEDs can be interfaced. The 8279 can be programmed for left entry or right entry. What are the different scan modes of of 8279? The different scan modes of 8279 are decoded scan and encoded scan. In decoded scan mode, the output of the scan lines will be similar to a 2-to-4 decoder. In encoded scan mode, the output of the scan lines will be binary count, and so an external decoder should be used to convert the binary count to the decoded output. What is the difference in programming the 8279 for encoded scan and decoded scan? the 8279 is programmed for decoded scan then the output of scan, lines will be decoded out aMititis programmed for encoded scan then the output of scan, lines will be binary count. "coded mode, an external decoder should be used to decode the scan lines. put In Scanned with CamScanner941 9.42 9.44 GAS 946 9.47 948 9.49 How is a keyboard matrix formed in keyboard interface using 8279? The return ines, RL, to RL, of 8279 are used to form the columns of keyboard matrix, f ees te castes oo i, ee ge Cr 2 ee scan mode, the sean Tine SLy 0 $ Monnected to input of decoder and the out decoder are used as rows of keyboard matrix. ofa timer 8254? in decor led M encode PUL Hines of are What are the operating modes 0 “The 8254 timer has six operating modes. These are: © Made-0-—» Unterrupt on termine! count Mode-1 > Hardware reriggerable one shot - Mode-2.—> Rato generator or Timed interrupt generator Modo-3—> Square wave mode Mode-4—> Software triggered strobe B. Mode-5 > Hardware triggered strobe What is the function of the GATE signal in timer 8254? tn timer 8254, the GATE signal acts as a control signal (0 start, stop or maintain the cou tre tn modes 0,2, 3 and 4, the GATE signal should remain high to start and maintain premting process. In modes 1 and 5, the GATE signal has to make a low-to-high transition os : cre tousing process and need not remain high to maintain the counting process, at What will be the frequency of the square wave generated by a 8254 timer in mode-3? ‘The frequency of the generated square wave is given by the frequency of input clock signal divided by the count value loaded in the count register. If the count value N is an even number then the square wave will be alternatively high and low for N/2 clock periods. Ifthe coun value Nisan odd number then the high time of square wave will be N + 1 clock periods and low time will bea What is resolution in DAC? ‘The resolution in DAC is the smallest possible analog value that can be generated by the n-bit binary input. Ifthe reference voltage in n-bit, DAC is V,,,» then the resolution is (1/2) x V,., ols, What are the internal devices of a typical DAC? ‘The internal devices of a DAC are R/2R resistive network, an internal latch and current to voltage converting amplifier. clock periods. What is settling or conversion time in DAC? The time taken by the DAC to convert a given digital data to the corresponding analog signalis called conversion time. What are the different types of ADC? The different types of ADC are successive approximation ADC, counter tyPe ADC, ADC, integrator converters and voltage-to-frequency converters. What is resolution and conversion time in ADC? It sas, “ The resolution in ADC is the minimum analog value that can be represented by the sin’ the ADC gives n-bit digital output and the analog reference voltage is Vg ten ene (1/2) x Vie, Volts. The conversion time in ADC is defined as the total time: requil analog signal into flash yee Scanned with CamScanner