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Ifc 130 LCD BLK

This block diagram shows the signal flow for a television's video input and output processing. It includes inputs from a tuner, AV ports, and scart ports that are multiplexed and processed. The processed video signal is then output through an LVDS interface to a flat panel display. Audio components and control signals are also shown.

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Ionica Bolbos
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0% found this document useful (0 votes)
91 views1 page

Ifc 130 LCD BLK

This block diagram shows the signal flow for a television's video input and output processing. It includes inputs from a tuner, AV ports, and scart ports that are multiplexed and processed. The processed video signal is then output through an LVDS interface to a flat panel display. Audio components and control signals are also shown.

Uploaded by

Ionica Bolbos
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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BLOCK DIAGRAM - SCHEMA SYNOPTIQUE - BLOCKSCHALTBILD - SCHEMA A BLOCCHI - ESQUEMA DE BLOQUES

CVBSOUT_AV2_CTRL CVBSOUT_AV1_CTRL MA_Tuner


_CVBS TEA6415C
Master_Mute
FE6233 TV K B
Audio_STBY
MA_Tuner MA_TUNER_CVBS RESET_AUDIO
'L'=YC Y YC_SEL_CTRL1
'H'=CVBS AV1_Y_OUT
I2 C YC_SEL_CTRL2 IR DV D KB
0xC2H CVBSOUT_AV1_CTRL
MM 1507 cv CHR CVBSOUT_AV2_CTRL
Mux/ Drv
+ AV1_CHR_OUT YC_DVD_SEL_CTRL

CVBS_OUT MM 1511
19
AV1_CVBS_OUT
Scart 1 AV1_CVBS/Y_IN RGB+FB
Flat Panel Display

MUX
Scart1 32.11
AV1_CHR_IN
FULL MHz
SCART 'L'=YC Y
'H'=CVBS AV2_Y_OUT
Video I2 C
AV1_CVBS/YC 0x40/
MM 1507 cv CHR Scart1 Decoder 0x48H
Mux/ Drv + AV2_CHR_OUT
SAA7117A
5 channel
AV2_CVBS/YC LVDS
CVBS_OUT MM 1511 Scart2 signal
19
AV2_CVBS_OUT
FAV_CVBS/YC

MUX
Scart 2 AV2_CVBS/Y_IN

LVDS OUT
FAV
AV2_CHR_IN
HALF H-port 8 bits
SCART MA_Tuner_CVBS I-port 8 bits 16-bits YCbCr
H+V+Clock CH1 H+V+Clock
CVBS SVHS FAV_CVBS/Y_IN

FRONT CINCH FAV_CHR_IN

DVD_CVBS CVBS_3D
RGB+FB Scart1, AV1_CVBS/YC Scart1
VGA_RGB I2 C LCD/Plasma TV
AV2_CVBS/YC Scart2 I2 C 0x66H
FAV_CVBS/YC FAV 0x06H Controller
YC_SEL_CTRL1 PW118B
YC_SEL_CTRL2 14.318
1 117/ MHz

MUX
24-bits RGB
CH0 H+V+Clock
C_AV1 MM1113/ COMP_YPbPr1
C_AV2 MM1224 COMP_YPbPr2
MM1506 Video

MU X
Y_AV1 MM1117/
AV3/FAV_CHR_IN C Mux C Mux C_AV_IN
Decoder 64kbit
Y_AV2 MM1228
PW2300 27 EEPROM
AV3/FAV_CVBS/Y_IN Y Mux MM1508 MHz
Y Mux Y_AV_IN I2 C
0xA0H
16bits data 32bits data
21bits address 12bits address

I2 CC 0x80, 82, 9AH 16MB


YC_DVD_SEL_CTRL
SDRAM DDR Frame Buffer
VGA_Right_Audio, VGA_Left_Audio Master_Mute Flash Memory 4Mx32bitsx4banks
Comp_Right_Audio, Comp_Left_Audio AUDIO_STBY
Audio Block Card Reader_Right_Audio, Card Reader_Left_Audio RESET_AUDIO INTERBOARD
32Mbit MT46V16M16-6T MT46V16M16-6T
256Mbit 256Mbi
Diagram CONNECTION LRCLK, BCLK, M29W320EB70N6 (166MHz) (166MHz)
PCMDATA
DVD_YC VGA_Right_Audio Comp_Right_Audio Card Reader_Right_Audio HDMI_Right_Audio
DVD_CVBS VGA_Left_Audi0 HDMI_Left_Audio
DVD_Right_Audio
Comp_Left_Audio Card Reader_Left_Audio HDMI Rx
LINE_O/P_L
DVD_Left_Audio LINE_O/P_R COMP_YPbPr1 COMP_YPbPr2
SiI9011
VGA_RGB VGA_TX, VGA_RX 28.322
MHz TMDS
VGA RS232
2kbit DRV I2 C IFC130E I/O Concept
DVD EEPROM
Card Reader 0x06H
Module
Audio Jack
I2 C Comp IN 2kbit
UART1
Audio Cinch Output 0xA0H EEPROM
Prepared I2 C
UART1 0xA0H

EFC031-IFC130-IFC230
First issue 12/05

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