Combinational Logic

Design
Unit-3

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List of Topics:
 Single output and multiple output combinational logic circuit design
 AND-OR, OR-AND, and NAND/NOR realizations
 Exclusive-OR and Equivalence functions
 Binary adders/subtractors
 Encoder, Decoder
 Multiplexer, Demultiplexer
 MUX realization of switching functions
 Parity bit generator
 Code-converters
 Contact Networks
 Hazards and hazard free realizations.

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Combinational Logic Design
 A process with 5 steps
 Specification
 Formulation
 Optimization
 Technology mapping
 Verification

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Functional Blocks
 Fundamental circuits that are the base building
blocks of most larger digital circuits
 They are reusable and are common to many
systems.
 Examples of functional logic circuits
 Decoders
 Encoders
 Code converters
 Multiplexers
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Where they are used
 Multiplexers
 Selectors for routing data to the processor, memory,
I/O
 Multiplexers route the data to the correct bus or
port.
 Decoders
 are used for selecting things like a bank of memory
and then the address within the bank. This is also
the function needed to ‘decode’ the instruction to
determine the operation to perform.
 Encoders
 are used in various components such as keyboards.
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Specifications step
 Write a specification for the circuits
 Specification includes
 What are the inputs: how many, how many bits in a
given output, how are they grouped, are they
control, are they active high?
 What are the outputs: how many and how many bits
in each, active high, active low, tristate output?
 The functional operation that takes place in the chip,
i.e., for given inputs what will appear on the outputs.
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Formulation step
 Convert the specifications into a variety forms
for optimal implementation.
 Possible forms
 Truth Tables
 Expressions
 K-maps
 Binary Decision Diagrams

 IF THE SPECIFCATION IS ERRONOUS OR INCOMPLETE (open for various

interpretation) then the circuit will perform as specified but will not
perform as desired.

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Digital Circuits:
 Combinational circuit consists of logic gates whose outputs
at any time are determined directly from the present
combination of inputs without regard to previous inputs.
 Sequential Circuit employ memory elements in addition to
logic gates. Their outputs are a function of the inputs and
the state of the memory elements.

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Combinational Circuit:
 A Combinational circuit consists of input variables, logic
gates and output variables. The gates accept signals from
the inputs and generate signals to the outputs.

Combinational
n input Logic Circuit m output
variables variables

Block Diagram of a Combinational Circuit

Design of Combinational Circuits:
The design procedure involves the following steps:
 The problem is stated.

 The number of available input variables and required

output variables is determined.
 The input and output variables are assigned letter symbols.

 The truth table that defines the required relationships

between inputs and outputs is derived.
 The simplified Boolean function for each output is
obtained.
 The logic diagram is drawn.
A Practical design method would have to consider
constraints such as:
 Minimum no. of gates.
 Minimum no. of inputs to the gates.
 Minimum propagation time of the signal through the
circuit.
 Minimum no. of interconnections and
 Limitations of the driving capabilities of each gate.
 Adders:
 A combinational circuit that performs addition of two bits is
called a Half Adder.

A Sum
inputs
Half Adder Outputs
B Carry
 K map simplification for HA

A 0 A 0
1 1
B B
0 0 0 0 0 1
1 0 1 1 1 0

For carry For sum

Logic diagram for half adder
Adders:
 A combinational circuit that performs addition of three bits
is called a Full Adder.
Cin

A Sum
Full Adder
B

Cout
Truth table for full adder
A B Cin Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
 K map simplification for full adder

B Cin B Cin
00 01 11 10 00 01 11 10
A A
0 0 0 1 0 0 0 1 0 1
1 0 1 1 1 1 1 0 1 0

For carry For sum

Logic diagram for full adder
Implementation of full adder with two half
adders and an OR gate
 Subtractors:
 A combinational circuit that subtracts two bits and
produces their difference is called Half Subtractor. It also
has an output to specify if a 1 has been borrowed.

A Difference
Outputs
inputs
Half Subtractor
B Borrow
K map simplification for half subtractor

A 0 A 0
1 1
B B
0 0 0 0 0 1
1 1 0 1 1 0

For Borrow For Difference

Logic diagram for half subtractor
 Full Subtractor
Borrowin

A Difference
Full Subtractor
B

Borrowout
Truth table for full subtractor
A B C Difference Borrow

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 1
1 0 0 1 0
1 0 1 0 0
1 1 0 0 0
1 1 1 1 1
 K map simplification for full subtractor

BC BC
00 01 11 10 00 01 11 10
A A
0 0 1 1 1 0 0 1 0 1
1 0 0 1 0 1 1 0 1 0

For Borrow For Difference

Logic diagram for full subtractor
Implementation of full subtractor using two half
subtractors and an OR gate
 Binary / Parallel Adder

Bn An B2 A2 B1 A1 B0 A0

Cout
Cout
FA FA FA FA
Cin

Cin
Sn S2 S1 S0
 Binary subtractor / Parallel subtractor

Bn An B2 A2 B1 A1 B0 A0

Cout Cout
FA FA FA FA
Cin

Cin=1
Sn S2 S1 S0
 Encoder

2n inputs
n data
2n:n ouputs

Encoder
Enable
inputs

• A digital circuit that performs the inverse operation of a decoder is

called an encoder. An encoder has 2n input lines and n output lines.
• In encoder the output lines generate binary code corresponding to the
input value.
Truth table of Octal to Binary Encoder
D0 D1 D2 D3 D4 D5 D6 D7 A B C
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Octal to Binary Encoder
 Decoders

• A decoder is a multiple-input, multiple-output logic circuit

which converts coded inputs into coded outputs, where the
input and output codes are different.

• The input code generally has fewer bits than the output code,

• Each input code word produces a different output code word.

 General structure of a decoder

n data
inputs

n:2 n Possible 2n
outputs
Decoder
Enable
inputs

Usually, a decoder is provided with enable inputs to activate

decoded output based on data inputs. When any one enable input
is unasserted, all outputs of decoder are disabled.
 Binary decoder

• A decoder which has an n-bit binary input code and a one

activated output out of 2n output code is called binary
decoder.

• A binary decoder is used when it is necessary to

activate exactly one of 2n output based on an n-bit input
value.
Truth table for 2 to 4 decoder

En A B Y3 Y2 Y1 Y0
0 X X 0 0 0 0
1 0 0 0 0 0 1
1 0 1 0 0 1 0
1 1 0 0 1 0 0
1 1 1 1 0 0 0
2 to 4 Decoder
 Truth table for 3 to 8 decoder

EN A B C Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
0 X X X 0 0 0 0 0 0 0 0
1 0 0 0 0 0 0 0 0 0 0 1
1 0 0 1 0 0 0 0 0 0 1 0
1 0 1 0 0 0 0 0 0 1 0 0
1 0 1 1 0 0 0 0 1 0 0 0
1 1 0 0 0 0 0 1 0 0 0 0
1 1 0 1 0 0 1 0 0 0 0 0
1 1 1 0 0 1 0 0 0 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0
Logic diagram for 3 to 8 decoder
 BCD to decimal decoder

• BCD decoders have four inputs and 10 outputs.

• The four bit BCD input is decoded to activate one of the ten
outputs.

• It accepts four active high BCD inputs and provides 10

independent active low outputs
 Multiplexer

• Multiplexer is a digital switch. It allows digital information

from several sources to be routed onto a single output line.

• The selection of a particular input line is controlled by a set of

selection lines.

• Normally, there are 2n input lines and n selection lines whose

bit combinations determine which input is selected.
4 to 1 line multiplexer
Quadruple 2 to 1 line multiplexer
Expanding multiplexers

Expansion of multiplexer
 Implementation of combinational logic using Mux
• A multiplexer consists of a set of AND gates whose outputs are connected to
single OR gate. Because of this construction any boolean function in a SOP
form can be easily realized using multiplexer.

• Each AND gate in a multiplexer represents a min term.

• In 8 to 1 mux, there are 3 select inputs and 2 3 minterms.

• By connecting the function variables directly to the select inputs, a multiplexer

can be made to select the AND gate that corresponds to the minterm of the
function.

• If a minterm exists in a function, we have to connect the AND gate data input to
logic 1; otherwise we have to connect it to logic 0.
 Demultiplexers

• A demultiplexer is a circuit that receives information on a single

line and transmits this information on one of 2n possible outputs.

• The selection of specific output line is controlled by the values

of n selection lines.
1 : 4 demultiplexer
Logic symbol of demultiplexer

Y0
Din Y1
1: 4 demux
Y2
Y3

S1 So
 Cascading Demultiplexers

Cascading demultiplexers is same as that of the

cascading decoders.
 Implementing boolean function using
demultiplexer

Demultiplexer gives min terms at the output so by

logically Oring required minterms we can implement
boolean functions.
Parity generator truth table for even and odd
parity
Logic diagram for even parity
Truth table for even parity checker
Logic diagram for even parity checker
 Code converters

1. Binary to BCD converter

2. BCD to binary converter
3. BCD to excess 3
4. Excess 3 to BCD
5. Binary to gray code
6. Gray code to binary
7. BCD to gray code
 1. Binary to BCD converter
Binary code BCD code
D C B A B4 B3 B2 B1 B0
0 0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 0 1
0 0 1 0 0 0 0 1 0
0 0 1 1 0 0 0 1 1
0 1 0 0 0 0 1 0 0
0 1 0 1 0 0 1 0 1
0 1 1 0 0 0 1 1 0
0 1 1 1 0 0 1 1 1
1 0 0 0 0 1 0 0 0
1 0 0 1 0 1 0 0 1
1 0 1 0 1 0 0 0 0
1 0 1 1 1 0 0 0 1
1 1 0 0 1 0 0 1 0
1 1 0 1 1 0 0 1 1
1 1 1 0 1 0 1 0 0
1 1 1 1 1 0 1 0 1
Logic diagram for binary to BCD converter
2. BCD to Binary converter

BCD to binary table

Logic diagram for BCD to binary code
converter
 3. BCD to excess 3
Decimal
B3 B2 B1 B0 E3 E2 E1 E0
0 0 0 0 0 0 0 1 1
1 0 0 0 1 0 1 0 0
2 0 0 1 0 0 1 0 1
3 0 0 1 1 0 1 1 0
4 0 1 0 0 0 1 1 1
5 0 1 0 1 1 0 0 0
6 0 1 1 0 1 0 0 1
7 0 1 1 1 1 0 1 0
8 1 0 0 0 1 0 1 1
9 1 0 0 1 1 1 0 0
Logic diagram for BCD to excess 3
4. Excess 3 to BCD code converter
E3 E2 E1 E0 B3 B2 B1 B0
0 0 1 1 0 0 0 0
0 1 0 0 0 0 0 1
0 1 0 1 0 0 1 0
0 1 1 0 0 0 1 1
0 1 1 1 0 1 0 0
1 0 0 0 0 1 0 1
1 0 0 1 0 1 1 0
1 0 1 0 0 1 1 1
1 0 1 1 1 0 0 0
1 1 0 0 1 0 0 1
Logic diagram for excess 3 to BCD code
converter
5. Binary to Gray code converter

Binary to gray code table

Logic diagram for Binary to gray code
converter
6. Gray code to binary code converter

Gray code to binary table

Logic diagram for gray code to Binary code
converter
 7. BCD to gray code converter

BCD code Gray code

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
Logic diagram for BCD to gray code converter
 Priority encoder

A Priority encoder is an encoder circuit that includes the priority

function. In priority encoder, if two or more inputs are equal to
1 at the same time, the input having the highest priority will take
precedence.
Priority Encoder:

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End