BITS Pilani

Pilani Campus

MEL G 621: VLSI Design

CMOS Inverter
Outlines

Design Metrics

CMOS Inverter Circuit

VTC of CMOS Inverter

Noise Margin

Power Dissipation

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Design Metrics
How to evaluate performance of a digital circuit (gate, block,


…)?

Cost (Yield)

Reliability (Noise Immunity)

Scalability (Fan-In, Fan-out)

Speed (delay, operating frequency)

Power dissipation

Energy to perform a function

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Five Critical Voltages on VTC
 VOH: Maximum output voltage when the output level is logic “1”

 VOL : Minimum output voltage when the output level is logic “0”

 VIL : Maximum input voltage which can be interpreted as logic “0”

 VIH : Minimum input voltage which can be interpreted as logic “1”

 VTH : Switching threshold

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus
Definition of Noise Margins

"1"
V
OH
NMH
V
Noise Margin High IH
Undefined
Region
Noise Margin Low
NML V
IL
V
OL
"0"

Gate Output Gate Input

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Mapping between Analog and Digital
V
out
V
“1” OH Slope = -1
V
V OH
IH

Undefined
Region

V
IL
Slope = -1

V
“0” V
OL
OL
V V V
IL IH in

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Noise Margin

NMH = VOH- VIH

NML = VIL-VOL

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Inverter

Ideal Voltage Transfer Characteristics (VTC)

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

VTC Design Issues

Static Power Consumption

Full Logic Levels

Sharp Transition

Switching threshold → Noise margins

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Resistive Load Inverter
 Enhancement nMOS transistor is the driver device

 Load is a resistor RL

 Drain current ID = Load current IR

 Taking VSB = 0

 Threshold voltage of the driver

transistor is VTO

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

Design for Vol
VTC Variation

Resistive Inverter Circuit

VTC of CMOS Inverter

Noise Margin

Power Dissipation

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Power Consumption
The average power consumption :

Vin= VOL(low) and Vin = VOH ( high)

PDC(average) = (VDD/2) [IDc ( Vin=low) + IDc ( Vin=high)]

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Power Consumption (Resistive Inv)
The average power consumption of a resistive load inverter circuit is
found by considering

Vin= VOL(low) and Vin = VOH ( high)

When Vin = VOL driver transistor cut-off ( ID = IR = 0) and the DC

power dissipation is zero.

When Vin = VOH driver and load conduct a non zero current.
Vout = VOL
ID = IR = (VDD - VOL)/RL

PDC(average) = (VDD/2) .( VDD- VOL) RL

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Power Consumption (Resistive Inv)
Note: Trade off exist between ?

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Enhancement Load nMOS Inverter

VDD Saturated enhancement load.

Single power supply

VOH = VDD- VTload

IL Vout

ID
Vin

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Drawback

VDD

IL Vout

ID
Vin VOH = VDD- VTload

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 VGG
VDD Linear- enhancement load.

Two power supplies

VOH = VDD
IL Vout

ID
Vin

Both consumes static DC Power.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Depletion Load nMOS inverter
Driver transistor enhancement
nMOS with V TO, driver > 0
VDD
VGG
Load is depletion type nMOS with
V TO, load < 0

V GS,
Load device always conducting as
IL Vout
load= 0 V GS, load > V T, load
ID
Load device subjected to substrate
Vin
bias.

Operation of load transistor

depends on the output voltage

Vout when small, the load is in

saturation.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
The shape of VTC , noise margin are determined by the threshold
voltages of the driver and load devices and by the ratio kdriver/ kload

Determined by the W/L ratio of the transistors.

Inverter requires relatively small driver-to-load ratios.

Total area occupied by the depletion load inverter with acceptable

circuit performance is expected to be much smaller than the area
occupied by a comparable resistive-load or enhancement load inverter.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Depletion Load nMOS inverter

- Fabrication slightly complicated

- Sharp VTC Transition

- Better noise Margin

- Smaller overall layout area.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 CMOS Inverter

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
CMOS Inverter
VDD

Vin
Vout

CL

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 CMOS Inverter
VDD It consists of an enhancement-
type nMOS transistor and an
enhancement type pMOS
transistor

Push-pull arrangement
Vin
Vout
For high input, nMOS pulls
CL down the output node while
pMOS acts as load

For low input pMOS pulls up

the output node while the nMOS
acts as the load

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Outlines

CMOS Inverter Circuit

VTC of CMOS Inverter

Noise Margin

Power Dissipation

Nitin Chaturvedi
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
VOH

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VOL

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VIL

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
VIH

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BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
V th -switching threshold

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Effect on kR

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Questions ?

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

MOS Transistors - Behaviors
Static Behavior:



Threshold Voltage

Channel-Length Modulation

Velocity Saturation

Sub-threshold Conduction
Dynamic (Transient) Behavior:


BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

I-V Relations: Long-Channel
Device

Quadratic
Relationship

Effective Length of the conductive channel is

inversely proportional to VDS
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Long-Channel I-V Plot (NMOS)

Quadratic dependence
X 10-4
6
VGS = 2.5V
5 VDS = VGS - VT

4
VGS = 2.0V
I D(A)

3
Linear Saturation
2 VGS = 1.5V

1
VGS = 1.0V
0
cut-off 0 0.5 1 1.5 2 2.5
VDS (V)

NMOS transistor, 0.25um, Ld = 10um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

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BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
BITS Pilani, Pilani Campus
 eq-7

eq-5

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
Drain current equation are complex expression.

A simpler model can be obtained by make two
assumptions:

Velocity saturates abruptly at ξ c and approximated by:


Drain-source voltage at which the critical electric field is
reached and velocity saturation comes into play is constant and
approximated by:

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Current Equation for resistive region remains
same
 The value of Idsat can be derived by plugging
the saturation voltage into current equation for
the resistive region

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Current equation changes

CONSTANT

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Short-Channel Devices
ID Long-channel device

VGS = VDD
Short-channel device

Extended
saturation

V DSA VGS - VT VDS

T
For an NMOS device with L of .25µ m, only a couple of volts
between S and D are needed to reach velocity saturation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
Short-Channel IV Plots (NMOS)
X 10-4
2.5 Early Velocity VGS = 2.5V
Saturation

Linear dependence
2
VGS = 2.0V
I D(A)

1.5

Linear Saturation VGS = 1.5V

1

0.5
VGS = 1.0V

0
0 0.5 1 1.5 2 2.5
VDS (V)

NMOS transistor, 0.25um, Ld = 0.25um, W/L = 1.5, VDD = 2.5V, VT = 0.4V

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

MOS

CONSTANT
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For velocity saturated device

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Estimation of NM USING Piecewise lin. approx.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Determine g at Vin~Vm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Variation in VM by (w/L)

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Impact Of Device Variations on Vm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Reducing supply voltage

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Determination of Req

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

In velocity saturated device

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Choose appropriate VM

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Questions ?

Thanks

Dr. Nitin Chaturvedi VLSI Design BITS Pilani, Pilani Campus

BITS Pilani, Pilani Campus