Verilog Labs: Introduction To Lab Exercises
Verilog Labs: Introduction To Lab Exercises
Verilog Labs
Introduction to Lab Exercises
The lab exercises are designed to make you understand the Verilog-HDL based design methodology.
They are organised in a way that takes you step by step until you become familiar with the tools and
language.
The labs are designed to maximize your hands on introduction to Verilog coding. Over this period, we
will gain the level of coding skill, syntax proficiency, and understanding that can only be achieved
through meaningful practice and effort.
The first few labs are to get you familiar with the EDA tools that we will be using, and the basic steps
involved in simulating and synthesizing a small design.
EDA Tools
The lab exercises are independent of any particular Verilog simulator or synthesizer or FPGA
technology.
In this Verilog training you will be using the following EDA tools for the design verification and
implementation.
Naming Conventions
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Contents
Objective: To understand the different modelling styles in Verilog and learn different port mapping methods
Objective: To understand how operators responds to unknown, known and high impedance values in an if-
else construct and ternary operators.
Objective: To understand how blocking and non-blocking assignments work with procedural delays.
Objective: To understand how synthesizable synchronous designs, tasks and functions are implemented.
Objective: To understand how file input/output operations work with memory designs and parameter over-
riding is implemented.
Objective: To understand how Moore/Mealy FSM outputs are calculated with different coding styles.
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Write RTL description and testbench for the Full Adder circuit using half adders and OR gate. The
block diagram of full adder, along with complete connections of full adder using two half adders and
an OR gate is shown below.
Procedure:
Step1. Draw truth table and analyse the inputs and outputs for Full Adder circuit.
Step2. Open Modelsim, create project in the sim directory of Lab1.
Step3. Add the RTL (rtl/half_adder.v, full_adder.v),
Step4. Add the TB files (tb/half_adder_tb.v & tb/full_adder_tb.v) to the project.
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Compile, elaborate and simulate the design and test bench of half adder.
Synthesize the design in Quartus II
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The ALU performs 16 different operations using command input on 8 bit inputs a and b. If the MSB
of the command input is low then the arithmetic operations are performed. If the MSB of command
input is high then the logical operations are performed. The output is of 16 bit. Input oe enables the
ALU, i.e. when oe is low, output is at high impedance.
Procedure:
Step1. Write down the functionality of ALU based on command (instruction set) given.
*Use arithmetic and logical operators & Switch Case Statement of Verilog.
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Compile, elaborate and simulate the design and testbench.
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Write RTL (Behavioural) description and test bench for a 4:1 Multiplexer circuit .The block diagram
of 4:1 multiplexer is shown below.
Procedure:
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Procedure:
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Compile, elaborate and simulate the design and testbench.
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Write RTL description and testbench for the Single Port RAM, which is 8 bit wide and has 16 memory
locations. The data can be written on a memory location by providing its address and making “we”
high and “enable” low. The data can be read from a memory location by providing the address and
making “enable” high and “we” low. This RAM has single port for data writing and reading.
Procedure:
Step1. Draw the input, output timing diagrams for Single Port RAM.
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Open the file lab5/rtl/ram
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Write RTL description and testbench for the Sequence Detector that detects “101” from input data
stream.
The block diagram and state diagram for the “101” sequence detector are shown below.
Procedure:
Step1. Draw the state transition diagram and state transition table for the given sequence detector
Step2. Draw the input, output timing diagrams for sequence detector.
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Open the file lab6/rtl/seq_det
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