VLSI Training Center

Setting Standards in VLSI Design

Verilog Labs
Introduction to Lab Exercises

The lab exercises are designed to make you understand the Verilog-HDL based design methodology.
They are organised in a way that takes you step by step until you become familiar with the tools and
language.

The labs are designed to maximize your hands on introduction to Verilog coding. Over this period, we
will gain the level of coding skill, syntax proficiency, and understanding that can only be achieved
through meaningful practice and effort.

The first few labs are to get you familiar with the EDA tools that we will be using, and the basic steps
involved in simulating and synthesizing a small design.

EDA Tools

The lab exercises are independent of any particular Verilog simulator or synthesizer or FPGA
technology.

In this Verilog training you will be using the following EDA tools for the design verification and
implementation.

Simulator: Modelsim -Altera

Synthesizer: Quartus Prime II

Naming Conventions

 Use meaningful names for the ports and signals

 File name should be same as the module name

 Use only lowercase letters

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Contents

Lab1: Familiarization with Verilog Syntax, Instantiation and Testbench

Objective: To understand the different modelling styles in Verilog and learn different port mapping methods

Lab2: Familiarization with Verilog Operators

Objective: To understand how operators responds to unknown, known and high impedance values in an if-
else construct and ternary operators.

Lab3: Familiarization with Combinational Logic Design

Objective: To understand how blocking and non-blocking assignments work with procedural delays.

Lab4: Familiarization with Sequential Design

Objective: To understand how synthesizable synchronous designs, tasks and functions are implemented.

Lab5: Familiarization with Memory design

Objective: To understand how file input/output operations work with memory designs and parameter over-
riding is implemented.

Lab6: Familiarization with FSM design

Objective: To understand how Moore/Mealy FSM outputs are calculated with different coding styles.

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LAB 1 - Familiarization with Verilog Syntax, Instantiation and Testbench

Example:

Write RTL description and testbench for the Full Adder circuit using half adders and OR gate. The
block diagram of full adder, along with complete connections of full adder using two half adders and
an OR gate is shown below.

Procedure:

Step1. Draw truth table and analyse the inputs and outputs for Full Adder circuit.
Step2. Open Modelsim, create project in the sim directory of Lab1.
Step3. Add the RTL (rtl/half_adder.v, full_adder.v),
Step4. Add the TB files (tb/half_adder_tb.v & tb/full_adder_tb.v) to the project.
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Open the file lab1/rtl/half_adder.v

Step1. Understand the syntax and functionality of half-adder.

Step2. Close the file.
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Open the file lab1/tb/half_adder_tb.v

Step1. Understand the test bench.

Step2. Close the file.
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Compile, elaborate and simulate the design and test bench of half adder.
Synthesize the design in Quartus II

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Open the file lab1/rtl/full_adder.v

Step1. Write down the port directions.

Step2. Declare the internal wires.
Step3. Instantiate two Half-Adders
Step4. Instantiate the OR gate
Step5. Save and close the file.
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Open the file lab1/tb/full_adder_tb.v

Step1. Understand the syntax and testbench.

Step2. Instantiate the full adder
Step3. Save and close the file.
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Compile, elaborate and simulate the design and test bench of full adder.
Synthesize the design in Quartus II
---------------------------------------------------------------------------------------------------

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LAB 2 - Familiarization with Verilog Operators

Write RTL description and testbench for an Arithmetic Logic Unit using arithmetic and logical
operators. The block diagram and instructions set for ALU are shown below.

The ALU performs 16 different operations using command input on 8 bit inputs a and b. If the MSB
of the command input is low then the arithmetic operations are performed. If the MSB of command
input is high then the logical operations are performed. The output is of 16 bit. Input oe enables the
ALU, i.e. when oe is low, output is at high impedance.

Command Operation Command Operation

4’b0000 Add a to b 4’b1000 And a, b

4’b0001 Increment a by 1 4’b1001 Or a, b
4’b0010 Subtract b from a 4’b1010 Invert a
4’b0011 Decrement a by 1 4’b1011 Nand a, b
4’b0100 Multiply a with b 4’b1100 Nor a, b
4’b0101 Divide a by b 4’b1101 Xor a, b
4’b0110 Shift a right by 1 bit 4’b1110 Xnor a, b
4’b0111 Shift a left by 1 bit 4’b1111 Buffer a

Procedure:

Open the file lab2/rtl/alu.v

Step1. Write down the functionality of ALU based on command (instruction set) given.
*Use arithmetic and logical operators & Switch Case Statement of Verilog.

Step2. Understand the tri-state output logic.

Step3. Save and close the file.
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Open the file lab2/tb/alu_tb.v

Step1. Instantiate the ALU design.

Step2. Write a task named "initialize" to initialize the inputs of DUT.
Step3. Understand the complete test bench and various tasks defined inside it.
Step4. Save and close the file.

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Compile, elaborate and simulate the design and testbench.

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LAB 3 - Familiarization with Combinational Logic Design

Example:

Write RTL (Behavioural) description and test bench for a 4:1 Multiplexer circuit .The block diagram
of 4:1 multiplexer is shown below.

Procedure:

Step1. Draw truth table for 4:1 Multiplexer circuit.

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Open the file lab3/rtl/mux4_1.v

Step1. Define the port directions with proper datatypes and ranges.
Step2. Write the MUX behaviour as a parallel logic using case statement in behavioural modelling.
Step3. Save and close the file.
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Open the file lab3/tb/mux4_1_tb.v
Step1. Instantiate the design.
Step2. Define body for the initialize task to initialize inputs of DUT to 0
Step3. Declare tasks with arguments for driving stimulus to DUT.
Step4. Call the tasks from procedural block
Step5. Use $monitor task in a parallel initial block to display inputs and outputs.
Step6. Use $finish task to finish the simulation in a parallel initial block with appropriate delay.
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Compile, elaborate and run the simulation.

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LAB 4 - Familiarization with Sequential Design

Example:

Write RTL description and testbench for the D flip-flop.

The block diagram, input and output waveforms of D flip-flop is shown below.

Procedure:

Step1. Draw state table of D flip-flop.

Step2. Draw the input, output timing diagrams for D flip-flop.
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Open the file lab4/rtl/dff.v
Step1: Declare Port Directions
Step2. Write the behavioral logic for D flip-flop functionality.
Step3. Assign complement of q to qb.
Step4. Save and close the file.
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Open the file lab4/tb/dff_tb.v
Step1. Define a parameter with name "cycle" which is equal to 10.
Step2. Instantiate the dff design
Step3. Understand the clock generation logic.
Step4. Understand the various tasks used and also how to use tasks in testbench.
Step5. Use $monitor task in a parallel initial block to display inputs and outputs.
Step6. Save and close the file.

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Compile, elaborate and simulate the design and testbench.
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LAB 5 - Familiarization with Memory design

Example:

Write RTL description and testbench for the Single Port RAM, which is 8 bit wide and has 16 memory
locations. The data can be written on a memory location by providing its address and making “we”
high and “enable” low. The data can be read from a memory location by providing the address and
making “enable” high and “we” low. This RAM has single port for data writing and reading.

The block diagram of the single port RAM is shown below.

Procedure:

Step1. Draw the input, output timing diagrams for Single Port RAM.
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Open the file lab5/rtl/ram

Step1. Declare an 8 bit wide memory having 16 locations.

Step2. Understand the logic for writing data into a memory location
Step3. Understand the logic of reading data from a memory location
Step4. Save and close the file
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Open the file lab5/tb/ram_tb.v

Step1. Instantiate the RAM module and connect the ports

Step2. Define body for the task named stimulus to initialize the "addr" and "tempd" inputs through i
and j variables. Use i for initialization of "addr" and j for initialization of "tempd".
Step3. Understand the various tasks defined in this testbench
Step4. Save and close the file
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Compile, elaborate and simulate the design and testbench
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LAB 6 - Familiarization with FSM design

Example:

Write RTL description and testbench for the Sequence Detector that detects “101” from input data
stream.

The block diagram and state diagram for the “101” sequence detector are shown below.

Procedure:

Step1. Draw the state transition diagram and state transition table for the given sequence detector
Step2. Draw the input, output timing diagrams for sequence detector.

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Open the file lab6/rtl/seq_det

Step1. Declare the sates as parameter "IDLE","STATE1","STATE2","STATE3" and use binary

encoding for encoding these states.
Step2. Write down the port declarations with proper directions.
Step3. Write down the sequential logic for present state.
Step4. Understand the combinational logic for next state.
Step5. Write down the logic for output dout.
Step6. Save and close the file.

Open the file lab6/tb/seq_tb.v

Step1. Generate clock, using parameter "cycle".

Step2. Write a task named "initialize" to initialize the input din of sequence detector.
Step3. Write a task named "RESET" to reset the design, use delay task for adding delay.
Step4. Write a task named "stimulus" which provides input to design on negative edge of clock.
Step5. Understand the remaining Logic defined in the program.
Step6. Save and close the file.
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Compile, elaborate and simulate the design and testbench.
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