Padmabhushan Vasantdada Patil Pratishtan’s

College of Engineering Sion, Mumbai-400 022

Mumbai University

Department of Electronics Engineering

Subject: Computer Organization and Architecture

Presentation Topic: ARM Cortex 32-Bit
Microcontroller
To Prof Sonali Pakhmode
By Surbhi Pal(VU2F1314044)
2019-2020
[1]
 Introduction

The ARM-Cortex microcontroller is a most popular

microcontroller in the digital embedded system world
and most of the industries prefer only ARM
microcontrollers since it consists of enormous features
to implement products with an advanced appearance.
The ARM microcontrollers are cost sensitive and high
performance devices which are used in a wide range of
application such as  industrial  instrument control
systems, wireless networking and sensors and
automotive body system etc. The ARM stands
for Advanced RISC machine and it is a 32-bit  reduced
instructions set computer (RISC) microcontroller. It
was first introduced by the Acron computers’
organization  in 1987. The ARM is a family of the
microcontroller developed by the different
manufacturers such as ST microelectronics, Motorola
and so on.  The ARM microcontroller architecture come
with a few different versions such as ARMv1, ARMv2
etc and each one has its own advantage and
disadvantages.

[2]
 Architecture
The cortex-M3 ARM processor is a high performance
32-bit processor, which offers the significant benefits to
the developers. The ARM architecture is a ‘Harward
architecture’ which offers separate data and instruction
buses for communicating with the  ROM and RAM
memories. It consist a 3-stage pipeline to fetch, decode
and execute the  instructions sequentially. The Cortex
processor is a cost sensitive device which is used to
reduce the processor area and has extensive improving
interrupt handling and system debug capabilities.

[3]
 Architecture Versions
Over the years, ARM has continued to develop
new processors and system blocks. These include
the popular ARM7TDMI processors, more
recently the ARM11 processor family and latest
being the ARM Cortex Processor family. Table 2.1
summarizes the various architecture versions and
processor families.
Architecture Processor Family
ARMv1 ARM1
ARMv2 ARM2, ARM3
ARMv3 ARM6, ARM7
ARMv4 StrongARM, ARM7TDMI,
ARM9TDMI
ARMv5 ARM7EJ, ARM9E,
ARM10E, XScale
ARMv6 ARM11, ARM Cortex –M
ARMv7 ARM Cortex-A, ARM Cortex-
R, ARM Cortex-M

ARM Microcontroller Register Modes

An ARM micrcontroller is a load store reducing
instruction set computer architecture means the core
cannot directly operate with the memory. The data
operations must be done by the registers and the
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information is stored in the memory by an address. The 
ARM cortex-M3 consists of 37 register sets wherein 31
are general purpose registers and 6 are status registers.
The ARM uses seven processing modes to run the user
task.
 USER Mode
 FIQ Mode
 IRQ Mode
 SVC Mode
 UNDEFINED Mode
 ABORT Mode
 Monitor Mode

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USER Mode: The user mode is a normal mode, which
has the least number of registers. It doesn’t have SPSR
and has limited access to the CPSR

FIQ and IRQ: The FIQ and IRQ are the two interrupt
caused modes of the CPU. The FIQ is processing
interrupt and IRQ is standard interrupt. The FIQ mode
has additional five banked registers to provide more
flexibility and high performance when critical interrupts
are handled.
SVC Mode: The Supervisor mode is the software
interrupt mode of the processor to start up or reset.
Undefined Mode: The Undefined mode traps when
illegal instructions are executed. The ARM core
consists of 32-bit data bus and faster data flow.
THUMB Mode: In THUMB mode 32-bit data is
divided into 16-bits and increases the processing speed.
THUMB-2 Mode: In THUMB-2 mode the instructions
can be  either 16-bit or 32-bit and it increases the
performance of the ARM cortex –M3 microcontroller.
The ARM cortex-m3 microcontroller uses only
THUMB-2 instructions.

Some of the registers are reserved in each mode for the

specific use of the core. The reserved registers are

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  Stack Pointer (SP).
 Link Register (LR).
 Program Counter (PC).
 Current Program Status Register (CPSR).
 Saved Program Status Register (SPSR).
The reserved registers are used for specific functions.
The SPSR and CPSR contain the status control bits
which are used to store the temporary data. The SPSR
and CPSR register have some properties that are
defined operating modes, Interrupt enable or disable
flags and ALU status flag. The ARM core operates in
two states 32-bit state or THUMBS state.

Evolution of the ARM Instruction Set

Enhancement and extension of instruction sets
used by the ARM processors has been one of the
key driving forces of the architecture’s evolution. 
Historically, two different instruction sets
were supported on the ARM processor: the ARM
instructions, which are 32 bits and Thumb
instructions, which are 16 bits. During program
execution, the processor can be dynamically
switched between the ARM state and the Thumb
state. The Thumb instruction set provides only a
subset of the ARM instructions, but it can provide
higher code density. It is useful for products with
tight memory requirements.
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 The Thumb-2 technology extended the
Thumb Instruction Set Architecture (ISA) into a
highly efficient and powerful instruction set that
delivers significant benefits in terms of ease of use,
code size and performance. The extended
instruction set in Thumb-2 is a superset of the
previous 16-bit Thumb instruction set, with
additional 16-bit instructions alongside 32-bit
instructions. It allows more complex operations to
be carried out in the Thumb state, thus allowing
higher efficiency by reducing the number of states
switching between ARM state and Thumb state.
The Cortex-M3 processor supports only the
Thumb-2 (and traditional Thumb) instruction set.
Instead of using ARM instructions, as in traditional
ARM processors, it uses Thumb-2 instruction set
for all operations. As a result, the Cortex-M3
processor is not backward compatible with
traditional ARM processors, which use the ARM
as well as Thumb instruction set.
The Thumb-2 instruction set is a very
important feature of the ARMv7 architecture. For
the first time, hardware divide instruction is
available on an ARM processor, and a number of
multiply instructions are also available.

[8]
Register
The Cortex-M3 has registers R0 through R15. R13 (the
stack pointer) is banked, with only one copy of the R13
visible at a time.
R0 – R12: General Purpose Registers. These are
32 bit registers for data operations. Some 16-bit
Thumb instructions can only access a subset of
these registers (low registers R0-R7).
R13: Stack Pointers.  Contains two stack
pointers. They are banked so that only one is
visible at a time.
Main Stack Pointer (MSP) – The main stack
pointer used by the Operating system and
exception handlers.
Process Stack Pointer (PSP) – used by the
application code.
R14: Link Register. When a subroutine is called,
the return address is stored in the link register.
R15: The Program Counter. The program
counter is the current program address.
The Cortex-M3 also has a number of special
registers. They are -
Program Status registers (PSR)

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Interrupt Mask registers (PRIMASK,
FAULTMASK and BASEPRI).
Control register (CONTROL)
The Cortex-M3 has 18 registers in total
compared to 37 registers for traditional ARM

3-stage Pipeline Core Based on Harvard

Architecture
The ARM Cortex-M3 3-stage pipeline includes
instruction fetch, instruction decode and instruction
execution. Cortex-M3 also has separate buses for
instructions and data. The Harvard architecture reduces
bottlenecks common to shared data- and instruction
buses. Quickly Servicing Critical Tasks and Interrupts
From the low energy modes, EFM32's Cortex-M3 is
active within 2 µs and delivers 1.25 DMIPS/MHz on
the Dhrystone 2.1 Benchmark. The NVIC is an integral
part of the Cortex-M3 processor and ensures
outstanding interrupt handling abilities. It is possible
configure up to 240 physical interrupts with 1-256
levels of priority, and Non-Maskable Interrupts further
increase interrupt handling. For embedded systems this
enhanced determinism makes it possible to handle
critical tasks in a known number of cycles.

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 Reducing the 32-bit Footprint
The Cortex-M3 has a small footprint which reduces
system cost. High 32-bit performance reduces an
application's active periods, the periods where the CPU
is handling data. Reducing the active periods increases
the application's battery lifetime significantly, and the
EFM32 can spend most of the time in the efficient low
energy modes.

Memory Map
The Cortex-M3 has predefined memory maps,
which allows built in peripherals, such as the
interrupt controller and debug components, to be
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accessed by simple memory access instructions.
The predefined memory map also allows the
Cortex-M3 processor to be highly optimized for
speed and ease of integration in system-on-a-chip
(SoC) designs.
The Cortex-M3 design has an internal bus
infrastructure optimized for this memory usage. In
addition, the design allows these regions to be used
differently. For example, data memory can still be
put into the CODE region, and program code can
be executed from an external Random Access
Memory (RAM) region. The Cortex-M3 memory
map is outlined in figure as shown.

Operation Modes
The Cortex-M3 processor has two modes of
operation and two privilege levels. The operation
modes (thread mode and handler mode) determine
whether the processor is running a normal program
or running an exception handler like an interrupt
handler or system exception handler. The privilege
levels provide a mechanism for safeguarding
memory accesses to critical regions as well as
providing a basic security model.
When the processor is running a main
program (thread mode), it can be either in a
privileged state or a user state, but exception
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handlers can only be in a privileged state. When
the processor exits reset, it is in thread mode with
privileged access right. In this state, a program has
access to all memory ranges and can use all
supported instructions.
Software in the privileged access level can
switch the program into the user access level using
the control register. When an exception takes
place, the processor will always switch back to the
privileged state and return to the previous state
when exiting the exception handler. A user
program cannot change back to the privileged state
by writing to the control register. It has to go
through an exception handler that programs the
control register to switch the processor back into
the privileged access level when returning to
thread mode.

Nested Vector Interrupt Controller (NVIC)

The Cortex-M3 processor includes an interrupt
controller called the Nested Vectored Interrupt
Controller (NVIC). It is closely coupled to the
processor core and provides a number of features
as follows:
 Nested interrupt support
 Vectored interrupt support
 Dynamic priority changes support
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 Reduction of interrupt latency
 Interrupt masking
Nested Interrupt support - All the external
interrupts and most of the system exceptions can
be programmed to different priority levels. When
an interrupt occurs, the NVIC compares the
priority of this interrupt to the current running
priority level. If the priority of the new interrupt
handler is higher than the current level, the
interrupt handler of the new interrupt will override
the current running task.
Vectored Interrupt Support - When an interrupt
is accepted, the starting address of the interrupt
service routine (ISR) is located from a vector table
in memory.
Dynamic Priority Changes Support - Priority
levels of interrupts can be changed by software
during run time. Interrupts that are being serviced
are blocked from further activation until the ISR is
completed, so their priority can be changed
without risk of accidental reentry.
Reduction of Interrupt Latency - The Cortex-M3
processor also includes a number of advanced
features to lower the interrupt latency. These
include automatic saving and restoring some
register contents and reducing delay in switching
from one ISR to another.

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 Interrupt Masking - Interrupts and system
exceptions can be masked based on their priority
level or masked completely using the interrupt
masking registers BASEPRI, PRIMASK, and
FAULTMASK.

ARM-Cortex Microcontroller Programming

In the  present days, the microcontroller vendors are
offering 32-bit microcontrollers based on ARM cortex-
m3 architecture. Many embedded system developers are
starting to use these 32-bit microcontrollers for their 
projects. The ARM microcontrollers supports for both
low-level and high level programming languages. 
Some of the traditional microcontroller architectures are
made with many limitations therefore, difficult to use
the high level programming language.

[15]
For example the  memory size is limited and
performance might not be sufficient. The ARM
microcontrollers runs at 100Mhz frequency and higher
performance, therefore it supports the higher level
languages. The ARM microcontroller is
programmed with different IDES such as keiluvision3,
keiluvision4, coocox and so on. A 8-bit microcontroller
use 8-bit instructions and the ARM cortex-M uses a 32-
instructions.

The ARM Microcontroller Assembly Level

Programming:
The ARM cortex microcontroller is a 32-bit
microcontroller therefore all instructions are 32-bit long

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which is executed in a single cycle. It consists of  an
instruction set to perform the arithmetic, logical
and boolean operations. The ARM is a load-store
architecture,  then instructions are executed
conditionally.
Syntax: Load a  // a obtained the value from the place
called a //
ADD12 // 12 is added to the load value a //
Store a // final value is stored in the variable a//
The assembly language programming is developed by
the mnemonics such as ADD, SUB, MUL so on but for
ARM programming, some extra instructions added such
as ADCNES and SWINE, etc.
EX: 1. ORG 0000h
MOV r1, #10
MOV r2, #15
ADD r3, r2, r1 // r3=r2+r1 and the final value stored in
r3 register//
2.ORG 0000h
MOV r1, #10
MOV r2, #15
SUB r3, r2, r1 // r3=r2-r1 and the final value stored in
r3 register//

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 The ARM Coretex-M3 Microcontroller Embedded
C Level Programming:
WAP to toggle the single LED through Embedded C
language using ARM cortex microcontroller.
#include “stm32f10x_gpio.h”
#include “stm32f10x_rcc.h”

GPIO_InitTypeDef GPIO_InitStructure;
int i;
#define LED_PORT GPIOB
Void binky();
Void main()
{
Void binky();
}
void binky(void)
{
RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPI
OB, ENABLE);  //enable the PORTB pins//
GPIO_InitStructure.GPIO_Speed =
GPIO_Speed_50MHz;    //set the port frequency//
GPIO_InitStructure.GPIO_Mode  =
GPIO_Mode_Out_PP;    //set the PORTB in output//
GPIO_InitStructure.GPIO_Pin   = GPIO_Pin_All ;
//enabled all PORTB pins//
GPIO_Init(GPIOB, &GPIO_InitStructure); //initialize
the PORTB pins//

[18]
while(1){
GPIO_WriteBit(LED_PORT,GPIO_Pin_8,Bit_SET);
for (i=0;i<1000000;i++);
GPIO_WriteBit(LED_PORT,GPIO_Pin_8,Bit_RESET)
;
for (i=0;i<1000000;i++);
GPIO_WriteBit(LED_PORT,GPIO_Pin_9,Bit_SET);
for (i=0;i<1000000;i++);
GPIO_WriteBit(LED_PORT,GPIO_Pin_9,Bit_RESET)
;
for (i=0;i<1000000;i++);
GPIO_WriteBit(LED_PORT,GPIO_Pin_10,Bit_SET);
for (i=0;i<1000000;i++);
GPIO_WriteBit(LED_PORT,GPIO_Pin_10,Bit_RESE
T);
for (i=0;i<1000000;i++);
}
}

Salient Features of the Cortex-M3

 32-bit microprocessor.
 32-bit data path, 32-bit register bank and 32-bit
memory interfaces.
 Harvard Architecture – separate instruction bus and
data bus.
 3-stage pipeline with branch speculation.
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 Thumb-2 instruction set.
 No switching between ARM state and thumb state.
 Instruction fetches are 32 bits. Up to two
instructions can be fetched in one cycle. As a
result, there’s more available bandwidth for data
transfer.
 ALU with hardware divide and single cycle
multiply.
 Configurable Nested Vector Interrupt Controller
(NVIC).
 Maximum of 240 external interrupts can be
configured.
 Low gate count, suitable for low power designs.
 Memory Protection Unit (MPU).
 Operation Mode Selection – user and privilege
modes.
 Advanced debug components.

*********

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