CD54/74HC540, CD74HCT540,

CD54/74HC541, CD54/74HCT541
Data sheet acquired from Harris Semiconductor
SCHS189C
High-Speed CMOS Logic
January 1998 - Revised July 2004 Octal Buffer and Line Drivers, Three-State

Features Description
• ’HC540, CD74HCT540 . . . . . . . . . . . . . . . . . . . Inverting The ’HC540 and CD74HCT540 are Inverting Octal Buffers
and Line Drivers with Three-State Outputs and the capability
[ /Title • ’HC541, ’HCT541 . . . . . . . . . . . . . . . . . . . . . . Non-Inverting
to drive 15 LSTTL loads. The ’HC541 and ’HCT541 are Non-
(CD74 • Buffered Inputs Inverting Octal Buffers and Line Drivers with Three-State Out-
HC540 puts that can drive 15 LSTTL loads. The Output Enables
• Three-State Outputs (OE1) and (OE2) control the Three-State Outputs. If either
, OE1 or OE2 is HIGH the outputs will be in the high imped-
• Bus Line Driving Capability
CD74 ance state. For data output OE1 and OE2 both must be LOW.
HCT54 • Typical Propagation Delay = 9ns at VCC = 5V,
CL = 15pF, TA = 25oC Ordering Information
0,
• Fanout (Over Temperature Range) TEMP. RANGE
CD74 PART NUMBER (oC) PACKAGE
- Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads
HC541 CD54HC540F3A -55 to 125 20 Ld CERDIP
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads
, CD54HC541F3A -55 to 125 20 Ld CERDIP
CD74 • Wide Operating Temperature Range . . . -55oC to 125oC
CD54HCT541F3A -55 to 125 20 Ld CERDIP
HCT54 • Balanced Propagation Delay and Transition Times CD74HC540E -55 to 125 20 Ld PDIP
• Significant Power Reduction Compared to LSTTL CD74HC540M -55 to 125 20 Ld SOIC
Logic ICs CD74HC540M96 -55 to 125 20 Ld SOIC
• HC Types CD74HC541E -55 to 125 20 Ld PDIP
- 2V to 6V Operation CD74HC541M -55 to 125 20 Ld SOIC
- High Noise Immunity: NIL = 30%, NIH = 30% of VCC CD74HC541M96 -55 to 125 20 Ld SOIC
at VCC = 5V
CD74HC541PW -55 to 125 20 Ld TSSOP
• HCT Types CD74HC541PWR -55 to 125 20 Ld TSSOP
- 4.5V to 5.5V Operation CD74HCT540E -55 to 125 20 Ld PDIP
- Direct LSTTL Input Logic Compatibility,
CD74HCT540M -55 to 125 20 Ld SOIC
VIL= 0.8V (Max), VIH = 2V (Min)
CD74HCT540M96 -55 to 125 20 Ld SOIC
- CMOS Input Compatibility, Il ≤ 1µA at VOL, VOH
CD74HCT541E -55 to 125 20 Ld PDIP
CD74HCT541M -55 to 125 20 Ld SOIC
CD74HCT541M96 -55 to 125 20 Ld SOIC
NOTE: When ordering, use the entire part number. The suffix 96
denotes tape and reel.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.
Copyright © 2004, Texas Instruments Incorporated
1
 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Pinouts
CD54HC540 CD54HC541, CD54HCT541
(CERDIP) (CERDIP)
CD74HC540, CD74HCT540 CD74HC541
(PDIP, SOIC) (PDIP, SOIC, TSSOP)
TOP VIEW CD74HCT541
(PDIP, SOIC)
OE 1 20 VCC TOP VIEW
A0 2 19 OE2
OE1 1 20 VCC
A1 3 18 Y0
A0 2 19 OE2
A2 4 17 Y1
A1 3 18 Y0
A3 5 16 Y2
A2 4 17 Y1
A4 6 15 Y3
A3 5 16 Y2
A5 7 14 Y4
A4 6 15 Y3
A6 8 13 Y5
A5 7 14 Y4
A7 9 12 Y6
A6 8 13 Y5
GND 10 11 Y7
A7 9 12 Y6
GND 10 11 Y7

Functional Diagram
OEA OEB

540 541
D0 Y0 Y0

D1 Y1 Y1

D2 Y2 Y2

D3 Y3 Y3

D4 Y4 Y4

D5 Y5 Y5

D6 Y6 Y6

D7 Y7 Y7

2
CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

TRUTH TABLE

INPUTS OUTPUTS

OE1 OE2 An 540 541

L L H L H

H X X Z Z

X H X Z Z

L L L H L

H = HIGH Voltage Level

L = LOW Voltage Level
X= Don’t Care
Z = High Impedance

3
 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V Thermal Resistance (Typical, Note 1) θJA (oC/W)
DC Input Diode Current, IIK E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
For VI < -0.5V or VI > VCC + 0.5V . . . . . . . . . . . . . . . . . . . . . .±20mA M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
DC Output Diode Current, IOK PW (TSSOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . 83
For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . 150oC
DC Drain Current, per Output, IO Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC
For -0.5V < VO < VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . . . . . .±35mA Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . . 300oC
DC Output Source or Sink Current per Output Pin, IO (SOIC - Lead Tips Only)
For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA
DC VCC or Ground Current, ICC . . . . . . . . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions
Temperature Range, TA . . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC
Supply Voltage Range, VCC
HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V
HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V
DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC
Input Rise and Fall Time
2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)
4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)
6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation
of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.

NOTE:
1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Specifications
TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
HC TYPES
High Level Input VIH - - 2 1.5 - - 1.5 - 1.5 - V
Voltage
4.5 3.15 - - 3.15 - 3.15 - V
6 4.2 - - 4.2 - 4.2 - V
Low Level Input VIL - - 2 - - 0.5 - 0.5 - 0.5 V
Voltage
4.5 - - 1.35 - 1.35 - 1.35 V
6 - - 1.8 - 1.8 - 1.8 V
High Level Output VOH VIH or VIL -0.02 2 1.9 - - 1.9 - 1.9 - V
Voltage
-0.02 4.5 4.4 - - 4.4 - 4.4 - V
CMOS Loads
-0.02 6 5.9 - - 5.9 - 5.9 - V
High Level Output - - - - - - - - - V
Voltage
-6 4.5 3.98 - - 3.84 - 3.7 - V
TTL Loads
-7.8 6 5.48 - - 5.34 - 5.2 - V
Low Level Output VOL VIH or VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V
Voltage
0.02 4.5 - - 0.1 - 0.1 - 0.1 V
CMOS Loads
0.02 6 - - 0.1 - 0.1 - 0.1 V
Low Level Output - - - - - - - - - V
Voltage
6 4.5 - - 0.26 - 0.33 - 0.4 V
TTL Loads
7.8 6 - - 0.26 - 0.33 - 0.4 V
Input Leakage II VCC or - 6 - - ±0.1 - ±1 - ±1 µA
Current GND

4
 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

DC Electrical Specifications (Continued)

TEST
CONDITIONS 25oC -40oC TO 85oC -55oC TO 125oC
VCC
PARAMETER SYMBOL VI (V) IO (mA) (V) MIN TYP MAX MIN MAX MIN MAX UNITS
Quiescent Device ICC VCC or 0 6 - - 8 - 80 - 160 µA
Current GND
Three- State Leakage IOZ VIL or VIH VO = 6 - - ±0.5 - ±5.0 - ±10 µA
Current VCC or
GND
HCT TYPES
High Level Input VIH - - 4.5 to 2 - - 2 - 2 - V
Voltage 5.5
Low Level Input VIL - - 4.5 to - - 0.8 - 0.8 - 0.8 V
Voltage 5.5
High Level Output VOH VIH or VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V
Voltage
CMOS Loads
High Level Output -6 4.5 3.98 - - 3.84 - 3.7 - V
Voltage
TTL Loads
Low Level Output VOL VIH or VIL 0.02 4.5 - - 0.1 - 0.1 - 0.1 V
Voltage
CMOS Loads
Low Level Output 6 4.5 - - 0.26 - 0.33 - 0.4 V
Voltage
TTL Loads
Input Leakage II VCC and 0 5.5 - ±0.1 - ±1 - ±1 µA
Current GND
Quiescent Device ICC VCC or 0 5.5 - - 8 - 80 - 160 µA
Current GND
Three- State Leakage IOZ VIL or VIH VO = 5.5 - - ±0.5 - ±5.0 - ±10 µA
Current VCC or
GND
Additional Quiescent ∆ICC VCC - 4.5 to - 100 360 - 450 - 490 µA
Device Current Per (Note 2) -2.1 5.5
Input Pin: 1 Unit Load
NOTE:
2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

HCT Input Loading Table

UNIT LOADS

INPUT HCT540 HCT541

A0 - A7 1 0.4

OE2 0.75 0.75

OE1 1.15 1.15

NOTE: Unit Load is ∆ICC limit specific in DC Electrical Specifications

Table, e.g., 360µA max. at 25oC.

5
 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Switching Specifications CL = 50pF, Input tr, tf = 6ns

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

HC TYPES
Propagation Delay tPLH, tPHL CL = 50pF
Data to Outputs (540) 2 - - 110 - 140 - 165 ns

4.5 - - 22 - 28 - 33 ns

CL = 15pF 5 - 9 - - - - - ns

CL = 50pF 6 - - 19 - 24 - 28 ns

Data to Outputs (541) tPLZ, tPHZ CL = 50pF 2 - - 115 - 145 - 175 ns

4.5 - - 23 - 29 - 35 ns

CL = 15pF 5 - 9 - - - - - ns

CL = 50pF 6 - - 20 - 25 - 30 ns

Output Enable and Disable tPLZ, tPHZ CL = 50pF 2 - - 160 - 200 - 240 ns
to Outputs (540)
4.5 - - 32 - 40 - 48 ns

CL = 15pF 5 - 13 - - - - - ns

CL = 50pF 6 - - 27 - 34 - 41 ns

Output Enable and Disable tPLZ, tPHZ CL = 50pF 2 - - 160 - 200 - 240 ns
to Outputs (541)
4.5 - - 32 - 40 - 48 ns

CL = 15pF 5 - 14 - - - - - ns

CL = 50pF 6 - - 23 - 29 - 35 ns

Output Transition Time tTHL, tTLH CL = 50pF 2 - - 60 - 75 - 90 ns

4.5 - - 12 - 15 - 18 ns

6 - - 10 - 13 - 15 ns

Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF

Three-State Output CO - - 20 - 20 - 20 - 20 pF
Capacitance

Power Dissipation Capacitance CPD CL = 15pF 5 - 50 - - - - - pF

(Notes 3, 4) (540)

Power Dissipation Capacitance CPD CL = 15pF 5 - 48 - - - - - pF

(Notes 3, 4) (541)

HCT TYPES

Propagation Delay tPHL, tPLH

Data to Outputs (540) CL = 50pF 4.5 - - 24 - 30 - 36 ns

CL = 15pF 5 - 9 - - - - - ns

Data to Outputs (541) tPHL, tPLH CL = 50pF 4.5 - - 28 - 35 - 42 ns

CL = 15pF 5 - 11 - - - - - ns

Output Enable and Disable tPLZ, tPHZ CL = 50pF 4.5 - - 35 - 44 - 53 ns

to Outputs (540, 541)
CL = 15pF 5 - 14 - - - - - ns

Output Transition Time tTLH, tTHL CL = 50pF 4.5 - - 12 - 15 - 18 ns

Input Capacitance CI CL = 50pF - 10 - 10 - 10 - 10 pF

6
 CD54/74HC540, CD74HCT540, CD54/74HC541, CD54/74HCT541

Switching Specifications CL = 50pF, Input tr, tf = 6ns (Continued)

-40oC TO -55oC TO
25oC 85oC 125oC
TEST
PARAMETER SYMBOL CONDITIONS VCC (V) MIN TYP MAX MIN MAX MIN MAX UNITS

Three-State Output CO - - 20 - 20 - 20 - 20 pF
Capacitance

Power Dissipation Capacitance CPD CL = 15pF 5 - 55 - - - - - pF

(Notes 3, 4) (540, 541)

NOTES:
3. CPD is used to determine the dynamic power consumption, per channel.
4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Test Circuits and Waveforms

tr = 6ns tf = 6ns tr = 6ns tf = 6ns

VCC 3V
90% 2.7V
INPUT 50% INPUT 1.3V
10% GND 0.3V GND

tTHL tTLH tTHL tTLH

90% 90%
50% 1.3V
INVERTING 10% INVERTING
10%
OUTPUT OUTPUT
tPHL tPLH tPHL tPLH

FIGURE 1. HC TRANSITION TIMES AND PROPAGATION FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC DELAY TIMES, COMBINATION LOGIC

6ns 6ns tr 6ns tf 6ns

OUTPUT VCC OUTPUT 3V
90% 2.7
DISABLE 50% DISABLE 1.3
10% 0.3
GND GND
tPLZ tPZL tPLZ tPZL

OUTPUT LOW OUTPUT LOW

TO OFF 50% TO OFF
10% 10% 1.3V

tPHZ tPZH tPHZ

tPZH
90% 90%
OUTPUT HIGH 50% OUTPUT HIGH
TO OFF TO OFF 1.3V

OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS OUTPUTS

ENABLED DISABLED ENABLED ENABLED DISABLED ENABLED

FIGURE 3. HC THREE-STATE PROPAGATION DELAY FIGURE 4. HCT THREE-STATE PROPAGATION DELAY

WAVEFORM WAVEFORM

7
Test Circuits and Waveforms (Continued)

OTHER OUTPUT
INPUTS IC WITH RL = 1kΩ
TIED HIGH THREE- VCC FOR tPLZ AND tPZL
OR LOW STATE CL GND FOR tPHZ AND tPZH
OUTPUT 50pF
OUTPUT
DISABLE

NOTE: Open drain waveforms tPLZ and tPZL are the same as those for three-state shown on the left. The test circuit is Output RL = 1kΩ to
VCC, CL = 50pF.
FIGURE 5. HC AND HCT THREE-STATE PROPAGATION DELAY TEST CIRCUIT

8
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CD54HC540F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC540F3A

CD54HC541F ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC541F

CD54HC541F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HC541F3A

CD54HCT541F ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HCT541F

CD54HCT541F3A ACTIVE CDIP J 20 1 TBD Call TI N / A for Pkg Type -55 to 125 CD54HCT541F3A

CD74HC540E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC540E
(RoHS)
CD74HC540M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC540M
& no Sb/Br)
CD74HC540M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC540M
& no Sb/Br)
CD74HC541E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC541E
(RoHS)
CD74HC541EE4 ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HC541E
(RoHS)
CD74HC541M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC541M
& no Sb/Br)
CD74HC541M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC541M
& no Sb/Br)
CD74HC541M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HC541M
& no Sb/Br)
CD74HC541PW ACTIVE TSSOP PW 20 70 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ541
& no Sb/Br)
CD74HC541PWR ACTIVE TSSOP PW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HJ541
& no Sb/Br)
CD74HCT540E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT540E
(RoHS)
CD74HCT540M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT540M
& no Sb/Br)
CD74HCT540M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT540M
& no Sb/Br)

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

CD74HCT541E ACTIVE PDIP N 20 20 Pb-Free NIPDAU N / A for Pkg Type -55 to 125 CD74HCT541E
(RoHS)
CD74HCT541M ACTIVE SOIC DW 20 25 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT541M
& no Sb/Br)
CD74HCT541M96 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT541M
& no Sb/Br)
CD74HCT541M96E4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT541M
& no Sb/Br)
CD74HCT541M96G4 ACTIVE SOIC DW 20 2000 Green (RoHS NIPDAU Level-1-260C-UNLIM -55 to 125 HCT541M
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC540, CD54HC541, CD54HCT541, CD74HC540, CD74HC541, CD74HCT541 :

• Catalog: CD74HC540, CD74HC541, CD74HCT541

• Military: CD54HC540, CD54HC541, CD54HCT541

NOTE: Qualified Version Definitions:

• Catalog - TI's standard catalog product

• Military - QML certified for Military and Defense Applications

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
CD74HC540M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
CD74HC541M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
CD74HC541PWR TSSOP PW 20 2000 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1
CD74HCT540M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1
CD74HCT541M96 SOIC DW 20 2000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
CD74HC540M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HC541M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HC541PWR TSSOP PW 20 2000 367.0 367.0 38.0
CD74HCT540M96 SOIC DW 20 2000 367.0 367.0 45.0
CD74HCT541M96 SOIC DW 20 2000 367.0 367.0 45.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DW0020A SCALE 1.200
SOIC - 2.65 mm max height
SOIC

10.63 SEATING PLANE

TYP
9.97
PIN 1 ID 0.1 C
A
AREA
18X 1.27
20
1

13.0 2X
12.6 11.43
NOTE 3

10
11
0.51
20X
7.6 0.31 2.65 MAX
B 0.25 C A B
7.4
NOTE 4

0.33
TYP
0.10

0.25
SEE DETAIL A GAGE PLANE

1.27 0.3
0 -8 0.40 0.1

DETAIL A
TYPICAL

4220724/A 05/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm per side.
5. Reference JEDEC registration MS-013.

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 EXAMPLE BOARD LAYOUT
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2) SYMM

1
20

20X (0.6)

18X (1.27)

SYMM

(R0.05)
TYP

10 11

(9.3)

LAND PATTERN EXAMPLE

SCALE:6X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220724/A 05/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DW0020A SOIC - 2.65 mm max height
SOIC

20X (2)
SYMM
1
20

20X (0.6)

18X (1.27)

SYMM

10 11

(9.3)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:6X

4220724/A 05/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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