CS 224: Computer Organization

S.KHABET

CHAPTER 12:
Memory Organization

Outline
• Memory organization
• Memory hierarchy
• Main Memory
•Memory address map
• Cache Memory
• Associative mapping
• Direct mapping
• Direct Mapped Cache Example
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 Memory Organization (1/6)
 Recall:
 Information is stored in the memory as a collection of bits.
 Collection of bits are stored or retrieved simultaneously is
called a word.
 Number of bits in a word is called word length.
 Word length can be 16 to 64 bits.
 Another collection which is more basic than a word:
 Collection of 8 bits known as a “byte”
 Bytes are grouped into words, word length can also be
expressed as a number of bytes instead of the number of bits:
 Word length of 16 bits, is equivalent to word length of 2
bytes.
 Words may be 2 bytes (older architectures), 4 bytes (current
architectures), or 8+ bytes (modern architectures).

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 Memory Organization (2/6)
 Accessing the memory to obtain information requires specifying
the “address” of the memory location.
 Recall that a memory has a sequence of bits:
 Assigning addresses to each bit is impractical and
unnecessary.
 Typically, addresses are assigned to a single byte.
 “Byte addressable memory”
 Suppose k bits are used to hold the address of a memory
location:
Size of the memory in bytes is given by: 2^k
where k is the number of bits used to hold a memory address.
E.g., for a 16-bit address, size of the memory is 2^16= 65536 bytes

What is the size of the memory for a 24-bit address?

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 Memory Organization (3/6)
Byte 0
 Memory is viewed as a sequence of
bytes.
 Address of the first byte is 0
k
 Address of the last byte is 2 – 1.
 Where k is the number of bits used to
hold memory address.

 E.g. when k = 16,

 Address of the first byte is 0
 Address of the last byte is 65535
k
Byte 2 -1

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 Memory Organization (4/6)
Consider a memory organization:
 16-bit memory addresses
Word #0 Byte 0
 Size of the memory is = 2^16 =65536 B
Byte 1
Byte 2  [Byte 0..Byte 65535]
Byte 3  Word length is 4 bytes
Word #1 Byte 4
Number of words = Memory size(bytes) = ?
Word length(bytes)
=16384 words
 Word #0 starts at Byte #0.
Word #? Byte 65532  Word #1 starts at Byte #4.
Byte 65533
Byte 65534
Byte 65535 Last word (Word #?) starts at Byte#?

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Memory Organization (5/6)

Byte 0 Word #0
Byte 1
Byte 2
MAR Byte 3
Byte 4 Word #1 MDR
MAR register
contains the
address of the
memory location
addressed
Addr 65532 Byte 65532 Word #16383
Byte 65533 MDR contains either the
Byte 65534 data to be written to that
Byte 65535
address or read from that
address.

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 Memory Organization (6/6)
 Memory read or load:
 Place address of the memory location to be read from, into
MAR.
 Issue a Memory_read command to the memory.
 Data read from the memory is placed into MDR
automatically (by control logic).

 Memory write or store:

 Place address of the memory location to be written to into
MAR.
 Place data to be written into MDR.
 Issue Memory_write command to the memory.
 Data in MDR is written to the memory automatically (by
control logic).
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Memory Hierarchy (1/3)
 The memory unit is then an essential component in any
digital computer since it is needed for storing programs
and data.
 The memory unit that communicates directly with the CPU is
called the main memory.
 Devices that provide backup storage are called auxiliary
memory (Magnetic disks and tapes).

 Only programs and data currently needed by the processor

reside in main memory.

 There is a special very – thigh – speed memory called cache

employed between the CPU & main memory to compensate
for the mismatch in operating speeds.

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 Memory Hierarchy (2/3)
 Cache memory is sometimes used to increase the speed of
processing by making current programs and data available to
the CPU at a rapid rate (extremely fast), Whose access time is
close to processor logic clock cycle time.

 It used for storing segments of programs currently being

executed in the CPU and temporary data frequently needed.

 The cache organization is then concerned with the transfer of

information between a main memory and CPU.

 The part of the computer system that supervises the flow of

information between auxiliary memory and main memory is
called the memory management system.

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Memory Hierarchy (3/3)
Memory hierarchy in a computer system

Auxiliary memory
(Secondary)

Magnetic
tapes Main
I/O
Processor memory
Magnetic
disks
CPU Cache
memory

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 Main Memory (1/4)
 The main 2 types of main memory are:
 RAM which is to used to refer to a read/write random-access
memory
 ROM which is to used to refer to a read only random-access
memory.

 Integrated circuit RAM chips are available in two possible

operating modes, static and dynamic .

 The static RAM consists essentially of internal flip–flops that

store the binary information, the stored information remains
valid as long as power is applied to the unit.

 The dynamic RAM stores the binary information in the form of

electric charges that are applied to capacitors.

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 Main Memory (2/4)
 The stored charge on the capacitors tend to discharge with time
and the capacitors must be periodically recharged by refreshing
the dynamic memory.
 The dynamic RAM offers reduced power consumption and
larger storage capacity in single memory chip.
 But the static RAM is easier to use and has shorter read and
write cycles.
 ROM is used for storing programs that are permanently
resident in the computer.
 The ROM portion of main memory is needed for storing an
initial program called a bootstrap loader.
 The bootstrap loader is a program whose function is the start
the computer software operating when power is turned on.
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 Main Memory (3/4)
 RAM and ROM chips are available in a variety of sizes.
 For example of a 1024 x 8 memory can be constructed with
128 x 8 RAM chips and 512 x 8 ROM chips.

Chip select 1 CS1

Chip select 2 CS2
Read RD 128X8 8-bit data bus
Write WR RAM
7-bit address AD7 Memory State of data bus
CS1 CS2 RD WR function
0 0 x x Inhibit High-impedance
0 1 x x Inhibit High-impedance
1 0 0 0 Inhibit High-impedance
1 0 0 1 Write Input data to RAM
1 0 1 x Read Output data from RAM
1 1 x x Inhibit High-impedance
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Main Memory (4/4)

Chip select 1 CS1

Chip select 2 CS2 8-bit
512X8 data bus
ROM
9-bit address AD9

CS1 CS2 Memory function State of data bus

0 0 Inhibit High-impedance
0 1 Inhibit High-impedance
1 0 Read Output data from ROM
1 1 Inhibit High-impedance

The data bus can only be in an output mode.

When chip is enabled by the 2 select inputs, the byte selected

by the address lines appears on the data bus 14
Main Memory: Memory address map (1/4)

Memory address map

 The addressing of memory can be established by means of a

table , called a memory address map, that specifies the
memory address assigned to each chip.

 For example, assume that a computer system needs 512

bytes of RAM and 512 bytes of ROM.

 The memory address map for this configuration is shown

in table following table.

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 Main Memory: Memory address map (2/4)
Memory Address Map for Microprocomputer

Address bus
Component Hexadecimal address 10 9 8 7 6 5 4 3 2 1
RAM 1 0000-007F 0 0 0 X X X X X X X
RAM 2 0080-00FF 0 0 1 X X X X X X X
RAM 3 0100-017F 0 1 0 X X X X X X X
RAM 4 0180-01FF 0 1 1 X X X X X X X
ROM 0200-03FF 1 X X X X X X X X X

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Main Memory: Memory address map (3/4)
 Although there are 16 lines in the address bus, the table shows
only 10 lines because the other 6 are not used in this example
and are assumed to be zero.
 The small x's under the address bus lines designate those lines
that must be connected to the address inputs in each chip.
 The RAM chips have 128 bytes and need 7 address lines.
 The ROM chip has 512 bytes and needs 9 address lines.
 The x's are always assigned to the low – order bus lines:
 lines 1 through 7 for the RAM
 and lines 1 through 9 for the ROM.
 The distinction between a RAM and ROM address is done
with another bus line. This can be done by choosing line 10 for
this purpose. 17
 Main Memory : Memory address map (4/4)
Memory address map & Connection to CPU
CPU
16 – 11 10 9 8 7 -1 RD WR Data bus CS1
CS2
RD 128X8
WR AM 1
Decoder AD7
3210 CS1
CS2
RD 128X8
WR RAM 2

Data
CS1 AD7
CS2
RD 128X8
WR RAM 3
CS1
CS2 AD7
RD 128X8
WR RAM 4
AD7
CS1
CS2
512X8
ROM
AD9
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 Cache Memory (1/5)
 Analysis of a large number of typical programs has shown that
the references to memory at any given interval of time tent to be
confined within a few localized areas in memory.

 This phenomenon is known as the property of locality of

reference.

 If the active portions of the program and data are placed in a fast
small memory, the average memory access time can be reduced,
thus reducing the total execution time of the program.

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Cache Memory (2/5)

 The performance of cache memory is frequently measured in terms

of a quantity called hit ratio.

 When the CPU refers to memory and finds the word in cache, it is
said to produce a hit.

 If the word is not found in cache , it is in main memory and it

counts as a miss .

 No. of hits = number of successful cache memory references.

 Misses = number of unsuccessful cache memory references.

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Cache Memory (3/5)
 The ratio of the number of hits divided by the total CPU
references to memory (hits plus misses) is the hit ratio,
[Hit ratio = hits/ (hits + misses)]
 Average access time for a memory with a single-level cache
formula. A = C + (1-H)M
 A is the average access time of the system
 M is the access time of the main memory
 C is the access time of the cache
 H is the percent of accesses that are satisfied from the
cache.
 Example, a computer with cache access time of 100 ns, a main
memory access time of 1000 ns , and a hit ratio of 0.9,
produces an average access time of 200 ns.
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Cache Memory (4/5)
 The transformation of data from main memory to
cache memory is referred to as a mapping process.
 Three types of mapping procedures are of practical
interest when considering the organization of cache
memory.
 Direct mapping.
 Associative mapping.
 Set-associative mapping.

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 Cache Memory (5/5)
 Small amount of fast memory
 Sits between normal main memory and CPU
 May be located on CPU chip or module
 For every word stored in cache, there is a duplicate copy in main
memory.
 To illustrate these 3 mapping procedures, a specific example of a
memory organization will be used as shown.

Bloc transfer Word transfer

Main Memory Cache Memory CPU

32k X 12 512 X 12

Example of Cache Memory 23

Cache Memory : Associative Mapping (1/2)
 The fastest and most flexible cache organization uses an
Associative Mapping, as illustrated in the following diagram.

Associative mapping cache (all numbers in octal)

CPU address (15 bits)

Argument register
15-bit Address 12-bit Data
01000 3450
02777 6710
22345 1234

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Cache Memory: Associative Mapping (2/2)
 The associative memory stores both the address and content
(data) of the memory word.
 This permits any location in cache to store any word from
main memory.
 A CPU address of 15 bits is placed in the argument register
and the associative memory is searched for a matching
address.
 If the address is found , the corresponding 12- bit data is read
and sent to the CU.
 If no match occurs, the main memory is accessed for the
word.
 The address-data pair is then transferred to the associative
cache memory based on a replacement algorithm.
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Cache Memory: Direct mapping (1/5)
 Associative memories are expensive compared to random access
memories, which can be used for the cache, because of the added
logic associated with each cell.
 This organization is shown in the following diagram:

6 bits 9 bits
Tag Index

00 000 000
Octal 512 X12
Octal 32 k X12
Address Cache memory
Address Main memory
Address= 9 bits
Address= 15 bits
Data= 12 bits
Data= 12 bits 777
77 777 26
Cache Memory: Direct mapping (2/5)
1. Direct mapping cache Organization:
Block size of one word (simplest cache)
Memory
address Memory data Index
00000 1220 address Tag data
000 00 1220
00777 2340
01000 3450

01777 4560
02000 5670

777 02 6710
02777 6710
Cache memory
Main memory 27
Cache Memory: Direct mapping (2/5 bis)
Address Main Memory Cache 4-Block Direct
0000 0 Index Mapped Cache
0001 1
0010 2
00 0
0011 3
01 1
0100 4
10 2
0101 5
11 3
Memory block address
0110 6
0111 7 Tag Index
1000 8
1001 9
1010 10  Index determines block in cache
1011 11  If number of cache blocks is power of
1100 12 2, then cache index is just the lower n
1101 13
bits of memory address
1110 14
1111 15 28
Cache Memory: Direct mapping (3/5)
2. Direct mapping cache Organization:
Block size of eight words
Index Tag Data
000 01 3450
Block 0
01 6578
6 bits 6 bits 3 bits
007
010 Tag Block Word
Block 1
017 Index

770 02 9989
Block 63
02 6710
777 29
Cache Memory: Direct mapping (3/5 bis)
 If block size > 1 word, rightmost bits of index are really the
offset of a word (possibly byte number) within the indexed block

ttttttttttttttttt iiiiiiiiii oooo

Tag to check if Index to select Word offset within

have correct block block block

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Cache Memory: Direct mapping (4/5)
 The CPU address of 15 bits is divided into two fields.
 The 9 least significant bits constitutes the index field and the
remaining 6 bits form the tag field.
 The number of bits in the index field = the number of
address bits required to access the cache memory.
 In the general case , there are 2^k words in cache memory and
2^n words in main memory . The n-bits memory address is
divided into two fields:
 k bits for the index to access the cache,
 n-k bits for the tag field.
 The direct mapping cache organization uses:
 The n-bit address to access the main memory,
 And the k-bit index to access the cache.
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Cache Memory: Direct mapping (5/5)
 Each word in cache consists of the data word and its
associated tag.

 When the CPU generates a memory request:

 The index field is used for the address to access the
cache.
 The tag field of the CPU address is compared with the
tag in the word read from the cache. If the two tags,
match , there is a hit and the desired data word is in
cache.
 If there is no match, there is a miss and the required
word is read from main memory.
 It is then stored in the cache together with the new tag,
replacing the previous value.
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Direct Mapped Cache Example
 Direct mapped – each memory block can occupy one
and only one cache block
 Example:
 Cache block size: 16 words
 Memory = 64K (4K blocks)
 Cache = 2K (128 blocks)
 Memory block n occupies cache block (n mod 128)
 Consider address $2EF4
001011101111 0100
block: $2EF = 751 word: 4
 Cache:
00101 1101111 0100
tag: 5 block: 111 word: 4
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Direct Mapped Cache Example

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