MIKPO 2 cheatsheet

Based on the book: AVR microcontroller and embedded systems Using Assembly and C by Muhamad Ali, Sarmad
Naimi, Sepehr Naimi

by christina_

25 Αυγούστου 2018

Περιεχόμενα

1 TIMERS 2
1.1 STEP TO PROGRAM TIMER0 IN NORMAL MODE . . . . . . . . . . . . . . . . . . . . . . . 2
1.2 FINDING VALUES TO LOAD INTO THE TIMER . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 CLEAR TIMER0 ON COMPARE MATCH (CTC) MODE . . . . . . . . . . . . . . . . . . . . . 4
1.4 Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.5 Timer1 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.6 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1.7 CTC Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2 Interrupts and Polling 12

2.1 Step in executing an interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
2.2 Compare Match and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.3 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

3 ADC 17
3.1 Programming ADC using polling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Programming ADC using interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.3 DAC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

4 Pulse Width Modulation (PWM) 21

4.1 PWM in 8-bit timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2 Fast PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3 Phase Correct PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
4.4 Difference betweeen Phase Correct PWM mode and Fast PWM mode . . . . . . . . . . . . . . 24
4.5 Generating waves using Timer2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.6 PWM modes in Timer1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4.7 Generating waves with different frequencies . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
4.8 Phase Correct PWM mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

5 Examples 38
5.1 Flashing Led example ( credits to : Maylo) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6 Σημειώσεις 40
TeX Gyre Schola

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1 TIMERS
• TCNTn(timer/counter): counts up w/every puls, reset->zero

• TOVn(Timer Overflow) flag: when timer overflows, it is set to 1, must be cleared later(clear by setting
1)

• TCCRn(timer/counter control register): sets modes ( counter or timer)

• OCRn(Output Compare Register): The content of the OCR is compared to the content of TCNT and
when they are equal the OCFn(Output Compare Flag) will be set

• TIFR(Timer/Counter Interrupt Flag Register): Contains the flag of different timers Timers are in
the I/O registers so we use IN and OUT instructions.

(
Σχήμα 1: TCCR0

1.1 STEP TO PROGRAM TIMER0 IN NORMAL MODE

1. Load the TCNT0 reg with initial value

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2. Load the value to TCCR0 indicating which mode is to be used and the prescaler option.
3. Monitor the TOV0 and get out of the loop when it is set
4. Stop the timer by disconnecting the clock source with [LDI r20, 0x00, out TCCR0, r20]
5. Clear the TOV0 flag for the next round
6. Start again by loading the register TCNT0

1
2 .INCLUDE "M32DEF. INC" cycles
3 .MACRO INITSTACK ; SET STACK
4 LDI R20 , HIGH(RAMEND)
5 OUT SPH, R20
6 LDI R20 , LOW(RAMEND)
7 OUT SPL, R20
8 .ENDMACRO
9 INITSTACK
10 LDI R16 , 1<<5 ; R16=00010 0000 FOR PB5
11 SBI DDRB, 5 ; PB5 AS AN OUTPUT
12 LDI R17 , 0
13 BEGIN:
14 OUT PORTB, R17 ;CLEAR PORTB
15 RCALL DELAY ;CALL TIMER DELAY 3
16 EOR R17 , R16 ;TOGGLE D5 OF R17 1
17 OUT PORTB, R17 ;TOGGLE PB5 1
18 RJMP BEGIN 2
19 −−−−−−−−−−−−−
20 DELAY:
21 LDI R20 , 0XF2 ;LOAD TIMER 1
22 OUT TCNT0, R20 1
23 LDI R20 , 0X01 1
24 OUT TCCR0, R20 ;TIMER 0 , NORMAL MODE, NO PRESCALER 1
25
26 AGAIN:
27 IN R20 , TIFR ;READ TIFR 1
28 SBRS R20 , TOV0 ; IF TOV0 IS SET SKIP NEXT INSTRUCTION 1/2
29 RJMP AGAIN 2
30 LDI R20 , 0X00 1
31 OUT TCCR0, R20 ;STOP TIMER 1
32 ;CLEAR TOV0 FLAG
33 LDI R20 , (1<<TOV0) 1
34 OUT TIFR , R20 1
35 RET 4
36 = 24

Each clock has period 1/XTAL. It also needs an extra clock when it rolls from FF to 00 and sets the TOV
flag. Concluding: Delay = (FF-XX+1) · 1/F where FF is 0b111111111 and XX is the TCNT initial value. or
(256 -NNN) · 1/F where NNN is the value of TCNT0 reg in decimal

1.2 FINDING VALUES TO LOAD INTO THE TIMER

1. Calculate the period of the timer clock with
Tclock = 1/Ftimer

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2. Divide the desired time delay by Tclock . This says how many clocks we need (n).

3. Perform x = 256-n

4. Convert x to hex,say xx. This is the initial value to be loaded into the timer’s register

5. Set TCNT0 = xx

ex.if XTAL=8MHz then each clock: T = 1/XT AL = 1/8M = 0.125µ sec

If we have a prescaler we perform the following steps: XTAL oscillator –> ÷prescaler —> TCNT0

1.3 CLEAR TIMER0 ON COMPARE MATCH (CTC) MODE

The timer is still incremented by a clock but it counts up until the contents of the register TCNT0
becomes equal to the contents of OCR0. Then the timer will be cleared and the OCF0 flag will be set in
the next clock.
1
2 .INCLUDE "M32DEF. INC"
3 .MACRO INITSTACK ; SET STACK
4 LDI R20 , HIGH(RAMEND)
5 OUT SPH, R20
6 LDI R20 , LOW(RAMEND)
7 OUT SPL, R20
8 .ENDMACRO
9 INITSTACK
10 LDI R16 , 0x08 ; R16=00010 0000 FOR PB5
11 SBI DDRB, 3 ; PB3 AS AN OUTPUT
12 LDI R17 , 0
13 BEGIN:
14 OUT PORTB, R17 ;CLEAR PORTB
15 RCALL DELAY ;CALL TIMER DELAY
16 EOR R17 , R16 ;TOGGLE D3 OF R17
17 RJMP BEGIN
18 −−−−−−−−−−−−−
19 DELAY:
20 LDI R20 , 0x00 ;LOAD TIMER
21 OUT TCNT0, R20
22 LDI R20 , 9
23 OUT OCR0, R20 ;LOAD OCR0
24 LDI R20 , 0X09
25 OUT TCCR0, R20 ;TIMER 0 , CTC MODE, INT CLOCK
26
27 AGAIN:
28 IN R20 , TIFR ;READ TIFR
29 SBRS R20 , OCF0 ; IF OCF0 IS SET SKIP NEXT INSTRUCTION
30 RJMP AGAIN
31 LDI R20 , 0x00
32 OUT TCCR0, R20 ;STOP TIMER
33 ;CLEAR OCF0 FLAG
34 LDI R20 , (1<<OCF0)
35 OUT TIFR , R20
36 RET

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If TCCNT0 is bigger than OCR0 then it counts up until FF , sets the TOV0 flag and then it counts up
until OCR0. The TMSK register containts the interrupt enable bits for the timers. We must set HIGH the
bits of the interrupts we want to enable.
*OCR0 = number of pulses we want -1.

FIND VALUES FOR DELAY

1. Find Tclock = 1/Fclock

2. Divide the wanted delay with Tclock . This gives us the number n of pulses needed.

3. Perform 256 - n.

4. Convert the result to hex.

5. Load the value to TCNT0.

PRESCALING
XT AL XT AL
• Find the prescaler: desired delay = N ·21 6
=⇒ desireddelay = N ·(OCR+1) =⇒ OCR = ..
prescaler
• Max Delay = 256 · XT AL
XT AL
• new frequency = prescaler

• new period (length of pulses) = Tclock · prescaler

desireddelay·XT AL
• Value for Timer: n = prescaler =⇒ T CN T 0 = 256 − n

1.4 Timer1
Since Timer1 is a 16bit timer, its 16bit register is split in two bytes:TCNT1L(Low Byte) and TCNT1H(High
Byte). It also has 2 control registers: TCCR1A and TCCR1B.Of course there is the TOV01 flag. Timer1 has
also prescaler options:1:1, 1:8, 1:64, 1:256 and 1:1024. There are two OCR registers in timer1 : OCR1A and
OCR1B, and each one has a seperate flag which acts independently. Whenever TCNT1 equals OCR1A, the
OCF1A flag will be set on the next timer clock. When TCNT1 equals OCR1B, the OCF1B flag will be set
on the next timer clock. OCR1A and OCR1B are both 16bit registers. For example, OCR1A is made from
2 8bit registers OCR1AH and OCR1AL.
There is also a register named ICR1 which is used for operations like capturing

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The WGM13, WGM12, WGM11 and WGM10 bits define the mode of Timer1.

1.5 Timer1 modes

1.5.1 Normal Mode
In this mode the counter counts up until $FFFF(max value) and then it rolls over to 0000. When it rolls
over the TOV1 flag

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1.5.2 CTC Mode

In mode 4 (CTC mode) it counts up until the content of TCNT1 register becomes equal to the content
of OCR1A(compare match occurs). Then the timer will be cleared in the next clock. Also the OCF1A flag
will be set.

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2 Interrupts and Polling

Interrupts: Upon receiving the interrupt signal , the microcontroller stops whatever its doing and
serves the device.The program associated with the interrupt is called Interrupt Service Routine or Interrupt
Handler. It can serve many devices(Not at the same time of course)

Polling: In polling the microcontroller always monitors the status of a given device. When status is met,
it performs the service. After that it moves on to monitor the next device until each on is served. It is not

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very efficient. It cannot assign priority.

2.1 Step in executing an interrupt

Upon activation of interrupt, the microcontroller goes through the following steps:

1. It finishes the instruction it is currently executing and saves the baddress of the next instruction(program
counter) on the stack.

2. It jumps to a fixed location in memory called the interrupt vector table. The interrupt vector table
directs the microcontroller to the address of the interrupt service routine (ISR).

3. The microcontroller starts to execute the interrupt service subroutine until it reaches the last instruction
of the subroutine, which is RETI ( return from interrupt)

4. Upon executing the RETI instruction, the microcontroller returns to the place where it was interrupted.
First, it gets the program counter (PC) address from the stack by popping the top bytes of the stack
into the PC. Then it starts to execute from that address.

*Notice: In the ISR the number of POPs and PUSHes must be equal otherwise it might have a problem
in step 4. Because the service routine for an interrupt is too long to fit into the memory space allocated, a
JMP instruction is placed in the vector table to point at the address of the ISR. It redirects the processor
away from the interrupt vector table.
Upon reset, interrupts are disabled. D7 of SREG is responsible for enabling and disabling interrupts
globally. We set it HIGH with SEI and LOW with CLI. If I=1 , each interrupt is enabled by setting to
HIGH the interrupt enable (IE) flag bit for that interrupt. If I=0, no interrupt will be responded to, even
if the IE bit is high. When it is serving an interrupt , it writes I=0 so it cannot serve any more interrupts
until this one is over. If we want it to, we should write SEI in the ISR. With the RETI instruction, it
automatically writes I=1. In the ISR for TIMER0 , there is no need to clear TOV0 flag since the AVR clears
it internally upon jumping to the interrupt handling table.
We cannot change the reset location 0x00 and the timers’ overflow addresses. We just use them to redirect
in location with more space (arbitrary address) where we write the ISR.

1 .ORG 0x { Vector Address }

2 JMP MyISRHandler
3 ;−−−−−
4 MyISRHandler :
5 ; ISR code t o execute here
6 RETI

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Σχήμα 2: Interrupt Vector of ATmega128

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2.2 Compare Match and Interrupts

When the content of TCNT matches with OCR, the OCF flag is set which causes the compare match
interrupt to occur.
Using Timer0, write a program that toggles pin PORTB.5 every 40μs while transfering at the same
time data from PORTC to PORTD.Assume XTAL=1MHz
1 1 / 1 Mhz = μ1s and μ40sμ / 1 s =40. OCR0=40−1=39
2
3 .INCLUDE "M32DEF. INC"
4 .ORG 0x0 ;LOCATION FOR RESET
5 JMP MAIN ; SKIP THE INTERRUPT VECTOR TABLE
6 .ORG 0x14 ; ISR LOCATION FOR TIMER0 COMPARE MATCH
7 JMP T0_CM_ISR
8 ;MAIN PROGRAM FOR INITIALIZATION AND KEEPING CPU BUSY
9 .ORG 0x100
10 MAIN:
11 INITSTACK
12 SBI DDRB, 5 ; PB5 AS AN OUTPUT
13 LDI R20 , (1<<OCIE0 )
14 OUT TIMSK, R20 ;ENABLE TIMER0 COMPARE MATCH INTERRUPT
15 SEI ; SET I (ENABLE INTERRUPTS GLOBALLY)
16 LDI R20 , 39
17 OUT OCR0, R20 ;LOAD TIMER0 WITH 39
18 LDI R20 , 0x09
19 OUT TCCR0, R20 ;START TIMER0, CTC MODE, INT CLK, NO PRESCALER
20 LDI R20 , 0x00
21 OUT DDRC, R20 ;MAKE PORTC INPUT
22 LDI R20 , OxFF
23 OUT DDRD, R20 ;MAKE PROTD OUTPUT
24 ;−−−−−−−−INFINITE LOOP
25 HERE:
26 IN R20 , PINC ;READ FROM PORTC
27 OUT PORTD, R20 ;AND SEND IT TO PORTD
28 JMP HERE ;KEEP CPU BUSY WHILE WAITING FOR INTERRUPT

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29 ;−−−−−−−−ISR FOR TIMER0( IT IS EXXECUTED EVERY μ40s )

30 T0_CM_ISR :
31 IN R16 ,PORTB ;READ PORTB
32 LDI R17 , 0x20 ; 00100000 FOR TOGGLING PB5
33 EOR R16 , R17
34 OUT PORTB, R16 ;TOGGLE PB5
35 RETI ;RETURN FROM INTERRUPT

If we wanted to use Timer1, XTAL=8MHz and prescaler=1024 :

1
Tclock = MHz · 1024 = 128µs
8
and
1s
= 7812
128µs
. That means OCR1A=7811 and we write:
1 LDI R20 , HIGH( 7 8 1 1 )
2 OUT OCR1AH, R20
3 LDI R20 , LOW( 7 8 1 1 )
4 OUT OCRIAL, R20

2.3 External Interrupts

We have 3 external interrupts INT0, INT1, INT2 and they are located at pins P1, P2 and P3 respectively.
They are enabled with the INTx bit in GICR register. When an external interrupt is in an edge-triggered
mode(falling edge, rising edge, changing level), upon triggering an interrupt request, the related INTFx
flag becomes set.If I=1, AVR will jump to the corresponding interrupt vector location and the INTFx flag
will be cleared automatically. Otherwise, the flag remains set.

The ISC2 bit of MCUCSR register defines whether INT2 activates in the falling edge or in the rising
edge(0 is falling edge triggered).

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If two interrupts are activated at the same time, the interrupt with the higher priority is served first.
The lower the address in the interrupt vector, the higher the priority of the interrupt is.

3 ADC
For an n-bit ADC the step size is
Vref
2n
We also have n outputs
D0 − Dn−1
with
Vin
Dout =
step size

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When SC (Start of Conversion) is activated the ADC starts converting the Vin to an n-bit digital number.
When the conversion is completed the EOC (End of Conversion) signal notifies the CPU that the converted
data is ready.
There are 5 major registers: ADCH(High Data), ADCL(Low Data), ADCSRA(ADC Control and Status
Register), ADMUX(ADC multiplexer selection register) and SPIOR(Special Function I/O register).

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In AVR , the first conversion takes 25 ADC clocks cycles and every other 13 ADC cycles.

3.1 Programming ADC using polling

1. Make the pin for the selected ADC channel as an input pin.

2. Turn on the ADC module in the AVR because it is disabled upon the power on reset.

3. Select the conversion speed. Use registers ADPS2:0.

4. Select voltage reference and ADC input channels. Use REFS0 and REFS1 bits in the ADMUX registers
to select voltage reference and the MUX4:0 bits in the ADMUX to select the ADC input channel.

5. Activate the Start of Conversion by writing 1 to ADSC bit of ADCSRA.

6. Wait for the conversion to finish by polling the ADIF bit in ADCSRA.

7. After the ADIF bit has gone HIGH, read the ADCL and ADCH registers to get the digital data
output.Notice: You HAVE to read ADCL BEFORE ADCH

8. If you want to read the seleced channel again go back to step 5

9. If you want to select another Vref source or input channel go back to step 4

1
2 .INCLUDE "M32DEF. INC"
3 LDI R16 , 0xFF
4 OUT DDRB, R16 ;MAKE PORTB AN OUTPUT
5 OUT DDRD, R16 ;MAKE PORTD AN OUTPUT
6 LDI R16 , 0
7 OUT DDRA, R16 ;MAKE PORTA AN INPUT FOR ADC
8 LDI R16 , 0x87
9 OUT ADCSRA, R16 ;ENABLE ADC AND SELECT CK/128
10 LDI R16 , 0xC0 ; 2.56 Vref , ADC0 SINGLE ENDED
11 OUT ADMUX, R16 ; INPUT, RIGHT−JUSTIFIED DATA
12 READ_ADC:
13 SBI ADCSRA, ADSC ;START CONVERSION
14 KEEP_POLLING: ;WAIT FOR CONVERSION TO END
15 SBIS ADCSRA, ADIF ; IS THE CONVERSION OVER YET?
16 RJMP KEEP_POLLING ;KEEP POLLING END OF CONVERSION
17 SBI ADCSRA, ADIF ;WRITE 1 TO CLEAR ADIF FLAG
18 IN R16 , ADCL ;YOU HAVE TO READ THE ADCL FIRST
19 OUT PORTD, R16 ; GIVE THE LOW BYTE TO PORTD
20 IN R16 , ADCH ;READ ADCH AFTER ADCL

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21 OUT PORTB, ADCH ; GIVE THE HIGH BYTE TO PORTB

22 RJMP READ_ADC ;KEEP REPEATING IT

3.2 Programming ADC using interrupts

To program ADC using interrupts we need to set HIGH the ADIE flag.Upon completion of conversion
the ADIF flag changes to HIGH; if ADIE is 1, it will force the CPU to jump to the ADC interrupt handler.
1 .INCLUDE "M32DEF. INC"
2 .CSEG
3 RJMP MAIN
4 .ORG ADCCaddr
5 RJMP ADC_INT_HANDLER
6 .ORG 40
7 ;−−−−−−−−−−−−−−−−−
8 MAIN:
9 LDI R16 , HIGH(RAMEND)
10 OUT SPH, R16
11 LDI R16 , LOW(RAMEND)
12 OUT SPL, R16 ; INITIALIZE STACK
13 SEI ;ENABLE INTERRUPTS
14 LDI R16 , 0xFF
15 OUT DDRB, R16 ;MAKE PORTB AN OUTPUT
16 OUT DDRD, R16 ;MAKE PORTD AN OUTPUT
17 LDI R16 , 0
18 OUT DDRA, R16 ;MAKE PORTA AN INPUT FOR ADC
19 LDI R16 , 0x8F
20 OUT ADCSRA, R16 ;ENABLE ADC AND SELECT CK/128
21 LDI R16 , 0xC0 ; 2.56 Vref , ADC0 SINGLE ENDED
22 OUT ADMUX, R16 ;INPUT RIGHT−JUSTIFIED DATA
23 SBI ADSCRA, ADSC ;START CONVERSION
24 WAIT_HERE:
25 RJMP WAIT_HERE ;KEEP REPEATING IT
26 ;−−−−−−−−−−
27 ADC_INT_HANDLER:
28 IN R16 , ADCL ;YOU HAVE TO READ ADCL FIRST
29 OUT PORTD, R16 ; GIVE THE LOW BYTE TO PORTD
30 IN R16 , ADCH ;READ ADCH AFTER ADCL
31 OUT PORTB, R16 ; GIVE THE HIGH BYTE TO PORTB
32 SBI ADCSRA, ADSC ;START CONVERSION AGAIN
33 RETI

3.3 DAC
Create a stair ramp using DAC
1
2 LDI R16 , 0xFF
3 OUT DDRB, R16 ;MAKE PORTB AN OUTPUT
4 AGAIN:
5 INC R16 ;INCREMENT R16
6 OUT PORTB, R16 ;SENT R16 TO PORTB
7 NOP ;LET DAC TO RECOVER

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8 NOP
9 RJMP AGAIN

4 Pulse Width Modulation (PWM)

The speed of the motor depends on three factors:(a)load (b)voltage and (c)speed.For a fixed load we can
maintain a stead speed with PWM.By changing the width of the pulse , we can change the power provided,
thereby changing the speed. The wider the pulse, the higher the speed.

4.1 PWM in 8-bit timers

The frequency of the generated wave is:
Foscillator
Fgenerated wave =
256 · N
, where N is depending on the prescaler.

4.2 Fast PWM mode

In the Fast PWM, the counter counts like it does in Normal Mode. After the timer is started, it
counts up until it reaches 0xFF. When it rolls over from0xFF to 00 , it sets HIGh the TOV0 flag. When
COM01:00=10, the waveform generator clears the OC0 pin whenever compare match occurs and sets it
at the top.This mode is called Non-Inverted PWM. When COM01:00=11, the waveform generator sets the
OC0 pin whenever compare match occurs and clears it at the top.This mode is called Inverted PWM.
The Duty Cycle of the generated wave in FAST PWM is:

OCR0 + 1
Duty Cycle = · 100 for non-inverted mode
256
and
255 − OCR0
Duty Cycle = · 100 for inverted mode
256
Example: To generate a wave with duty cycle of 75% in non inverted mode, calculate the OCR0. Solution:
75 = (OCR0) · 100/256->OCR0=191

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1 .INCLUDE "M32DEF. INC"

2 RJMP MAIN
3 .ORG 0x16 ;TIMER OVERFLOW INTERRUPT VECTOR
4 NEG R20 ;NEGATIVE R20
5 OUT OCR0, R20 ;OCR0=R20
6 RETI ;RETURN INTERRUPT
7 MAIN:
8 INITSTACK
9 SBI DDRB, 3 ;OC0 AS OUTPUT
10 LDI R20 , 88 ; R20=99
11 OUT OCR0, R20 ;OCR0 = 99
12 LDI R16 0x69 ; FAST PWM MODE, NON INVERTED, NO PRESCALER
13 OUT TCCR0, R16
14 OUT OCR0, R20 ;OCRO BUFFER=99
15 LDI R16 , (1<<TOIE0 ) ;ENABLE OVERFLOW INTERRUPT
16 OUT TIMSK, R16
17 SEI
18 HERE: RJMP HERE ;WAIT HERE

The wave generator is in non inverted Fast PWM mode, which means that on compare match the OC0 pin
will be set high. The OCR0 register is loaded with 00; so compare match occures when TCNT0 reaches
99. When the timer reaches the top value and overflows, the interrupt request occures, and the OCRo

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bugger is loaded with 157(the 2’s complement of 99). The next time that the timer reaches the top value,
the contnetns of the OCR0 buffer(157) will be loaded into the OCR0 register. Then the second interrupt
occurs and the OCR0 buffer will be loaded with 99(2s complement of 157)

4.3 Phase Correct PWM mode

*For timer0 In the Phase correct the TCNT0 goes up and down like a yo yo! First it counts up until
it reaches the top value and the it counts down until it reaches zero. The TOV0 flag is set whenever it
reaches zero.
Foscillator
The frequency of the generated wave is Fgeneratedwave = 2×N ×T op The Duty Cycle of the generated wave
in FAST PWM is:
OCR0
Duty Cycle = · 100 for non-inverted mode
255
and
255 − OCR0
Duty Cycle = · 100 for inverted mode
255

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4.4 Difference betweeen Phase Correct PWM mode and Fast PWM mode

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4.5 Generating waves using Timer2

4.6 PWM modes in Timer1

In Timer1 we have five Fast PWM modes: modes 5,6,7,14 and 15. In modes 5,6 and 7 the top value is
fixed in 0xFF, 0x1FF and 0x3FF, while in modes 14 and 15, the ICR1 and OCR1A registers represent the
top value, respectively.

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In non inverted PWM, the duty cycle of the generated wave increases when the value if OCR1A increases,
In inverted PWM, the duty cycle of generated wave decreases when the value of OCR1A increases. The
frequency of the generated wave is:
Foscillator
Fgenerated wave =
(Top + 1) · N

, where N is depending on the prescaler.

The Duty Cycle of the generated wave in FAST PWM is:

OCR1x + 1
Duty Cycle = · 100 for non-inverted mode
Top + 1

and
Top − OCR1x
Duty Cycle = · 100 for inverted mode
Top + 1

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4.7 Generating waves with different frequencies

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4.8 Phase Correct PWM mode

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The frequency of the generated wave is:

Foscillator
Fgenerated wave =
2 · Top · N

, where N is depending on the prescaler.

The Duty Cycle of the generated wave in Phase Correct PWM is:

OCR1A
Duty Cycle = · 100 for non-inverted mode
Top

and
Top − OCR1A
Duty Cycle = · 100 for inverted mode
Top

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In modes 10 abd 11, the Top value can be specified by ICR1 and the OCR1A registers.

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If we use mode 11 instead of mode 10, OCR1A is bufferd, and the contents of the buffer will be loaded
into OCR1A, when the timer reaches its top value. In mode 11 we can only use the OC1B wave generator
and we cannot use the OC1A wave generator since the OCR1A register is used for defining the Top value.

5 Examples
5.1 Flashing Led example ( credits to : Maylo)
• Led in PortB.3 +Vcc (PortPin = 0 -> Led On, Negative Logic)

• AVR 4MHz

• Led flashing for 0.5sec

For 0.5sec in 4Mhz we need ( f = N/T, f=1/T): 4000000 = N/0.5 -> N=4000000/2 = 26 cycles. (max for
8bits 28 − 1)
Timer counts clock cycles so we set prescaler to 1024. 2000000/1024=1953,25≃ 1953. This still doesn’s
fit in 8bits(255), but in 16bits(2 registers) If we chose 64 prescaler(from TCCRnB): 2000000/64=31250
(accuracy). 0x0000-31250 = -31250 in TCNT1. 31250 = 0111101000010010 so -31250 will be its complement.
If we add 1 to it then we have: 1000010111101110 ISR will reload timer1 every time it is called(CTC bit
in TCCRnB). To eneable timer we must:

• Set up Interrupt Vector

• Initialise the timer

• Write an ISR which toggles LED(connected to PortPin)

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In the following example we don’t use Output Compare Mode

1 .EQU TIMER_VALUE=0x85EE
2 .ORG 0x0000
3 RJMP RESET
4 .ORG 0x0005
5 RJMP TIMER_OVF
6 ;BECAUSE OF THE NEGATIVE LOGIC 0−>INPUT AND 1−>OUTPUT
7 RESET:
8 INITSTACK
9 LDI R16 , 0b00000100
10 OUT TIMSK, R16 ;ENABLE INTERRUPTS IN TIMER1
11 LDI R16 , HIGH(TIMER_VALUE) ;TCNT1 IS 16BITS SO WE USE
12 OUT TCNT1H, R16 ;HIGH AND LOW
13 LDI R16 , LOW(TIMER_VALUE)
14 OUT TCNT1L, R16
15 LDI R16 , 0b00000011 ;CHOOSE PRESCALER
16 OUT TCCR1B, R16 ; CS12=0 , CS11=1 , CS10=1 −> 1/64
17 SEI ; SET GLOBAL INTERRUPT FLAG (ENABLE)
18 SBI DDRB, 3
19 CBI PORTB, 3 ;LED ON UPON RESET
20
21 LOOP:
22 RJMP LOOP ;LOOP ETERNALLY UNTIL INTERRUPT OCCURS
23
24 TIMER_OVF: ; ISR
25 IN R16 , SREG
26 PUSH, R16 ;SAVE STATUS REGISTER
27 IN R16 , PORTB
28 LDI R17 , Ob00001000
29 EOR R16 , R17 ;TOGGLE LED
30 OUT PORTB, R16
31 POP R16
32 OUT SREG, R16
33 RETI

In the following example we use Output Compare Mode

1 .EQU TIMER_VALUE=31250
2 .ORG 0x0000
3 RJMP RESET
4 RESET:
5 INITSTACK
6 LDI R16 , Ob000100000
7 OUT TIMSK, R16 ;ENABLE OCIE1A INTERRUPT
8 LDI R16 ,HIGH(TIMER_VALUE) ;LOAD IN OCR1A SO COMPARE MATCH OCCURS
9 OUT OCR1AH, R16 ;BETWEEN OCR1AH−L /TCNT1AH−L
10 LDI R16 , LOW(TIMER_VALUE)
11 OUT OCR1AL, R16
12 LDI R16 , Ob01000000 ; SET OUTPUT COMPARE 1 TO TOGGLE MODE
13 OUT TCCR1A, R16
14 LDI R16 , 0b00000011
15 OUT TCCR1B, R16 ; SET PRESCALER TO 1/64
16 SBI DDRB, 3

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17 CBI PORTB, 3
18 LOOP:
19 RJMP LOOP

6 Σημειώσεις
• LDI R20,1«5 means: set the 5th bit of R20 to 1.

• memory allocation:

.dseg
.org 0x0060− > f or Ram
array_f lag : .Byte n(bytes − 8 bit f or every cell)
.cseg

• store in RAM:

> initialize
ldi zh, high(array_f lag)
ldi zl, low(array_f lag)
> store
st z+, R16

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