Chapter 6

Programmable Logic Devices

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6.0 Introduction
Programmable logic devices PLDs is produced as the results of large scale
integration technology where more gates are integrated in a single piece of
silicon. They consist of pre-fabricated blocks of AND and OR gates. They are
devices that can be programmed to build complex combinational circuits on just
a single chip have flexible interconnection layers so that the end-user can use
them for more complex applications. Each input feeds both a non-inverting
buffer and an inverting buffer to produce the true and inverted forms of each
variable. No wiring is needed and just need to program to achieve the function.
Three classes of this device group are studied in this chapter. They are
programmable read-only memory PROM, programmable logic array PLA,
programmable array logic, and generic array logic GAL. We will also briefly
discuss complex programmable logic device CPLD and field programmable
gate array FPGA. Programmable logic device is a versatile device whereby
combinational logic circuit can be designed by fusing appropriate column and
row fuses of the device. Programmable logic device has a general structure
which consist of input buffer inverter, AND array, which contains minterm and
OR output array. The structure of the PLDs is shown in Fig. 6.1. Generally
PLDs is the sum of product terms.

Figure 6.1: The structure of a programmable logic device

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The buffer/inverter provides two logic state simultaneously which are true and
its complement. The AND and OR arrays contain AND gates and OR gates
where their inputs have fuse link connection which can be programmed to
disconnect by blowing the fuse. An AND gate showing the fuse link and its
n

blown.

(a) (b)
Figure 6.2: (a) An AND gate with fuse link and (b) its notation of link

Figure 6.3(a) illustrates that the fuse link of input A is blown and Fig. 6.3(b)
shows the notation.

(a) (b)
Figure 6.3:

As mentioned earlier, there are three types of programmable logic device. They
are programmable ready-only-memory PROM, programmable logic array PLA,
and programmable array logic PAL. The differences between them are listed in
Fig. 6.4.

Device AND-Array OR-Array

PROM Fixed Programmable
PLA Programmable Programmable
PAL Programmable Fixed
Figure 6.4: Types of programmable logic device

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6.1 Programmable Read-Only Memory

Programmable read-only memory PROM has fixed AND arrays which are
decoder basically containing the minterms that has n buffers/inverters and a
programmable OR-array that has m outputs. The number of AND gate depends
on the number of input buffer/inverter. If there are n input buffers/inverters, the
number of AND gates shall be 2n. This will provide 2n input lines to the OR
array. The block diagram of the programmable read-only memory is shown in
Fig. 6.5.

Figure 6.5: A n input buffer/inverters and m outputs PROM

Taking 3 input lines as an example, the AND array, which basically containing
decoder of the PROM is shown in Fig. 6.6.

Figure 6.6: 3 input lines decoder of a PROM

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A two output OR-array of the three input PROM is shown in Fig. 6.7. Note that
the fuse link is at the input of the OR array. To disconnect a particular minterm
to the OR array is by blowing the fuse link.

Figure 6.7: Two output OR array of a three input PROM

The circuits mentioned in Fig. 6.6 and 6.7 can be simplified to a single line print
instead drawing multiple lines. The simplified circuits of Fig. 6.6 and Fig. 6.7
are shown in Fig. 6.8 and Fig. 6.9 respectively.

Figure 6.8: Simplified circuit for 3 input lines decoder of a PROM

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Figure 6.9: Simplified two output OR array of a three input PROM

Example 6.1

An programmable 4x2 PROM is shown in figure below.

If the engineer would like to program to the PROM to get the follow result
shown in the truth table, How should be be done? And what is the logic
equation of F1 and F2 after programmed?

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Address Ouput
A1 A0 F1 F0
0 0 1 0
0 1 0 1
1 0 0 1
1 1 1 0

Solution
The fuse link as shown in the figure are blown to show the required output.

The logic equation of the output is

and . Alternatively, the the implementation can be shown
below.

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Example 6.2
Implement the following functions using harded wired diode logic ROM.

Solution
The block diagram and truth table of the function are shown below.

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Input Output
A B C F0 F1 F2 F3
0 0 0 1 0 1 0
0 0 1 1 0 1 0
0 1 0 0 1 1 1
0 1 1 0 1 0 1
1 0 0 1 1 0 0
1 0 1 0 0 0 1
1 1 0 1 1 1 1
1 1 1 0 1 0 1

The ROM consists of a 23 AND decoder array and 4 programmed output OR

array.

The 23 decoder is as follow:

Input
A B C
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1

The hard-wired diode decoder is shown as follow.

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The 3 input generic decoder circuit is

The OR array for the output is shown below:

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The three input generic OR gate is

6.2 Programmable Array Logic

Programmable array logic PAL has fixed output OR array and programmable
input AND array. The output OR gate is tied permanent or hard-wired to some
outputs of the AND gate. The PAL shown in Fig. 6.10 has two OR gates have
their input tied to output of AND gate and one with input tied to output of two
AND gates. The design of a simple 4 input-to-3 output PAL device is shown in

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Fig. 6.10. Any combinational logic function can be implemented using the
programmable array logic PAL device.

Figure 6.10: A 4 input-to 3 output programmable array logic device

An example of programmed programmable array logic is shown in Fig. 6.11.

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06 Programmable Logic Devices

Figure 6.11: An example of programmed programmable array logic

The outputs O1, O2, O3, and O4 have Boolean functions ,

, , and respectively.

Example 6.3
The implementation of function stated in example 6.2 using programmable
array logic device that used hard wired diode is shown in below.

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6.3 Programmable Logic Array

Programmable logic array PLA has programmable input AND array and
programmable output OR array. If the device has n input then the the number of
input for the AND gate shall be 2n. The device can also be designed with p
number of product term which all the input and its complement as input. Each
output OR gate has p number of input. Like the programmable array logic
device, programmable logic array can be used to implemented any
combinational logic function. A 4 input-10 column-4 output programmable
logic array PLA device is shown in Fig. 6.12.

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06 Programmable Logic Devices

Figure 6.12: A 4 input-10 column-4 output programmable logic array device

It may be viewed as shown in Fig. 6.13.

Figure 6.13: Simplified block of a programmable logic array device

Example 6.4
Use PLA to program the output using the following truth table.

Input Output
Term
A B C F1 F2
1 0 - 1 -
1 - 1 1 1
- 1 1 - 1
0 1 0 1 -

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Solution
The corresponding PLA implementation of outpu shown in truth table is

Example 6.5
Use PLA to program the output for a one-bit comparator.

Solution
The truth table for a one-bit comparator is shown below.

Input Output
A B EQ NE LT GT
0 0 1 0 0 0
0 1 0 0 1 0
1 0 0 0 0 1
1 1 1 0 0 0

The Boolean equations of the outputs are

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The corresponding PLA implementation of one-bit comparator is shown below.

6.4 Read Only Memory

The contents of read only memory ROM cells are permanently fixed. The cell is
designed so that a logic 0 or logic 1 is presented to the bit line upon activation
of its word line. The desired logic level is created during the fabrication of the
device. Figure 6.14 shows several ways to implement logic 0 and logic 1 for the
ROM cells.

Diode ROM has default logic 0 at bit line. When the word line of ROM is
selected, it provides logic 1 at bit line due low forward voltage of the diode.

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(a) Diode ROM (b) MOS ROM 1 (c) MOS ROM 2

Figure 6.14: Different methods for implementing logic 0 and logic 1 ROM cells

The MOS ROM 1 has default logic 0 at bit line. When the word line is selected,
the n-MOS transistor switches on and provides logic 1 at bit line. The MOS
ROM 2 has default logic 1. When the word line is selected, it provides logic 0 at
bit line.

An example of a 4x4-bit NOR ROM is shown in Fig. 6.15. The pull-up p-

MOS transistor and the n-MOS bit-transistor forms a pseudo n-MOS NOR gate.
ROM is designed with background logic 1. When the WORD line is asserted
the cell that has n-MOS transistor would be switched on to provide logic 0 at the
BIT line upon switched on by signal on p-MOS transistor. Normally the
clock is pre-charged to half of VDD for enable fast access of the memory
cell. The WORD line and BIT line matrix that does not contain any n-MOS
transistor would provide logic 1 upon clock line is asserted. The one that
contains an n-MOS transistor would provide logic 0 because the n-MOS
transistor is a high-asserted low device. When it is selected, the output would be
at logic 0 simply because the transistor is switched on.

The ROM has data value WORD 0 = 0001, WORD 1 = 1000, WORD 2 =
0010, and WORD 3 = 0100.

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Figure 6.15: A 4x4-bits NOR ROM

Instead of having the pull-up p-MOS transistor, ROM design with pull-down n-
MOS transistor and n-MOS transistor cell tied to VDD is called OR ROM. Figure
6.16 shows a 4x4 bit OR ROM.

Figure 6.16: A 4x4 OR ROM

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The background bit of the OR ROM is logic 0. When a word line is selected, the
bit that has an n-MOS transistor would provide logic 1 at the bit line.

The 4x4 MOS NAND ROM is shown in Fig. 6.17. The background of the
ROM is logic 1. All the n-MOS transistors in the column have to be switched on
in order logic 0 is shown in bit line.

Figure 6.17: A 4x4 NAND ROM

ROM also can be designed using pseudo n-MOS gate both for the decoder and
the memory cell design, which is basically the n-MOS design technique. The
logic to row or word is provided by the pseudo n-MOS transistor, which act as
decoder.

6.5 Random Access Memory Devices

In this section the designs of static RAM, dynamic RAM, and ROM will be
discusses. The block diagram of a 1kx8 SRAM is shown in Fig. 6.18.

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Figure 6.18: Block diagram of a 1kx8 SRAM

This memory device has 128 row addresses and 8 column addresses. The
memory has 8 matrix blocks and each block has 128x8 cells. The other main
parts of the memory are the sense amplifier, control unit, input/output data
control, output data control, address bus, and data bus.

We shall discuss the approaches used to design memory cell static and
dynamic cell, the sense amplifier, and the address decoders row and column
decoders, and I/O data control circuits.

6.5.1 RAM Memory Cell

There are many methods to design the static and dynamic random access
memory cells. In this section, three methods are presented. They are six-
transistor static memory cell, three-transistor dynamic memory cell, and one-
transistor dynamic memory cell.
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6.5.1.1 Six-Transistor Static Memory Cell

The six-transistor static memory cell is shown in Fig. 6.19. MOS transistor M1,
M2, M3, and M4 forms the bi-stable memory element, whilst n-MOS transistor
M5 and M6 are served as pass-transistors.

Figure 6.19: The six-transistor static RAM cell

During the write cycle, the desired logics are placed on bit line and line.
When the WORD line is asserted, the desired data will be latched into the bi-
stable memory element. For an example, to write logic 1 into the memory, the
BIT line is set at logic 1, whilst the line is at logic 0.

However, due to high pack density of the memory cell whereby many
column memory cells are connected in the same bit line, the total drain-bulk
capacitance of the pass-transistors is sufficiently large that the charging and
discharging of the bit lines would take long time. Thus, during the read cycle,
the BIT and lines are pre-charged to the pre-defined level, which is usually
0.5 of VDD voltage level. These lines are then allowed to float. When the
WORD line is asserted, the BIT line and line begin to charge or discharge
that reflect the logic level stored in memory cell. The small change in voltage
level is passed to the sense amplifier for output user. The read cycle is a
destructive cycle whereby the data stored in the memory can be erased.
Therefore, it is necessary to refresh the memory. Other mean to prevent the bit
data being erased is to design the pass-transistor to have large width and length.
But this is not desired because in the modern design, scale down is necessary to
save cost and fast access time.

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6.5.1.2 Three-Transistor Dynamic Memory Cell

The three-transistor dynamic RAM structure is shown in Fig. 6.20. Transistor

M1 is used to write the BIT logic into the source of transistor M 1 and gate of
transistor M2. With the present of source capacitance CS, depending on the logic
being written, the gate voltage of transistor M2 is either at logic 0 or logic 1 that
has voltage (VDD Vtn(M2)) due to threshold loss.

Figure 6.20: A three-transistor dynamic RAM cell

The BIT value is logic 0 then the gate voltage shall be 0V. If the BIT value is at
logic 1 then the gate voltage will be at logic 1 that has voltage (V Write Vtn(M2)).
This voltage is held on as long as the Read transistor M3 is not switched on.

During the read cycle, transistor M3 is switched on and if the BIT value is
logic 1 then the line would turn logic 0. Likewise, if the BIT value is logic
0 then upon reading the line would turn to logic 1 that has maximum value
(VRead Vtn(M3)).

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6.5.1.3 One-Transistor Dynamic Memory Cell

One-transistor dynamic RAM cell uses capacitor to temporarily store the charge
on a memory capacitor CM. A simple 1-bit dynamic RAM cell is shown in Fig.
6.21.

During the write cycle, the logic level is placed on the BIT line. The
WORD line is then asserted to charge or discharge the memory capacitor C M.
The capacitor is leaky and will not hold the charge for long time. Thus, it is
necessary to refresh it periodically.

During the read cycle, the BIT line is pre-charged and placed in tri-state
mode. When the WORD line is asserted, the BIT capacitor CBIT is either
charging or discharging depending on the charge stored in memory capacitor
CM. The sense amplifier is then used to detect small change in voltage level and
output the appropriate logic level.

Figure 6.21: A 1-bit dynamic RAM cell

Read cycle is a destructive operation. Thus, the data must be re-written into the
memory capacitor CM.

6.6 Generic Array Logic

Generic array logic GAL has a programmable AND array connects to output
logic microcell OLMC that has a fixed OR array and programmable logic. The
basic structure of the generic array logic is shown in Fig. 6.22.

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Figure 6.22: Basic structure of generic array logic GAL

A typical output logic microcells OLMC of a popular GAL22V10 device is

shown in Fig. 6.23.

Figure 6.23: The structure of output logic microcells OLMC

The program output logic OLMC allows the implementation of sequential

circuit using GAL device. The macrocell can be individually configured to
bypass the flip-flop.

The PLD can be programmed as sequential or combinational logic.

The output can either be programmed to be register with flip-flop or
combinational circuit with flip-flop bypassed.

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6.7 Complex Programmable Logic Device

Complex programmable logic device CPLD is are integrated circuit containing
several PLAs and PALs, and memory elements like flip-flops. CPLDs are
formed by function blocks connected to a programmable interconnect array
PIA. A function block diagram of a CPLD is shown in Fig. 6.24.

Figure 6.24: Block diagram of complex programmable logic device

Each function block contains several macrocells, which will vary for products
from different manufacturers. A typical macrocell will have an AND array, a
product select matrix, an OR gate, and a programmable register. A simplified
macrocell is shown in Fig. 6.25. Company lie Altera, Cypress, Lattice, and
Xilinx make CPLDs.

Figure 6.25: A simplified block diagram of macrocell

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6.8 Field Programmable Gate Array

Field programmable gate Array FPGA contain an array of identical logic cells
with programmable interconnections. FPGAs consists of an array of logic
blocks linked by a programmable row and column interconnections, and
surrounded by I/O blocks. A typical block diagram of a FPGA is shown in Fig.
6.26.

Each logic block contains several logic elements a shown in Fig. 6.27. Note
that LUT is look-up table, which in general terms is basically a table that
determines what the output is for any given input. Like in combinational logic,
it is the truth table. This truth table effectively defines how your combinatorial
logic behave.

The look-up table LUT is a 16-word x 1-bit ROM that can be used to
implement logic functions of 4 variables. Suppose the combinational logic
function is then only the locations 0011 and 1100 will
rest of the 14 locations in the The outputs
from the logic elements can be taken directly out of the LUTs or can be stored
in a flip-flop before being accessed.

Figure 6.26: A typical block diagram of a FPGA

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Figure 6.27: The simplified logic block of FPGA

Tutorials
6.1. Describe the difference between three classes of programmable logic
devices.

6.2. Use a 4 input-8 output PROM to design a 7-segment decoder to display 0

to 9.

6.3. Using hard-wired diode, construct the circuit for a 2-input AND gate, a 2-
input OR gate and logic function .

6.4. From the design of logic fucntion of Q6.3, explain how the

6.5. Use a 4 input-8 output PROM to design a POS M(0,1,3,7).

6.6. Using the PAL device shown in Fig. 6.10, implement logic function O 1 =
m(1, 2, 4, 5, 7).

6.7. Use the programmable logic array device shown in Fig. 6.11 to design a
4-bit binary to gray code converter.

6.8. Use PLA to program a one bit full adder.

6.9. A 4x4 ROM designed using pseudo n-MOS transistor concept is shown
in the figure below.

(i). Derive the logic functions for the rows and output D3, D2, D1, and
D0.
(ii). Write down the content of the memory.
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References
1. Donald D. Givone, "Digital Principles and Design", McGraw- Hill 2003.
2. Thomas L. Floyd, "Digital Fundamentals", Seventh Edition, Prentice-Hall
International, Inc., 2000.
3. Victor P. Nelson, H. Try Nagle, Bill D. Carroll, and J. David Irwin, "Digital
Logic Circuit Analysis & Design", Prentice-Hall Englewood Cliffs.NJ,
1995.

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