VLSI Modulation Circuits - Signal Processing, Data Conversion, and Power Management im le)ate)it=1ale mere) ale]VLSI MODULATION CIRCUITS Signal Processing, Data Conversion and Power Management Vat) oF &) 1 \Ro Oscillator Hongjiang SongSignal Processing, Data Conversion, and Power Management Copyright © 2014 by Hongiiang Song, ISBN: 978-1-312-21861-1 All rights reserved. No part of this book may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying, recording, or by any information storage and retrieval system, without permission in writing from the copyright owner. ‘This book was printed in the United States of America. ‘To order additional copies of this book, contact the publisher or copyright owner.VLSI Modulation Circuits CONTENTS Preface Chapter 1 LE 1.2 RE Introduction Characteristics of VLSI Modulation 1.11 Linear VLSI Signal Processing Circuits 1.1.2 Linear VLSI Circuit Model and Design 1.1.3. Modulation Based Linear VLST Circuits Basic Modulation Operations 1.24 Limiting Operations 1.2.2 Multiplication Operations 1.23 Switched-Network Modeling of Modulation Circuits Key Benefits of VLSI Modulations 1.41 High Precision Data Conversions 1.42 LowNois Siganl Amplifications 1.43 High Efficiency Power Amplifications 1.44 — High Efficiency Power Conversions 1.45 Other Special Circuit Functions Applications of VLSI Modulation Circuits 1.5.1 Frequency Translation 1.52 Pulse Density Modulation 1.5.3 Pulse Width Modulation 1.5.4 Pulse Code Modulation 1.55 Phase and Delay Modulation 156 Chopping Organization of Book Chapters 19 20, 23 25 26 27 30 31 36 37 37 38 38 38 38 38. 40 40) 40 41 x1VLSI Modulation Circuits Chapter 4 AL 42 430 44 45 Chapter 5 Bb 5.2 3.3.2 High-Order Modulation 3. Modulator Implementation VLSI Class-D Amplifier Circuits Class-D amplifier Principle Analog Class-D Amplifier Architectures 4.24 Open-Loop Analog Class-D Amplifier, 4.2.2 Closed-Loop Analog Class-D Amplifier 423. Self-Oscillation Class-D Amplifiers 4.2.4 Altemative class-D Amplifier Stricture Digital Class-D Amplifier Architectures 4.3.1 Hybrid Class-D Amplifier 4.3.2 Direct PCM-PWM CI s-D Amplifier VLSI PWM Circuit Implementations ‘angular Ramp Signal Generation 442 PWM Signal Generation Circuits 4.4.3 Ramp-Less PWM Circuit 4.44 Direct Input PWM Signal Generation PWM Signal Power Spectra clay) Interpolation Circuits VLSI Phas Phase Interpolation Principle 5.1.4 __ Sinusoidal Phase Interpolation 5.1.2 Triangular Phase Interpolation VLSI Phase Interpolator Implementations VLSI Phase Interpolator Noise Model I Copyrighted materialing, Data Conversion, and Power Management 6.3 6.4 6.5 6.6 6.7 Chapter 7 TA id Chopper Stal VLSI Noise Effects and Compensation VLSI Auto-Zero Circuits 6.2.1 Auto-Zero Circuit Principle 6.2.2 Auto: ‘ero Circuit Implementation 62.3. Aliasing Effect of Auto-Zero Circuits VLSI Chopper Stabilization Circuits 6.3.1 Chopper Circuit Principle 6.3.2 VLSI Chopper Circuit Structures VLSI Circuit Implementations GAL Tove ted Gain Chopper Stage 64.2 Open-Loop CDS Circuits 64.3 Closed-Loop CDS Circuits 64.4 — Inverted CDS Comparator Circuits 64.5 CDS Sample/Hold Circuit 64.6 CDS Amplifier Circuits VLSI Compound Zero-Drift Amplifier 6.5.1 Compound Circuit Structures. 6.5.2. Compound Amplifier Characteristics 6 Design Considerations Comparison of Circuit Techniques Basic VLSI Chopper Circuit Elements 6.71 Basic Chopper Modulator Circuit 6.72 VLSI Chopper Opamp Circuits Introduction to VLSI Lock-In Amplifier Circuits Lock-In Amplification Principle TAA Weak Signal Detection Concept 7.1.2 Phase Sensitive Signal Detection 455 156 158 162 165 167 168 171 174 174 175 177 179 181 182 186 187 196 197 198 200 200 200 10VLSI Modulation Circuits Ta Chapter 8 8.1 8.3 7.1.3 Basic Lock-In Amplifier Model VLSI Lock-In Amplifier Implementations Na) 7.21 Low-Noise Amplifier ( 7.22 Analog PSD 7.23 Switching PSD 7.24 Digital PSD 7.25 Lowpass Filter 7.2.6 Reference Signal Noise Effects and Dynamic Reserve 7.3.1 Intrinsic Noise Sources 7.32 External Noise Sources 7.33. Dynamic Reserve VLS Switched-Capacitor DC/DC Converter Circuits VLSI Charge Pump Circuit Principle 8.1.1 Basic Charge Pump Circuit Concept 8.1.2 Basic Charge Pump Circuit Components ‘sifications 8.1.3 Charge Pump Circuit Cl Charge Pump Circuit Structures 8.2.1 H-Bridge Charge Pump Circuits 8.22 Cockeroft-Walton Charge Pumps 8.23 Villard Charge Pump Circuit 8.24 Greinacher Charge Pump Circuit 8.25 Delon Charge Pump Circuit 826 Marx Charge Pump Circuit 8.2.7 Dickson Charge Pump Circuits 828 — Cross-Coupled Charge Pump Circuits Charge Pump Circuit Configurations 8.3.1 Regulated VLSI Charge Pump Circuits 210 211 212 213 214 216 216 217 217 218 220 225 226 226 227 228 230 232 242 248 249 250 251 252 261 203 263ing, Data Conversion, and Power Management 8.4 8.5 8.6 8.7 Chapter 9 of o2 Buck-Boost Regulator Inverter Regulator 83.4 Configurable Charge Pumps 83.5 Hybrid Charge Pump Circuit Charge Pump Circuit Modeling 8.4.1 Circuit Performance Paramet 8.4.2. Micro-, Macro- and Simulation Modeling 84.3 Charge Pump Circuit Operation Modes Voltage Source and Impedance Models 85.1 H-Bridge Charge Pumps 85.2 Dickson Charge Pumps 85.3 Cockcroft-Walton Charge Pumps 85.4 Cross-Coupled Charge Pumps 85.5 Parasitic Capacitance Effects ‘Transformer Based Charge Pump Circuit Models 8.6.1 Ideal Transformer Characteristics 8.6.2 H-Bridge Charge Pumps 8.6.3 Dickson Charge Pumps 86.4 Cross-Coupled Charge Pumps Gain Hopping ‘Techniques VLSI Switched-Capacitor Filter Circuits VISI Switched-Capacitor Circuit Principle 9.1.1 Charge Redistribution Analysis Method 9.1.2. Non-Inverted Switched-Capacitor Integrator 9.1.3 Inverted Switched-Capacitor Integrator 9.1.4 Doubly Pumped Switched-Capacitor Integrator Basic VLSI Switched-Capacitor Cireuit Elements 9.2.1 Analog Switch Circuit Structures 265 2066 267 2069 271 309 310 313 314 317 319 321 321 12VLSI Modulation Circuits 9.3 Chapter 10 10.1 10.2 10.3 10.4 Chapter 11 WA 11.2 9.2.2 Non-Overlap Clock Generation Circuits 9.23 WLSLOTA Cs ‘itcuit Structures Sample/Hold Circuit Structures 9.3.1 Buffered Sample/Hold Circuit 9.3.2 The Correlated Double Sampling Techniques 9.33. Non Unity Gain Sample/Hold Circuit 9.3.4 — Charge Injection Compensation Techniques 9.3.5 Fully Differential Sample/Hold Circuit VLSI Switched-Current Circuits VLSI Switched-Current Circuit Principle Basic Switched-Current Signal Processing Elements 10.2.1 Unit Delay Circuit 10.2.2 Adder Circuit 10.2.3. Scaler Circuit VLSI Dynamic Switched-Current Circuits Charge Injection Compensation Techniques 104.1 Charge Injection Attenuation Circuits 104.2. Charge Injection Cancellation Circuits 104.3. Algorithmic Charge Injection Cancellation 10.4.4 Fall Differential Switched-current Circuits 10.4.5 Controlled Clocking and Input ‘Techniques VLSI Switched-Inductor DC/DC Converter Circuits Switched-Inductor DC/DC Converter Principle 11.1.1 Voltage Divider Based Model 11.1.2 LC Filter Based Model 11.13. Syn and Asynchronous Modes Basic DC/DC Converter Architectures 324 325, 326 328 329 8 3 334 347 348 349 349 350 351 352 354 356 357 359 359 367 368 368ing, Data Conversion, and Power Management 11.3 114 11.6 17 Step Down Converter Step Up Converter Step Up/Down Converter Cuk DC/DC Converter Sepic DC/DC Converter 41.2.7__Forward Converter 11.28 Resonant Converter Switched-Inductor Regulators 11.3.1 Hysteretic Regulator 11.3.2 Voltage-Mode PWM Control Loop 11.3.3 Current-Mode PWM Control Loop Special Operation Modes 11.4.1 Discontinuous Mode 11.42 Skip Mode 11.4.3. PFM Mode 11.44 LDO Mode 11.45 Comparison of Operation Modes Behavioral DC/DC Converter Model 11.5.1 2-S Switched —Inductor Model 11.5.2 _4-S Switched-Inductor Model 11.5.3 Conversion between 2-S and 4-S Models 11.54 Voltage Domain Conversion 11.5.5 Steady-State DC/DC Converter Model Closed-Loop Modeling of Regulators 11.6.1 Voltage Mode Regulators 11.6.2. Current Mode Regulators Converter Performance Models 11.7.1 Energy Fi ‘actor 375, ats: 381 383 386 388 389, 391 392 304 307 402 402 406 407 408 408 409 409 412 413 416 417 417 419 421 426 426 14VLSI Modulation Circuits 11.8 Chapter 12 434 12.2 12.3 12.4 11.7.2 Power Efficiency TEES 11.7.4 Dumping Time Constant 11.7.5 ‘Time Constant Ratio Selections Converter Paramet 11.8.1 Switch Selection 11.8.2 Inductor Selection 11.8.3. Capacitor Selection 11.8.4 Los 11.8.5 Zero Voltage Switching (ZVS) Control in DC/DC Converters Introduction to VLSI Mixer Circuits VLSI Mixer Circuit Principle VLSI Mixer Performance Parameters 12.2.1 Conversion Gain 12.2.2 Noise figure 12.2.3 Signal Isolation 12.2.4 Linearity 12.2.5 Spurs 12.6.5 Dynamic Range 12.2.7 Image 12.2.8 DC-Offset 12.2.9 LO Drive Level 12.2.10 Voltage Standing Wave Ratio VLSI Mixer Examples VLSI Mixer Circuit Implementations 12.4.1 Single Device Mixer 12.4.2 Balanced Mixer 12.4.3 Image Rejection Mixer 427 428 428 429 429 430 431 432 433 435 439 440 441 441 442 442 443 446 446 446 447 447 447 448 449 450Signal Pro ing, Data Conversion, and Power Management Chapter 13 13.1 13.3, Chapter 14 14.1 Appendix A Ad 12.4.4 Sub-Harmonic Mixer 12.4.5 Phase Selection Mixer VLSI Spread Spectrum Clocking Circuits Spread Spectrum Clocking Principle 13.1.1 Electromagnetic Interference (EMI) 13.1.2 Spread Spectrum Clocking Basis Spread Spectrum Clocking Modeling 13.2.1 Modulation Frequency 13.2.2 Modulation Index 13.2.3 Rate of Modulation 13.2.4 Modulation Profile 13.2.5 Spread of Spectrum under VLSI SSC Circuit Implementations 13.3.1 Direct VCO Modulation SSC Circuit 13.3.2 Feedback Modulation SSC Circuit vi SI Fractional-N PLI. Circuits VLSI Phase-Locked Loop Principle 14.1.1 Integer Phase-Locked Loop 14.1.2 Fractional-N Phas Locked Loop VLSI Fractional-N PLL Implementations 14.2.1 Multi-Modulus Divider 14.22 Modulator VLSI Amplifier Families VLSI Amplifier Basis A. Amplifier Gain A..2 Power Efficiency 454 461 462 462 463 465 466 466 467 467 468 469 469 483 484 485 487 488 488 496 503 504 504 506 16VLSI Modulation Circuits AA3 Amplifier Linearity Intermodulation A2 Amplifier C) Class-A Amplifier Class-B Amplifier Class-AB Amplifier Class-C Amplifier Class-D Amplifier A.2.6 — Class-E and Class-F Amplifiers A.2.7— Class-G and Class-H Amplifiers 506 509 511 512 514 516 517 519 522 17Signal Processing, Data Conversion, and Power Management 1.1 CHARACTERISTICS OF VLSI MODULATION As a special family of VLSI signal processing circuits, VLSI modulation circuits are constructed based on nonlinear and time varying VLSI signal processing circuit operations, such as clamping, multiplication, and_ switched-network operations. These basic VIST circuit operations can be combined with other basic linear VLSI signal processing circuit operations, induding the addition, scaling and integration to realize various specific VLSI circuit operations in signal processing, data conve: ions and power managements. VLSI modulation circuits have some special properties in common: © In time domain, these circuits usually employ the nonlinear or time varying circuit networks. The circuit topology changes can be realized using either the nonlinear or the switched circuit networks. Examples of such circuits are the switched-capacitor filter circuits, the de/de (switched-capacitor or switched-inductor) converter circuits, the chopper circuits, the lock-in amplifier circuits, the sigma-delta modulator circuits, and the VLSI passive mixer circuits. * In frequency domain, these circuits usually employ frequency manipulation circuit operations. VLSI modulation circuits purposely translate the input signal (and noise) frequencies to frequency bands that are more suitable for VLSI signal processing circuit operations, such as the signal amplification, the noise minimization, and the power transformations, etc. © In signal aspect, these circuits offer high linearity in the signal path between the signal inputs and the modulated signal outputs even though the circuits are inherently time varying or non-linear 1.1.1 LINEAR VLSI SIGNAL PROCESSING CIRCUITS For a given VSI linear signal process circuit and any two signals xi(t) and xo(t) shown in figure 1.1, the two signal process circuit operations with respect to two constant a and b are equivalent. Both circuit provide the same output y(t) Ge. yx = ya(t) 20ing, Data Conversion, and Power Management 1 o—-—0 o—-—o. a 1/s 1 (a) Addition () Sacling (©) Integration Fig.1.4 Basic continuous-time linear signal processing operations 1 o——o o-——o a 1/z 1 (b) Addition (©) Sacling (© Integration Fig.1.5 Basic discreet-time linear signal processing operations ‘These basic linear signal processing operations can be mapped to VLSI circuit directly for the VLSI circuit implementation. Example 1.3 Shown in figure 1.6 are the prototype VLSI active-RC circuit representation of the basic linear signal processing operations. Vis) OTe - Ri Vis) 1/Ri x R Kole * ——O Vols) Vals) & © OTR, (b) Active-RC addition with scaling Vvi)04—,—— ; aa Ra 1/80) Vils) Vi(s)O 4° Re Lov.) vas) 1/(SC) Vols) T/Ra (@) Active RC integration with scaling Fig.1.6 VLSI active-RC linear signal processing elements 24ing, Data Conversion, and Power Management higher than the limiting threshold (ignoring the forward diode drop in this conceptual description for simplicity) x(t) y(t) Non Fig.1.11 Diode-based VLSI high-side limiting circuit ¢ Low-Threshold Limiting is used to limit the low value of a given signal to a specific low-side threshold as shown in figure 1.12. ‘The mathematic model of a single-threshold clamping operation is given as: y (1.11) X XK NX gy fl Xe X>X yy, Xing XX, Xi XS X, The THE TH THL Xtnu is the high-side threshold of the limiting circuit. Fig. 1.12 Low-side limiting operation © = Dual-Threshold Limiting is used to limit both the high and the low value of a given signal to within the specific thresholds as shown in figure 1.12. “The mathematic model of a Dual threshold limiting operation is given as: 28Signal Pro ing, Data Conversion, and Power Management 1.3 MODELING OF MODULATION CIRCUITS Laplace, Z- and Fourier transforms have been used very effectively for modeling the linear time-invariant VLSI circuits and systems. For nonlinear and linear time-variant signal processing circuits, these well- developed LTT modeling techniques and methodologies must be modified for modeling the LTV circuits and systems, ‘There are major types of models for the L'T'V circuits and systems including: ¢ Micro-Modeling: This modeling approach zooms into the details of the nonlinear circuit operation of the modulation circuits at the carrier frequency. It provides the detail information of the circuit operations at the cost of the modeling complexity, time, and resources. © Macro-Modeling: This modeling approach ignores the detail operation of the carrier signal band and focus on the signal frequency band of the interest. It provides highly simplified linear model for the behavioral of high level linear time invariant circuit and system of the modulation circuit. Example 1. modeling is realized by partitioning the circuit into two equivalent linear circuit for two operation carrier clock phases. For the switched-capacitor filter shown in figure 1.17, a micro- @Phase 1: Vi 0 Oo) Vie) OF ow) —c >a t c t CG @ Phase 2: | Vi(nt+1/2) O- pO Vuln+1/2) 1 2 1 = +1/2. +1 /T 2 ET TIL Fig.1.17 Micro-modeling of VLSI switched-capacitor lowpass filter 32ing, Data Conversion, and Power Management v@=(-e*) (1.30) 1.4 KEY BENEFITS OF VLSI MODULATIONS VLSI modulation circuits serve as alternatives to the linear VLSI signal processing circuit solution. However from the VISI circuit technology aspects, VLSI linear signal processing circuit offer circuit solution that conventional li VISI signal processing functions can only be realized using VLSI modulation circuits cannot be offer. Or in the other worlds, some of the specific circuit techniques. ‘There are a few classic VLSI modulation circuit applications to the linear VLSI signal processing problems: * High precision data conversions. © Low noise and low de offset signal amplification * High efficiency high performance signal power amplification. © High efficiency power conversion and power management. © Other special circuit functions. 1.4.1 HIGH PRECISION DATA CONVERSIONS All conventional VSI data conversion circuits, such as the flash, the pipeline, the SAR and single or dualslope converters are typically limited by the achievable de offset caused by the random mismatch of the VLSI devices. ‘Typical values of VLSI comparator circuits are in the order of one tenth of mV to tens of mV. This limits the typical data conversion precision of within 14bits even with calibration circuit techniques. On the other hand high-resolution (220 bits) data conversion (ADC and DAC) can be realized employing the noise shaping operation of sigma-delta modulation circuit techniques, Such 36VLSI Modulation Circuits minimized impacts on the de and 1/f noises of the VLSI amplifier circuit elements. The amplified noise-free ac signal is then frequency translated back (.e. demodulated) to the original signal frequency band using a second chopper. Such circuit approach can be used to significantly improve the performance of the VLSI amplifier cireuit. Frequency translations are the basis of VLSI RF mixers where the baseband signals are frequency translated into the RF band that can be transmitted effectively in air. The received RF signal can then be translated back to the baseband using an inverse frequency translation employing a down conversion mixer in the receiver circuit. Frequency translations have been used in many other VLSI signal processing, circuit applications, such as the lock-in amplifier where frequency translation is used to detect a weak signal in strong noise background. In the switched- capacitor circuits, the baseband signal is frequency translated to a frequency band near the carrier clock frequency such that the charge redistribution circuit operation can be realized. In the de/de converter circuit applications, the frequency translations are used to convert the de voltage into the ac form such that the voltage level can be converted effectively using the energy storage circuit elements such as the capacitors and the inductors. 1.5.2 PULSE DENSITY MODULATION ‘The pulse density modulation (PDM) provides 2 method to represent the analog signal in the digital or digital-like forms, where the average of the discrete level signal over a given time period represents the input analog signal value. ‘The PDM and the power conversion such as the class-D amplifiers and the de/de ves as the basis of the high efficiency signal power amplification conversion that allows the analog input to be amplified in the digital domain for better power efficiency and SDNR. In a VLSI class-D amplifiers, the analog signal is first converted into the pulse density signal form using either the pulse width modulation (PWM) or the pulse code modulation (PCM) technique such that the signal amplification operation can be implemented in the full digital form for better fidelity and efficiency. 39Signal Pro ing, Data Conversion, and Power Management 1.5.3 PULSE WIDTH MODULATION ‘The pulse width modulation (PWM) is a special type of the pulse density modulation. Under the pulse width modulation, an analog signal is represented by the duty-cycle of a digital (or digital-like) signal with discrete signal magnitude values, where the analog signal is the local average of the PWM signal across a given time period. ‘The PWM signal is commonly used in the VLSI class-D amplification and the de/de supply voltage conversion circuits. 1.5.4 PULSE CODE MODULATION ‘The pulse code modulation (PCM) is another form of pulse density modulation (PDM). A major difference of a signal in the PCM form versus the PWM form is that the transition of the PCM is synchronous to the carrier clock. In the VLSI circuit implementations, the PCM signal can be generated from an analog signal using a sigma-delta modulation circuit. Due to their high VEST implementation simplicities and superior performances, the PCM techniques are also commonly used in the VLSI class-D amplifications and the data conversions (A/D or D/A conversion) operations. 1.5.5 PHASE AND DELAY MODULATION The VLSI phase and delay techniques that are commonly used in VLSI high-speed 1/O circuit applications modulation are special VLSI modulation circuit where the phase interpolation (PI) and the delay manipulation are critical circuit operations in VEST high-speed 1/O data recovery circuits is also commonly used for spread spectrum clocking A phase modulation in the PLL circuits. 40VLSI Modulation Circuits 1.5.6 CHOPPING The VLSI chopper circuit techniques employ the time varying (switched) networks that swap the two signal paths (usually the two signal paths in a differential signal) in the circuit operation. 1.6 ORGANIZATION OF BOOK CHAPTERS ‘The materials in this text are organized into 15 specific chapters covering the basic modulation theory, the circuit and the system modeling methods, the VLSI circuit implementations and their applications. Chapter 1 provides an overview to the VLSI modulation techniques. The VIST modulations are special VLSI signal processing operations that are related to signal frequency spectrum manipulations. VLSI modulations are widely used for VISI circuit non-ideality compensation, for ease of the VLSI signal processing and for high effective data conversion and power conversion. The basic VLSI modulation theories are discussed in detail in Chapter 2, where the mathematic models of the VLSI modulations are provided. Various VLSI modulation techniques, such as the frequency translation, the PDM, the PWM and the PCM are analyzed and the applications are also discussed, The VLSI sigma-delta modulation circuits are presented in Chapter 3. The sigma-delta modulations have been widely used in applications such as the data conversion, the PCM coding and the random pattern generation. A sigma-delta modulation offers the attractive noise shaping operation for VLSI data conversion that pushes the quantization noise away from the signal band into higher frequency band. Such a noise shaping technique serves as the basis of high accuracy data conversions. In the sigma-delta modulator an analog signal is presented in the digital domain synchronous to the control clock where the relative density of the pulses that corresponds to the analog amplitude of the signal (also called pulse-code modulation-PCM). VISI class-D amplifier circuit techniques are discussed in Chapter 4. ‘The class- D amplifier employs either PWM or PCM technique to provide high efficiency 41Signal Pro ing, Data Conversion, and Power Management analog power amplification with high linearity that is insensitive to VLSI device non-idealities. Such circuit techniques are widely used in VLST audio and RF band signal amplifications. ‘The class-D amplifiers offer v (= 90%) with compact siz where high efficiency is achieved by operating the output stages in switching y high power efficien e/light weight for high power amplification modes that are cither fully on or fully off, thereby minimizing the power dissipation. The switching (or digital) operation of the class-D output stage also avoids the requirement of linear characteristic of power device to achieve high amplification linearity VLSI phase interpolation (PI) circuit is introduced in Chapter 5. VLSI phase interpolation circuits employ VLSI phase modulation techniques to manipulate the phase (or delay) of a clock. VLSI PI circuit is widely used in VIST systems such as VLST high speed I/O circuit and VLST clocking circuits. VLSI zero-drift amplifier circuit techniques are discussed in Chapter 6. The de offset and 1/f noise as the major performance limitation factors in CMOS analog circuits and systems can be minimized using special VLSI circuit techniques such as the auto-zero circuits, the synchronous choppers and the chopper stabilize circuits. An auto-zero circuit uses the correlative double sampling (CDS) citcuit techniques to cancel the de offset and low frequency noise such as 1/F noise. A chopper amplifier relies on shifting the de and low frequency noise to higher frequency band such that they can be eliminated by lowpass filtering. A chopper stabilized amplifier uses the compound amplifier of auto-zero and chopper circuit techniques to separate the normal high bandwidth signal amplification path from the low bandwidth offset and drift compensation path therefore offers excellent performance in de and low frequency noise compensation. VLSI lock-in amplifier circuit techniques are introduced in Chapter 7. Lock-in amplifiers can be used to measure very weak ac signals down to few nano-volts under extremely high noise background of a few orders magnitude higher than the signal. Lock-in amplifier separates the noise from signal in the frequency domain based on the ph ive detection, where noise signals, at frequencies other than the reference frequency, can be rejected and therefore will not affect the measurement. VL circuits are discussed in Chapter 8. VLSI charge pumps offer the best choice for switched-capacitor de/de converter (also known as the charge pump) power management applications that require both low power and low cost, where the available supply sails are not directly usable, nor are the direct use of battery voltage. VLSI charge pumps are very suitable for de/de voltage 42VLSI Modulation Circuits conversion applications that require some combination of low power, simplicity, and low cost. VLSI charge pump circuits use capacitors (instead of inductor) as the main energy storage elements to create either a higher, lower or inverted power supply sources. Switched-capacitor charge pump circuits are capable of high efficiencies, sometimes as high as 90-95% while being electrically simple. VLSI switched-capacitor signal processing circuit techniques are discussed in Chapter 9. VLSI switched-capacitor circuits based on the discrete-time (DT) signal processing operation offer high analog signal processing accuracy at voice-band frequencies in fully integrated form. VLSI switched-capacitor signal processing circuits also offer attractive features such as low power, high accuracy, compact design and fully compactable to VLSI digital process technologies. VLSI switched-current circuit techniques are discussed in Chapter 10 where current mode signals are used as functional circuit elements for signal processing, VLSI switched-current circuits employing MOS current mirror and switches offer circuit operations that are fully compatible to the VLSI digital process technologies. VIST switched-inductor de/de converter circuit is introduced in Chapter 11. Such de/de converters employ switched-inductor circuit networks to realize the circuit topology change by turning on and off specific switches according to appropriate PWM feedback control. VEST voltage regulators based on switched- s such as better switching inductor de/de converters offer several advantagi ss thermal management requirement and ficiency, smaller components and flexible de/de conversion, such as boost, buck and inverter conversions and isolations. VLSI fractional-N phase locked-loop circuit is introduced in Chapter 12. VLST phase-locked loop (PL) circuits offer control clock sources for various integrated circuits such as microprocessors, high-speed I/Os, memory interfaces, audio, and video ports, ‘The fractional-N PLIs can be used to generate multiple frequencies from one clock source with fast settling time, low frequency error, better spurious performance, and low phase noise that are suitable for various VEST communication circuit applications. VESI spread spectrum clocking (SSC) circuits are introduced in Chapter 13. SSC circuit techniques allow spreading signal power spectrum in the frequency domain for the purposes of establishing secure communications, increasing resistance to natural interference and jamming, preventing detection, and limiting power flux density. SSC techniques are commonly used to reduce the 43Signal Processing, Data Conversion, and Power Management electronic emission interference (EMI) or electronic emission compliance (EMC) effects of the digital signals and associated harmonics. SSC circuits make a narrowband signal broadband through the frequency or phase modulation of C circuit spreads the radiation energy in the As the result of the frequency and phase modulation, the amplitudes of the harmonics of all the digital signals resulted from this clock can be reduced. These circuit techniques can be used to reduce the EMI effects by typically 2-22dB, the control clock of the system. frequency domain such that peak energy of the system is minim depending of the circuit implementation and measurement methods. VLSI mixer circuit is introduced in Chapter 14. Mixer circuit can be used to translate signal frequency band through the up-conversion or the down- conversion. Such frequency conversion is the basis for both receiver and transmitter in radio frequency (RF) systems. An appendix chapter is included in this text. The basis of VLSI switched amplifier circuits is discussed. A, class-B and class-AB amplification types, VLSI switched amplifiers offer the ability to amplify a relatively small input signal into a larger output signal very effectively. Compared with conventional cla 44VLSI Modulation Circuits Reference: i 2] B] M4] 1] [6] 7) [8] 19 J. Hol, "Pulse width modulation-a survey,” IE Transactions on Industrial Electronics, Volume: 39, Issue: 5, 1992, Page(s): 410-420. B, Putzeys, “Digital audio's final frontier," TE Issue: 3, 2003, Page(s): 34-41. ‘pectrum, Volume: 40, E. Raab, "Radio Frequency Pulse width Modulation,” IEEE ‘Transactions on Communications, Volume: 21, Issue: 8, 1973, Page(s): 958-966. C.CEnz, G. C.Tem« amp imperfectio: "Circuit techniques for reducing the effects of op- autozeroing, correlated double sampling, and chopper stabilization," Proceedings of the TE! 1996, Page(s): 1584-1614. 3, Volume: 84, Issue: 11, Miguel Gabal, Nicolas Medrano, Belen Calvo, Santiago Celma, "A Low- Voltage Single-Supply Analog Lock-in Amplifier for Wireless Embedded Applications," 2010 European Workshop on Smart Objects: Syste "Technologies and Applications (RFID Sys Tech), Page(s): 1-6. R.'T. Baird, ‘I. S.Fiez, "Linearity enhancement of multibit Delta Sigma; A/D and D/A converters using data weighted averaging," ‘Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 42, Issue: 12, 1995, Page(s): 753-762. us On-Cheong Mak, Yue-Chung Wong, A. Toinovici, "Step-up de power Transactions on 0-97. supply based on a switched-capacitor circuit,” IE! Industrial Electronics, Volume: 42, Issue: 1, 1995, Page(s L. J. Bloom, "Past, present and future dynamics within the power supply industry” Conference Proceedings 1998. Thirteenth Annual Applied > '98. Volume: 1, Power Electronics Conference and Exposition. AP 1998, Page(s): 278-283. M. Klapfish, "Trends in AC/DC switching power supplies and de/de converters,” Conference Proceedings 1993. Eighth Annual Applied Power Electronics Conference and Exposition, 1993. APEC "93. 1993, Page(s): 87-91[11] J. Crols, M. Signal Processing, Data Conversion, and Power Management [10] Ju-Ming Chou, Yu-Tang Hsieh, Jich-Tsorng Wu, "Phase averaging and interpolation using resistor strings or resistor rings for multi-phase clock generation,” T ‘Transactions on Circuits and Systems I: Regular Papers, Volume: 53, Issue: 5, 2006, Page(s): 984-991. eyaert, "Switched-opamp: an approach to realize full CMOS switched-capacitor circuits at very low power supply voltages,” TBE Journal of Solid-State Circuits, Volume: 29, Issue: 8, 1994, Page(s): 936- 942. 12] J. BHughes, K. W. Moulding, "Switched-current signal processing for video frequencies and beyond,” IEEE Journal of Solid-State Circuits, Volume: 28, Issue: 3, 1993, Page(s): 314 — 322. 46VLSI Modulation Circuits CHAPTER 2 BASIC VLSI MODULATION THEORY Modulation provides a special VLSI signal processing approach where the frequency contents of the signal under processing is manipulated in specific way for optimizing the VLSI circuit operation, mitigating the V component non-ideality, and for the manufacture and application circuit compatibilities. Sev al modulation operations are very suitable for VIST circuit implementation, such as the frequency translation, phase modulation (PM), pulse density modulation (PDM), pulse width modulation (PWM) and pulse code modulation (PCM). These modulation techniques have been wide adopted in VLSI circuits and systems to support wide range of applications. 47Signal Processing, Data Conversion, and Power Management 2.1 PULSE DENSITY MODULATION (PDM) A pulse-density modulation can be used to represent the analog signal in digital- like (ic. discrete in values) form. For a PDM signal, the rdlative density of the pulses represents the analog signal valuc. Pul vidth modulation (PWM) and pulse code modulation (PCM) are two special types of PDM where a PWM signal represents continuous time PDM analog signal and a PCM signal represents a discrete time PDM analog signal. 2.1.1 PDM PRESENTATION OF ANALOG SIGNAL Shown in figure 2.1 is a 2-level PDM bit stream X(n'T), where a1 represents a pulse of positive polarity (Vier-) and a 0 represents @ pulse of negative polarity (Veer) where Vers and Vas. are predefined voltage references for the PDM. The analog signal represented by such a PDM signal stream is given as: V(nT) = Voeg, Veg JX (NT) + Voy (2.1) Analog t PDM Veet. a > t Veet Ll} Fig.2.1 2-level PDM modulation 48VLSI Modulation Circuits In the PDM stream all 1s represent the maximum (Vr) amplitude value, all Os represent the minimum (Vac) amplitude value, and alternating 1s and Os represent an average of the two reference values. A data stream of the combinations of 1s and Os can be used to represent the analog values between the two specified references. ‘The PDM modulation can also be realized using multi-level coding methods where multiple digital values correspond to specific multiple analog references ‘A 3- level PDM signal example is shown in figure 2.2. Analog PDM (fT TM . =) WUT Fig2.2 3-level PDM modulation 2.1.2 DEMODULATION OF PDM SIGNALS Since the pulse density of a PDM signal corresponds to the magnitude of the value of an analog signal, a PDM data stream can be demodulated (ce. recovered) back to the analog signal using a low-pass filter. 2.2 PULSE CODE MODULATION (PCM) ‘The pulse-code modulation (PCM) represents the sampled analog signals where the value of the analog signal is sampled regularly at uniform intervals, with each sample being quantized to the nearest value within a range of digital steps. 49Signal Pro ing, Data Conversion, and Power Management PCM streams have two basic properties that determine their fidelity to the original analog signal including the sampling rate and the quantization bit Sampling rate is the number of times per second that samples are taken. On the other hand, the quantization bit specifies the umber of possible digital values that cach sample can take. The pulse-code modulation (PCM) can be realized using the sigma-delta modulator. Shown in figure 2.3 is a simple sigma-delta modulator employing a first-order continuous-time loop filter. ./s +f + Dn) A | TTI Fig.2.3 1 order continuous-time Sigma-Delta modulator Such a modulator can be modeled mathematically using a linear system by introducing.a quantization noise term as shown in figure 2.4 NO) ss + ae X) SPF v/s + Dols) Fig.2.4 Linear 1* order continuous-time Sigma-Delta modulator model ‘The signal and noise transfer functions of such modulator can be derived respectively as: (2.2) 50VLSI Modulation Circuits 23) ‘The frequency responses of the signal and noise transfer functions are plotted in figure 2.5. It is important to see that the passband of the signal and noise transfer functions is separated in frequency. This interesting behavior (known as noise sharping) is the basis of all sigma-delta modulation circuit techniques. Signal TF Noise TF o Fig.2.5 Typical signal and noise transfer functions of sigma-delta modulator In general case, the PCM signal can be generated using single-loop sigma-delta modulation shown as figure 2.6. N@ +1 His) ade + Dols) F() x oe Fig.2.6 General single-loop Sigma-Delta modulator structure 51Signal Pro ing, Data Conversion, and Power Management The signal and noise transfer functions of the circuit can be expressed respectively as: », As) _ (24) X 1+H(s)F(s) D, I ae —. (25) N 1+H(s)F(s) We can see that if H(s) has a lowpass response with infinite de gain the signal transfer function will have lowpass frequency response as: { H(s) |, © 26 |G) |, 5. 0 On the other hand, the noise transfer function will have the highpass frequency response. ‘A PCM signal can also be generated using discrete-time VLSI circuit such as the switched-capacitor circuit. Shown in figure 2.7 is a typical sigma-delta modulator employing the discrete-time circuit. + Dols) xo Fig.2.7 2nd order discrete-time Sigma-Delta modulator ‘The signal and noise transfer functions of such modulator can be derived respectively as: 52VLSI Modulation Circuits 27) (28) ‘The frequency response of the modulator has an allpass frequeney response for the signal path: (29) On the other hand, the noise will be highpass shaped by the modulator as: - OT, .> or = @sin (2.10) 2.3 PULSE WIDTH MODULATION (PWM) A pulse width modulation represents an analog signal ing, the local duty of the signal between two or more digital reference levels be continuously selected (analog PWM) or has very high resolution (digital PWM) compared with the modulation control clocks. 2.3.1 TWO-LEVEL PWM MODULATIONS ‘A two-level PWM signal can be generated by subtracting the signal from a triangular (or sawtooth) carrier and clamp it to power rails afer a high gain amplification as shown in figure 2.8. Such PWM signal is commonly used in the power amplification circuits due to the fact that the power loss in the switching devices is very low, since when a switch is off there is practically no current, and when it is on, there is almost no voltage drop across the switch. Power loss, being the product of voltage and 53Signal Pro ing, Data Conversion, and Power Management current, is thus in both cases close to zero. PWM also works well with digital controls, which, because of theit on/off nature, can easily set the needed duty- cycle. ‘The PWM has also been used in the communication systems where its duty- cycle is used to convey the information over a communication channel. -t Fig,2.8 2-level PWM modulation. 2.3.2 MULTI-LEVEL PWM MODULATION Shown in figure 2.9 is a multi-level pseudo-differential PDM scheme where the effective output is expressed by the difference of the positive and the negative outputs. Vou Fig.2.9 Muli level pseudo differential analog PWM modulation 54VLSI Modulation Circuits ‘This modulation method is equivalent to a 3-level modulation of [V+-V-] = -1, 0, 1] with the combination of the output polarity [Do+, Do] = [0, 1]. [1,1] oF [0, O}, [1, 0]. An attractive feature of such modulation is that the di ential output has a very small equivalent duty- cle when the input is clo: c close to 50%, This ¢ switching frequency at such condition is shaped significantly higher than the to zero even though each output has a duty-cy is that the single-end modulation that has the 50% duty-cycle. Consequently, the switching noise of the PWM can be significantly attenuated by the parasitic lowpass response of the load without using an additional filter (Le. the filter-less class-D solution). Shown in figure 2.10 is an alternative multi-level PWM. that uses slightly different sawtooth waveform. Fig.2.10 Alternative multi-level pseudo-differential analog PWM modulation 2.4 FREQUENCY TRANSLATION A frequency translation can be used to shift the signal power spectrum by a given frequency offset fi, as shown in figure 2.11 ‘The frequency translation operations -tve as basis of VLSI frequency mixer circuits where two signals at frequencies f and f are used to produce new signals with frequency at the sum f + fm or difference f - fm of the original frequencies. Frequency translations are also commonly used in VLSI circuits 55Signal Processing, Data Conversion, and Power Management such as the chopper stabilize circuit, the lock-in amplifier circuit, the switched- capacitor and switched-current circuits where the signals are frequency translated for the offset and 1/f noise compensation, for the signal detection and for ease of VLSI signal processing. P Fig.2.11 Frequency translation | Pp Fr f Sin(2nft) F | Soli)=Sin(2n(f+F,)t) irequency Translator t fn Fim f Fig.2.12 Basic frequency translation circuit model In the RE transmitter mixer applications, frequency translation is used to shift the baseband signal up to RF frequencies (passbands of air) such that it can be transmitted effectively in the air. On the other hand, the received RF signal in the RF receiver is frequency translated dowa to baseband to recover the original signal contents. In the chopper stabilized amplifier applications, the low frequency input signals are translated to higher frequencies such that the signals can be amplified effectively with minimized impacts of the amplifier de offset and 1/f noise. 56VLSI Modulation Circuits In the lock-in amplifier application a weak low frequency signal within a high noise floor can be modulated to a higher frequency band and therefore can be amplified effectively. The amplified signal is then detected using the demodulation circuit technique employing a phase sensitive detection circuit. In the switched-capacitor and switched-current circuit, the low frequency (baseband) signal is frequency translated to control frequency such that the switched-capacitor resistance or switched-current circuit can be used for effective VLIS signal processing, The modulated signal will be modulated back to baseband after the processing. 2.4.1 ANALOG MULTIPLICATION A simple way for realizing the frequency translation is through the analog multiplication that generates the product of two input signals. In the simplest form, a mixer is a multiplier. ‘The mixer multiplies the input signal to produce output signal at new frequencies. Such mixing operation is used as modulator and demodulator in the transmitter and the receiver path of a communication system, where the bi and vice versa. seband signal is converted into RF signal ‘A mixer based on the analog multiplication is shown in figure 2.13. The output of the mixer contains two frequency terms including the sum and difference of the frequencies given as: Ady V, = Acos(@Z)A, cos(@,t) = 5 cos(@, +.@,)t + cos(@, —@,)t] (2.11) Acoso!) fh th ve) A, co(o,t) fp th ht Al -i-Al +ih-Al ++ Al Fig.2.13 Analog multiplication frequency translation 57Signal Pro ing, Data Conversion, and Power Management 2.4.2 SWITCHING FREQUENCY TRANSLATION Since analog multiplier suffers from noise effect as it depends on modulation control signal magnitude, a switching frequency translation can be used to improve the performance of the frequency translation operation. Shown in figure 2.14 is a switching frequency translation circuit. R, Vi) O—}+—. 7 i Volt) Ru Fig.2.14Sampling frequency translation ‘The switch in this mixer is controlled by a LO (local oscillator) circuit. For a switch control clock with period ‘I’ and 50% duty-cycle, the transfer function of this circuit can be expressed as: S()= Desin(2k-+)-22-4)) (2.12) a NI— Tecan be scen that a single tone input will be multiplied by multiple modulation frequency tones. 2.5 PHASE TRANSLATION Shown in figure 2.15 is a phase translation circuit that translates the signal to a new value with a modulation phase offset. Such signal processing operation is the basis of the VLSI phase interpolation (PT) and the delay locked-loop circuits. 58VLSI Modulation Circuits in(2nft) Phase Modulator i cy Fig2.15 Basic phase translation circuit model 59Signal Processing, Data Conversion, and Power Management Reference: [1] J. Holtz, "Pulse width modulation-a survey,” ID ‘Transactions on Industrial Electronics, Volume: 39, Issue: 5, 1992, Page(s): 410-420 [2] B. Putveys, “Digital audio's final frontier," IEEE Spectrum, Volume: 40, Issue: 3, 2003, Page(s): 34-41. [3] CC. Benz, G. C. Temes, "Circuit techniques for reducing the effects of op-amp imperfections: auto zeroing, correlated double sampling, and chopper stabilization,” Proceedings of the [EEE Volume: 84, Issue: 11, Page(s): 1584 - 1614, 1996. [4] Hongjiang Song, Yan Song, Tai-hua Chen, “VLSI passive switched- capacitor signal processing circuits: Circuit architecture, closed form modeling and applications,” 2008 IBEE Intemational SOC Conference, Page(s): 297 - 300, 2008. 60VLSI Modulation Circuits CHAPTER 3 VLSI SIGMA-DELTA DATA CONVERTER CIRCUITS ‘The VLSI sigma-delta (ZA) modulators offer the VLSI circuit realization fully compatible to the digital VLSI technologies and therefore they are very suitable for SOC implementations. ‘The oversampling and noise shaping techniques employed in the sigma-delta converters allow trading circuit speed for system accuracy to resolve the issues of the traditional data converters for higher overall conversion accuracy. In this way, a device imperfection insensitive signal processing operation can be obtained at the cost of incre: speed in the associated digital circuit forms. sing complexity and In the sigma-delta modulator an analog, signal is presented in the digital form where the relative density of the pulses corresponds to the analog signal's amplitude (also known as pulse code modulation - PCM). ‘The sigma-delta -width modulation (PWM) where the pul density of the output represents the input analog signal amplitude. However in modulation is similar to the pulss the sigma-delta modulator, the output can only change discretely as determined by the control clock. 61Signal Processing, Data Conversion, and Power Management 3.1 SIGMA-DELTA MODULATION PRINCIPLE ‘The sigma-delta modulator is based on the basic techniques of the oversampling, the error processing and the feedback to improve the effective resolution from a coarse quantizer. 3.1.1 QUANTIZATION MODEL, Shown in figure 3.1 is the quantization error model of an ideal conventional 2- bit A/D converter. 2-bit © @ Fig.3.1 Quantization error model of ideal A/D converter Such converter maps an analog signal into the digital form based on the mapping rule shown in figure 3.la. Such a mapping will introduce the signal amplitude dependent error (called quantization error) as shown in figure 3.1b where the highest quantization error is determined by resolution A of the A/D 62Signal Pro ing, Data Conversion, and Power Management ‘The power spectral density of the additive white noise from the quantization can then be approximately expressed as: SN ae 3.1.2 DYNAMIC RANGE OF IDEAL A/D CONVERTER ‘The dynamic range (DR) of an ideal A/D converter can be expressed by the ratio of the output power at the input signal frequency with the maximum amplitude (Avs/2) to the inband quantization error power. For full-scale sinusoidal signal, the signal power is given as: 1 Pos (Ap 2)? = Ay /2? 63) For an M-bit A/D converter, the full scale signal magnitude can be expressed as: Ags =2M A (3.6) Since the inband quantization error power is given as: wz a 6 ‘The dynamic range of an ideal A/D converter can be expressed as: 64Signal Processing, Data Conversion, and Power Management H,(s)=(1-z")* (3.19) ‘The quantization noise power is given as: +f Py= ie [Hy (2a fF af = 12 (2N+)OSR°™" The dynamic range of the ideal sigma-delta modulator can be derived as: px (Ase! 29/2 3 B 2 24 ON) ose aan DRx 6.02M +1.76+10log(=% + (2N-+1)10og(OSR) (6.22) 3.1.5 PERFORMANCE METRICS ‘A few performance metrics are commonly used to specify a sigma-delta modulator, including the signal-to-noise ratio (SNR), signal-to-noise plus distortion ratio (SNDR), the dynamic range (DR), the effective number of bits (ENOB) and the overload level (Kor). * Signal-to-Noise Ratio (SNR) is the ratio of output power at the frequency of the input sinusoidal signal to the total in-band noise power at the output. ‘The SNR of an ideal sigma-delta modulator with signal amplitude Ag, and the only the quantization error is given approximately as SNR(4B) = 10 log A,, (2P,)) (3.23) 68Signal Processing, Data Conversion, and Power Management Vv, ~® | 5 A/D > Ds D/A Fig.3.7 1* order continuous-time Sigma-Delta modulator Shown in figure 3.8 is the linear s-domain model of the first order continuous time sigma-delta modulator, where parameter k, ki, PF: are the input path gain, the integration gain and the feedback gains respectively. Fig.3.8 S-doma in model of 1* order continuous-time Sigma-Delta modulator ‘The signal and noise transfer functions of this first order sigma-delta modulator under the unity loop gain constrain (,e. KiFi= 1) are given respectively as: Dil), __ kk ; 7) 7s 631) Q, H(s)= 72Signal Pro ing, Data Conversion, and Power Management A linear s-domain model of such modulator is shown in figure 3.14, where K, Ku, Ki, Fi, Fe are the gain factors, -F, Fig.3.14 S-domain 2nd order CT Sigma-Delta modulator model ‘The signal and noise transfer functions of the second-order continuous-time sigma-delta modulator are given respectively D, K-K,Ky H,(s)= pat ba (3.36) S\2 Cy) D, Ay(s)= = % , (6.37) (9 KE ARF , @, Tt can be seen that such a modulator is always stable. By further applying the constraint to the gain factors such that the signal and noise transfer function can be further expressed respectively as: (eee =A (3.38) K,F,=1/0 16ssing, Data Conversion, and Power Management G=K-K,-K,...K, G, =F K,°K,..K, G, = Fy: Ky..K, (3.46) G, =F,-K, -Gi Fig.3.18 S-domain high-order CT Sigma-Delta modulator model The signal and noise transfer functions of such modulator can be expressed respectively as: H,(s)2 Po), j= Fey MO) 6, 46,2) +..4G, (297 + 0, 0, e, aay H, (=P), = oe hi “ptHinet ay MO GG det GE y+ Oo, 80VLSI Modulation Circuits Bo Fig.3.21 Alternative high-order Sigma-Delta modulator structure 3.2.4 CASCADE MODULATION TOPOLOGIES ‘The cascade sigma-delta modulation topology can be used to improve the circuit stability for high order sigma-delta converter implementation. ‘The cascade sigma-delta modulations are also known as the multi-stage sigma-delta (MASH). In the MASH sigma-delta modulation shown in figure 3.22, each stage re- modulates a signal containing the quantization error generated in the previous stage. In the digital domain, the outputs of the stages are properly processed based on certain DSP algorithm to cancel out the quantization errors of all the stages except the last one in the cascade. This provides a high order noise shaping using multiple stages. Since the feedback loops in the MASH modulator are localized, unconditional stability can be achieved for high order modulations constructed based on the first and second-order modulation segments. Such approach offers noise shaping performance similar to high order modulation without stability ue.on, and Power Management >| Stage-1 >| Hila) —__I + | Stage-2 >| H(z) a> De — + >| Stage-n >| H(z) Fig, Sigma-Delta modulator structure Shown in figure 3.23 is a MASH modulator example that is based on the cascade of a second-order modulator with a first order modulator. Such a circuit effectively realizes a 3 order sigma-delta modulation, > Ki@o/s) > di 3 order 2-stage 2-1 MASH modulator model 84ing, Data Conversion, and Power Management oro 2” sin" (OT /2)Y, [7-490 657) ait ‘The above equation can be realized based on the circuit shown in figure 3.27. ZA Fig,3.27 Completed high-order digital Sigma-Delta modulator 3.3.3 MODULATOR IMPLEMENTATION Show in figure 3.28 is 2 VLSI circuit implementation of the first-order digital sigma-delta modulator circuit structure using a full adder with the feedback. 88Signal Pro ing, Data Conversion, and Power Management [18] 191 (20) (21] (22] (23) [24] [25] [26] on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 45, Issue: 9, Page(s): 1232 - 1241, 1998. B. P. Brandt, B. A. for 12-b 2-MHy Volume: jooley, "A 50-MHz multibit sigma-delta modulator sion,” IEEE Journal of Solid-State Circuits, 1746 - 1756, 1991. E. J. Vander Zwan, E. C. Dijkmans, "A 0.2-mW CMOS. sigma- deltaModulator for Speech Coding with 80 dB Dynamic Range,” IEEE Journal of Solid-State Circuits, Volume: 31, Issue: 12, Page(s): 1873 - 1880, 1996. M. R Miller, C. S. Petrie, "A multibit sigma-delta ADC for multimode receivers,” IEEE Journal of Solid-State Circuits, Volume: 38, Issue: 3, Page(s): 475 - 482, 2003. A. Jayaraman, P. F, Chen, G. Hanington, L. Larson, P. Asbeck, “Linear high-efficiency microwave power amplifiers using bandpass delta-sigma modulators)” IBEE Microwave and Guided Wave Lewers, Volume: 8, Issue: 3, Page(s): 121 - 123, 1998. L. J. Breems, R. Rutten, G. Wetzker, “A Cascaded Continuous-time sigma-deltaModulator with 67-dB Dynamic Range in 10-MHz bandwidth,” IEEE Journal of Solid-State Circuits, Volume: 39, Issue: 12, Page(s): 2152 - 2160, 2004. B, Dufort, G. W: Roberts, "On-chip analog signal generation for mixed- signal built-in self-test?” IEEE Journal of Solid-State Circuits, Volume: 34, Issue: 3, Pag 318 - 330, 1999. R. Adams, K. Q Nguyen, "A 113-dB SNR oversampling DAC with segmented noise-shaped scrambling,” IEEE Journal of Solid-State Circuits, Volume: 33, Issue: 12, Page(s): 1871 - 1878, 1998. Ki Young Nam; Sang-Min Lee; D. K. Su, Wooley, B.A; “A low-voltage low-power sigma-delta modulator for broadband analog-to-digital conversion,” IEEE Journal of Solid-State Circuits, Volume: 40, Issue: 9, Page(s): 1855 - 1864, 2005. E. Roza, "Analog-to-digital conversion via duty-cycle modulation,” IE tansactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 44, Issue: 11 Page(s): 907 - 914, 1997. 92Signal Processing, Data Conve sion, and Pow Management 96ing, Data Conversion, and Power Management L Vi) O—+ PDM Diive)SYYYV. Vo(t) Vat) Ri Vv (a) class-D amplifer va 4Van() — kT | (WT k 1 vt 123 4 5 UT (b) PWM () PCM Fig.4.2 PDM for class-D amplification It is obvious that the average value of the signal (0) is directly related to the duty-cycle k of the PWM signal. In the PCM signal case, the analog signal can be represented by the number of “1” pulses divided by the total clock period that can be extracted using a lowpass filter. Due to their ideally perfect efficiency and linearity, the class-D amplifiers have become a very attractive solution to implement power amplification for audio band signals and now even RF signals. Shown in figure 4.3 are normalized power efficiency curves for the typical power amplifier families reported in literatures. It can be seen that class-1 amplifiers may offer significantly higher power efficiency compared with the class-A and class-B amplifier counterparts. 100VLSI Modulation Circuits ‘The duty-cycle for the analog signal input V(t) can be derived in term of the ramp signal parameter Vey and Vaceas: VOVew V, Ref k (45) ‘The analog voltage output at the load after the lowpass filtering is given We YO=r, Ref VO-Vaw) (46) Where Vec is the power supply voltage of the driver. ‘The advantage of the above analog class-D amplifier is the circuit simplicity D amplifier suffers from poor PSRR performance since the output analog signal magnitude is directly proportional to the power supply voltage Vec. ‘The PSRR since only one comparator is needed. However such open-loop clas of such open-loop class-D amplifier circuit can be improved by making the modulation gain (i.e. the ratio of power supply voltage to the magnitude of the ramp signal) relatively constant: V.. (Vee ¢ = Cons tant (47) Shown in figure 4.6 is a linear s-domain SFG model of the open-loop clas amplifier circuit. V. MP Ne (2} fe} a,) Qo, Fig, 4.6 SFG model of open-loop class-D amplitice 103,Signal Pro ing, Data Conversion, and Power Management Where Vy is the equivalent quantization noise due to PWM modulation. Vec/Veer represents the modulation gain of the class-D amplifier. @; and Q are the equivalent resonant frequency and the quality factor of the output lowpass filter that are given approximately as: (48) ie (49) RVC : ‘The signal and noise transfer functions of such open-loop class-D amplifier are given respectively as: H,(s)= ‘The signal and noise transfer functions of the circuit are basically the same (no noise shaping), implying that the signal and modulation noise band must be separated before the amplifier to ensure good THD+N at the load. In addition the resonant frequency and the quality factor of the post lowpass filter should be selected such that the useful signal will be able to pass the circuit without significant attenuation and distortion. Since the signal transfer function is directly proportional to the power supply voltage. Such clas poor PSRR as described in early section. D amplifier has 104VLSI Modulation Circuits A fully differential circuit implementation of the open-loop class-D amplifier is shown in figure 4.7. ‘The modulator output waveforms of such differential PWM modulation are shown in figure 4.8. Comparator Driver “+ Vin V T ny Ov, O fomparatot Driver Vi + Vie St Fig 4.7 Fully differential class-D amplifier cixeuit ‘The positive, the negative and the differential duty-cycles of modulation can be derived respectively as: g, =e O-Vouw (4.12) Veep VO-Vew (4.13) Ves (4.14) 105t Fig4.8 Digtevential analog PWM modulation Since the load resistor in this circuit is connected in the BTL configuration, this circuit structure can be used to provide much higher output power than the single-end class-D amplifier circuit configuration. ‘There are four commonly used ways to generate a PWM signal for class-D amplification: e The pulse center is fixed to the center of the time window and both edges of the pulse moved to compress or expand the width. e The lead edge is fixed and the tail edge is modulated, e The tail edge is fixed and the lead edge is modulated, © The pulse repetition frequency is varied by the signal with the pulse width fixed. Note that this method has a stricted range of average output than the other three. more: 4.2.2 CLOSED-LOOP ANALOG CLASS-D AMPLIFIERS ‘The closed-loop class-D amplifiers utilize negative feedback from the PWM output back to the input. Such a closed-loop approach not only improves the 106VLSI Modulation Circuits linearity of the device, but also allows the device to have high power-supply ed and fed back to the input of the amplifier in a closed-loop topology, deviations in the supply rail are noise rejection. Because the output waveform is sen: detected at the output and corrected by the control loop. ‘Typical class-D amplifiers operate with a noise-shaping type of feedback loop, which greatly reduces inband noise due to the nonlinearities of the pulse-width modulator, the output stage, and the supply-voltage deviations. This circuit similar to the noise-shaping operation used in sigma-delta ‘igure 4.9 shows a simplified block diagram of a first-order noise shaper to illustrate this noise-shaping function. The feedback network typically consists of a resistive network. The transfer function for the integrator has been simplified to equal 1/s. b proportional to frequency. It is also assumed that the PWM block has a unity- topology modulators. ause the gain of an ideal integrator is inversely gain and zero-phase-shift contribution to the control loop. Using basic control- block analysis, the following expression can be derived for the output closed- loop class-D amplifier circuit configurations. & Compattor Fig.49 First-order closed-loop analog, class-D amplitier citcuit ‘The linear SEG model of a closed-loop class-D amplifier circuit is shown in figure 4.10. 107Fig.4.10 SFG model of closed-loop class-D amplifier ‘The signal and noise transfer functions of this closed-loop class-D amplifier are given respectively as: H,(s)=——— 7 (4.15) 1+sCR,() | _s_ Vee oO; Ay (j= _. ! (4.16) vat .fLN 1+scr,C*) {8 | , 1/5 ),, Yoo lw, ) ~ Ola, Based on the above transfer function expressions, we can see that © The power supply voltage is eliminated from the gain parameter of the signal transfer function, implying an improved PSRR; © The amplifier gain programming capability using the feedback versus the input resistance ratio; © The lowpass frequency response of the signal transfer function that allows the useful signal ro pass without attenuation and distortion; © ‘The highpass frequency response of the noise transfer function to shape the modulation noise to higher frequency band for effective filtering. 108VLSI Modulation Circuits Shown in figure 4.11 is a fully differential circuit implementation of the first- order closed-loop class-D amplifier that employs a BTL load configuration. Jt Ry Vow CoT Fig.4.11 Fully difterential first order closed-loop class-D amplifier circuit Comparator 1 Vin I/YYY\. OV. Driver @ AN R MW" Fig.4.12 Second-order closed-loop analog class-D amplifier circuit 109Signal Processing, Data Conversion, and Power Management Such a circuit consists of two integrators to provide second-order noise shaping operation. A SFG model of such second-order class-D amplifier is shown in figure 4.13. Fig.4.13 SFG model of closed-loop class-D amplifier Where Hip() is the post lowpass filter transfer function given as Hs) = + 1) (=) -ale} 0) “Ola, ‘The signal and noise transfer functions of such second-order class-D amplifier are given respectively as: H,(s) = ——,;,. -H,,(s) (4.18) [CR PGD +a[sCR,]+1 [sCR,P Hy(s)= “HiplS) 4.19) (sR, FU") +alscR, +1 c ct ‘This class-D amplifier circuit offers a few important properties 110VLSI Modulation Circuits * A higher PSRR since the gain parameter of the signal transfer function is independent of power supply voltage; © More flexible gain programming capability using the feedback versus the input resistance ratio; * A minimized inband signal loss and distortion with lowpass frequency response of the signal transfer function; * A second-order noise shaping with highpass frequency response of the noise transfer function for effective filtering, The second-order cl: s-D amplifier circuit can also be implemented in the circuit form as shown in figure 4.14. Ry Voa c Comparator SS OV. Fig.4.14 Alternative second-order closed-loop analog class-D amplitiet Shown in figure 4.15 is a fully differential second-order closed-loop class-D amplifier circuit. 11Signal Processing, Data Conversion, and Power Management ‘Tr IW S245 Fig.4.15 Pully differential 2nd-order closed-loop class-D amplifier circuit 4.2.3 SELF-OSCILLATION CLASS-D AMPLIFIERS ‘The ramp signals of class-D amplifier can be eliminated using a delay based self oscillation circuit structure as shown in figure 4.16. Voa | Ve Comparator z z L tp + LIYYY\. OV. Driver ¢ AN[] R Vv Fig-4.16 Delay based self-oscillating class-D amplifier circuit ‘The self-oscillation frequency of this class-D amplifier can be derived as: 112VLSI Modulation Circuits -M? _1-(2-k-1 4t, At, Sonne = (4.20) Where M is the modulation depth. ‘The self-oscillation class-D amplifier can also be constructed using the hysteretic in comparator as shown in figure 4.17. Comparator Driver ¢ Vv Vv Fig.4.17 Hystetetic selé-oscillating class-D amplifier ciscuit ‘The self-oscillation frequency of such amplifier can be derived as I-M* _1-(2k-1) 4hRC 4hRC Fount = (4.21) Shown in figure 4.18 is a differential hysteretic self-oscillation class-D amplifier structure. 113Signal Processing, Data Conversion, and Power Management Fig.4.18 Fully differential hysteretic closed-loop clss-D amplifier circuit 4.2.4 ALTERNATIVE ANALOG CLASS-D AMPLIFIERS -D amplifier circuit can be replaced by using the square signal as shown in figure 4.19. Vis Rog Ry a }| Comparator LS Vv Fig4.19 Altemative first-order closed-loop class-D amplitier 4.3 DIGITAL CLASS-D AMPLIFIER ARCHITECTURES ‘The class-D amplifiers based on the digital input are commonly used in the DVD, the iPOD and the notebook PCs applications that store and process the signals in the digital forms. 114VLSI Modulation Circuits One conventional implementation for digital class-D amplification is to convert the digital signal into the analog first and then apply the analog class-D amplification as shown in figure 4.20. However this approach may suffer from D amplification use the digital PCM to digital PWM conversion as shown in figure 4.21. the penalty in the power efficiency. The alternative methods for digital clas —| Digital Input s-D Amplifier Fig. 4.20 Hybrid digital class-D amplifier Power — > DSP }—» PCM to PWM -p—» Dtiver Digital Input Fig.4.21 Ditect PCM-PWM digital class-D amplitier A method for digital class-D amplifier as shown in figure 4.22 employs the sigma-delta modulation to generate bit stream. Power —>} Sigma-Delta L-} peice Digital Input Fig.4.22 Sigma-delta digital class-D amplitierSignal Processing, Data Conversion, and Power Management 4.3.1 HYBRID CLASS-D AMPLIFIER ‘The digital audio data at the input of the digital class-D amplifier is usually a pulse code modulation (PCM) signal from sources such as CD and DVD. A s a. D/A converter to convert the conventional way shown in figure 4.23 us signal into analog form and then to use the analog class-D amplifier for power amplification. bad Di >) DSP L) Sa DacH rpsc) tee] A&A) So Ramp Gen Fig.4.23 Sigma-delta digital class-D amplifier Such approach can be realized using a digital sigma-delta D/A converter to boost the frequency of the multiple bit digital input to single-bit digital streams and then feed it to the circuit as shown in figure 4.24 and figure 4.25. 116VLSI Modulation Circuits py = O 1010. % Veu—@—_______J x R p,_R ey O10L Fig4.24 Hybrid digital class-D amplitier Fig4.25 Fully differential 3-order digital class-D amplifier circuit 4.3.2 DIRECT PCM-PWM CLASS-D AMPLIFIER ‘The direct stream digital sound encoding method uses a generalized form of pulse-width modulation called pulse density modulation (PDM), at a high enough sampling rate (typically in the order of MHz) to cover the whole 7Signal Processing, Data Conve sion, and Power Management acoustic frequencies range with sufficient fidelity. The reproduction of the encoded audio signal is essentially similar to the method used in the class-D amplifiers. Many digital circuits can generate PWM signals. ‘hey normally use a counter that increments periodically (it is connected directly or indirectly to the clock of the circuit) and is reset at the end of every period of the PWM. When the counter value is more than the reference value, the PWM output changes state from high to low (or low to high). ‘The incremented and periodically reset counter is the discrete version of the intersecting method's sawtooth. The analog comparator of the intersecting method becomes a simple integer comparison between the currcat counter value and the digital (possibly digitized) reference value. The duty-cycle can only be varied in discrete steps, as a function of the counter resolution. However, a high-resolution counter can provide quite satisfactory performance. Shown in figure 4.26 are two open-loop PWM class-D amplifier circuits with digital inputs. In these class-D amplifier circuit structures, the PWM modulations are directly realized in the digital domain without using D/A conversion. Py Sigme Digital | 4 re gma igital Correction Delta PWM (a) Pre-cotrection Digital [S- H(z) : . PWM —1+H-4 (b) PWM-Sigma-Delta Fig.4.26 Digital open loop PWM circuit steuctures 118VLSI Modulation Circuits In the sigma-delta modulation PWM scheme shown in figure 4.27, the waveform is the reference signal, on which the output signal is subtracted to form the error signal and this error is integrated when the integral of the error exceeds the limits of the output changes state. -1 Fig, 427 Single-bit 3¢-order Sigma-Delta modulator 4.3.3 VLSI CLASS-D AMPLIFIER TOPOLOGIES Class-D amplifier can be realized in different circuit topologies such as the half bridge and the full bridge. A full bridge uses two half-bridge stages to drive the load differentially. This configuration is often referred to as a bridge-tied load (BTL). The full-bridge configuration operates by alternating the conduction path through the load. This allows bi-directional current to flow through the load without the need of a negative supply or a DC-blocking capacitor. A full-bridge class-D amplifier offers similar advantages of a class-AB BTL amplifier with higher power efficiency. ‘The first advantage of BTL amplifiers is that they do not require DC-blocking capacitors on the output when operating from a single suppl output swings between Vcc and ground and idles at 50% duty-cycle. This means that its output has a Voc/2 de offset. With a full-bridge amplifier, this offset ‘The same is not true for a half-bridge amplifier as its appears on each side of the load, which means that zero de current flows at the 119Signal Pro ing, Data Conversion, and Power Management output. The second advantage is that they can achieve twice the output signal swing when compared to a half-bridge amplifier with the same supply voltage because the load is driven differentially. This results in a theoretical 4x increase in the maximum output power over a half-bridge amplifier operating from the same supply. A full-bridge class-D amplifier, however, requires twice as many MOS switches as a half-bridge topology. Someone consider this to be a disadvantage, because more switches typically mean more conduction and switching losses, However, this generally is only true with high-output power amplifiers (e.g. > 10W) due to the higher output currents and supply voltages involved. For this reason, half- bridge amplifiers are typically used for high-power applications for their slight efficiency advantage. Most high-power full-bridge amplifiers exhibit power efficiencies in the range beyond 80% with 8Q loads. However, half-bridge amplifiers achieve power than 14W per channel into 8Q. iciencies greater than 90% while delivering more 4.4 VLSI PWM CIRCUIT IMPLEMENTATIONS ‘The class-D amplifier circuits can be realized in VLSI circuit form using the VLSI manufacture process technologies that are compatible to most digital circuits for SOC applications. 4.4.1 TRIANGULAR RAMP SIGNAL GENERATION A sawtooth or triangle wave as shown in figure 4.28 is used in PWM circuit to convert the audio signal into a pulse width modulated (PWM) signal. ‘The triangle wave generator typically consis of an integrator and a hysteresis comparator. ‘The circuit integrates a square wave that was created by the hysteresis comparator. ‘he frequency of the sawtooth oscillator impacts the performance of the class-D amplifier. A balance between performance and component times the maximum signal frequency that is typically 250kH to 1.5 MHz for can usually be achieved with an oscillator frequency at least 10 audio band signal of 10 to 20 kHz. Such selection allows attenuating the switching frequency sufficiently while allowing most of the audio signal to pass to the load without attenuation. ‘Too low oscillator frequency can introduce 120VLSI Modulation Circuits distortion because of the amplifier's lower sampling rate. A lower oscillator frequency also requires a lower filter-cutoff frequency to sufficiently attenuate the switching frequency that requires larger circuit component values and increasing the overall cost. A higher oscillator frequency allows the filter cutoff to be higher, thus attenuating the switching noise sufficiently while allowing smaller component values Ip Ip Var | Fig.4.28 VLSI Triangular voltage signal generation circuit Reasonably high oscillator frequency also reduces the cost and the component sizes for the output filter while extending the amplifier's frequency range. However, higher sampling rate reduces distortion to a certain extent, but slew sates for the comparator and bridge drivers become a limiting factor at high frequencies. 121Signal Processing, Data Conversion, and Power Management 4.4.2. PWM SIGNAL GENERATION CIRCUITS A typical pulse width modulation (PWM) circuit shown in figure 4.29 and 4.30 uses the natural sampling operation where the signal is compared to a triangular (sawtooth) waveform to generate the digital signal. ‘The slope of the triangular waveform can be expressed Slope = Mu (4.22) ‘The pulse widths of the two comparator outputs can be expressed respectively as (4.23) (4.24) (4.25) 122VLSI Modulation Circuits —— D+ PWM Signals & 2 & «a -- a Fig.4.29 BTL PWM scheme 7M circuit Fig.4.30 BTL PW 123,Signal Processing, Data Conversion, and Power Management Aq alternative PWM modulation generation circuit is shown in figure 4.31 and 4.32. ‘The pulse widths of the two comparator outputs can be expr as d respectiv t, (4.26) = (4.27) Finally the differential pulse width is given as t-t a (4.28) Wy Fig.4.31 Alternative BTL PWM scheme 124VLSI Modulation Circuits V+ fs Sy D+ v- ? a Lf KRI RI - + var} 4 Vou 2 R Fig.4.32 Alternative PWM circuit ‘The slope of the triangular waveform in this modulation scheme can be expressed as: Slope = ae (4.29) 4.4.3, RAMP-LESS PWM CIRCUIT Ramp signal generation circuit can be eliminated using a self-oscillation PWM modulation circuit as shown in figure ‘The hysteresis voltage in this PWM circuit can be expressed as: AV =KV ay —Vaay = 20V y (4.30) 125Signal Processing, Data Conversion, and Power Management Vas ae r Vs View: R c RI (e1yR1 re + rye Var +, Van = R Fig.4.33 Self oscillation PWM circuit ‘The time durations in this circuit can be derived as: (k=D)ARC ! V, 14 Vy f (4.31) (K=DkRC : a oa tt Vu (4.32) ‘The period of the PWM signal that is given as the sum of the above time parameters is given as: 126VLSI Modulation Circuits Taierh= Aeon or G ) M ‘The duty-cycle of the modulation can then be expressed as function of the input signal magnitude as: (4.34) Ath Vy It can be scen that there is a linear relation between the duty-cycle k and the signal voltage, implying the high linearity amplification of the circuit. 4.4.4 DIGITAL INPUT PWM SIGNAL GENERATION CIRCUITS Shown in figure 4.34 and 4.35 are two typical digital PWM modulator implementations, where the analog PWM circuits are realized in the digital circuit forms. Such circuits offer the advantages of fully digital technology compatibility and simpler interfaces with the digital signal sources. PWM Sigma- Integeator |p| Hysteresis . Delta Comparato Delay Fig.4.34 First-order PWM modulator 127Signal Processing, Data Conversion, and Power Management =p Sigma. Tagine Integrator|_,| Hysteresis [PWM Delta Comparator Delay Fig.4.35 Second-order PWM modulator 4.5 PWM SIGNAL POWER SPECTRA. "he spectra of various PWM signals are similar, and each usually contains a de component, a base sideband containing the modulating signal and phase modulated carriers at each harmonic of the frequency of the pulse. ‘The amplitudes of the harmonic groups are restricted by a sinx/x envelope (sine function) and extend to infinity. On the other hand, the pulse slew rate and the modulation modes will impact the power spectrum of the PWM modulated signals. As shown in figure 4.36, the pulse slew rate has impact similar to a lowpass PIR filter that impacts the high frequency contents of the modulation output. In practical applications, this behavior can be used to minimize the EMI effect of the class-D amplifier circuits. The PWM modulation modes, such as the BD and AD modulation modes shown in figure 4.37 and 4.38 will also impact the spectrum content of the signal. Power (8) Slew Rate =105, @ée@sees 88 8 0 2 © «© 8 100 m0 14 160 180 20 Frequency (Mhz) Fig.4.36 Power spectrum versus amplifier driver output slew rate 128VLSI Modulation Circuits In order to extract the amplified audio signal from this PWM waveform, the output of the class-D amplifier can be fed to a lowpass filter with cut off, frequency at least one order of magnitude lower than the switching frequency. As the result, the output of the filter is equal to the average value of the square wave. In addition, the lowpass filter prevents high-frequency switching energy from being dissipated in the resistive load. Assume that the filtered output voltage remain constant during a single switching period. This assumption is fairly accurate because switching frequency is much higher than the highest input audio signal frequency. Therefore, the relationship between the duty-cycle and resulting filtered output voltage can be derived using a simple time-domain analysis of the inductor voltage and current. Power (48) Frequency (kHz) Fig.4.37 Power spectrum of | KHz signal with 250 KHz BD model PWM 129Signal Processing, Data Conversion, and Power Management ° Power (d8) » 100 120 1 0 100 1000 10000 Frequescy (kHz) Fig.4.38 Power spectrum of | kHz signal with 250 kHz AD model PWM. ‘The feedback loop in a close-loop class-D amplifier helps to shape the quantization noise that greatly reduces in-band noise due to the nonlinearities of the pulse-width modulator, the output stage, and the supply-voltage deviations. Such topology is similar to the noise shaping in the sigma-delta modulators. One of the major drawbacks of traditional class-D amplifiers is the need for an external LC filter. This need not only increases a solution’s cost and board space requirements, but also introduces the possibility of additional distortion due to filter component nonlinearities. Fortunately, many modern class-D amplifiers utilize advanced “filterless” modulation schemes to eliminate, or at least minimize, external filter requirements. One disadvantage of filterless operation of radiated EMI from the speaker cables. Because the class-D amplificr output waveforms are high-frequency square waves with fast-moving is the po: transition edges, the output spectrum contains a large amount of spectral energy at the switching frequency and integer multiples of the switching frequen Without an external output filter located within close proximity of the device, the speaker cables can radiate this high-frequency energy. In such case, spread spectrum modulation can help to mitigate possible EMI problems in filterless class-D amplifiers. 130VLSI Modulation Circuits Reference: (t] [2] GB] [4] 65] [6] [3] 1] [10] (11) te Bah-Hwee Gwee, et al, “A Micro-power Low-Distortion Digital clas: D Amplifier Based on an Algorithmic Pulse width Modulation,” IE ‘Tran. Circuits and Systems-I: Regular Papers. Vol. 52. No. 10. Oct. 005. Miguel Angel Roja-Gonzalez, et al, “Low-Power High-Efficiency class- D Audio Power Amplifiers,” IEEE Vol. 44, No. 12. Dec 2009. Kyoungsik, et al, “class-D Audio Amplifier using 1-Bit Fourth-Order Delta-Sigma Modulation,” IEEE Tran. Circuits and Systems-I: Express Briefs. Vol. 55. No, 8. August 2008, F. nyboe, et al, “A 240W Monolithic class-D Audio Amplifier Output Stage,” ISSCC 2006. Mikkel C. W. Hoyerby, et al, “Cartier Distortion in Hysteretic Self- Oscillating class-D Audio Power Amplifiers; Analysis and Optimization,” TF 2009, ‘Tran. Power Electronics. Vol. 24. No.3. March Vahid M. Tousi, et al, “A 3.3V/1W class-D Audio Power Amplifier with 103dB DR and 90% Efficiency,” Proc. 23" International Conference on Microelectronics. Vol. 2. NIS Yugoslavia. 12-15 May 2002. Patrick P. Siniscalchi, et al, “A 20W/Channel class-D Amplifier with Significantly Reduced Common-Mode Radiated Emission,” ISSCC2009. Mykhaylo Teplechuk, et al, “Filterless Integrated class-D Audio Amplifier Achieving 0.0012% THD+N and 96dB PSRR When Supplying 1.2W,” ISSCC 2011. Marco Berkhout, “A 460W class-) Output Stage with Adaptive Gate Drive,” ISSCC 2009. Toru IDO, et al, “A Digital Input Controller for Audio class-D Amplifier with 100W 0.004% THD+N and 113dB DR,” ISSCC2006. Miguel A. Rojas-Gonzalez, et al, “T'wo class-D Audio Amplifiers with 89/90% Efficiency and 0.02/0.03% THD+N consuming Less than ImW of Quiescent Power,” ISSCC 2009. Marco Berkhout, “An Integrated 200-W class-D Audio Amplifier,” IEEE JSSC. Vol. 38. No.7. July 2003. 131Signal Pro ing, Data Conversion, and Power Management (13) (14) (15) 116) (17] [18] (19) [20] [23] Simon Cimin Li, et al, “New High-Efficiency 25V/0.45W RWDM class-D Audio Amplifier for Portable Consumer Electronics,” TE ‘Tran, Circuits and Systems-I: Regular Papers. Vol. 52. No.9. Sept. 2005. Mei-Ling Yeh, et al, “An Electromagnetic Interference (EMI) Reduced High-Efficiency Switching Power Amplifier,” IEEE Tran. Power Electronics. Vol. 25. No.3. March 2010. Wei Shu, et al, “Power Supply Noise in Analog Audio class-D Amplifier,” IE No. 1. Jan. 2009. ‘Tran. Circuits and Systems-I: Regular Papers. Vol. 56. Kwang-Chan Lee, et al, “A High-Performance Fast Switching Charge Dump assist anted class-K Audio Amplifier,” IEEE Tran. Circuits and tems-I: Regular Papers. Vol. 57. No. 6. June 2010. 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Page(s): 1198 - 1206, 2003, Koizumi, H; Suetsugy, T's Fujii, My Shinoda, K; Mori, S "class-DE high-efficiency tuned power amplifier,” I on Circuits and Systems I: Fundamental Theory and Applications, , Page(s): 51 - 60, 1996 Chang, J.85 Meng-Tong Tan; Zhihong Chen; Tked, Ks {BE Transactions Volume: 43, Issue: chow Tong; “Analysis and design of power efficient cl s-D amplifier output stages,” IEEE Transactions on Circuits and Systems I: Fundamental ‘Theory and Applications, Volume: 47, Issue: 6 Page(s): 897 - 902, 2000. Kyu Min Cho; Won Seok Oh; Young Tae Kim; Hee Jun Kim; "A New Switching Strategy for Pulse Width Modulation (PWM) Power Converters,” IEEE Transactions on Industrial Electronics, Volume: 54, Issue: 1, Page(s): 330 - 337, 2007. Ertl, H. Kolar, J.W of switched-mode assisted linear power amplifiers," IEEE Zach, F.C. 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Kavimierczuk, MK; Szaraniev, W.; “class-D_ zero-voltage-switching inverter with only one shunt capacitor,” Electric Power Applications, IEE Proceedings B Volume: 139, Issue: 5, Page(s): 449 - 456, 1992. Bah-Hwee Gwee; Chang, JS; Adrian, V3 “A micropower low- distortion digital class-D amplifier based on an algorithmic pulsewidth modulator,” Circuits and Systems I: Regular Papers, TE ‘Transactions on Volume: 52, Issue: 10, Page(s): 2007 - 2022, 2005. Oliva, A. SS. Vo, T.V.3 "A mult-loop voltage feedback filterless class-D switching audio amplifier using unipolar pulse-width- modulation,” Consumer Electronics, IEE 5), Issue: 1, Page(s): 312 - 319, 2004. Ertl, Hs Kolar, JW; Zach, F.C; "Analysis of a multilevel multicell switch-mode power amplifier employing the "flying-battery” concept,” TEEE Transactions on Industrial Electronics, Volume: 49, Issue: 4, Page(s): 816 - 823, 2002. ; Ang, Transactions on Volume: 133,Signal Pro ing, Data Conversion, and Power Management [33] 34] [35] (36) 37] [33] [41] Walker, G.R; "A class-B switch-mode assisted linear amplifier,” TEE. Transactions on Power Electronics, Volume: 18, Issue: 6, Page(s): 1278 - 1285, 2003 Li, S.C; Lin, V.C.-C.; Nandhasti, K; Ngarmnil, |.; "New high-efficiency 2.5 V/0.45 W RWDM class-D audio amplifier for portable consumer E Transactions on Circuits and Systems I: Regular electronics,” TE! Papers, Volume: 52, Issue: 9, Publication Year: 2005, Page(s): 1767 - 1774, 2005 Digital audio's final frontier,” IEEE 40, Issue: 3, Page(s): 34 - 41, 2003. Spectrum, Volume: Rojas-Gonzalez, M.A; Sanchez-Sinencio, Ej “Design of a class-D Audio Amplifier IC Using Sliding Mode Control and Negative Feedback,” IEEE Transactions on Consumer Electronics, Volume: 53, Issue: 2, 609 - 617, 2007. Chudobiak, W, class-D transistor amplifiers,” Volume: 4, Issue: 1, Page(s): 25 - Mosely, LD. Mellor, P.H.; Bingham, CM; "Effect of dead time on harmonic distortion in class-D audio power amplifiers,” Electronics 2, Page(s): 950 - 952, 1999. 4; Page, D.F.; “Frequency and power limitations of Journal of Solid-State Circuits, 7, 1969. Letters. Volume: 35, Issue: Midya, P Rocckner, B.; Bergstedt, S. “Digital correction of PWM switching amplificrs,’ IEEE Power Electronics Letters, Volume: 2, Issuc: 2, Page(s): 68 - 72, 2004. Sang-Hwa Jung; Nam-In Kim; Gyu-Hyeong Cho; "class-D audio power amplifier with fine hysteresis control,” Electronics Letters Volume: 38, Issue: 22, Page(s): 1302 - 1303, 2002. Gaalaas, ; Liu, BY. Nishimura, N.; Adams, R; Swectland, K.; * Integrated stereo AX class-D amplifier,” IEEE Journal of Solid-State Circuits, Volume: 40, Issue: 12, Page(s): 2388 - 2397, 2005.1 imierczuk, M.K.; "class-D voltage-switching MOSF amplifier,” IEE Proceedings B Electric Power Applications, Volume: 138, Issue: 6, 285 - 296, 1991. Wei Shu; Chang, J.S.; "THD of Closed-Loop Analog PWM class-D Amplifiers,” IEEE ‘Transactions on Circuits and Systems I: Regular Papers, Volume: 55, Issue: 6, 1769 - 1777, 2008. power 134VLSI Modulation Circuits [43] 44] [46] [7] 148] [49] 150] Koizumi, H.; Kurokawa, K Mori, S.; "Analysis of class-D inverter with irregular driving patterns,” IEEE Transactions on Circuits and Systems 5. :3, Page(s): 677 - 687, 2006. I: Regular Papers, Volume: 53, Is ‘Tong Ge; Chang, J.S3 "Modeling and Technique to Improve PSRR and PS-IMD in Analog PWM class-D Amplifiers,” IEEE ‘Transactions on Circuits and Systems I: Express Briefs, Volume: 55, Issue: 6, Page(s): 512 - 516, 2008. Meng ‘Tong Tan; Chang, J. Hock Chuan Chua; Bah Hwee Gwee; "An investigation into the parameters affecting total harmonic distortion in low-voltage low-power class-D amplifiers,” TE Transactions on Circuits and Systems I: Fundamental Theory and Applications, Volume: 50, Issue: 10 Page(s): 1304 - 1315, 2003. Himmelstoss, F. idelmoser, K.H.; “High dynamic class-D power amplifier,” IEEE Transactions on Consumer Electronics, Volume: 44, Issue: 4, Page(s): 1329 - 1333, 1998. Morrow, P., Gaalaas, E.; McCarthy, O.; “A 20-W stereo class-D audio ‘output power stage in 0.6-um BCDMOS technology,” Journal of Solid-State Circuits, Volume: 39, Issue: 11, Page(s): 1948 - 1958, 2004. Mellor, P.H. Leigh, S.P.; Cheetham, B.M.G.; "Reduction of spectral distortion in class-D amplifiers by an enhanced pulse width modulation sampling process,” IEE Proceedings G Circuits, Devices and Systems, Volume: 138, Issue: 4, Page(s): 441 - 448, 1991, Burrow, S.; Grant, D.; “Efficiency of low power audio amplifiers and 4 Transactions on Consumer Electronics, Volume: 22 - 630, 2001. loudspeakers,” TEI 47, Issue: 3, Page( ‘Tsai-Pi Hung; Metzger, AG. Zampardi, P.Js Iwamoto, M. Asbeck, P.M; “Design of high-efficiency current-mode class-D amplifiers for wireless handsets,” IEEE ‘Transactions on Microwave Theory and ‘Techniques, Volume: 53, Issue: 1, Page(s): 144 - 151, 2005 135Signal Processing, Data Conv sion, and Power Management 136VLSI Modulation Circuits CHAPTER 5 VLSI PHASE (DELAY) INTERPOLATION CIRCUITS A VEST phase interpolation (PI) circuit belongs to the phase shift key modulation circuit that can be used to adjust the phase of the output reference clock signal A PI offers a finite number of tunable discrete output clock pha is represented by a particular digital input code. In the VISI high- Each phas speed 1/O circuit applications, the PT circuit can be used to generate an optimal reference clock to sample the receiver incoming data stream, ‘There are two basic types of VLSI phase interpolation schemes that can be used to provide perfectly linear phase interpolation operation, including the sinusoidal phase interpolation and the triangular (or linear) phase interpolation. A VLSI phase interpolation operation is typically realized based on the weighted summation (called mixing) of two or more signals of same frequency and different phase (commonly known as the I/Q signals if the signals are 90 degr apart), ‘The practical VISI phase interpolations are usually based on the combination of the basic phase interpolation algorithms that employs the single tone-like preconditioning using band-limiting circuits and the linear weighting coefficients, Such an approach provides a workable solution for the trade-off between the design simplicity and the circuit performance. 137ing, Data Conversion, and Power Management 5.1 PHAS E INTE POLATION PRINCIPLE There are two basic types of VLSI phase interpolation schemes that can provide perfectly linear phase interpolation, including the sinusoidal phase interpolation and the triangular (or linear) phase interpolation. ‘The sinusoidal interpolation algorithm is based on the weighted summation of two single-tone sinusoidal signals of same frequency and 90 degrees phase difference (known as 1/Q signals). The linear phase interpolation, on the other hand, is based on the weighted summation of the two or more triangular (linear ramping) clock signals. A VLS implementation simplicity in the signal pre-condition that relies on the single- tone signals, which can be generated using a simple lowpass or bandpass filter to eliminate the harmonic contents of the input I/O clock references. However the sinusoidal phase interpolation may suffer from the constraint in the VLSI circuit implementation since it usually requires nonlinear weighting coefficients for perfectly linear phase interpolation. ‘The VLSI triangular phase interpolation circuit, on the other hand, offers the advantage of high VLSI circuit implementation simplicity in the weighting coefficient generation circuit. However, @ triangular phase interpolation circuit typically suffers from the design complexity in the VLSI signal precondition circuit implementations for highly linear triangular signal generation for the perfectly linear phase interpolation. sinusoidal phase interpolation circuit usually offers the advantage of 5.1.1 SINUSOIDAL PHASE INTERPOLATION A pha: by weighted addition of two sinusoidal clock signals of same frequency with e interpolation based on the I/Q sinusoidal clock signals can be realized n/2 (.c. 90°) phase difference as shown in figure 5.1. ‘The sinusoidal phase interpolation operation can be mathematically expressed by the phase interpolation equation as V, (t) = Asin(at - ) = Alcos(g)sin(ar) -sin(¢)cos(ort)] (5.1) 138VLSI Modulation Circuits ‘This equation implies that an arbitrary phase sinusoidal signal output can be realized by weighted combination of the 1/Q signal sinusoidal clock input as: V(t) = Asin(ot + @) =a, -V,(0) + aq -Vo(0) V,(t)= Asin(ot) V(t) =-Acos(ot) (6.2) a, = cos) ap =sin(@) Vi(t) = Asin(ot) Volt) = Asin(t-n/2) n/2 — 3n/2 o Vo(t) = Asin(ot-) Fig.5.1 Phase interpolation based on I/Q sinusoidal signals 139Signal Processing, Data Conve sion, and Power Management ‘The operation of the sinusoidal phase interpolation can also be expressed using a phase diagram as shown in figure 5.2 that represents the relation between the interpolation weights (or coefficients) of the input 1/Q clock signals and the interpolated output clock phase. Fig.5.2 Phase diagram for sinusoidal phase interpolation Tt can be seen that for a sinusoidal phase interpolation the relationship between the output clock phase and the interpolation weighting coefficient is non-linear. In addition, we can also see that the sum of the two weighting coefficient is not constant: a, = tan (2% ¢ Ge (63) aj +a5=1 Such nonlinear properties have a major drawback in VEST circuit implementation, which may significantly increase the complexity for the interpolation circuit implementation. 5.1.2. TRIANGULAR PHASE INTERPOLATION The nonlinear phase relation and the non-consta nt weighting coefficient sum in the sinusoidal phase interpolation can be avoided using the triangular phase interpolation technique as shown in figure 5.3. The triangular phase interpolation offers linear relation between the interpolation phase and the 140VLSI Modulation Circuits interpolation weight coefficients. ‘The constant sum of the weighting coefficients is very suitable for the VLSI circuit implementation. Vi(t) Velt)=Vit-T/4) Fig.5.3 Linear signal based phase interpolation algorithm ‘The operation of the triangular phase interpolation can be expressed by the following equation: g yt o-Tl4 0) Vu E+ A Vy —)=0 54) a, +a Tr = b= 09°F 65) 141Signal Pro ion, and Power Management ‘ing, Data Conver: It is important to see that the zero-crossing time of the weighted [/Q triangular waveforms are linear with respect to the interpolation coefficient. ‘The phase diagrams for the above triangular phase interpolation scheme is shown in figure 5.4 Fig. 54 Phase diagram for linear signal based phase interpolation It can be seen that for the triangular phase interpolation the interpolated phase is linearly related to the interpolation weighting coefficients and that the sum of the weighting coefficients is constant. Such relation can also be demonstrated based on the circuit simulation results as shown in figure 5.5 for various weighting coefficients. 142VLSI Modulation Circuits 5.2. VLSI PI CIRCUIT IMPLEMENTATIONS, A typical VSI phase interpolator circuit usually consists of four major building components as shown in figure 5.6, including the polyphase clock generator, the conditioner, the mixer and the control circuit. n lock | 54>} Conditioner +2} Mixer | tay Generator Control Circuit Fig.5.6 VLSI phase interpolation circuit block diagram A VLSI phase interpolation circuit typically includes the following functions: * The polyphase clocks are generated in the polyphase clock generation circuit, employing either a VCO, a VCDL or other methods; ¢ The polyphase clocks are pre-conditioned either through a lowpass or bandpass filter or through a linear ramps generation circuit based on the sinusoidal or triangular method, that shapes the harmonic contents in the clocks; © The pre-conditioned polyphase clocks are mixed based on programmable weighted addition operation. The mixed clock is amplified and limited for output; © The phase interpolation control circuit for output clock phase tuning s the weighting coefficients. 143Signal Pro Shown in figure 5.7 are two VLSI digital phase interpolation circuit ing, Data Conversion, and Power Management implementations that are based on the direct phase interpolator circuit structure, where one additional phase is interpolated from the two phases (0 and 90), Oj 459 90° ag 90° (a) 1-to-2 interpolation 30° 60° 90° ARRARARARARA | 0° 90° (b) 1-to-3 interpolation Fig. 5.7 VLSI direct phase interpolation circuits Shown in figure 5.8 is a VLSI R-ring phase interpolation circuit structure, where the signal conditioning is realized using a simple RC lowpass filter. ‘The 1/Q phase mixing coefficients in this phase interpolation circuit structure are implemented through the weighted addition of the conditioned 1/Q clock phase signal based on the ratio of the resistors as shown figure 5.9: ae 18° 36° 54° i aa RARAA He HHH A A 0° ‘90° H Fig, 3.8 VLSI R-ring I-to-5 phase interpolation circuit 144VLSI Modulation Circuits Yo RI R2 Xa(t) Xo) Fig. 5.9 VLSI resistor ratio phase interpolation circuit Based on the weighted summation of two clock signal 11 1 1 YOG PRI MOR tXOOR 66) 1 we have that YQ=a,-X,(t)+aq-Xo(t) Tt can be seen that a, +a, =1 (6.8) ‘Therefore such PI circuit belongs to the linear coefficient phase interpolation type and it is preferred to have triangular input 1/Q clock signals for the phase interpolation. 145Signal Pro ing, Data Conversion, and Power Management Shown in figure 5.10 is a VLSI phase interpolation circuit based on the current 1/Q clock mixing operation. This circuit can be used to approximate the sinusoidal phase interpolation circuit operations. xo at AG Gk Xelt) Fig. 5.10 VEST current steeling phase interpolation circuits For this current stecling PI mixer circuit, the differential input and output signal relation can be expressed as YOR Bm -X(O+R- Sz Xo 8m = 261, 6%) 8m = V2Bh By lewing Y= dla, -X,()+ ay Xo a, = 1,10, +1. 6.10) Gq =VIy IU, +1) 146VLSI Modulation Circuits We can see that 4 + h =1 (6.11) Eptdy Typtdy 4a gto ap tag = It implies that such a phase interpolation circuit is suitable for the sinusoidal 1/Q clock signals. ‘The differential VLSI circuit shown in figure 5.11 can usually be used to control the weight current for the VLSI phase interpolation operation. an Fig. 5.11 VLSI phase interpolation coefficient generation circuit For such circuit structure we have that (5.12) And 1+h=l, 6.13) 147Signal Pro ing, Data Conversion, and Power Management Shown in figure 5.12, figure 5.13 and figure 5.14 are several VLSI phase interpolation mixer circuit implementations that are based on the symmetrical load differential buffer circuit structures. Such circuits provide regulated signal voltage swing for the mixer circuit core and the pre-conditioner circuit employing a replica biasing circuit stracture. Above circuit structures can be used to implement the PI mixer circuit by including the digital control circuits that provide the digitally controlled weights to support the VISI PI mixing operations qk 4D Ot Pcki# Ck2 Ck2# PI Mixer Fig. 5.12 VLSI phase interpolation based on CML circuit Fig, 5.13 VLSI PI mixer circuit employing the replica biasing circuit 148VLSI Modulation Circuits Prias — Tell] Noss Fig, 5.14 Alternative VLSI PI mixer circuit 5.3 VLSI PI CIRCUIT PHASE NOISE MODEL The VLSI PI circuit structures are similar to the basic delay buffer circuit structures, where the random phase noise of the PI circuit can be approximately Meus . PAT [2.1 . MS = |——— 14+ =a, — 14) ty CV 3" 7, en) expressed as: Or (5.15) 149Signal Processing, Data Conversion, and Power Management Reference: (1) (2) 13] i4] 6] (6) [8] 0 [10] (124 (13] [14] (15] F. Yang, et al, “A CMOS Low-Power Multiple 2.5-3.125 Gb, Macrocell for High IO Bandwidth Network ICs”, IEEE JSS No. 12, Dee. 2002. erial Link , Vol 37, ‘T. Kim, et al, “Phase Interpolator Using Delay Locked Loop”, SSMSD 2003. L. Yang, et al, “An Arbitrarily Skewable Multiphase Clock Generator Combing Direct Interpolation with Phase Error Averaging”, 2003 J-M Chou, et al, “A 125Mhz 8b Digital-to-Phase Converter," ISSCC 2003. R. Kreienkamp, et al, “A 10-Gb/s CMOS Clock and Data Recovery $2003 Custom Circuit with an Analog Phase Interpolator," TEI Integrated Circuits Conference. A. Maxim, “A 0.16-2.55Ghz CMOS Active Clock Deskewing PLL Using JSSC. Vol. 40, No. 1, Jan. 2006. Analog Interpolator," TE J-M. Chou, et al, “Phase Averaging and Interpolation Using Resistor Strings or Resistor Rings for Multi-Phase Clock Generation," IEEE ‘Trans. Circuits & Systems, Vol53, No. 5, May 2006. W. Rhee, et al, “A Semi-Digital Del Based Finite State Machine”, IE! No.11, Dec. 2004. B. W. Garlepp, et al, Interface Circuits," “Locked Loop Using an Analog- Trans. Circuits & Systems, Vol51, “A Portable Digital DLL for High-Speed CMOS 4 JSSC Vol.34, No. 5, May 1999. G, Jovannovic, et al, “Delay Locked Loop with Linear Delay Element," , September 28-30, 2006. J. G. Maneatis, “Low-Jitter Process-Independent DLL and PLL Based on. Self-Biased Techniques,” IEF Vol. 31, No. 11, Nov. 1996. B. W. Garlepp, et al, “A Portable Digital DLL for High-speed CMOS. Interface Circuits”, IEEE JSSC, Vol. 34, No. 5, May 1999. Serbia and Montenegro, Nis S-S Hwang, et al, “A DLL Based 10-320 Mhz Clock Synchronizer," ISCAS 2000, May 28-31, Geneva, Switzerland. C. Kim, et al, “A Low-Power Small-Area +/- 7.28ps Jitter 1-Ghy DLL~ Base Clock Generator”, IEEE JSSC, Vol. 37, No. 11, Now. 2002 150VLSI Modulation Circuits (16) 17] [18] 19] (20) (26) 7 25) P29] Y Arai, “A High-Resolution Time Digitizer Utilizing Dual PLL Circuits," TEEE2004, H. J. Song, “Digital Delay Locked Loop for Adaptive De Generation”, US Patent, No. 6275555, 2001. skew Clock H. J. Song, “Programmable De-Skew Clock Generation based on Dual Digital Delay Locked Loop Structure”, SOCC2001. G.C. Hsieh, ef al, “Phase-Locked Loop ‘Techniques-A Survey”, IE ‘Transactions on Industrial Electronics, Vol.43, No.6, Dec.1996. P. Heydari, et al, “Analysis of the PLL Jitter Due to Power/Ground and Substrate Noise," TEER Transactions on Circuits and System Papers, Vol 51, No. 12, Dee. 2004. I: Regular ‘I. M. Almeida, et al, “High Performance Analog and Digital PLL Design,” IEEE 1999. V. F. Kroupa, “Noise Properties of PLL Systems,” IEEE Transactions on Communications, Vol COM-30, No. 10, Oct. 1982. A. Maxim, “A 0.16-2.55-Ghz CMOS Active Clock De-Skewing PLL. E, JSSC, Vol. 40, No.1, Jan. 2006. Using Analog Phase Interpolation,” M. Inoue, e af, “Over-Sampling PLL for Low-Jitter and Responsive Clock Synchronization,” IEEE2006. T. Toifl, ef ak “A 0.94ps-RMS-Jitter 0.016-mm2 25Ghz Multiphase Generation PLL with 3600 Digitally Programmable Phase Shift for 10- Gb/s Serial Links,” IEEE JSSC Vol. 40, No.12, December 2005 J. B. Bulzacchelli, ef a4, “A 10-Gb/s 5-Tap DFE/4-Tap FFE Transceiver in 90nm CMOS Technology,” E, JSSC_Vol. 41, No. 12, December 2006. B.C TE Kim, e/ a, “A 250 Mhz-2Ghz Wide Range Delay-Locked Loop,” C Vol. 40, No.6, June 2005. T. Matano, ¢f, a, “A 1-Gb/s/pin 512-Mb DDRIT SDRAM Using a Digital DLL and a Slew-Rate-Controlled Output Buffer,” TE Vol38, No. 5, May 2003. R. H. Van de Beek, ¢ al, “Low-Jitter Cl Comparison Between PLLs and DLIs,” TE! lock Multiplication: A 1 Tran. Circuits and System-II: Analog and Digital Signal Processing, Vol.49, No. 8, Aug. 2002. 151Signal Pro ing, Data Conversion, and Power Management [39] [49] [41] [42] {43] T. C. Weigandt, ¢f, al, “Timing, Jitter Analysis for High-frequency Low- power CMOS Ring-Oscillator Design,” Proc. Int. Symp., Circuits and Systems, London, UK., June 1994, P. Vancorenland, ¢, af, “A Wideband IMRR Improved Quadrature Mixer/LO Generator,” IE P. Minami, ef, a/, “A 1Ghz Portable Digital Delay-Locked Loop with Infinite Phase Capture Range,” 2000 IEEE ISSCC. J. G. Maneatis, ef, af, “Pre Oscillators,” 1993 IEEE ¢ Delay ‘ime Generation Using Coupled SSCC. M. Kokubo, , ah “Spread spectrum Clock Generator for Serial ATA using Fractional PLL. Controlled by AZ Modulator with Level Shifter” 2005 IF ISSCC. P. Lu, 4, ai, “A Low-Jitter Frequency Synthesizer with Dynamic Phase Interpolation for High-Speed Ethernet,” 2000 IEEE ISSCC. T. Matsumoto, “High-Resolution On-Chip Propagation Delay Detector for Measuring Within-Chip and Chip-to-Chip Variation,” 2004 Sympos m on VLSI Circuits Digest of Technique Papers. M. Bazes, , af, “An Interpolating Clock Synthesizer,” IEEE JSSC, vol. 31, no. 9, Sept. 1996. Y. J. Jung, ef, al, “A Dual-loop Delay-Locked Loop Using Multiple E2001 Voltage-Controlled Delay Lines,” TE M. G, Johnson, ¢, a4 “A Variable Delay Line PLL for CPU-Coprocessor Synchronization,” IEEE JSSC, vol. 23, no. 5, Oct, 1988. A. Ghaffari, ef, a/, “A Novel Wide-Range Delay Cell for DLLs,” ICE 2006. M.'T. Hsieh, ¢, af, “Clock and Data Recovei for Spread Spectrum § y with Adaptive Loop Gain B 2005. Des Applications,” I J. M. Chou, ef, af, “Phase Averaging and Interpolation Using Resistor Strings or Resistor Rings for Multi-Phase Clock Generation,” IEI Circuits and Systems-I: Regular Papers, vol. 53, No. 5, May 2006. C. C. Wang, ¢, al, “Clock-and-Data Recovery Design for LVDS ‘Transceiver Used in LCD Panels,” IEEE Tran. Circuits and Systems-II: Express Briefs, vol. No. 11, Nov. 2006. Tran. 152VLSI Modulation Circuits [44] U. Yodprasit, of, af, “Realization of a Low-Voltage and Low-Power Colpitts Quadrature Oscillator,” IEEE Tran. Circuits and Systems-I: Express Briefs, vol. 53, No. 11, Nov. 2006. 153Signal Processing, Data Conver sion, and Pow Management 154VLSI Modulation Circuits CHAPTER 6 VLSI AUTO-ZERO AND CHOPPER STABLIZATION CIRCUITS Static voltage offset and ac noise effects (especially the 1/f noise and thermal drift) ace among the major performance limitations of VSI analog circuits. Various VLSI circuit techniques have been developed to mitigate these effects. A static voltage offset can usually be minimized by using circuit techniques such as by employing symmetric circuit structure, by using matched device layout and by adopting the laser or fuse trimming techniques. On the other hand, the ac ich as noises can usually be minimized employing two major circuit techniques the auto-zero and the chopper stabilization circuit techniques. A VLSI auto-zero circuit is based on the correlative double sampling (CDS) method to cancel out the de offset and the low frequency noises. Alternatively a chopper circuit modulates the static offset and low frequency noise to higher frequency band such that they can be filtered out using a lowpass filter. These circuit techniques can also be combined for better offset and ac noise cancellations.Signal Pro ing, Data Conversion, and Power Management 6.1 VLSI NOISE EFFE( AND COMPENSATION The VLSI circuits suffer from various noise effects such as the de offset, the drifts, the 1/f noise and the white noise as shown in figure 6.1. The typical de offset in a CMOS circuit technology is in the order of 1~10mV that is main] caused by the component mismatch in VLSI circuit. The VLSI circuit offset also depends on the circuit structure, the device size and the circuit operation conditions ‘The drift of the circuit is usually caused by time varying VLSI devices non-idealities such as temperature variation, aging and package stress. VLSI circuits also suffer from the ac noise as such the 1/f noise, white noise, the power supply noise, and the cross-talk noise effects. In VLSI CMOS process technologies, the de offset and the 1/f noise are usually among the dominant noise effects since they are typically a few orders of magnitude higher than that of a circuit fabricated using bipolar technology. DC offset and Drift J dB 1/Enoise 1/fcomer white noise frequency loge Fig.6.1 Typical VLSI circuit noise power spectrum For a VLSI amplifier circuit, the input referred differential noise can typically be modeled as: B= #8 Uy.Ry, +p RI (4) aR + ma 7 PSRR 156VLSI Modulation Circuits ‘These noise effects can be used to calculate the input referred noise by dividing the open-loop gain of the amplifier circuit. The second and the third terms are due to the loading effects of the amplifier to the signal source. The 4% and 5 terms are noise contents due to the common-mode noise and the supply noise effects. ‘The offs difference between input pins of an amplifier that causes the output to be the 1 voltage of a differential amplifier circuit is defined as the voltage same as the plus input pin as shown in figure 6.2. Vv > Ve + Fig.6.2 VLST amplifier input referred noise ‘The sources of the amplifier offset include the device Vir and Ts mismatches of input differential MOS pair and the non-symmetry in the circuit structure. In most VLSI amplifier circuits, the de offset, the drift and the 1/f noise are the major contributors of the circuit noises. The input offset voltage of an amplifier becomes important when a small signal is amplified with a high gain ‘There are a few major static circuit methods to mitigate the VLSI circuit de offset, the drift and the low frequency noise effects such as (a) circuit design optimization practices using symmetric circuit structure (c.g. fully differential izes and careful device physical layout for circuit), (b) the use of large device better device parameter matching and low 1/f noise, and (¢) the trimming based circuit techniques employing the laser trimming or fuse. ch as the auto-zero and the chopper stabiliz ed to minimize both the de and ac noise effects. These dedicated techniques or combination of both -y low (in the nV-level) input offset and such as the temperature drift On the other hand, dynamic circuit techniques tion circuit techniques can be techniques can be used to achieve v s the circuit issues voltage drifts therefore to addre: and the 1/f noise. In addition, such zero-drift amplifiers can offer higher open- 157Signal Processing, Data Conversion, and Power Management loop gain, power-supply rejection, and common-mode rejection than the standard amplifiers. ‘The VLSI amplifiers based on the auto-zero circuit techniques can be used to Such circuits also offer wide bandwidth operation with very low ripple noise (especially at the sampling frequency). However, these amplifiers may have degraded low frequency noise due to the aliasing effect. In addition, they usually have higher power dissipation, achieve very low de oft VLSI amplifiers based on the synchronous chopper circuit technique may offer very low de offset at low power dissipation. However, these amplifiers have narrower bandwidth and higher ripple noise specially at the chopping frequency). ‘The VLSI amplifiers may combine both the auto-zero and the chopper- stabilization circuit techniques to achieve very low de offset through the noise shaped over frequency. Such amplifiers offer the widest operation bandwidth with lower ripple at the chopper frequency. 6.2 VLSI AUTO-ZERO CIRCUITS, VLSI auto-zero circuits are based on the correlative double sampling (CDS) principle that works in two or more clock phases, where the noise signal is first sampled and stored. ‘The sampled noise signal is then subtracted from the sampled signal in the later phase either at the input, the output or at some intermediate nodes of the circuit. As the result, the noise signal can be eliminated from the circuit output. ‘This CDS operation can be used together with the signal amplification operation. An auto-zero amplifier based on such technique corrects the input offset in the similar way. However this sample-and-hold operation turns auto- zero amplifiers into sampled-data circuits, making them prone to aliasing and fold-back effects. At low frequency, the noise changes slowly, so the subtraction of the two consecutive noise samples results in true cancellation. ‘This correlation diminishes at higher frequencies, with subtraction errors causing wideband components to fold back into the baseband. Thus, the auto-zero amplifiers usually have more in-band noise than standard amplifiers. 158VLSI Modulation Circuits 6.2.1. AUTO-ZERO CIRCUIT PRINCIPLE Shown in figure 6.3 is a simple VLSI auto-zero amplifier circuit structure. ‘This circuit works with a noise sampling phase (1 phase) and a noise cancellation phase (2 phase). Vio - +| i alow Fig.6.3 CDS based VLSI auto-zero technique Shown in figure 6.4 is the equivalent circuit of the auto-zeroing phase where Vx is the effective input referred low frequency noises (eg. the de offset and the 1/£ noise) of the amplifier circuit. ‘The parameter A is the gain of the noise free ideal amplifier. In this circuit configuration, the input is connecting to a ground (or reference) and the amplifier input and output terminals are shorted together. c At 2 - {Es oA Loy, | ou $2 ve Wa. To ata 4 /T Fig.6.4 Auto-zeroing circuit ‘The effective noise voltage in this noise sampling phase is sampled and stored in the sampling capacitor as: Von +aT)=-0-1y(nt-+ar) (62) 159VLSI Modulation Circuits [18] [19] [20] (21) (224 ba 25) 26) van Zeijl, P.M; Eikenbroek, } Setty, S; Tangenberg, Js Shipton, G.; Kooistra, E.3 Keekstra, 1; Belot, D5 “A Bluetooth radio in 0.18 um CMOS,” Digest of ‘Technical Papers, 2002 IEEE International Solid-State Circuits Conference, Volume: 1, 2002, Page(s): 86 - 448 vol. ; Vervoort, P.- Meninger, S.E.; Perrott, M.H: "A fractional- N frequency synthesizer architecture utilizi a mismatch compensated PED/DAC structure for reduced quantization-induced phase noise,” IRER. Transactions on Circuits and Systems IT: Analog and Digital Signal Processing, Volume: 50, Issue: 11, 2003, Page(s): 839-849. Bram De Muer; Steyaert, MS.J; "On the analysis of AY fractional-N frequency synthesizers for high-spectral purity.” TEEE ‘Transactions on Circuits and Systems II: Analog and Digital Signal Processing, Volume: 50. Issue: 11, 2003, Page(s): 784-793. See ‘Taur Lee; Sher Jiun Fang; Allstot, DJ; Bellaouar, Ay Fridi, ARs Fontaine, PA; "A quad-band GSM-GPRS transmitter with digital auto- calibration,’ IEEE Journal of Solid-State Circuits, Volume: 39, Issue: 12, 2004, Page(s): 2200-2214. Wilingham, S.; Perrott, M, Setterberg, Bs Grzegorek, A. McFarland, Bs “An integrated 2.5 GHz XA frequency synthesizer with 5 ps settling and 2 Mb/s closed loop modulation,” Digest of ‘Technical Papers 2000 IKI International Solid-State Circuits Conference, 2000, Page(s): 200 - 201, 457. ‘Temporiti, E.; Albasini, G.; Bietti, I.; Castello, R Colombo, M.; "A 700- kHz bandwidth XA fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications,’ IKEE Journal of Solid-State Circuits, Volume: 39, Issue: 9, 2004, Page(s): 1446-1454. “A pipelined noise shaping coder for fractional-N synthesis” IEEE ‘Transactions on Instrumentation and ie: 5, 2001, Page(s): 1154-1161. Measurement, Volume: 50, Iss ‘A 3GHz Fractional-N AlLDigital PLL with Precise Time-to-Digital Converter Calibration and Weltin-Wu, C.; 'Temporiti, E.; Baldi, Ds Svelto, F Mismatch Correction,” Digest of ‘Technical Papers. IEEE International Solid-State Circuits Conference, 2008, Page(s): 344-618.