This article has been accepted for inclusion in a future issue of this journal.

Content is final as presented, with the exception of pagination.

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS 1

Low-Cost, High-Precision DAC Design Based

on Ordered Element Matching
You Li , Member, IEEE, and Degang Chen , Fellow, IEEE

Abstract— Digital-to-analog converter (DAC) is one of the The most important cost in achieving a high-precision DAC
circuits with increasing demands on high-accuracy requirements. is the resistor area on the chip. In general, 1-bit linearity
However, the cost of existing high-precision DACs is high and dif- enhancement leads to quadrupling of the circuit area [5]. Nev-
ficult to reduce because implementation hardly benefits from the
scaling of digital circuits. In this paper, a low-cost, high-precision ertheless, the maximum allowed area is limited by the available
DAC structure based on ordered element matching (OEM) theory die size as growing numbers of circuits and systems are
was proposed and its design methodology is discussed. It achieves integrated into a single chip. Therefore, the implementation of
high matching accuracy by applying the OEM calibration to a high-precision DAC requires high-precision analog processes
the resistors in unary weighted segments and calibrating the with high-precision resistors, such as silicon-chromium thin-
gain error between different segments by small calibration DAC.
A MATLAB behavioral model of a 20-bit R-2R DAC is built, film resistors [2]. Unfortunately, such processes are usually
and the statistical results show that the proposed DAC structure associated with large transistor feature size and do not scale.
can achieve the same accuracy in less than 1/62 resistor area Aside from the resistor area, resistor trimming is often
compared with state of the art. applied to achieve a high-precision DAC, which also demands
Index Terms— High-precision, low-cost, DAC design, linearity. high cost. Popular trimming techniques are divided into two
main categories: laser trimming and fuse trimming [6], [7].
Laser trimming employs laser beams to accurately adjust
I. I NTRODUCTION the resistor parameters at the wafer level, while fuse trim-
ming utilizes a fuse or anti-fuse for opening or closing the
U NTIL now, the performance of digital circuits has been
constantly enhanced by the scaling of device dimensions
and voltage supply. However, the technology advancement
interconnections of a network of resistive elements intended
to minimize mismatch errors. However, trimming techniques
usually require high expenses such as extra layers or more die
does not benefit many analog and mixed-signal circuits, and in
area for trim pads, and the achieved accuracy is reduced by
fact it imposes higher requirements on their performance. The
temperature and aging effects [6].
digital-to-analog converter (DAC) is one of the circuits seeing
High-accuracy calibration circuits are usually employed in
a demand for increased high accuracy in precision medical,
high-precision DACs. They decrease the mismatch errors by
instrumentation, and test and measurement applications [1].
either digital or analog feed-back signals from error-measuring
High-precision 12-bit DACs were once considered to be dif-
circuits, such as a high-resolution high-accuracy analog-to-
ficult to implement; however, 16-bit accuracy is now widely
digital converter (ADC) [8], [9] or DAC [10]–[12]. However,
used in high-precision applications. Recently, even a 20-bit,
the price of implementing those calibration circuits is high.
1-ppm-accurate DAC integrated circuit was proposed to meet
It requires accurate measurement and complicated feedback
the needs of the precision instrumentation market [2].
circuits, which occupy a large silicon area, especially for
Most high-precision DACs rely on accurate resistor arrays
high-precision analog processes whose feature sizes are large.
to perform data conversion tasks, so their accuracy is very
In addition, specific calibration tests, other than the general
sensitive to the matching performance of the resistor networks.
DAC tests, are required to implement the calibration, making
However, the integrated-circuit (IC) fabrication technology
the expense of calibration circuits even higher.
cannot produce perfectly matched resistors, and with the
Dynamic element matching (DEM) is another popular
process scaling, the random mismatch errors increase signifi-
means of implementing a high-precision DAC. It dynamically
cantly [3], [4]. Therefore, implementing a high-precision DAC
changes the positions of mismatched elements at different
is very costly and depends on many different techniques.
times so that the equivalent component at each position is
nearly matched on a time average. Several popular DEM
Manuscript received May 13, 2018; revised August 23, 2018; accepted
September 9, 2018. This work was supported in part by the National Science algorithms are available, such as butterfly randomization [13],
Foundation, in part by Semiconductor Research Corporation, and in part by individual level averaging [14], and data weighted averag-
Texas Instruments, Inc. This paper was recommended by Associate Editor ing [15]. Unlike the static random mismatch compensation
H. Zhang. (Corresponding author: You Li.)
The authors are with the Department of Electrical and Computer Engineer- techniques, DEM translates mismatch errors into noise. How-
ing, Iowa State University, Ames, IA 50011 USA (e-mail: [email protected]; ever, the translated noise is only partially shaped where the
[email protected]). in-band residuals could possibly affect the data converters
Color versions of one or more of the figures in this paper are available
online at http://ieeexplore.ieee.org. signal-to-noise ratio (SNR) [16]. Furthermore, the output will
Digital Object Identifier 10.1109/TCSI.2018.2870665 be inaccurate at one instant of time, since DEM guarantees
1549-8328 © 2018 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See http://www.ieee.org/publications_standards/publications/rights/index.html for more information.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

matching only on average, so that its applications are limited

to sigma delta modulators.
In summary, existing high-precision DACs require a large
die area, high-precision analog processes, advanced resis-
tor trimming techniques, complicated calibration circuits and
additional test costs. As a result, their cost is high and difficult
to reduce, because their implementation benefits very little
from the scaling of digital circuits.
A different approach, called ordered element match-
ing (OEM), was firstly proposed in [5] and [17] and a
15-bit binary-weighed current steering DAC was implemented
in [18] to demonstrate the OEM technique can significantly
reduce random mismatch errors and improve the linearity
performance of DACs. Based on the OEM technique, a
high-precision segmented DAC structure has been introduced
in [19] and has achieved accuracy of about 20-bit from the Fig. 1. OEM process.
MATLAB simulation. Nevertheless, its implementation needs
additional switch circuits to calibrate the gain errors between unary-weighted segment. Component can be a resistance,
different segments, which requires extra circuits area and may conductance or any other amplitude whose random mismatch
cause leakage problems. errors are targeted to be minimized [20], with X AV G as the
In this paper, a low-cost, high-precision DAC structure average amplitude. First, all components are measured and
based on the OEM technique is presented and its design sorted according to their amplitudes. The second step is to
methodology is systematically discussed. It consists of three choose the component with amplitude closest to X AV G . Third,
segments: binary weighted least significant bits (LSB), unary complementary ordered components are paired, which is called
weighted intermediate significant bits (ISB) and most sig- one “folding”. The original 3-bit unary coded component array
nificant bits (MSB). The optimized OEM process [19] is is converted into a 2-bit unary-weighted and 1-bit binary-
applied to the unary weighted ISB and MSB segments. A sub- weighted array. In detail, the amplitude of each 2-bit unary
radix-2 calibration DAC (CalDAC) is implemented to calibrate weighted array is nearly twice of the X AV G , and the random
the gain errors between the ISB and MSB segments. The variations in the components are reduced. Mismatch errors
implementation of CalDAC only requires small area, and consistently diminish after each choosing and folding opera-
avoids the extra switch circuits issues in [19]. On the basis tion. As shown in Fig. 1, if the choosing and single folding
of the proposed structure, a MATLAB behavioral model of a operations are repeated until the 3-bit unary weighted array is
20-bit R-2R DAC is built and the statistical results show that converted into a 3-bit binary weighted array, mismatch errors
the proposed DAC structure can achieve the same accuracy in are further reduced. This process is called “OEM binarization.”
much smaller resistor area compared to state of the art.
This paper is organized as follows. In section II, the pro-
posed high-precision DAC structure based on OEM is intro- B. High-Precision DAC Structure
duced; section III discusses the design of the gain calibration Fig. 2 shows the proposed high-precision DAC structure
pseudo DAC included in the proposed DAC structure; section based on OEM. Although the design requires an external
IV illustrates the OEM calibration process and implementa- feedback resistor that creates noise and endpoint errors [2],
tion; behavioral simulation results are provided in section V, the commonly called current-mode R-2R ladder network DAC
and conclusions are stated in section VI. is selected, for the following reasons. First, the current-mode
structure avoids the resistor non-linearity caused by self-
II. L OW-C OST, H IGH -P RECISION DAC S TRUCTURE heating, which is the dominant contributor to resistor non-
BASED ON O RDERED E LEMENT M ATCHING linearity [21]. In the voltage mode R-2R ladder network,
In this section, a low-cost, high-precision DAC structure different currents flow through different resistors and the cur-
based on OEM is illustrated. First, the OEM technology rents vary with the DAC codes, causing the non-linearity prob-
used to reduce the mismatch error is introduced. Then a lem. In contrast, all resistors in the same segment of the current
segmented high-precision DAC structure is proposed and ana- mode R-2R ladder network have the same current, which do
lyzed. To minimize the gain error between different segments, not change with the DAC codes. Thus, self-heating will not
a gain calibration DAC (CalDAC) is integrated in the proposed cause non-linearity errors in the current-mode structure, saving
DAC structure and its design is discussed. Finally, the process the cost of calibrating the resistor non-linearity that is due
of applying OEM calibration and its implementation in digital to self-heating. The second reason to use the current-mode
circuits are interpreted. structure is to minimize the INL error caused by unequal
resistance in switch pairs. In a voltage-mode structure, pairs of
A. OEM Technology PMOS and NMOS switches are usually used. To minimize the
Fig. 1 shows the process of OEM technology. Each rectangle INL error due to the different on-resistance between PMOS
denotes a component with random mismatch errors in the and NMOS, techniques [2] and [22] are needed, requiring
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LI AND CHEN: LOW-COST, HIGH-PRECISION DAC DESIGN BASED ON OEM 3

rather than resistances of the ISB and MSB segments to

improve their linearity performance.
The proposed DAC structure consists of three segments:
the binary weighted LSB, unary weighted ISB and MSB.
Compared with the traditional two-segment DAC structure [2],
the proposed DAC structure achieves higher linearity perfor-
mance by application of OEM binarization to both the ISB and
MSB segments. A unary weighted array with more than 7 bits
requires digital circuits that are too complicated for OEM bina-
rization to be applied to. OEM binarization cannot be utilized
in binary weighted array, and the LSB segment accomplishes
its targeted accuracy through the resistor’s intrinsic matching.
For a 16 ∼ 20 bit high-precision two-segment DAC structure,
the intrinsic matching of the resistors in the binary weighted
LSB should be above the 9 to 13 bit level, assuming the MSB
segment is 7-bit and calibrated by OEM binarization. However,
Fig. 2. Proposed OEM based high-precision DAC structure. resistors with a 9 to 13 bit matching level require large
areas if high-precision analog processes are not being used.
Thus another unary weighted ISB segment is needed in high-
high-performance amplifiers and other circuitry on the chip precision DAC design. By applying OEM binarization to both
for high-precision DACs. However, the current-mode structure the ISB and MSB segments, the matching level of resistors in
uses pairs of NMOS switches, whose on-resistance difference the two segments can be significantly improved [19]. More-
can be minimized by using common-centroid layout tech- over, the requirement of intrinsic matching level of resistors in
niques and reasonable switch areas. As a result, the current- the LSB segment is greatly relaxed, thereby reducing the area
mode structure is preferable for a low-cost, high-precision of LSB resistors. For example, a 20-bit DAC with 5-bit ISB
DAC design. Endpoint errors associated with the external and 7-bit MSB requires only about 8-bit matching resistors in
feedback resistor can be minimized by using high-accuracy the LSB segment, which significantly decreases the area of the
feedback resistors. Assuming the high-precision DACs are LSB segment and the total area of the DAC. However, adding
mostly used in pseudo DC applications, the noise problem the ISB segment into the DAC produces a gain error problem
caused by the feedback resistor in the external current-to- between the ISB and MSB segments, which can be minimized
voltage converter [23] (not shown in Fig. 2) is negligi- by a gain calibration method discussed in the next section.
ble, since the bandwidths of high-precision DACs are nar-
row. Furthermore, the output impedance of the current-mode C. Segmentation Choices
R-2R DAC changes with the code, which causing the variation
of the offset/noise of the amplifier in the external current-to- For proposed DAC structures, the segmentation choice
voltage converter. However, by using high-gain and low-offset should be carefully taken into consideration. First, resistors
amplifiers, the resultant non-linearity errors can be minimized. in different segments do not have the same effect in DAC
To meet the linearity target of DACs, the area requirements linearity performance. In INL, the contribution of LSB resistor
of resistors are often calculated by the resistors matching level, non-linearity could be approximated as,1
as shown in the following subsection. The matching level of I N L (R L S B ) ≈ 2nlsb × σ R L S B , (2)
the resistance of a resistor is the same as its corresponding
conductance, as shown in where σ R L S B is the standard deviation of the LSB resistor
(2R in the Fig. 2, and R is the parallel of two 2R) random
1 −R G R
G= ⇒ G = 2
⇒ =− , (1) mismatch error, and nlsb is the number of LSB segment bits.
R R G R Although the current-mode structure is applied in the design,
where resistance R is the resistance of a resistor and G is the variation of the output current depends mainly on the
its corresponding conductance. Yet, the mismatching level of difference between resistors.
resistors is easily found in a process design manual instead The contribution of the ISB and MSB resistors non-linearity
of their corresponding conductance mismatching level. As a could also be separately estimated as [24], [25],
result, resistors in the ISB and MSB segments are marked
I N L (R I S B ) ≈ 2nlsb+nisb/2+0.5 × σ R I S B , (3)
R I S B and R M S B in Fig. 2. However, because the proposed
nlsb+nisb+nmsb/2+0.5
DAC is a current output DAC, its linearity performance is I N L (R M S B ) ≈ 2 × σ RM S B , (4)
determined by the output current relationship with the DAC where σ R I S B is the standard deviation of the ISB resistor
input codes. In the unary weighted segments, the resulting out- random mismatch error, σ R M S B is the standard deviation of
put current of each resistor is determined by its conductance. the MSB resistor random mismatch error, ni sb is the number
For instance, the output current generated by the i th MSB of ISB bits and nmsb is the number of MSB bits.
resistor is Iout (i) = V R E F /R M S B(i) = V R E F × G M S B(i). As a
result, OEM binarization should be applied to conductances 1 Detailed explanations of (2)-(6) were shown in the Appendix.
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

TABLE I manual or simulation. Then, the area of the switch (A S W M S B ,

OEM R EDUCTION FACTOR A S W I S B and A S W L S B ) and the digital circuit ( A Digit al ) can
be roughly estimated by design. With different segmentation,
the effort to implement OEM calibration are changed, e.g.,
different mux circuits and memory cells as illustrated in
section IV-B, and the complexity for signal routing, etc.
By changing different segmentations, the total required area
can be estimated from calculations of (8). The segmentation
After applying the OEM process as described in section
should be chosen based on minimizing the total area and the
II, the resultant INL caused by random mismatch errors in
design effort, and decided by specific design requirements.
ISB/MSB segments is modeled as,
Another important consideration for segmentation is power
I N L (R I S B ) ≈ 2nlsb+nisb/2+0.5−X 1 × σ R I S B , (5) consumption. The power consumption of a DAC is,
I N L (R M S B ) ≈2 nlsb+nisb+nmsb/2+0.5−X 2
× σ RM S B , (6) P = Vre
2
f /Rt ot al , (9)
where X1 and X2 are called OEM INL reduction factors. For where the Rt ot al = Rmsb /2nmsb is the total impedance of the
the MSB segment, an outlier elimination technique is used DAC. Thus, the unit resistor value and number of bits in MSB
to further improve the matching performance [5], and about segment are limited by power consumption. In most general
20% being the best percentage of outlier number. The OEM analog processes, resistors with higher matching performance
INL reduction factors vary with process and resistor areas, usually have lower resistance density. Large Rt ot al needed to
but their approximate values can be obtained from statistical reduce power consumption, causing large area requirements
simulations and are shown in TABLE I. for resistors with high matching performance but low resis-
The required area of resistors is estimated from the standard tance density. On the other hand, with one more bit in the MSB
deviation of their mismatch error, segment, required resistance of the MSB resistor doubles for
σu 2 the same power consumption. Therefore, the number of bits in
Areq = Au ( ) , (7)
σreq MSB segment should be carefully selected, not only from the
where σu is the standard deviation of unit resistor, σreq is the matching level to achieve, but also from power consumption
required standard deviation of the mismatch errors, and Au limitations.
is the area of unit resistor. From equations (2) (5) (6) (7),
the total area can be estimated as following,2 III. G AIN C ALIBRATION P SEUDO DAC D ESIGN
σu A. Gain Error Between Different Segments
At ot al ≈ (Au ( )2
log2 (I N L M S B /2 nlsb+nisb+nmsb/2+0.5−X 2) Aside from mismatch errors in each segment, an important
+ A Digit al + A S W M S B ) × (2nmsb − 1) × 1.2 non-linearity error in the segmented DAC is the gain error
σu between different segments. For example, in an ideal matched
+ (Au ( )2 three-segment DAC, the following relation exists between the
log2 (I N L I S B /2 nlsb+nisb/2+0.5−X 1)
ISB and MSB segments:
+ A Digit al + A S W I S B ) × (2nisb − 1)
σu Vre f G I L S B (2 N−nmsb ) = Vre f G M S B (1), (10)
+ (Au ( )2 + A S W L S B )
log2 (I N L L S B /2nlsb ) where N is the total bits of the DAC, G M S B (1) =
×(3nlsb + 1), (8) (R M S B(1))−1 is the conductance of the lowest bit of MSB
where A Digit al is the OEM digital circuit for each resistor segment, and G I L S B (2 N−Nmsb ) is the total conductance of
(illustrated in section IV), A S W M S B , A S W I S B and A S W L S B are the LSB and ISB segments. The gain error between the
the single switch areas for the MSB, ISB and LSB segments, ISB segment and the MSB segment from (10) generates the
respectively. following output current:
From TABLE I, the X1 and X2 increase with the number IGain = Vre f (G I L S B (2 N−nmsb ) − G M S B (1)) = Vre f G.
of bits, so more unary weighted bits (more bits in the ISB and
(11)
MSB segments) the linearity performance further improves.
Therefore, more unary weighted bits decreases more of the Since the lowest bit of MSB stands for LSB of the 2 N−nmsb
area of resistors. However, with more unary-weighted bits, whole DAC, the following equation is required to make the
more digital circuits are required to implement OEM. Thus total INL error less than 1 LSB:
a trade-off exists between the digital circuits and the resistor I M S B (1)
area when segmentation should be performed based on the |IGain | < N−nmsb . (12)
2
specific design. Similar analysis is applied to the gain error between the ISB
Firstly, the standard deviation of unit resistor (σu ) and the and LSB segments, and the required gain error is:
area of the unit resistor can be obtained from process design

|IGain | = |Vre f (G L S B (2nlsb ) − G I S B (1))|
2 Here, the area of bridge resistors R
B R1 , R B R2 ,R B R3 , and the CalDAC I I S B (1) I I S B (1)
are ignored. The reason is that their area are very small compared with the < = N−nmsb−nisb . (13)
resistors array, which will be illustrated in following section. 2nlsb 2
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LI AND CHEN: LOW-COST, HIGH-PRECISION DAC DESIGN BASED ON OEM 5

where G I S B (1) = (R I S B(1))−1 is the conductance of the

lowest bit of ISB segment, and G L S B (2nlsb ) is the total
conductance of the LSB segment.
Compared with (12) and (13), the accuracy requirement of
the gain between ISB and MSB segments is much more higher
than the gain between ISB and LSB segments.
In the structure proposed in [19], gain calibration is achieved
by changing different bridge resistors, and both the gain
error between the LSB and ISB segments and the gain error
between ISB and MSB segments are calibrated. Nevertheless, Fig. 3. Simplified CalDAC structure.
its implementation needs additional switch circuits to calibrate
the gain errors between different segments, causing additional
circuit area and potential leakage problems. As a result, the input of the external current-to-voltage converter [23]),
in the proposed DAC structure shown in Fig. 2, no additional ni sb is the bits of the ISB segment, G cal is the conductance
switches in the unary weighted segments to calibrate the gain of the CalDAC, and R M S B(1) is the lowest bit resistance of
errors between different segments are used. Instead, the gain the MSB segment. In this structure,
error between LSB and ISB is minimized by appropriately R I L S B (2 N−nmsb )
assigning the area of the bridge resistor R B R1 and resistors in
= R B R3 G cal (2−nisb Rav I S B
the ISB segment, and a calibration pseudo DAC (CalDAC) is
inserted between the ISB and MSB segments for calibrating + R B R2 ) + 2−nisb Rav I S B + R B R2 + R B R3
the gain errors. = R B R3 G cal (2−nisb Rav I S B + R B R2 ) + RT . (17)
where RT = 2−nisb Rav I S B + R B R2 + R B R3 . By setting
B. Gain Calibration DAC
The results of (11) and (12) are R I L S B (2 N−nmsb )|nom
G M S B (1) = R B R3 G cal |nom (2−nisb Rav I S B + R B R2 ) + RT
|G| = |G I L S B (2 N−nmsb ) − G M S B (1)| < , (14)
2 N−nmsb = R M S B(1)|nom , (18)
creating,
where G cal |nom is the nominal value of the G cal , and
1 R M S B (1)|nom is the nominal value of R M S B (1). We can make
G M S B (1)(1 − )
2 N−nmsb RT < R M S B(1), then the gain error can be reduced to our
< G I L S B (2 N−nmsb ) required accuracy by tuning G cal to minimize R.
1 Assuming the standard deviation of R M S B (1) variation is
< G M S B (1)(1 + )
2 N−nmsb σ R M S B (1), the largest variation of R M S B (1) can be estimated
1 as 3σ R M S B (1) = R S . With assignment of an area similar to
⇒− R M S B(1)
2 N−nmsb +1 R M S B (1), the largest variation of R B R2 + R B R3 is the same as
< R I L S B (2 N−nmsb ) − R M S B (1) R S . Since the variation of RT in the proposed structure is
1 mainly determined by the variation of R B R2 +R B R3 , the largest
< N−nmsb R M S B (1), (15) variation of RT also approximates R S . The calibration range
2 −1
of CalDAC is analyzed as shown in Fig.4. Meeting the
where R I L S B (2 N−nmsb ) = (G I L S B (2 N−nmsb ))−1 and condition RT < R M S B(1) requires that
R M S B (1) = (G M S B (1))−1 .
Assuming 2 N−nmsb >> 1, (15) is simplified to R M S B (1)|nom − RT |nom ≥ 2R S . (19)
|R I L S B (2 N−nmsb ) − R M S B (1)| = |R| where RT |nom is the nominal value of RT . Condi-
1 tions (16) and (19) require the tuning range of G C AL to
< R M S B (1). (16)
2 N−nmsb calibrate the range
From (16), the gain error is reduced to meet the DAC
RC AL ≥ 4R S . (20)
accuracy requirement if |R| is calibrated to the required
level. However, since N − nmsb = nlsb + ni sb is large, Together with (18) and (17), the calibration range for the
it requires quite large area of MSB resistors and the bridge proposed CalDAC structure is:
resistors between ISB and MSB segments to minimize the gain
4R S
error. Therefore, a gain calibration DAC (CalDAC) is needed G C AL ≥ . (21)
to calibrate the gain errors between ISB and MSB segment. R B R3 (2−nisb Rav I S B + R B R2 )
Fig. 3 shows the simplified structure of the proposed pseudo From (21), the calibration range G C AL can be changed by
calibration DAC structures. In the simplified pseudo calibra- choosing different ratios between R B R3 and R B R2 , so it results
tion DAC structure, shown in Fig. 3, Rav I S B is the average in a flexible CalDAC design.
value of all the resistors and switch on-resistances in the ISB In addition to the calibration range, the calibration step of
and LSB segments connecting to the Iout (virtual ground, the CalDAC, i.e., the bits of CalDAC, should also be taken into
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

Fig. 5. CalDAC implemented as a sub-radix-2 DAC.

Fig. 4. CalDAC range.

R S = 2nlsb+1
1
R I S B(1)|nom , the accuracy requirement of the
R B R1 is only
consideration. Assuming R S = 2 1Nk R M S B (1), to meet (16),
1
requires the number of codes in the CalDAC RT < R I S B(1)|nom . (27)
2nlsb+1
4R S
NG ≥ = 2 N−nmsb−Nk , (22) (27) can be achieved by simply assigning the similar area
1
R
2 N−nmsb M S B
(1) of R I S B(1) to R B R1 . Therefore, the gain error between the
ISB and LSB segments can be minimized by appropriately
and thus requires at least N − nmsb − Nk bits CalDAC to
assigning area for resistors in the ISB segment and the R B R1 .
calibrate the gain error to the expected accuracy. In practice,
extra bits should be added to compensate for the resistor
tolerance and variations of processes and temperature. C. Implementation of Gain Calibration
For the gain error between ISB and LSB segments, it can be In previous sub-section, gain calibration was discussed;
analyzed as following. Similar to (16), the gain error between however, its implementation needs to be further investigated.
ISB and LSB should meet the following accuracy requirement, From (21) and (22), the required calibration range and number
1 of bits can be calculated, respectively. However, there is no
|R L S B (2nlsb ) − R I S B (1)| < R I S B (1), (23) linearity requirement for the CalDAC, because it works as
2nlsb
a pseudo DAC and its input code is fixed after the best
where R L S B (2nlsb ) = (G L S B (2nlsb ))−1 and R I S B (1) = gain calibration. Thus, a sufficiently large calibration range
(G I S B (1))−1 . We also have with enough number of calibration steps are enough for
implementation the required CalDAC. The most efficient way
R L S B (2nlsb ) = R L S B (total) + R B R1 , (24)
to implement the CalDAC is to employ the sub-radix-2 DAC,
where R L S B (total) is the total resistance of the LSB seg- as shown in Fig. 5. The output of the CalDAC is connected
ment when all its resistors switch to the Iout . The value of to node V B R , as shown in Fig. 2.
R L S B (total) is about one R in the Fig. 2, and can be regarded In CalDAC, each branch has a resistor and a switch. By con-
as approximate the average of resistance of each bit in the LSB necting the switch to ground (Gnd), the corresponding bit
segment, so its variation can be assumed much smaller than contributes a conductance G n = R1n . The ratio of the resistors
the R B R1. between adjacent bits is αn < 2, e.g. R2 = α1 R1 . The ratio
It can be set that αn between different bits is determined by the variations of
resistance, as shown in Fig. 6. To make the ratio between
R L S B (2nlsb )|nom = R I S B(1)|nom , (25) adjacent bits less than two, the following relationship can be
used:
where R L S B (2nlsb )|nom is the nominal value of the
R L S B (2nlsb ), and R I S B (1)|nom is the nominal value of αn−1 Rn−1 + 3σn < 2 × (Rn−1 − 3σn−1 )
R I S B (1). ⇒ αn−1 < 2 − (3σn +6σn−1 )/Rn−1 , (28)
Assuming the largest variation of R M S B (1) and R B R1 can be
estimated as R S and RT , respectively, and the variation of where Rn−1 is resistance of n − 1 bit of CalDAC, αn−1
the R L S B (2nlsb ) is dominated by R B R1 , the accuracy require- is the resistance between Rn and Rn−1 , σn and σn−1 are
ment of the RT can be estimated as following from (23), the standard deviation of resistance of n and n − 1 bits of
CalDAC, and assuming their largest vairaiton are 3σn and
1
RT < (R I S B(1)|nom − (2nlsb − 1)R S ) 3σn−1 , respectively.
2nlsb The gain calibration process is shown in Fig. 7. All the
1
≈ R I S B(1)|nom − R S . (26) LSB and ISB resistors are connected to Iout and MSB
2nlsb resistors to Gnd. The CalDAC codes are swept from the
Since nlsb is often a small number, it only requires small area smallest to the largest, and the total conductances of LSB
to implement R S < 2nlsb
1
R I S B(1)|nom . For example, choosing and ISB segments for each CalDAC code i are obtained as
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LI AND CHEN: LOW-COST, HIGH-PRECISION DAC DESIGN BASED ON OEM 7

TABLE II
A REA OF A 9-bit C AL DAC

extremely low resistance is assigning the area of each bit

as following. The resistance of bit (ncsb + 1)/2 + 1 should
Fig. 6. CalDAC ratio.
be α R(ncsb+1)/2 , which can be implemented by combing two
α R(ncsb+1)/2 /2 resistors series. Similarly, bit (ncsb + 1)/2 + 2
is composed of four α 2 R(ncsb+1)/2/4 resistors series, etc. The
resistance of bit (ncsb + 1)/2 − 1 is implemented as two
2 R(ncsb+1)/2/α resistors in parallel, and bit (ncsb + 1)/2 − 2
implemented as four 4 R(ncsb+1)/2/α 2 resistors in parallel. For
example, the resistor and area ratio between different bits in a
9-bit CalDAC is summarized in TABLE II. From (30), the total
area of the CalDAC is calculated as
1 − α5 4(α 4 − 256) α (ncsb+1)/2
At ot al = [ + ] . (31)
1−α α 5 − 4α 4 G C AL R
Assuming α = 1.8, ncsb = 9, and G C AL = 0.1 m S
by changing the ratio between R B R2 and R B R3 from (21),
the At ot al is about 1.226E7/R. Since CalDAC is a sub-
radix-2 DAC, the resistors with high resistance density but low
matching performance can be used. For example, the R of
poly resistor is 1000 ∼ 2000/ in a general analog process,
Fig. 7. The gain calibration process.
so the At ot al for a 9-bit CalDAC is only 6130 ∼ 12260 R.
For comparison, a 7-bit MSB segment was built to implement
G I L S B (2 N−nmsb )C ALcode(i) . The best CalDAC code which has
a 20-bit DAC, and the matching level of the unit resistor in
the minimal value of |G I L S B (2 N−nmsb )C ALcode(i) − G M S B (1)|
MSB segment was 11-bit. Its resistor area can be estimated
among the different CalDAC codes, is selected. Therefore,
as:
the gain error can be calibrated by the CalDAC.
The gain calibration range (G C AL ) of the CalDAC is 2−5 2
Ar ea = (27 − 1)A5−bit ( ) ≈ 219 A5−bit , (32)
determined by (21). Assuming that R S , 2−nisb Rav I S B are 2−11
defined from the segmentation choice, G C AL is modified by where A5−bit is the resistor area to achieve 5-bit matching
changing the R B R2 and R B R3 . The number of bits for CalDAC level. We can assume the A5−bit is the same as the area of
(ncsb) is determined by (22). On this basis, the area of the one R of poly resistor, which is often an underestimate in
CalDAC is analyzed as the following: analog processes without high-precision resistors. Even with
Without loss of generosity, we assume ncsb is a odd such conservative estimation, the resistor area of the CalDAC
number, and the middle bit of the CalDAC is bit (ncsb +1)/2. is only about 1 ∼ 2 percents of the MSB resistor array, which
To simplify the analysis, resistance ratios between adjacent is small enough to be regarded as negligible compared with
bits αi are the same and equal to α. Since CalDAC works as the area of the resistor array in the DAC.
a pseudo DAC and there is no linearity requirement for the
CalDAC, all resistors in the CalDAC can have the minimum
IV. OEM C ALIBRATION
width. As a result, the area of each bit depends on resistance
density R, G C AL and ncsb. For example, the resistance of A. OEM Calibration
the middle bit is OEM calibration is applied to the resistances of the ISB
α (ncsb+1)/2 and MSB segments in [19]. The calibration can be made more
R(ncsb+1)/2 = , (29) accurate by applying OEM calibration to the conductances of
G C AL
the ISB and MSB segments, because the proposed structure
so its area requirement is calculated as is that of a current output DAC. Moreover, since the CalDAC
is employed to calibrate the gain error, the OEM calibration
α (ncsb+1)/2
A(ncsb+1)/2 = . (30) applied to the proposed DAC after fabrication is greatly
G C AL R simplified by following the steps shown in Fig.8.
Since the resistance ratio between the highest and lowest bits Step 1 applies OEM binarization to the MSB segment.
is 2ncsb−1 , one way to optimize the CALDAC area and avoid In this step, all resistors in LSB and ISB segments are
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

TABLE III
D IGITAL C ODING FOR OEM B INARIZATION (7-bit)

Fig. 9. OEM calibration circuits.

from the standard INL test results. After OEM binarization,

each element in the unary-weighted segment is assigned to a
specific “address code”, which is recorded in the memories
cells illustrated in the following sub-section.

B. Digital Circuits to Implement OEM Calibration

Fig. 8. OEM calibration process (a) apply OEM binarization to MSB To implement OEM binarization, each resistor in a N-bit
segment, (b) apply OEM binarization to ISB segment.
unary weighted segment needs to be connected to one of the
N-bit lines. This requires an N-to-1 digital mux and a log2 N
switched to Gnd and all switches in the CalDAC are opened. bit number of memories cells to store the mux address code
Resistors in the MSB segment are sequentially switched to for each element, similar to [18].
Iout , and the corresponding values of conductance G M S B(i) = The calibration circuit for a 7-bit unary weighted segment is
1/R M S B(i) are obtained one by one. From the measurement shown in Fig.9, where the OEM binarization is realized by the
results of G M S B(i), OEM binarization can be applied to 3-bit memory cells and 7-bit muxes. The memory cells, which
MSB conductances. are arranged as serial-in parallel-out connections, can be either
Step 2 is similar to Step 1 but applies the OEM binarization registers or one time programming (OTP) cells, depending
to the ISB segment. In this step, all resistors in LSB and MSB on the application. TABLE III illustrates the corresponding
segments are switched to Gnd and all switches in the CalDAC address code and number of elements for different bit lines
are opened. Resistors in the ISB segment are sequentially during the normal conversion phase. A 7-bit unary weighted
switched to Iout , and the corresponding conductance values segment has 127 components in total, and it can be converted
G I S B(i) = 1/R I S B(i) are obtained one by one. OEM binariza- into a 7-bit binary weighted array by assigning different
tion is then applied to the ISB conductances. number of components to different binary bits. For example,
It worth mentioning the required supporting instruments if the address code “010” is assigned to two resistors, D[1] will
to implement the OEM calibration. The OEM measurement be selected to control them. With these arrangements, the 7-bit
only relies on the standard instruments to test the linearity unary weighted segment operates in a binary weighted manner.
performance of the DAC. The instruments to measure the
linearity of a DAC in the standard INL/DNL test, can be V. B EHAVIORAL S IMULATION R ESULTS
used to implement its OEM and gain calibration. Based on A MATLAB model of a 20-bit R-2R DAC with
the OEM measurement results, the sorting and choosing can 8-5-7 segmentation was built on the basis of the proposed
be implemented by simple test program or circuits. In [26], structure to verify its matching performance. We chose
it even provides one method to implement the sorting only Rmsb = 2Rmid , Rlsb = Rmid and the same width for all
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LI AND CHEN: LOW-COST, HIGH-PRECISION DAC DESIGN BASED ON OEM 9

Fig. 10. (a) INL plot of the original 13-bit LSB and ISB segments; (b) DNL
plot of the original 13-bit LSB and ISB segments. Fig. 12. (a) INL plot of the 20-bit DAC after adding MSB segment without
gain error; (b) DNL plot of the 20-bit DAC after adding MSB segment without
gain error.

Fig. 11. (a) INL plot of the 13-bit LSB and ISB segments after applying
OEM binarization to ISB segment; (b) DNL plot of the 13-bit LSB and ISB
segments after applying OEM binarization to ISB segment. Fig. 13. (a) INL plot of the 20-bit DAC after applying OEM binarization
to MSB segment without gain error; (b) DNL plot of the 20-bit DAC after
applying OEM binarization to MSB segment without gain error.
resistors. To compare the model with state of the art models,
the R-2R DAC model in [2] was also included, because it is
the first and only one existing 20-bit R-2R DAC reported in the
literature. It has a two-segment structure with 14-6 segments
and could correct up to ±16 LSBs of INL by CALDAC.
First, the unit L S B in n bit level (L S Bn ) was defined as

L S Bn = F S/2n (33)

where F S is the full scale of the DAC. If the matching level

is the n bit, the standard deviation of the mismatch error
Fig. 14. (a) INL plot of the 20-bit DAC after applying OEM binarization to
σ ≈ 1/2n . MSB segment with positive gain error; (b) DNL plot of the 20-bit DAC after
Fig. 10 shows the INL and DNL of a 13 bit DAC, which applying OEM binarization to MSB segment with positive gain error.
consists of only the 8 bit LSB and 5 bit ISB segments. The
intrinsic matching level of the unit resistors in the ISB segment However, there is another important source of nonlinearity
is about 8 bit, and the unit 2R resistor in the LSB segment has error: the gain error between the ISB and MSB segments.
about 8 bit matching accuracy. As shown in Fig. 10, the INL In this model, the bridge resistor R B R2 and R B R3 was matched
of the 13 bit DAC is about 1.2 L S B and the DNL is 1.1 L S B. to the 11 bit level. Without CalDAC, there were two types
It should be noted the LSB used here is in the 13 bit level. of gain error. The first is G I L S B (2 N−nmsb ) < G M S B (1) and
After OEM binarization is applied to the ISB segment, the INL is called the positive gain error, as shown in Fig. 14. The
was improved to about 0.18 L S B and the DNL improved to negative gain error is that with G I L S B (2 N−nmsb ) > G M S B (1).
about 0.19 L S B, as shown in Fig. 11. If positive gain error existed, the INL and DNL plot after
To implement a 20-bit DAC, a 7-bit MSB segment was OEM binarization is applied to the MSB segment is shown
added, and the matching level of the unit resistor in MSB in Fig. 14, and results for a negative gain error case are shown
segment was 11 bit. If there was no gain error between the in Fig. 15. In both cases, the gain error dominated the INL
ISB and MSB segments, the linearity performance of the and DNL errors. A 9-bit CalDAC was modeled, and after the
20-bit DAC was dominated by the matching performance of gain calibration is applied to the gain error shown in Fig. 15,
the MSB segment. As shown in Fig. 12, the INL of the the INL and DNL plots are as shown in Fig. 16. After gain
20-bit DAC was about 45 L S B and DNL was 7 L S B. After calibration, the INL dropped from about 14.9 L S B to 0.22
applying OEM binarization to the MSB segment, the INL L S B and the DNL was reduced from 12.9 L S B to 0.21 L S B.
decreased to a 0.45 L S B and the DNL decreased to 0.46 L S B, Fig.17 shows DNL and INL distributions of 1,000 randomly
as shown in Fig. 13. Results showed OEM binarization generated 20-bit DACs with the proposed structure, with a
significantly reduced the mismatch error and improved standard deviation σ Rmsb = 4.7E − 4. After OEM operation,
linearity performance. the DNL was reduced from 43.3 L S B to 0.75 L S B and
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS–I: REGULAR PAPERS

significantly improved linearity performance and decreased the

total resistor area.
VI. C ONCLUSION
Existing high-precision DACs require large die areas, high-
precision analog processes, advanced resistor trimming tech-
niques, complicated calibration circuits and additional test
costs. As a result, costs are high and difficult to reduce because
implementation benefits very little from the scaling of digital
Fig. 15. (a) INL plot of the 20-bit DAC after applying OEM binarization circuits.
to MSB segment with negative gain error; (b) DNL plot of the 20-bit DAC In this paper, a low-cost, high-precision DAC structure
after applying OEM binarization to MSB segment with negative gain error.
based on OEM theory was proposed and its design methodol-
ogy discussed. It achieves high matching accuracy by applying
OEM calibration to the resistors in unary weighted segments
and calibrating the gain error between different segments by
small calibration DAC (CalDAC). A MATLAB behavioral
model was created, and the simulation results show that the
proposed DAC structure can achieve the same accuracy as
that of state-of-the-art model, in a much smaller resistor area.
Moreover, with the scaling of digital devices, its advantage
could be constantly enhanced.
A PPENDIX
Fig. 16. (a) INL plot of the 20-bit DAC after gain calibration; (b) DNL plot
of the 20-bit DAC after gain calibration. P ROOF OF THE E QUATIONS IN S ECTION II-C
The INL calculation of binary-weighted or unary-weighted
DAC was proved in [24] and [25].
σ I N L ≈ 2nbit /2−1 × σ Runit , (34)
where σ I N L is the standard deviation of the INL error of
the DAC, and σ Runit is the standard deviation of the unit
resistor random mismatch error, and nbi t is the number of
bits. However, the 3-sigma variation is more often to be used
in practical circuit design and 21.5 ≈ 3, so we have
I N L ≈ 2nbit /2+0.5 × σ Runit . (35)
The assumption of the equation (35) is based on the
independence of each bit in the binary-weighted or unary-
weighted DAC, i.e., the output of every bit is only decided
by one or a group of unit resistors. However, the output of
Fig. 17. DNL and INL distribution comparison of 1,000 randomly generated
resistor arrays in 20-bit R-2R DAC with σ Rmsb = 4.7e − 4. each bit in the R-2R DAC (the LSB segment shown in the
Fig. 2) is determined by the variations of all the resistors
TABLE IV in the R-2R DAC [27]. Therefore, it is too complicated to
S IMULATION R ESULTS OF R ESISTOR A REA C OMPARISON derive a equation to calculate the INL of R-2R DAC by
mathematics. However, an approximate equation (2) can be
obtained by statistical simulations. A model of the current-
mode R-2R DAC was built in the MATLAB. The compari-
son between 1000 MATLAB simulation results (approximate
INL decreased from 69.9 L S B to 0.59 L S B! Results showed 3-sigma INL) with the estimation by equation (2) is shown
that the linearity performance improvement of the proposed in Fig. 18. It simulated with different sigma (σ R L S B ) and
structure is much higher than that of [2]. different number of bits (nlsb), and compare the maximum
The resistor area requirement of two types of 20-bit INL in 1000 MATLAB simulation results with the estimation
R-2R DAC are compared in Table.IV. Yield estimations by the of equation (2). It shows the equation (2) can be used as a
Monte Carlo simulation showed the required resistors standard rough estimation for the INL of the R-2R DAC (the LSB
deviation of each type of DAC model. The area calculation was segment in the Fig. 2)).
based on assuming σ 2 = Areak
and k = 1e−4. To achieve yield Since each unit resistor in the ISB segment stands for 2nlsb
> 99.7% with INL < 1 L S B, TABLE IV shows the required LSB of the whole DAC, it gets the equations (3) from (35).
total resistor area of the proposed DAC is less than 1/62 of Similarly, each unit resistor in the MSB segments stands for
DAC calibrated by CALDAC in [2]. Thus the proposed DAC 2nlsb+nisb LSB, it gets the (4). The OEM INL reduction factors
 This article has been accepted for inclusion in a future issue of this journal. Content is final as presented, with the exception of pagination.

LI AND CHEN: LOW-COST, HIGH-PRECISION DAC DESIGN BASED ON OEM 11

[17] T. Zeng and D. Chen, “New calibration technique for current-steering

DACs,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS), May/Jun. 2010,
pp. 573–576.
[18] T. Zeng, K. Townsend, J. Duan, and D. Chen, “A 15-bit binary-weighted
current-steering DAC with ordered element matching,” in Proc. IEEE
Custom Integr. Circuits Conf. (CICC), Sep. 2013, pp. 1–4.
[19] Y. Li and D. Chen, “A novel 20-bit R-2R DAC structure based on ordered
element matching,” in Proc. IEEE Int. Symp. Circuits Syst. (ISCAS),
May 2015, pp. 1030–1033.
[20] H. Van de Vel et al., “11.7 A 240mW 16b 3.2GS/s DAC in 65nm CMOS
with <-80dBc IM3 up to 600MHz,” in IEEE ISSCC Dig. Tech. Papers.,
Feb. 2014, pp. 206–207.
[21] P. Steinmann et al., “Simple analytical model of the thermal resistance
of resistors in integrated circuits,” IEEE Trans. Electron Devices, vol. 57,
no. 5, pp. 1029–1036, May 2010.
[22] R. A. Meaney and R. J. Speer, “Voltage-switching d/a converter using
Fig. 18. INL comparison between the 1000 MATLAB simulation results and p- and n-channel MOSFETs,” U.S. Patent 5 075 677 A, Dec. 24, 1991.
the estimation of equation (2). [23] W. A. Kester, Data Conversion Handbook. New York, NY, USA:
Newnes, 2005, pp. 418–420.
[24] C.-H. Lin and K. Bult, “A 10-b, 500-MSample/s CMOS DAC in 0.6
in TABLE I are obtained from statistical simulations. From mm2 ,” IEEE J. Solid-State Circuits, vol. 33, no. 12, pp. 1948–1958,
those INL reduction factors, we can have equations (5) and (6). Dec. 1998.
[25] H. Khorramabadi. UC Berkeley EECS 247 Analog-Digital Interface Inte-
ACKNOWLEDGMENT grated Circuits. Accessed: Jun. 2, 2018. [Online]. Available: http://www-
inst.eecs.berkeley.edu/~ee247/fa08/files07/lectures/L14_2_f08.pdf
Any opinions, findings, and conclusions or recommenda- [26] Y. Li, T. Zeng, and D. Chen, “A high resolution and high accuracy
tions expressed in this paper are those of the authors and do R-2R DAC based on ordered element matching,” in Proc. IEEE Int.
not necessarily reflect the views of the sponsors. Symp. Circuits Syst. (ISCAS), May 2013, pp. 1974–1977.
[27] D. Marche and Y. Savaria, “Modeling R −2R segmented-ladder DACs,”
R EFERENCES IEEE Trans. Circuits Syst. I, Reg. Papers, vol. 57, no. 1, pp. 31–43,
Jan. 2010.
[1] M. Egan, “The 20-bit DAC is the easiest part of a 1-ppm-accurate
precision voltage source,” Analog Dialogue, vol. 44, no. 4, p. 1, 2010. You Li (S’12–M’18) received the B.S. degree
[2] R. C. McLachlan, A. Gillespie, M. C. Coln, D. Chisholm, √and in electrical engineering from Xiangtan University,
D. T. Lee, “A 20b clockless DAC with sub-ppm INL, 7.5 nV/ Hz Hunan, China, in 2004, the M.S. degree in electri-
noise and 0.05 ppm/°C stability,” IEEE J. Solid-State Circuits, vol. 48, cal engineering from Tsinghua University, Beijing,
no. 12, pp. 3028–3037, Dec. 2013. China, in 2008, and the Ph.D. degree in electri-
[3] A.-J. Annema, B. Nauta, R. van Langevelde, and H. Tuinhout, “Analog cal engineering from Iowa State University, Ames,
circuits in ultra-deep-submicron CMOS,” IEEE J. Solid-State Circuits, in 2017.
vol. 40, no. 1, pp. 132–143, Jan. 2005. From 2008 to 2011, was a Circuit Design Engi-
[4] P. R. Kinget, “Device mismatch and tradeoffs in the design of analog neer with the IBM China Design Center, Shanghai,
circuits,” IEEE J. Solid-State Circuits, vol. 40, no. 6, pp. 1212–1224, China. From 2011 to 2012, he was a Senior Cir-
Jun. 2005. cuit Design Engineer at the AMD Research Design
[5] T. Zeng and D. Chen, “An order-statistics based matching strategy for Center, Shanghai. In 2014, he was with Texas Instruments Inc., Tucson,
circuit components in data converters,” IEEE Trans. Circuits Syst. I, Reg. as a Design Co-Op, involved in high-resolution DAC products. His research
Papers, vol. 60, no. 1, pp. 11–24, Jan. 2013. interests focus on mixed-signal and analog circuit design and verification
[6] F. Maloberti, Data Converters, vol. 1. Dordrecht, The Netherlands: against undesired operating points.
Springer, 2007. Dr. Li received the Excellent Student Award for his B.S. degree and the
[7] D. Marche, Y. Savaria, and Y. Gagnon, “Laser fine-tuneable deep- Excellent Master Thesis Award for his M.S. degree.
submicrometer CMOS 14-bit DAC,” IEEE Trans. Circuits Syst. I, Reg.
Papers, vol. 55, no. 8, pp. 2157–2165, Sep. 2008.
[8] A. R. Bugeja and B.-S. Song, “A self-trimming 14-b 100-MS/s CMOS Degang Chen (S’90–M’92–SM’02–F’16) received
DAC,” IEEE J. Solid-State Circuits, vol. 35, no. 12, pp. 1841–1852, the B.S. degree in instrumentation and automation
Dec. 2000. from Tsinghua University, Beijing, China, in 1984,
[9] Y. Cong and R. L. Geiger, “A 1.5-V 14-bit 100-MS/s self-calibrated and the M.S. and Ph.D. degrees in electrical
DAC,” IEEE J. Solid-State Circuits, vol. 38, no. 12, pp. 2051–2060, and computer engineering from the University of
Dec. 2003. California at Santa Barbara, Santa Barbara,
[10] D. A. Mercer, “Low-power approaches to high-speed current-steering in 1988 and 1992, respectively.
digital-to-analog converters in 0.18-μm CMOS,” IEEE J. Solid-State From 1984 to 1986, he was with the Beijing
Circuits, vol. 42, no. 8, pp. 1688–1698, Aug. 2007. Institute of Control Engineering. In 1992, he
[11] G. A. Miller, M. C. Coln, L. A. Singer, and P. R. Oaklander, “A true 16 was the John R. Pierce Instructor of electrical
b self-calibrating BiCMOS DAC,” in IEEE ISSCC Dig. Tech. Papers., engineering with the California Institute of
Feb. 1993, pp. 58–59. Technology, Pasadena. Then, he joined Iowa State University, Ames,
[12] R. McLachlan and S. Blackburn, “Voltage mode DAC with calibra- where he is currently a Professor with the Department of Electrical and
tion circuit using current mode DAC and ROM lookup,” U.S. Patent Computer Engineering. He was with Boeing Company in summer 1999,
8 089 380 B2, Jan. 3, 2012. Dallas Semiconductor–Maxim in summer 2001, and Texas Instruments
[13] L. R. Carley, “A noise-shaping coder topology for 15+ bit converters,” Inc., in summer 2011. His current research interests are in the area of
IEEE J. Solid-State Circuits, vol. 24, no. 2, pp. 267–273, Apr. 1989. VLSI design and testing, with emphasis on low-cost high-accuracy testing,
[14] F. Chen and B. H. Leung, “A high resolution multibit sigma-delta built-in-self-test, and test-based self-calibration of analog, mixed-signal, and
modulator with individual level averaging,” IEEE J. Solid-State Circuits, RF circuits.
vol. 30, no. 4, pp. 453–460, Apr. 1995. He was a A. D. Welliver Faculty Fellow with Boeing Company in 1999.
[15] R. E. Radke, A. Eshraghi, and T. S. Fiez, “A 14-bit current-mode  He received the IEEE Fellow Award in 2016 for his contributions to
DAC based upon rotated data weighted averaging,” IEEE J. Solid-State testing of analog and mixed-signal integrated circuits. He received the Best
Circuits, vol. 35, no. 8, pp. 1074–1084, Aug. 2000. Paper Award from the 1990 IEEE Conference on Decision and Control,
[16] J. Yu and F. Maloberti, “A low-power multi-bit  modulator in the Best Transaction Paper Award from the Journal of Dynamic Systems,
90-nm digital CMOS without DEM,” IEEE J. Solid-State Circuits, Measurement, and Control (ASME) in 1995, and the SRC Technology
vol. 40, no. 12, pp. 2428–2436, Dec. 2005. Invention Reward in 2005.