VLSI and Embedded Systems Laboratory

Subject Code : 15A04712

Regulations : JNTUA – R15

Class : VII Semester (ECE)

CHADALAWADA RAMANAMMA ENGINEERING COLLEGE

(AUTONOMOUS)
Chadalawada Nagar, Renigunta Road, Tirupati – 517 506

Department of Electronics and Communication Engineering

 SYLLABUS

JAWAHARLAL NEHRU TECHNOLOGICAL UNIVERSITY

ANANTAPUR
L T P C
B. Tech IV-I Sem. (ECE) 0 0 4 2
15A04712 VLSI & EMBEDDED SYSTEMS LABORATORY

Note: The students are required to perform any Six Experiments from each Part of the following.
Part-A: VLSI Lab
Course Objective:
 To design and draw the internal structure of the various digital integrated circuits
 To develop VHDL/Verilog HDL source code, perform simulation using relevant simulator and
analyze the obtained simulation results using necessary synthesizer.
 To verify the logical operations of the digital ICs (Hardware) in the laboratory.

Course Outcome:
After completion of the course the students will be able to
 Design and draw the internal structure of the various digital integrated circuits
 Develop VHDL/Verilog HDL source code, perform simulation using relevant simulator andanalyze
the obtained simulation results using necessary synthesizer.
 Verify the logical operations of the digital IC‟s (Hardware) in the laboratory

Note: For the following list of experiments students are required to do the following.
 Target Device Specifications
 Simulation
 Synthesize the design
 Generate RTL Schematic.
 Generate Technology Map.
 Generate Synthesis report.
 Design Summary.

List of Experiments:

Note: Use VHDL/ Verilog HDL

1. Realization of Logic Gates.
2. 3- to - 8Decoder- 74138.
3. 8 x 1 Multiplexer-74151 and 2 x 4 De-multiplexer-74155.
4. 4-Bit Comparator-7485.
5. D Flip-Flop-7474.
6. Decade counter-7490.
7. Shift registers-7495.
8. ALU Design.
Part B : Embedded C Experiments using TM4C processor:
1. Learn and understand how to configure EK-TM4C123GXL Launchpad digital I/O pins. Write a C
program for configuration of GPIO ports for Input and output operation (blinking LEDs, push buttons
interface).
Exercises:
a) Modify the code to make the red LED of EK-TM4C123GXL Launchpad blink.
b) Modify the code to make the green and red LEDs blink:
I. Together
II. Alternately
c) Alter the code to turn the LED ON when the button is pressed and OFF when it is released.
d) Modify the delay with which the LED blinks.
e) Alter the code to make the green LED stay ON for around 1 second every time the button is
pressed.
f) Alter the code to turn the red LED ON when the button is pressed and the green LED ON
when the button is released.
2. Learn and understand Timer based interrupt programming. Write a C program for EK-TM4C123GXL
Launchpad and associated Timer ISR to toggle onboard LED using interrupt programming technique.
Exercises:
a) Modify the code for a different timer toggling frequency.
b) Write the code to turn on interrupt globally.
3. Configure hibernation module of the TM4C123GH6PM microcontroller to place the device in low
power state and then to wake up the device on RTC (Real- Time Clock) interrupt.
Exercises:
a) Write a program to configure hibernation mode and wake up the EK-TM4C123GXL
Launchpad when onboard switch SW2 is pressed.
4. Configure in-build ADC of TM4C123GH6PM microcontroller and interface potentiometer with EK-
TM4C123GXL Launchpad to observe corresponding 12- bit digital value.
Exercises:
a) Tabulate ten different position of the Potentiometer and note down the Digital value and
calculate the equivalent analog value.
b) Use the ADC to obtain the analog value from the internal temperature sensor.
c) Configure Dual ADC modules to read from 2 analog input (could be from 2
potentiometers)
d) What are the trigger control mechanism for this ADC?
e) What does the resolution refer on ADC Specification?
f) The current sampling method is single ended sampling. This ADC could also be
configured to do differential sampling. What is the difference between the two methods
of sampling?
5. Learn and understand the generation of Pulse Width Module (PWM) signal by configuring and
programming the in-build PWM module of TM4C123GH6PM microcontroller.
Exercises:
a) Change the software to output a set Duty Cycle, which can be user programmed.
b) Change the frequency of the PWM Output from 6.25 KHz to 10 KHz and do the tabulation
again.
c) Generate Complementary signals, route it to two pins, and observe the waveforms.
d) What is dead band generation mean and where is it applied?
e) Is it possible to construct a DAC from a PWM? Identify the additional components and
connection diagram for the same.
 f) Sketch the gate control sequence of 3 phase Inverter Bridge and how many PWM generator
blocks are required? Can we generate this from TIVA Launchpad?
6. Configure the PWM and ADC modules of TM4C123GH6PM microcontroller to control the speed of
a DC motor with a PWM signal based on the potentiometer output.
Exercises:
a) With the same ADC input configure 2 PWM generator modules with 2 different frequencies.
b) Read the Internal temperature sensor and control a DC Motor that could be deployed in fan
Controller by observing the unit or ambient temperature.
c) What is the resolution of the PWM in this experiment?
d) What would be the maximum frequency that can be generated from the PWM generator?
e) Briefly explain an integrated application of ADC and PWM based control.
7. Learn and understand to connect EK-TM4C123GXL Launchpad to PC terminal and send an echo of
the data input back to the PC using UART.
Exercises:
a) Change the baud rate to 19200 and repeat the experiment.
b) What is the maximum baud rate that can be set in the UART peripheral of TIVA?
c) Modify the software to display “Switch pressed” by pressing a user input switch on the
Launchpad.
8. Learn and understand interfacing of accelerometer in Sensor Hub Booster pack with EK-
TM4C123GXL Launchpad using I2C.
Exercises:
a) Make a LED ON when the acceleration value in the x axis crosses a certain limit, say +5.
b) What is the precaution taken in this experiment in order to avoid the overflow of UART
buffer?
c) Change the value of PRINT_SKIP_COUNT to 100 and see the difference in the output.
d) Change MPU9150_ACCEL_CONFIG_AFS_SEL_2G to
MPU9150_ACCEL_CONFIG_AFS_SEL_4G on line 461 of the same source file and
Observe the difference.
9. USB bulk transfer mode:
Learn and understand to transfer data using bulk transfer mode with the USB2.0 peripheral of the
TM4C123GH6PM device.
Exercises:
a) What are the different modes offered by USB 2.0?
b) What are the typical devices that use Bulk transfer mode?
10. Learn and understand to find the angle and hypotenuse of a right angle triangle using IQmath library
of TivaWare.
Exercises:
a) Change the base and adjacent values in the program to other values, build the program and
observe the values in the watch window.
b) Open IQmathLib.h and browse through the available functions. What function is to be used if
the IQ number used in the program is to be converted to a string?
11. Learn and understand interfacing of CC3100 WiFi module with EK-TM4C123GXL Launchpad and
configuration of static IP address for CC3100 booster pack.
Exercises:
a) Try pinging the same IP address before connecting to the Access Point (AP) and note down
the observation.
b) What is the difference between static IP address and dynamic IP address?
12. Configure CC3100 Booster Pack connected to EK-TM4C123GXL Launchpad as a Wireless Local
Area Network (WLAN) Station to send Email over SMTP.
 Exercises:
a) In the terminal output window, we have received a debug message “Pinging…!”. Search in
the code and change the message to “Pinging the website”. Repeat the experiment to observe
this change in the Serial Window.
b) In line no:62 of main. C replace www.ti.com with any non-existing web address and repeat
the experiment and observe what happens
c) In line no: 62 of main. C replace again with www.ti.comand repeat the experiment.
d) Identify the code that helps in establishing connection over SMTP. Modify the code to
trigger E-mail application based upon external analog input.
e) How to configure the AP WLAN parameters and network parameters (IP addresses and
DHCP parameters) using CC3100 API.
13. Configure CC3100 Booster Pack connected to EK-TM4C123GXL Launchpad as a HTTP server.
Exercises:
a) Where are the webpages stored in the CC3100?
b) What happens if we try to access a webpage, which is not there inside the CC3100?
c) List 3 applications with a 3 to 4-line brief description that you think can be performed with
this experimental setup.
 CHADALAWADA RAMANAMMA ENGINEERING COLLEGE
(AUTONOMOUS)

Chadalawada Nagar, Renigunta Road, Tirupati – 517 506

Department of Electronics and Communication Engineering

INDEX

S. No Name of the Experiment Page No

Part-A: VLSI Lab

1 Introduction to ISE Xilinx Software and Spartan 3E FPGA

2 Realization of LOGIC GATES

3 3x8 Decoder– 74138
4 8 X 1 Multiplier-74151 and 2 X 4 Demultiplexer-74155
5 4-Bit Comparator-7485

6 D Flip-Flop-7474

7 Decade Counter – 7490

8 Shift Registers-7495
9 ALU Design

Part B : Embedded C Experiments using TM4C processor

10

11

12

13

14
 EXPERIMENT – 1

Introduction to ISE Xilinx Software and Spartan 3E FPGA

AIM: TO Become familiar with the Xilinx ISE Foundation software package and Simulate and verify
functionality of XOR Gate

SOFTWARE REQUIRED:

1. Xilinx ISE Foundation Series

2. Personal Computer
3. Spartan 3E

PROCEDURE:

1. Read the Introductory Tutorial for Xilinx ISE Foundation v10.1

2. Go through the steps of the tutorial and implement the given logic function.
3. Implement the XOR Gate.

Introductory Tutorial for Xilinx ISE Foundation

# Open Xilinx Project Navigator.

# Create new project.

# Specify device properties.

# Add new source to the project.

# Select source type [VHDL or Verilog].

# Specify input and output port names.

# New source summary window will appear as shown below.

# Enter program code in the HDL editor window.

# Save the program and synthesize the process.

# The design summary window after synthesis appears as shown below.

# Create another new source.

# Select source type as Test bench wave form.

# Associate the test bench to the source.

# Test bench wave form summary window will appear as shown below.
# Assign clock and timing details.

# Give the input waveforms for the source.

# Save the input waveforms and perform behavioral simulation.

# The simulated output waveforms window will be as shown below.

# Dumping process:

# Assign pin numbers to input and output ports.

# Select JTAG clock in the startup options of process properties by right clicking on ‘Generate
programming file.

# Select configure device using Boundary scan in the impact window.

# Generate ‘programming file generation report’.

# Select the generated bit file.

# Xilinx boundary scan window will appear as shown below.

# Select the program by right clicking on Xilinx component.

# The programming properties window will appear as shown below.

# After successful dumping the program succeeded window will appear as shown
below.

Result: Thus the VHD code for half adder is verified and simulated, synthesis report is generated and the
design is implemented using FPGA
 EXPERIMENT – 2

Realization of Logic Gates

AIM: To design and simulate logic gates using VHDL

SOFTWARE REQIURED:

1. Personal computer
2. ISE Xilinx software

HARDWARE REQUIRED:

1. SPARTAN – 3E XC3S500E KIT

THEORY

A logic gate is an elementary building block of a digital circuit. Most logic gates have
two inputs and one output. At any given moment, every terminal is in one of the
two binary conditions low (0) or high (1), represented by different voltage levels. The
logic state of a terminal can, and generally does, change often, as the circuit
processes data. In most logic gates, the low state is approximately zero volts (0 V),
while the high state is approximately five volts positive (+5 V).

There are seven basic logic gates: AND, OR, XOR, NOT, NAND, NOR, and XNOR.

The AND gate acts in the same way as the logical "and" operator. The output is
"true" when both inputs are "true." Otherwise, the output is "false."

The OR gate gets its name from the fact that it behaves after the fashion of the logical
inclusive "or." The output is "true" if either or both of the inputs are "true." If both
inputs are "false," then the output is "false."

A logical inverter, sometimes called a NOT gate to differentiate it from other types of
electronic inverter devices, has only one input. It reverses the logic state.
The NAND gate operates as an AND gate followed by a NOT gate. It acts in the
manner of the logical operation "and" followed by negation. The output is "false" if
both inputs are "true." Otherwise, the output is "true."

The NOR gate is a combination OR gate followed by an inverter. Its output is "true" if
both inputs are "false." Otherwise, the output is "false."

The XOR (exclusive-OR) gate acts in the same way as the logical "either/or." The
output is "true" if either, but not both, of the inputs are "true." The output is "false" if
both inputs are "false" or if both inputs are "true." Another way of looking at this
circuit is to observe that the output is 1 if the inputs are different, but 0 if the inputs
are the same.

The XNOR (exclusive-NOR) gate is a combination XOR gate followed by an inverter.

Its output is "true" if the inputs are the same, and "false" if the inputs are different.

The following figure/table shows the circuit symbols and logic combinations of
different logic gates
PROCEDURE:

1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package pins’
and after that double click on ‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’
clock in startup options.
9. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
10. In ‘generate programming file’ double clicking on ‘programming file
generation report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right
click on Xilinx component and select program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be seen
on the kit.

PROGRAM (IN VHDL):

AND GATE:
Output wave Form:

OR GATE:
Output wave Form:

NOT GATE:
Output wave Form:

NAND GATE:
NOR GATE:
RESULT: Thus the VHDL/Verilog code for half adder is verified, synthesis report is
generated and the design is implemented using FPGA.

VIVA QUESTIONS:

1. Implement the following function using VHDL coding. (Try to minimize if you can).
F(A,B,C,D)=(A′+B+C) . (A+B′+D′). (B+C′+D′) . (A+B+C+D)
2. What will be the no. of rows in the truth table of N variables?
3. What are the advantages of VHDL?
4. Design Ex-OR gate using behavioral model?
5. Implement the following function using VHDL code f=AB+CD.
6. What are the differences between half adder and full adder?
7. What are the advantages of minimizing the logical expressions?
8. What does a combinational circuit mean?
9. Implement the half adder using VHDL code?
10. Implement the full adder using two half adders and write VHDL program in
structural model?
 EXPERIMENT – 3

3x8 DECODER – 74138

AIM: To design and simulate 3:8 Decoder - 74138 using VHDL.

SOFTWARE REQIURED:

1. Personal computer
2. ISE Xilinx software

HARDWARE REQUIRED:

1. SPARTAN – 3E XC3S500E KIT

THEORY:
In digital electronics, a decoder can take the form of a multiple-input, multiple-
output logic circuit that converts coded inputs into coded outputs, where the input and
output codes are different e.g. n-to-2n , binary-coded decimal decoders. Decoding is
necessary in applications such as data multiplexing, 7 segment display and memory
address decoding.
It uses all AND gates, and therefore, the outputs are active- high. For active- low
outputs, NAND gates are used. It has 3 input lines and 8 output lines. It is also called as
binary to octal decoder it takes a 3-bit binary input code and activates one of the 8(octal)
outputs corresponding to that code.

PIN DIAGRAM:
TRUTH TABLE:

PROCEDURE:

1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package pins’
and after that double click on ‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’
clock in start up options.
9. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
10. In ‘generate programming file’ double clicking on ‘programming file generation
report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right click
on Xilinx component and select program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be seen on
the kit.
PORGRAM:
INTERNAL DIAGRAM OF 3X8 DECODER

RESULT: Thus the VHDL code for 3x8 Decoder 74138 is verified, synthesis report is
generated and the design is implemented using FPGA.
 VIVA QUESTIONS:

1. Write the behavioural code for the IC 74x138.

2. Write the VHDL code for the IC 74x138 using CASE statement.
3. Write the VHDL code for the IC 74x138 using WITH statement.
4. Write the VHDL code for the IC 74x138 using WHEN--ELSE statement.
5. Write the structural program for IC 74x138.
6. What does priority encoder mean?
7. How many decoders are needed to construct 4X16 decoder?
8. What is the difference between decoder and encoder?
9. Write the syntax for exit statement?
10. Explain briefly about next statement?
11. How to specify the delay in VHDL program?
12. Write the syntax for component declaration.
 EXPERIMENT – 4

8 X 1 MULTIPLEXER-74151 AND 2 X 4 DEMULTIPLEXER-74155

AIM: To design and simulate MUX & DEMUX using VHD.

SOFTWARE REQIURED:

1. Personal computer
3. ISE Xilinx software

HARDWARE REQUIRED:

2. SPARTAN – 3E XC3S500E KIT

THEORY:

Multiplexing is defined as the process of feeding several independent signals to a

common load, one at a time. The device or switching circuitry used to select and
connect one of these several signals to the load at any one time is known as a
multiplexer.

The reverse function of multiplexing, known as de-multiplexing, pertains to the

process of feeding several independent loads with signals coming from a common
signal source, one at a time. A device used for de-multiplexing is known as de-
multiplexer.

Multiplexing and de-multiplexing, therefore, allow the efficient use of common circuits
to feed a common load with signals from several signal sources, and to feed several
loads form a single, common signal source, respectively.
PIN DIAGRAM:

8 X 1 MULTIPLEXER

2x4 Dual - DE MULTIPLEXER

TRUTH TABLE:

8 X 1 MULTIPLEXER
 2x4 Dual - DE MULTIPLEXER

PROCEDURE:

14. Open Xilinx ISE 9.1i.

15. Create a new source file in a new project with suitable name.
16. Create the file in VHDL/Verilog module.
17. Select the appropriate input and output ports according to the requirements.
18. Type the program and save it.
19. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
20. In the process window, go to ‘user constraints’ and select ‘assign package pins’
and after that double click on ‘implement design’.
21. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’
clock in start up options.
22. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
23. In ‘generate programming file’ double clicking on ‘programming file generation
report. Bit file will be generated.
24. Xilinx boundary scan window will appear when the bit file is selected. Right click
on Xilinx component and select program.
25. Programming properties will appear and finally program will be succeeded.
26. Thus the program can be dumped into FPGA kit and finally output can be seen on
the kit.
PROGRAM
8 X 1 MULTIPLEXER

2x4 DUAL - DE MULTIPLEXER

Library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity decoder1 is
port(
a : in STD_LOGIC_VECTOR(1 downto 0);
b : out STD_LOGIC_VECTOR(3 downto 0)
);
end decoder1;
 architecture bhv of decoder1 is
begin

process(a)
begin
if (a="00") then
b <= "0001";
elsif (a="01") then
b <= "0010";
elsif (a="10") then
b <= "0100";
else
b <= "1000";
end if;
end process;

end bhv;

Output:

8X1 MULTIPLEXER
8X1 MULTIPLEXER
RESULT: Thus the VHDL code for 8 X 1 MULTIPLEXER-74151 AND 2 X 4
DEMULTIPLEXER-74155 is verified, synthesis report is generated and the design is
implemented using FPGA
VIVA QUESTIONS:

1. Write the behavioural code for the IC 74x151.

2. Write the VHDL code for the IC 74x151 using IF statement.
3. Write the VHDL code for the IC 74x151 using WITH statement.
4. Write the VHDL code for the IC 74x151 using WHEN--ELSE statement.
5. Write the structural program for IC 74x151.
6. What is meant by multiplexer?
7. What does demultiplexer mean?
8. How many 8X1 multiplexers are needed to construct 16X1 multiplexer?
9. Compare decoder with demultiplexer?
10. Design a full adder using 8X1 multiplexer?
11. What are the two kinds of subprograms?
12. What are the difference between function and procedure?
13. Explain briefly about subprogram overloading?
 EXPERIMENT – 5

4-BIT COMPARATOR-7485

AIM: To design and simulate 4-BIT COMPARATOR using VHDL.

SOFTWARE REQIURED:

1. Personal computer
4. ISE Xilinx software

HARDWARE REQUIRED:

3. SPARTAN – 3E XC3S500E KIT

THEORY:

A comparator is a special combinational circuit designed primarily to

compare the relative magnitudes of two binary numbers. If a comparator
receives two n-bit numbers A and B as inputs and the outputs are A>B,
A=B, A<B. Depending upon the relative magnitudes of the two numbers, one
of the outputs will be high.

IC7485 is a bit comparator. It can be used to compare two 4-bit binary words.
These ICs, can cascade to compare words of almost any length.

PIN DIAGRAM:
PROCEDURE:

1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package pins’
and after that double click on ‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’
clock in start-up options.
 9. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
10. In ‘generate programming file’ double clicking on ‘programming file generation
report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right click
on Xilinx component and select program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be seen on
the kit.
PROGRAM
RESULT: Thus the VHDL code for 4-BIT COMPARATOR is verified, synthesis report is
generated and the design is implemented using FPGA
 VIVA QUESTIONS:

1. Write the dataflow model for the IC 74x85.

2. Write the VHDL code for the IC 74x85 using CASE statement.
3. Write the VHDL code for the IC 74x85 using WITH statement.
4. Write the VHDL code for the IC 74x85 using WHEN--ELSE statement.
5. Write the structural program for IC 74x85.
6. How many 4-bit comparators are needed to construct 12-bit comparator?
7. What does a digital comparator mean?
8. Design a 2-bit comparator using gates?

9. Explain the phases of a simulation?

10. Explain briefly about wait statement?
 EXPERIMENT – 6

D Flip-Flop-7474

AIM: To design and simulate D Flip-Flop-7474 using VHDL

SOFTWARE REQIURED:

1. Personal computer
5. ISE Xilinx software

HARDWARE REQUIRED:

4. SPARTAN – 3E XC3S500E KIT

THEORY:

The D-flip flop has only a single data input .The data input is connected to
the S input of an RS flip flop, while the inverse of D is connected to the R
input. This prevents that the input combination ever occurs. To allow the flip
flop to be in a holding state, a D-flip flop has a second input called “Enable.”
The Enable-input is AND with the D-input, such that when Enable=0, the R
& S of the RS-flip flop are 0 and the state is held. When the Enable-input is
1, the S input of the RS flip flop equals the D input and R is the inverse of D
determines the value of the output Q when Enable is 1. When Enable returns
to 0, the most recent input D is “remembered.”
PIN DIAGRAM:

PROCEDURE:

1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package pins’
and after that double click on ‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’
clock in start-up options.
9. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
10. In ‘generate programming file’ double clicking on ‘programming file generation
report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right click
on Xilinx component and select program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be seen on
the kit.
CIRCUIT DESIGN AND TRUTH TABLE

PROGRAM
RESULT: Thus the VHDL code for D Flip-Flop is verified, synthesis report is generated
and the design is implemented using FPGA
VIVA QUESTIONS:

1. Write the behavioral code for the IC 74x74.

2. Write the dataflow code for the IC 74x74.
3. What is the difference between sequential and combinational circuit?
4. What is a flip-flop?
5. Explain the functions of preset and clear inputs in flip-flop?
6. What is meant by a clocked flip-flop?
7. What is meant by excitation table?
8. What is the difference between flip-flop and latch?
9. What are the various methods used for triggering flip-flops?
10. Explain level triggered flip-flop?
11. Write the behavioral code for IC 74X74.
12. Write the syntax of IF statement?
 EXPERIMENT – 7

DECADE COUNTER - 7490

AIM: To design and simulate Decade counter using VHDL

SOFTWARE REQIURED:

1. Personal computer
2. ISE Xilinx software

HARDWARE REQUIRED:

1. SPARTAN – 3E XC3S500E KIT

THEORY:

A binary counter can be constructed from J-K flip-flops by taking the output of one cell
to the clock input of the next. The J and K inputs of each flip flop are set to 1 to produce
a toggle at each cycle of the clock input. For each two toggles of the first cell, a toggle is
produced in the second cell, and so on down to the fourth cell. This produces a binary
number equal to the number of cycles of the input clock signal. This device is sometimes
called a ripple through counter. The same device is useful as a frequency divider, a BCD
counter or decade counter can be constructed from a straight binary counter by
terminating the ripple through counting when the count reaches decimal 9(binary 1001).
Since the next toggle would set the two most significant bit, a NAND gate tied from those
two outputs to the asynchronous clear line will start the count over after 9. A frequency
divider can be constructed from J-K flip flops by taking the output of one cell to the clock
input of the next. The J and K inputs of each flip flop are set to 1 to produce a toggle at
each cycle of the clock input. For each two toggles of the first cell, a toggle is produced in
second cell, so its output is at half the frequency of the first. The output of the fourth cell
is 1/16 the clock frequency. The same device is useful as a binary counter.
PIN DIAGRAM:

PROCEDURE:

1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package pins’
and after that double click on ‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’
clock in start-up options.
9. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
10. In ‘generate programming file’ double clicking on ‘programming file generation
report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right click
on Xilinx component and select program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be seen on
the kit.
 JK-FLIPFLOP

RESULT: Thus the VHDL code for Decade counter is verified, synthesis report is
generated and the design is implemented using FPGA
VIVA QUESTIONS:

1. What is a sequential circuit?

2. Differentiate between synchronous and asynchronous counter?
3. How many no. of flip-flops are required for decade counter?
4. What is meant by excitation table?
5. What are the meanings of different types of values in std_u logic?
6. What are the objects in VHDL?
7. Write the syntax for a signal?
8. Write the difference between signal and variable?
9. Explain about enumeration types?
10. If the modulus of a counter is 12 how many flip-flops are required?
 EXPERIMENT – 8

SHIFT REGISTERS-7495.

AIM: To design and simulate shift register using VHDL.

SOFTWARE REQIURED:

1. Personal computer
3. ISE Xilinx software

HARDWARE REQUIRED:

2. SPARTAN – 3E XC3S500E KIT

THEORY:

Today, there are many high speed bi-directional “universal” type Shift
Registers available such as the TTL 74LS194, 74LS195 or the CMOS 4035 which are
available as 4-bit multi-function devices that can be used in either serial-to-serial, left
shifting, right shifting, serial-to-parallel, parallel-to-serial, or as a parallel-to-parallel
multifunction data register, hence their name “Universal”.

These universal shift registers can perform any combination of parallel and serial
input to output operations but require additional inputs to specify desired function and
to pre-load and reset the device. A commonly used universal shift register is the TTL
74LS194 as shown below.

4-bit Universal Shift Register 74LS194

 Universal shift registers are very useful digital devices. They can be configured to
respond to operations that require some form of temporary memory storage or for the
delay of information such as the SISO or PIPO configuration modes or transfer data
from one point to another in either a serial or parallel format. Universal shift registers
are frequently used in arithmetic operations to shift data to the left or right for
multiplication or division.

PROCEDURE:

1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package pins’
and after that double click on ‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’
clock in start-up options.
9. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
10. In ‘generate programming file’ double clicking on ‘programming file generation
report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right click
on Xilinx component and select program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be seen on
the kit.

PROGRAM

library ieee;
use ieee.std_logic_1164.all;

entity universal is
port(clk,clr_l,Lin,Rin,s1,s0:in std_logic;
a,b,c,d:in std_logic;
q:inout std_logic_vector(3 downto 0));
end universal;
architecture universal of universal is

component and3
port(a,b,c:in std_logic;y:out std_logic);
end component;

component or4
port(a,b,c,d:in std_logic;y:out std_logic);
end component;

component not1
port(a:in std_logic;b:out std_logic);
end component;

component dff
port(pre_l,clr_l,d,clk:in std_logic;q,q_l:inout std_logic);
end component;

signal s1_l,s0_l:std_logic;
signal q_l:std_logic_vector(3 downto 0);
signal s:std_logic_vector(1 to 20);
signal pr:std_logic;
begin
l1:not1 port map(s1,s1_l);
l2:not1 port map(s0,s0_l);
l3:and3 port map(Lin,s1,s0_l,s(1));
l4:and3 port map(q(0),s1_l,s0_l,s(2));
l5:and3 port map(d,s1,s0,s(3));
l6:and3 port map(q(1),s1_l,s0,s(4));
l7:or4 port map(s(1),s(2),s(3),s(4),s(5));
--18:not1 port map(clr_l,clr);
l9:dff port map(pr,clr_l,s(5),clk,q(0),q_l(0));
l10:and3 port map(q(0),s1,s0_l,s(6));
l11:and3 port map(q(1),s1_l,s0_l,s(7));
l12:and3 port map(c,s1,s0,s(8));
l13:and3 port map(q(2),s1_l,s0,s(9));
l14:or4 port map(s(6),s(7),s(8),s(9),s(10));
l15:dff port map(pr,clr_l,s(10),clk,q(1),q_l(1));
l16:and3 port map(q(1),s1,s0_l,s(11));
l17:and3 port map(q(2),s1_l,s0_l,s(12));
l18:and3 port map(b,s1,s0,s(13));
l19:and3 port map(q(3),s1_l,s0,s(14));
l20:or4 port map(s(11),s(12),s(13),s(14),s(15));
l21:dff port map(pr,clr_l,s(15),clk,q(2),q_l(2));
l22:and3 port map(q(2),s1,s0_l,s(16));
l23:and3 port map(q(3),s1_l,s0_l,s(17));
l24:and3 port map(a,s1,s0,s(18));
l25:and3 port map(Rin,s1_l,s0,s(19));
l26:or4 port map(s(16),s(17),s(18),s(19),s(20));
l27:dff port map(pr,clr_l,s(20),clk,q(3),q_l(3));
end universal;

Thus the VHDL code for universal shift register is verified, synthesis report is
generated and the design is implemented using FPGA
VIVA QUESTIONS:

1. What is shift register?

2. Differentiate between register and shift register?
3. The full form of SIPO?
4. What is mean by bidirectional shift register?
5. What data types will support by VHDL?
6. What is meant by parallel load of a shift register?
7. What Is The Difference Between Concurrent & Sequential Statements?
8. Explain Various Types Of Delays In VHDL?
9. List Out The Four Modes For Port In Vhdl?
10. Types of universal shift registers?
 EXPERIMENT – 9

ALU

AIM: To design and simulate 16 bit ALU

SOFTWARE REQIURED:

1. Personal computer
4. ISE Xilinx software

HARDWARE REQUIRED:

3. SPARTAN – 3E XC3S500E KIT

THEORY:

Arithmetic logic unit (ALU) is a digital circuit used to perform arithmetic and logic
operations. It represents the fundamental building block of the central processing unit
(CPU) of a computer. Modern CPUs contain very powerful and complex ALUs. In
addition to ALUs, modern CPUs contain a control unit (CU).

Most of the operations of a CPU are performed by one or more ALUs, which load data
from input registers. A register is a small amount of storage available as part of a CPU.
The control unit tells the ALU what operation to perform on that data, and the ALU
stores the result in an output register. The control unit moves the data between these
registers, the ALU, and memory.
PROCEDURE:

1. Open Xilinx ISE 9.1i.

2. Create a new source file in a new project with suitable name.
3. Create the file in VHDL/Verilog module.
4. Select the appropriate input and output ports according to the requirements.
5. Type the program and save it.
6. Select Synthesize XST, check for syntax errors and generate report and RTL
schematic.
7. In the process window, go to ‘user constraints’ and select ‘assign package pins’
and after that double click on ‘implement design’.
8. Select properties by right clicking on ‘generate programming file’. Select ‘JTAG’
clock in start-up options.
9. Select boundary scan in ‘impact window’ after double clicking on ‘configure
device’.
10. In ‘generate programming file’ double clicking on ‘programming file generation
report. Bit file will be generated.
11. Xilinx boundary scan window will appear when the bit file is selected. Right click
on Xilinx component and select program.
12. Programming properties will appear and finally program will be succeeded.
13. Thus the program can be dumped into FPGA kit and finally output can be seen on
the kit.
PROGRAM

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity alu16 is
Port (
r : in std_logic_vector(15 downto 0);
w : in std_logic_vector(15 downto 0);
d : in std_logic_vector(3 downto 0);
f : out std_logic_vector(15 downto 0)
);
end alu16;

architecture alu16 of alu16 is

begin
process(r,w,d)
begin
case d is

when "0000"=> f<= w and r;

when "0001"=> f<=w or r;
when "0010"=> f<=w nor r;
when "0011"=> f<=w xor r;
when "0100"=> f<=w xnor r;
when "0101"=> f<=w nand r;
when "0110"=> f<=not r;
when "0111"=> f<=w + r;
when "1000"=> f<=r - w;
when "1001"=> f<=r+"0000000000000001";
when "1010"=> f<=w-"0000000000000001";
when "1011"=> f<=r;
when others => f<="0000000000000000";
end case;
end process;
end alu14;
 output:

Result:

Thus the VHDL code for ALU is verified, synthesis report is generated and
the design is implemented using FPGA