Challenges with Power Aware

Simulation and Verification

Methodologies
Divyeshkumar Vora
Staff Design Engineer

© Accellera Systems Initiative 1

 Agenda
• Introduction
• Power-aware (PA) simulation overview
• Integrated PA Verilog model
• Liberty based assertions
• UPF Macro models using successive refinement
• Library validation flow
• Summary

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 Introduction
• Constant push to make electronic products both energy
and power efficient resulted in increased design
implementation complexity
• It is of utmost importance to catch any issue early in the
implementation cycle
• IEEE-1801 (a.k.a. Unified Power Format - UPF), allows
users to define the design power intent which can be
used during the entire implementation flow
• UPF enables user to perform power intent verification
from the RTL stage and Power Aware (PA) simulation is
one such verification

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 PA Simulation Flows
Design Inputs Testbench

Library Views
Liberty – IO, Mem
RTL,
PA Sim Functional Verilog
Design UPF
– IO, Mem

Liberty – SC, IO, Mem

Liberty(UPF) LP Synthesis PA Sim Functional Verilog
– SC, IO, Mem

Power Aware Verilog

LP PnR PA Sim
– SC, IO, Mem
 Sample Design UPF
create_supply_set VDDSupply \ set_isolation …
-function {power VDD} \ set_retention …
-function {ground VSS} \ set_level_shifter …
-function {nwell VDD} \
add_power_state PVDD.VDDSupply \
-function {pwell VSS}
-state vdd_on { \
create_power_domain PVDD \ -supply_expr {..} -simstate NORMAL} \
-supply {VDDSupply} -state vdd_off { \
associate_supply_set VDDSupply \ -supply_expr {..} -simstate CORRUPT}
-handle PVDD.primary
add_power_state PVDD \
set_port_attributes -elements { . } \ -state P1 { \
-applies_to inputs \ -logic_expr {(VDDSupply == vdd_on)} } \
-driver_supply VDDSupply -state P2 { \
-logic_expr {(VDDSupply == vdd_off)} }
create_power_switch …

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 Sample Liberty Model
cell(A2LVLUO) { pin(A) {
is_level_shifter : true ; related_power/ground_pin : VDD/VSS ;
level_shifter_type : HL_LH ; related_bias_pin : “VNW VPW";
input_voltage_range(0.8, 1.2); level_shifter_data_pin : true ;
output_voltage_range(0.8, 1.2);
pin(EN) {
pg_pin(VNW) { pg_type : nwell; related_power/ground_pin : VDDO/VSS ;
pg_pin(VPW) { pg_type : pwell; related_bias_pin : "VPW";
pg_pin(VDDO) {pg_type : primary_power ; level_shifter_enable_pin : true ;
pg_pin(VSS) {pg_type : primary_ground ;
pg_pin(VDD) {pg_type : primary_power ; pin(Y) {
std_cell_main_rail : true ; related_power/ground_pin : VDDO/VSS ;
related_bias_pin : "VPW";
power_down_function :
"!VDDO+(!VDD&EN)+VSS+VPW+!BIASNW";

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 Sample Verilog Models
Functional Power Aware
module A2LVLUO (Y, A, EN); module A2LVLUO (Y, A, EN,
output Y; VDD, VDDO, VSS, VNW, VPW);
input A, EN; output Y;
input A, EN;
and I0 (Y, A, EN); inout VDDO, VDD, VSS, VNW, VPW;

endmodule
and I0 (out_temp, A, EN);
assign Y = ((VDDO === 1'b1) && (BIASNW ===
1'b1) && (VPW === 1'b0) && (VSS === 1'b0) &&
(!EN|VDD === 1'b1))? out_temp : 1'bx;

endmodule

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INTEGRATED VERILOG MODEL
 Problem Statement
• Maintain separate Functional and PA Verilog models
• Rely on simulator to infer correct functionality from
Functional Verilog + Liberty (UPF) model, which
should match with the PA Verilog model
• Create separate testbenches for RTL and gate-level
simulation, if the Liberty standard doesn’t support
exact PA Verilog behaviour for any cell.

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 Proposal and Solution
• Embed PA functionality in the functional Verilog model
• Simulator disables overlaying UPF PA information on the
cells, and uses PA functionality within the Verilog model
• Advantages
– Same Verilog model can be used for all types of simulation
• Functional simulation
• PA simulation with UPF
• PA simulation without UPF
– Reduced development and verification overhead
– No impact on implementation flow

Note: Support for PA simulation without UPF is still in concept phase.

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 Model Example
module PVSENSE (RTO, SNS, RETON);
output RTO,SNS; VDD
PVDD Power
input RETON;
supply1 DVDD, VDD;
Manag
RETON ement
supply0 DVSS, VSS;
PVSENSE block
reg RTO_reg, SNS_reg;

assign RTO = DVDD? RTO_reg:1'b0; PBIDIR

assign SNS = DVDD? SNS_reg:1'b0; Logic

always @(VDD) PBIDIR

if (!VDD) Core
RTO_reg = !RETON;
SNS_reg = RETON; D RS V
else V T N D
RTO_reg = 1'b1; D OS D
SNS_reg = 1'b1;
D
endmodule

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 Simulation Behaviour
PVSENSE PBIDIR
RETON VDD DVDD RTO SNS RTO SNS VDD DVDD PAD Y

0 On On 1 1 1 1 On On A A
0 Off On 1 0 - 0 Off On z 0
0 On Off 0 0 - x On Off x x
LIBERTY BASED ASSERTIONS
 Problem Statement
• Today’s designs exhibit complex retention capabilities
– Even basic save and restore operation could depend on complex
sequences of various control signals
– Any incorrect state of the register controls like clock, set, reset
or violation of power control sequence could cause incorrect
retention values
• Synthesis tools pick retention cells only based on the cell
classification and functionality
– Cell-level protocol requirements are not enforced
– If escapes happen, it can lead to silicon failures

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 Proposal and Solution
• Use low power attributes defined in Liberty to infer
assertion proofs and firings
– Instrument an SV based assertion within the tool to check
the protocol behaviour
– Validate assertion against applied vectors during dynamic
simulation, and obtain the time when the assertion fails to
ease the debugging

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 Sample Liberty Model
cell(DRFFQ) {
pg_pin(VDD) { pg_type : primary_power ;
pg_pin(VDDG) { pg_type : backup_power ; pin(Q) {
pg_pin(VSS) { pg_type : primary_ground ; direction: output;
pg_pin(VSSG) { pg_type : backup_ground ; related_power/ground_pin : VDD/VSS ;
pg_pin(VNW) { pg_type : nwell ; power_down_function :
pg_pin(VPW) { pg_type : pwell; "!VDD+!VDDG+!VNW+VSS+VSSG+VPW" ;

pin(RETN) {
pin(CK) { direction : input;
clock : true ; related_power/ground_pin : VDDG/VSSG;
direction: input; always_on : true;
related_power/ground_pin : VDD/VSS ; retention_pin (save_restore, "1");
save_action : H;
pin(D) { restore_action : L;
direction: input; restore_condition : !CK;
related_power/ground_pin : VDD/VSS ; restore_edge_type : trailing;

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Simulation Waveform and Assertion

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UPF MACRO MODELS USING
SUCCESSIVE REFINEMENT
 Problem Statement
• Need to know the boundary / interface power
information at SoC level for all the hard macros
– Defined in Liberty using pg_pin attribute
– Specify pg_pin connections for each cell with corresponding
design power net using connect_supply_net command
• Liberty standard lacks attributes to define
– Feedthrough and floating ports
• Results in spurious issues during PA simulation, synthesis, P&R, etc.
– Valid power modes
• Results in escape of unsupported power mode

Note: Valid power mode checking is still in concept phase

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 Solution – UPF Power Model
• Macro Model: A block that has been completely
implemented and can be used as it is in other blocks
– Sub-block of design
– Library cell used for implementation
• The UPF Power Model can be used to define the power
intent of a hard IP/macro
– Advantages
• Has all the capabilities that are missing in Liberty
• Supply set based mapping makes integration much easier
– Limitations
• Tools are just catching up with the support for the UPF Power Model
– Alternative
• Use UPF successive refinement flow

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 Successive Refinement Flow
• Successive refinement in UPF
– Allows the IP provider to capture the low power constraints
inherent in an IP block without predicating a particular
configuration
– Enables IP licensee to configure within these constraints, for
their particular application
– Makes it agnostic to technology specific implementation
• Advantages
– Mature and supported by most EDA tools
– All UPF constructs available for modelling macros
• Limitation
– Instance based hierarchical mapping for each supply set

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 Cell UPF Model
create_supply_set AVDDSupply -function {power AVDD} -function {ground AVSS}
create_supply_set VDDSupply -function {power VDD} -function {ground VSS}

create_power_domain PVDD -supply {AVDDSupply} -supply {VDDSupply}

associate_supply_set VDDSupply -handle PVDD.primary

set_port_attributes -ports {RTO SNS} -unconnected

set_port_attributes -ports {PAD PADC} –feedthrough

add_power_state PVDD.AVDDSupply -state avdd_on { -supply_expr {..} -simstate NORMAL} \

-state avdd_off { -supply_expr {..} -simstate CORRUPT}

add_power_state PVDD.VDDSupply -state vdd_on { -supply_expr {..} -simstate NORMAL} \

-state vdd_off { -supply_expr {..} -simstate CORRUPT}

add_power_state PVDD -state P1 { -logic_expr {(AVDDSupply == avdd_on) && (VDDSupply == vdd_on)} } \

-state P2 { -logic_expr {(AVDDSupply == avdd_on) && (VDDSupply == vdd_off)} } \
-state P3 { -logic_expr {(AVDDSupply == avdd_off) && (VDDSupply == vdd_on)} } \
-state P4 { -logic_expr {(AVDDSupply == avdd_off) && (VDDSupply == vdd_off)} }

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 Integration with the Design UPF
create_supply_set VDDswSupply -function {power VDDsw} -function {ground VSS}
create_supply_set AVDD1p8swSupply -function {power AVDD1p8sw} -function {ground AVSS}

add_power_state PVDD \
-state P1 { -logic_expr {(AVDD1p8swSupply == avdd_on) && (VDDswSupply == vdd_on)} } \
-state P2 { -logic_expr {(AVDD1p8swSupply == avdd_on) && (VDDswSupply == vdd_off)} } \
-state P3 { -logic_expr {(AVDD1p8swSupply == avdd_off) && (VDDswSupply == vdd_on)} } \
-state P4 { -logic_expr {(AVDD1p8swSupply == avdd_off) && (VDDswSupply == vdd_off)} }

load_upf -scope /my_dut_tb/i_ana PANA.upf

associate_supply_set VDDswSupply -handle /my_dut_tb/i_ana/PVDD.VDDSupply
associate_supply_set AVDD1p8swSupply -handle /my_dut_tb/i_ana/PVDD.AVDDSupply

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 Simulation Waveform
VDD

PANALOG
PBRKANA

PBRKANA
PVSENSE

PBIDIR
PVDD
RTO
SNS
DVDD

With Liberty With UPF

© Accellera Systems Initiative 24
LIBRARY VALIDATION FLOW
 Problem Statement
• Missing/wrong attributes results in simulation failure
– Incorrect power_down_function (PDF) or
related_power/ground_pin attribute
• Unexpected signal corruption
– Incorrect special cell attributes
• Policy to cell mapping will not happen
• Correct library view doesn’t guarantee correct
simulation behaviour due to
– Wrong interpretation by Simulator
– UPF standard limitation
PA Simulation – Library Level Check
Product Library Cell based Templates

Validation LP
Liberty(UPF) Verilog
UPF vectors

Design UPF
Verilog Testbench
containing all
cells
containing all cells

Simulation

Library Validation
 Validation UPF
create_power_domain Paon -supply {AONSupply}
create_power_domain Psw -supply {SWSupply} \
-elements { u1}
create_power_switch uVDDsw -domain Psw \
VDD
-input_supply_port {in AONSupply.power} \
-output_supply_port {out SWSupply.power} \
-control_port {sw_ctr VDD} \
-on_state {on_state in {sw_ctr}} \
RETN -off_state {off_state {!sw_ctr}}
create_power_switch uVSSsw -domain Psw \
(switchable) -input_supply_port {in AONSupply.ground} \
VDDsw = 1.0 -output_supply_port {out SWSupply.ground} \
VSSsw = 0.0 -control_port {sw_ctr VSS} \
-on_state {on_state in {!sw_ctr}} \
VSS -off_state {off_state {sw_ctr}}
set_retention uretain -domain Psw \
(always on) -retention_supply_set AONSupply
VDDon = 1.0 -save_signal {RETN high} \
VSSon = 0.0 -restore_signal {RETN low}
 Testbench and LP Vectors
module TEST_DRFFQ_X1_0; LP Vectors
wire VDDG, VSSG, VDD, VSS;
wire RETN, D, CK, Q_exp; V V V V D C R Q
D S D S K E
DRFFQ_X1 u1 (.VDD(VDD), .VSS(VSS), D S D S T
.RETN(RETN), .D(D), .CK(CK), .Q(Q)); G G N
always @(VDDG) 1 0 1 0 0 0 1 0
if(VDDG) pg_VDD = supply_on("u1/VDDon",1.0);
else pg_VDD = supply_off("u1/VDDon");
1 0 1 0 0 1 1 0
1 0 1 0 1 0 1 1
assign {VDDG, VSSG, VDD, VSS, RETN, D, CK, Q_exp}
= presentVector; 1 0 1 0 1 1 1 1
Save
1 0 1 0 1 0 0 1
initial begin Power off
$readmemb(vector_file,tstvector,0,depth-1); 1 0 0 0 x x 0 x
for (n=0; n<depth; n=n+1) Power on
presentVector = tstvector[n];
1 0 1 0 x 0 0 1
Restore
if (Q !== Q_exp) $display("Mismatch”); 1 0 1 0 x 0 1 1
end
endmodule
 Summary
• PA simulation is a very powerful way to check the design
power requirement early in the implementation cycle
• PA simulation is still in early phase and with increasing
complexity, more check points need to be put in place to
catch issues
• Identified enhancements fix some of the quality holes in
existing PA simulation flow
• Library validation flow enables ARM to carry out
comprehensive verification of cell power aware
behaviour, thereby ensuring seamless PA simulation flow
for our partners

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 Questions?

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