VLSI Lab Report

Submitted By:

Ajith.A
M.Tech (Electronics)
First Semester, Digital Electronics
DOE, CUSAT
Program

--------------------------------------------------------------------------------
-- Module Name: Basic_gates - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION

entity basic_gates is
Port ( a : in bit;
b : in bit;
and_op : out bit;
or_op : out bit;
xor_op : out bit;
inv_op_a : out bit;
inv_op_b : out bit);
end basic_gates;

--ARCHITECTURE DECLARATION

architecture Behavioral of basic_gates is

begin
process(a,b)
begin
and_op <= a and b;
or_op <= a or b;
xor_op <= a xor b;
inv_op_a <= not a;
inv_op_b <= not b;
end process;
end Behavioral;
Test Bench:

--------------------------------------------------------------------------------
-- Design Name: basic_gates
-- Module Name: testbench.vhd
-- Project Name: Basic_Gates
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION

ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION

ARCHITECTURE behavior OF testbench_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT basic_gates
PORT(
a : IN bit;
b : IN bit;
and_op: OUT bit;
or_op : OUT bit;
xor_op : OUT bit;
inv_op_a : OUT bit;
inv_op_b : OUT bit
);
END COMPONENT;

--INTERMEDIATE SIGNALS
--Inputs
SIGNAL a : bit := '0';
SIGNAL b : bit := '0';
--Outputs
SIGNAL and_op : bit;
SIGNAL or_op : bit;
SIGNAL xor_op : bit;
SIGNAL inv_op_a : bit;
 SIGNAL inv_op_b : bit;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: basic_gates PORT MAP(
a => a,
b => b,
and_op => and_op,
or_op => or_op,
xor_op => xor_op,
inv_op_a => inv_op_a,
inv_op_b => inv_op_b
);
tb : PROCESS
BEGIN
wait for 10 ns;
a <= '1';
b <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
wait for 10 ns;
a <= '0';
b <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
wait for 10 ns;
a <= '0';
b <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
wait for 10 ns;
 a <= '0';
b <= '1';
wait for 10 ns;
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: Univ_Gates - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION

entity Univ_Gates is
Port (a : in std_logic;
b : in std_logic;
nor_op : out std_logic;
nand_op : out std_logic;
xnor_op : out std_logic);
end Univ_Gates;

--ARCHITECTURE DECLARATION

architecture Behavioral of Univ_Gates is

begin
process(a,b) is
begin
nor_op <= a nor b;
nand_op <= a nand b;
xnor_op <= a xnor b;
end process;
end Behavioral;
Test Bench:

--------------------------------------------------------------------------------
-- Design Name: univ_gates
-- Module Name: testbench.vhd
-- Project Name: Universal_Gates
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION

ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION

ARCHITECTURE behavior OF testbench_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT univ_gates
PORT( a : IN std_logic;
b : IN std_logic;
nor_op : OUT std_logic;
nand_op : OUT std_logic;
xnor_op : OUT std_logic
);
END COMPONENT;

--INTERMEDIATE SIGNALS
--Inputs
SIGNAL a : std_logic := '0';
SIGNAL b : std_logic := '0';
--Outputs
SIGNAL nor_op : std_logic;
SIGNAL nand_op : std_logic;
SIGNAL xnor_op : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: univ_gates PORT MAP(
a => a,
b => b,
nor_op => nor_op,
nand_op => nand_op,
xnor_op => xnor_op
);

tb : PROCESS
BEGIN
wait for 10 ns;
a <= '1';
b <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
wait for 10 ns;
a <= '0';
b <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
wait for 10 ns;
a <= '1';
b <= '1';
wait for 10 ns;
a <= '0';
b <= '0';
wait for 10 ns;
a <= '1';
b <= '0';
wait for 10 ns;
a <= '0';
b <= '1';
wait for 10 ns;
 wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: 4x1 Mux - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION

entity Mux is
Port (
a : in std_logic_vector(2 downto 0);
b : in std_logic_vector(2 downto 0);
c : in std_logic_vector(2 downto 0);
d : in std_logic_vector(2 downto 0);
sel : in std_logic_vector(1 downto 0);
y : out std_logic_vector(2 downto 0));
end Mux;

--ARCHITECTURE DECLARATION

architecture Behavioral of Mux is

begin
process (a,b,c,d,sel)
begin
case sel is
when "00" =>
y <= a;
when "01" =>
y <= b;
when "10" =>
y <= c;
when "11" =>
y <= d;
when others =>
y <= "000";
end case;
end process;
end Behavioral;
Test Bench:

--------------------------------------------------------------------------------
-- Design Name: Mux
-- Module Name: testbench.vhd
-- Project Name: 4x1 Mux
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION

ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION

ARCHITECTURE behavior OF testbench_vhd IS

-- Component Declaration for the Unit Under Test (UUT)
COMPONENT mux
PORT(
a : IN std_logic_vector(2 downto 0);
b : IN std_logic_vector(2 downto 0);
c : IN std_logic_vector(2 downto 0);
d : IN std_logic_vector(2 downto 0);
sel : IN std_logic_vector(1 downto 0);
y : OUT std_logic_vector(2 downto 0)
);
END COMPONENT;

--INTERMEDIATE SIGNALS
--Inputs
SIGNAL a : std_logic_vector(2 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(2 downto 0) := (others=>'0');
SIGNAL c : std_logic_vector(2 downto 0) := (others=>'0');
SIGNAL d : std_logic_vector(2 downto 0) := (others=>'0');
SIGNAL sel : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL y : std_logic_vector(2 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: mux PORT MAP(
a => a,
b => b,
c => c,
d => d,
sel => sel,
y => y
);

tb : PROCESS
BEGIN
wait for 10 ns;
a <= "111";
b <= "110";
c <= "100";
d <= "101";
sel <= "00";
wait for 10 ns;
sel <= "01";
wait for 10 ns;
sel <= "10";
wait for 10 ns;
sel <= "11";
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: Two_Four_Dec - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION

entity Two_Four_Dec is
Port (
a : in std_logic_vector(1 downto 0);
clk : in std_logic;
reset : in std_logic;
y0 : out std_logic;
y1 : out std_logic;
y2 : out std_logic;
y3 : out std_logic);
end Two_Four_Dec;

--ARCHITECTURE DECLARATION

architecture Behavioral of Two_Four_Dec is

begin
process(clk,reset,a)
begin
if ( reset = '1') then
y0 <= '0';
y1 <= '0';
y2 <= '0';
y3 <= '0';
elsif ( clk'event and clk = '1') then
case a is
when "00" =>
y0 <= '1';
y1 <= '0';
y2 <= '0';
y3 <= '0';
when "01" =>
 y0 <= '0';
y1 <= '1';
y2 <= '0';
y3 <= '0';
when "10" =>
y0 <= '0';
y1 <= '0';
y2 <= '1';
y3 <= '0';
when "11" =>
y0 <= '0';
y1 <= '0';
y2 <= '0';
y3 <= '1';
when others =>
y0 <= '0';
y1 <= '0';
y2 <= '0';
y3 <= '0';
end case;
end if;
end process;
end Behavioral;

Test Bench:

--------------------------------------------------------------------------------
-- Design Name: two_four_dec
-- Module Name: testbench.vhd
-- Project Name: Two_Four_Dec
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION

ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION

ARCHITECTURE behavior OF testbench_vhd IS

 -- Component Declaration for the Unit Under Test (UUT)
COMPONENT two_four_dec
PORT(
a : IN std_logic_vector(1 downto 0);
clk : IN std_logic;
reset : IN std_logic;
y0 : OUT std_logic;
y1 : OUT std_logic;
y2 : OUT std_logic;
y3 : OUT std_logic
);
END COMPONENT;

--INTERMEDIATE SIGNALS
--Inputs
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
SIGNAL a : std_logic_vector(1 downto 0) := (others=>'0');
--Outputs
SIGNAL y0 : std_logic;
SIGNAL y1 : std_logic;
SIGNAL y2 : std_logic;
SIGNAL y3 : std_logic;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: two_four_dec PORT MAP(
a => a,
clk => clk,
reset => reset,
y0 => y0,
y1 => y1,
y2 => y2,
y3 => y3
);

tb : PROCESS
BEGIN
wait for 10 ns;
a <= "00";
clk <= '1';
wait for 10 ns;
 clk <= '0';
wait for 10 ns;
a <= "01";
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
reset <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
reset <= '0';
a <= "10";
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
a <= "11";
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: N_Bit_Adder - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION

entity N_Bit_Adder is
generic(N : integer := 8);
Port (
a : in std_logic_vector(N downto 1);
b : in std_logic_vector(N downto 1);
cin : in std_logic;
sum : out std_logic_vector(N downto 1);
cout : out std_logic);
end N_Bit_Adder;

--ARCHITECTURE DECLARATION
architecture Behavioral of N_Bit_Adder is
begin
p1: process(a, b, cin)
variable vsum : std_logic_vector(N downto 1);
variable carry : std_logic;
begin
carry := cin;
for i in 1 to N loop
vsum(i) := (a(i) xor b(i)) xor carry;
carry := ( (a(i) and b(i) ) or (b(i) and carry) or (a(i) and carry) );
end loop;
sum <= vsum;
cout <= carry;
end process p1;
end Behavioral;
Test Bench:

--------------------------------------------------------------------------------
-- Design Name: n_bit_adder
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION
ENTITY testbench_vhd IS
generic(N : integer := 8);
END testbench_vhd;

--ARCHITECTURE DECLARATION
ARCHITECTURE behavior OF testbench_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT n_bit_adder
PORT(
a : IN std_logic_vector(N downto 1);
b : IN std_logic_vector(N downto 1);
cin : IN std_logic;
sum : OUT std_logic_vector(N downto 1);
cout : OUT std_logic
);
END COMPONENT;

--INTERMEDIATE SIGNALS
--Inputs
SIGNAL cin : std_logic := '0';
SIGNAL a : std_logic_vector(N downto 1) := (others=>'0');
SIGNAL b : std_logic_vector(N downto 1) := (others=>'0');
--Outputs
SIGNAL sum : std_logic_vector(N downto 1);
SIGNAL cout : std_logic;

BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: n_bit_adder PORT MAP(
a => a,
b => b,
cin => cin,
sum => sum,
cout => cout
);
 tb : PROCESS
BEGIN
wait for 10 ns;
a <= "11111010";
b <= "10101111";
wait for 10 ns;
a <= "10101010";
b <= "11101111";
wait for 10 ns;
a <= "11010101";
b <= "10101100";
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: N_bit_Comparator - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION
entity N_bit_Comparator is
Generic (n : natural:= 4);
Port (
a : in std_logic_vector((n-1)downto 0);
b : in std_logic_vector((n-1)downto 0);
less : out std_logic;
equal : out std_logic;
greater : out std_logic);
end N_bit_Comparator;

--ARCHITECTURE DECLARATION
architecture Behavioral of N_bit_Comparator is
begin
process (a,b)
begin
if (a>b) then
greater <='1';
less <='0';
equal <='0';
elsif (a<b) then
greater <='0';
less <='1';
equal <='0';
else
greater <='0';
less <='0';
equal <='1';
end if;
end process;
end Behavioral;
Test Bench:
--------------------------------------------------------------------------------
-- Design Name: n_bit_comparator
-- Module Name: testbench.vhd
-- Project Name: N_Bit_Comparator
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION
ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION
ARCHITECTURE behavior OF testbench_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT n_bit_comparator
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
less : OUT std_logic;
equal : OUT std_logic;
greater : OUT std_logic
);
END COMPONENT;
--INTERMEDIATE SIGNALS
--Inputs
SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL less : std_logic;
SIGNAL equal : std_logic;
SIGNAL greater : std_logic;
BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: n_bit_comparator PORT MAP(
a => a,
b => b,
less => less,
equal => equal,
greater => greater
);
 tb : PROCESS
BEGIN
wait for 10 ns;
a <= "1001";
b <= "0010";
wait for 10 ns;
a <= "0001";
b <= "1110";
wait for 10 ns;
a <= "1011";
b <= "1011";
wait for 10 ns;
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: multiplier - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION
entity multiplier is
Port (
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
result : out std_logic_vector(7 downto 0));
end multiplier;

--ARCHITECTURE DECLARATION
architecture Behavioral of multiplier is
begin
process(a,b)
variable d,t : std_logic_vector(7 downto 0);
begin
d := "00000000";
t := "00000000";
while t < a loop
d := d + b;
t := t + '1';
end loop;
result <= d;
end process;
end Behavioral;
Test Bench:

--------------------------------------------------------------------------------
-- Design Name: multiplier
-- Module Name: testbench.vhd
-- Project Name: Multiplier
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION
ENTITY testbench_vhd IS
END testbench_vhd;
--ARCHITECTURE DECLARATION
ARCHITECTURE behavior OF testbench_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT multiplier
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
result : OUT std_logic_vector(7 downto 0)
);
END COMPONENT;
--INTERMEDIATE SIGNALS
--Inputs
SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL result : std_logic_vector(7 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: multiplier PORT MAP(
a => a,
b => b,
result => result
);
tb : PROCESS
BEGIN
wait for 10 ns;
a <= "0100";
 b <= "1001";
wait for 10 ns;
a <= "1000";
b <= "1000";
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: ALU - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION

entity ALU is
Port (
a : in std_logic_vector(3 downto 0);
b : in std_logic_vector(3 downto 0);
cin : in std_logic;
sel : in std_logic_vector(3 downto 0);
y : out std_logic_vector(3 downto 0));
end ALU;

--ARCHITECTURE DECLARATION

architecture Behavioral of ALU is

signal arith_result,logic_result : std_logic_vector(3 downto 0);
begin
-----ARITHMETIC UNIT-------
with sel(2 downto 0) select
arith_result <= a+1 when "000",
a-1 when "001",
b+1 when "010",
b-1 when "011",
a+b when "100",
a when "101",
b when "110",
a+b+cin when others;

-----LOGICAL UNIT-------
with sel(2 downto 0) select
logic_result <= NOT a when "000",
NOT b when "001",
 a AND b when "010",
a OR b when "011",
a NAND b when "100",
a NOR b when "101",
a XOR b when "110",
NOT(a XOR b) when others;

------MUX-------
with sel(3) select
y <= arith_result when '0',
logic_result when others;
end Behavioral;

Test Bench:

--------------------------------------------------------------------------------
-- Design Name: alu
-- Module Name: testbench.vhd
-- Project Name: ALU
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION
ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION
ARCHITECTURE behavior OF testbench_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT alu
PORT(
a : IN std_logic_vector(3 downto 0);
b : IN std_logic_vector(3 downto 0);
cin : IN std_logic;
sel : IN std_logic_vector(3 downto 0);
y : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--INTERMEDIATE SIGNALS
--Inputs
SIGNAL cin : std_logic := '0';
 SIGNAL a : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL b : std_logic_vector(3 downto 0) := (others=>'0');
SIGNAL sel : std_logic_vector(3 downto 0) := (others=>'0');

--Outputs
SIGNAL y : std_logic_vector(3 downto 0);
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: alu PORT MAP(
a => a,
b => b,
cin => cin,
sel => sel,
y => y
);
tb : PROCESS
BEGIN
wait for 10 ns;
a <= "1100";
b <= "1010";
cin <= '1';
sel <= "0000";
wait for 10 ns;
a <= "1100";
b <= "1010";
cin <= '1';
sel <= "1000";
wait for 10 ns;
a <= "1100";
b <= "1010";
cin <= '1';
sel <= "0010";
wait for 10 ns;
a <= "1100";
b <= "1010";
cin <= '1';
sel <= "0100";
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: RAM - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
-- ENTITY DECLARATION
entity RAM is
generic(
width : integer := 4;
depth : integer := 4;
addr : integer := 2);
Port ( Clock : in std_logic;
Enable : in std_logic;
Read : in std_logic;
Write : in std_logic;
Read_Addr : in std_logic_vector((addr-1) downto 0);
Write_addr : in std_logic_vector((addr-1) downto 0);
Data_in : in std_logic_vector((width-1) downto 0);
Data_out : out std_logic_vector((width-1) downto 0));
end RAM;
--ARCHITECTURE DECLARATION
architecture Behavioral of RAM is
type ram_type is array(0 to depth-1) of std_logic_vector(width-1 downto 0);
signal tmp_ram : ram_type;
begin
-- Read Functional Section
process(Clock,Read)
begin
if(Clock'event and Clock = '1') then
if(Enable = '1') then
if (Read = '1') then
-- building function conv_integer change the type
-- from std_logic_vector to integer
Data_out <= tmp_ram(conv_integer(Read_Addr));
else
Data_out <= (Data_out'range => 'Z');
end if;
end if;
 end if;
end process;
-- Write Functional Section
process(Clock,Write)
begin
if(Clock'event and Clock = '1') then
if(Enable = '1') then
if (Write = '1') then
tmp_ram(conv_integer(Write_Addr)) <= Data_in;
end if;
end if;
end if;
end process;
end Behavioral;

Test Bench:
--------------------------------------------------------------------------------
-- Design Name: ram
-- Module Name: testbench.vhd
-- Project Name: RAM
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION
ENTITY testbench_vhd IS
END testbench_vhd;
--ARCHITECTURE DECLARATION
ARCHITECTURE behavior OF testbench_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT ram
PORT(
Clock : IN std_logic;
Enable : IN std_logic;
Read : IN std_logic;
Write : IN std_logic;
Read_Addr : IN std_logic_vector(1 downto 0);
Write_addr : IN std_logic_vector(1 downto 0);
Data_in : IN std_logic_vector(3 downto 0);
Data_out : OUT std_logic_vector(3 downto 0)
);
END COMPONENT;
--INTERMEDIATE SIGNALS
--Inputs
SIGNAL Clock : std_logic := '0';
SIGNAL Enable : std_logic := '0';
SIGNAL Read : std_logic := '0';
SIGNAL Write : std_logic := '0';
SIGNAL Read_Addr : std_logic_vector(1 downto 0) := (others=>'0');
SIGNAL Write_addr : std_logic_vector(1 downto 0) := (others=>'0');
SIGNAL Data_in : std_logic_vector(3 downto 0) := (others=>'0');
--Outputs
SIGNAL Data_out : std_logic_vector(3 downto 0);

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: ram PORT MAP(
Clock => Clock,
Enable => Enable,
Read => Read,
Write => Write,
Read_Addr => Read_Addr,
Write_addr => Write_addr,
Data_in => Data_in,
Data_out => Data_out
);

Clk_sig: process --clock cycle 10 ns

begin
Clock <= '1';
wait for 5 ns;
Clock <= '0';
wait for 5 ns;
end process;

tb : PROCESS
BEGIN
wait for 10 ns;
Enable <= '1';
for i in 0 to 3 loop
Write_addr <= Write_addr+ '1';
Data_in <= Data_in + "10";
Write <= '1';
wait for 10 ns;
end loop;
 for i in 0 to 2 loop
Read_addr <= Read_addr+ '1';
Write <= '0';
Read <= '1';
wait for 10 ns;
end loop;
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: D-Latch - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION
entity Latch is
Port (
D : in std_logic;
EN : in std_logic;
Yout : out std_logic);
end Latch;

--ARCHITECTURE DECLARATION
architecture Behavioral of Latch is
begin
process (D,EN)
begin
if (EN = '1') then
if (D = '1') then
Yout <= '1';
else
Yout <= '0';
end if;
else
Yout <= '0';
end if;

end process;
end Behavioral;
Test Bench:
--------------------------------------------------------------------------------
-- Design Name: D-Latch
-- Module Name: testbench.vhd
-- Project Name: D-Latch
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION
ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION
ARCHITECTURE behavior OF testbench_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT latch
PORT(
D : IN std_logic;
EN : IN std_logic;
Yout : OUT std_logic
);
END COMPONENT;
--INTERMEDIATE SIGNALS
--Inputs
SIGNAL D : std_logic := '0';
SIGNAL EN : std_logic := '1';
--Outputs
SIGNAL Yout : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: latch PORT MAP(
D => D,
EN => EN,
Yout => Yout
);
tb : PROCESS
BEGIN
wait for 10 ns;
d <= '0';
wait for 10 ns;
d <= '1';
wait for 10 ns;
EN <= '0';
wait for 10 ns;
d <= '1';
wait for 10 ns;
d <= '0';
wait for 10 ns;
EN <= '1';
wait for 10 ns;
d <= '1';
wait for 10 ns;
d <= '0';
wait for 10 ns;
d <= '1';
wait for 10 ns;
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: D_FF - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION
entity D_FF is
Port ( d : in std_logic;
clk : in std_logic;
reset : in std_logic;
y : out std_logic);
end D_FF;

--ARCHITECTURE DECLARATION
architecture Behavioral of D_FF is
begin
process (clk, reset)
begin
if reset = '1' then
y <= '0';
elsif (clk'event and clk = '1') then
y <= d;
end if;
end process;
end Behavioral;

Test Bench:

--------------------------------------------------------------------------------
-- Design Name: D_FF
-- Module Name: testbench.vhd
-- Project Name: D_FF
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
-- ENTITY DECLARATION
ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION
ARCHITECTURE behavior OF testbench_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT d_ff
PORT(
d : IN std_logic;
clk : IN std_logic;
reset : IN std_logic;
y : OUT std_logic
);
END COMPONENT;
--INTERMEDIATE SIGNALS
--Inputs
SIGNAL d : std_logic := '0';
SIGNAL clk : std_logic := '0';
SIGNAL reset : std_logic := '0';
--Outputs
SIGNAL y : std_logic;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: d_ff PORT MAP(
d => d,
clk => clk,
reset => reset,
y => y
);
tb : PROCESS
BEGIN
wait for 10 ns;
clk <= '1';
d <= '0';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
d <= '1';
wait for 10 ns;
 clk <= '0';
reset <= '1';
wait for 10 ns;
clk <= '1';
d <= '0';
wait for 10 ns;
clk <= '0';
reset <= '0';
wait for 10 ns;
clk <= '1';
d <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
d <= '1';
wait for 10 ns;
clk <= '0';
reset <= '1';
wait for 10 ns;
clk <= '1';
d <= '0';
wait for 10 ns;
clk <= '0';
reset <= '0';
wait for 10 ns;
clk <= '1';
d <= '1';
wait for 10 ns;
wait; -- will wait forever
END PROCESS;
END;

Output:
Program:

--------------------------------------------------------------------------------
-- Module Name: JK_FF - Behavioral
--------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

-- ENTITY DECLARATION
entity JK_FF is
Port (
J : in bit;
K : in bit;
clk : in bit;
reset : in bit;
y : out bit);
end JK_FF;
--ARCHITECTURE DECLARATION
architecture Behavioral of JK_FF is
signal y1 : bit := '0';
begin
process (clk,reset)
begin
if reset = '0' then
y1 <= '0';
y <= '0';
elsif (clk'event and clk = '1') then
if ((J = '0') and (K = '0')) then
-- no change at the output
elsif ((J = '0') and (K = '1')) then
y1 <= '0';
y <= '0';
elsif ((J = '1') and (K = '0')) then
y1 <= '1';
y <= '1';
elsif ((J = '1') and (K = '1')) then
y1 <= not(y1);
y <= not(y1);
end if;
end if;
 end process;
end Behavioral;
Test Bench:

--------------------------------------------------------------------------------
-- Design Name: JK_FF
-- Module Name: testbench.vhd
-- Project Name: JK_FF
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

-- ENTITY DECLARATION
ENTITY testbench_vhd IS
END testbench_vhd;

--ARCHITECTURE DECLARATION
ARCHITECTURE behavior OF testbench_vhd IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT jk_ff
PORT(
J : IN bit;
K : IN bit;
clk : IN bit;
reset : IN bit;
y : OUT bit
);
END COMPONENT;
--INTERMEDIATE SIGNALS
--Inputs
SIGNAL J : bit := '0';
SIGNAL K : bit := '0';
SIGNAL clk : bit := '0';
SIGNAL reset : bit := '1';
--Outputs
SIGNAL y : bit;
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: jk_ff PORT MAP(
J => J,
K => K,
clk => clk,
reset => reset,
y => y
);

tb : PROCESS
BEGIN
wait for 10 ns;
--TC 1
clk <= '1';
J <= '0';
K <= '0';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
J <= '1';
K <= '0';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
J <= '0';
K <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
J <= '1';
K <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
-- TC 2
reset <= '0';
clk <= '1';
wait for 10 ns;
 clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
-- TC 3
reset <= '1';
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
--TC 4
clk <= '1';
J <= '0';
K <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
J <= '0';
K <= '0';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
J <= '1';
K <= '0';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
clk <= '1';
J <= '1';
K <= '1';
wait for 10 ns;
clk <= '0';
wait for 10 ns;
wait; -- will wait forever
END PROCESS;
END;
Output: