Paper Presentation

On
Programming FPGA's
Using Handel-C

Submitted By

Balasaheb S.Darade Tarun A.Parmar

T.E. Electronics & Telecomm. T.E. Electronics & Telecomm.

Abhishek Singh Chauhan

T.E. Computer Science Engg.

Jawaharlal Nehru Engineering College

Aurangabad
 ABSTRACT

Availability of reprogrammable technologies has enabled the configuration of

flexible system allowing runtime configuration of system hardware and software
This paper presents the benefits of programming FPGA using Handel-C. The design
methodology combines a C-based software design targeting FPGAs as a device and rapid
FPGA hardware design flow based on Handel-C, a C-like programmable language.
FPGAs provide the benefits of custom CMOS VLSI design while avoiding the
initial cost, time delay and inherent risk of a conventional masked gate array. They are
customized by loading configuration data into the internal memory cell.
RAM based FPGA's can be infinitely reprogrammed in-circuit in only a fraction
of seconds. Design revisions even for fielded products can be implemented quickly and
precisely.
Taking advantage of reconfiguration can also reduce hardware and because of
that, they are becoming part of every system design.
So here we are using Handel-C for programming FPGA's. By targeting FPGA's
directly, Handel-C provides a fast route for hardware prototyping and development of
electronics products.
Basically it is a C-based innovative language for implementing algorithms in
hardware (FPGA's) architectural design and hardware, software co-design.
Since it supports a large set of ANSI-C constructs, easy porting between two
languages is possible.
Imperative nature of Handel-C also makes it easier to debug and upgrade the
hardware design.
Due to Handel-C's high-level nature it makes possible for the same person to do both
hardware and software implementation. Thus greatly reduces the development cost.
Explicit parallelism, well defined timing, high-level alternative, behavioral
compilation, C-based approach are some features which makes Handel-C reliable for
programming the FPGA's more efficiently.
For the fulfillment of above matter we have provided the Real-World
implementations where FPGA's are programmed using Handel-C
 Contents

Introduction 01
 SPLD
 CPLD
 FPGA
Classes of FPGA
Different Technologies Used
 Static RAM(SRAM) Technology
 Anti-Fuse Technology
 EPROM Technology
 EEPROM Technology

Handel-C 06
The Language
Similarities with ANSI-C
Design Procedure
Comparison between Handel-C and VHDL
A C-based Language Approach
The Deign Environment
-DK1 Design Suite
Predefined Hardware Libraries
Benefits of using Handel-C

Implementations 13
 A Real-World FPGA Design Example
 Converting MP3 Software to Hardware
 Hardware Implementation of Communications
Protocol in a “Voice Over IP” Phone

Conclusion 22

References 23
 Introduction
Programmable logic is loosely defined as a device with configurable logic and
flip-flops linked together with programmable interconnect. Memory cells control and
define the function that the logic performs and how the various logic functions are
interconnected. Though various devices use different architectures, all are based on this
fundamental idea.
There are a few major programmable logic architecture available today. Each architecture
typically has vendor-specific sub-variants within each type. The major types include:
 Simple Programmable Logic Devices (SPLDs),
 Complex Programmable Logic Devices (CPLDs), and
 Field Programmable Gate Arrays (FPGAs)
 Field Programmable InterConnect (FPICs)
SPLD - Simple Programmable Logic Device
Also known as:
 PAL (Programmable Array Logic, Vantis)

 GAL (Generic Array Logic, Lattice)

 PLA (Programmable Logic Array)

 PLD (Programmable Logic Device)

SPLDs are the smallest and consequently the least-expensive form of programmable
logic. An SPLD is typically comprised of four to 22 macrocells and can typically replace
a few 7400-series TTL devices. Each of the macrocells is typically fully connected to the
others in the device. Most SPLDs use either fuses or non-volatile memory cells such as
EPROM, EEPROM, or FLASH to define the functionality.
CPLD - Complex Programmable Logic Device
Also known as:
 EPLD (Erasable Programmable Logic Device)

 PEEL

 EEPLD (Electrically-Erasable Programmable Logic Device)

 MAX (Multiple Array matriX, Altera)

CPLDs are similar to SPLDs except that they are significantly higher capacity. A
typical CPLD is the equivalent of two to 64 SPLDs. A CPLD typically contains from tens
to a few hundred macrocells. A group of eight to 16 macrocells is typically grouped
together into a larger function block. The macrocells within a function block are usually
fully connected. If a device contains multiple function blocks, then the function blocks
are further interconnected. Not all CPLDs are fully connected between function blocks-
this is vendor and family specific. Less that 100% connection between function blocks
means that there is a chance that the device will not route or may have problems keeping
the same pinout between design revisions.
In concept, CPLDs consist of multiple PAL-like logic blocks interconnected together
via a programmable switch matrix. Typically, each logic block contains 4 to 16
macrocells, depending on the architecture.
FPGA - Field Programmable Gate Array
FPGA is a silicon chip with unconnected logic gates. It is an integrated circuit that
contains many (64 to over 10,000) identical logic cells that can be viewed as standard
components. The individual cells are interconnected by a matrix of wires and
programmable switches. Field Programmable means that the FPGA's function is defined
by a user's program rather than by the manufacturer of the device. Depending on the
particular device, the program is either 'burned' in permanently or semi-permanently as
part of a board assembly process, or is loaded from an external memory each time the
device is powered up.

The FPGA
The FPGA has three major configurable elements: configurable logic blocks
(CLBs), input/output blocks, and interconnects. The CLBs provide the functional
elements for constructing user's logic. The IOBs provide the interface between the
package pins and internal signal lines. The programmable interconnect resources provide
routing paths to connect the inputs and outputs of the CLBs and IOBs onto the
appropriate networks.

The Field-Programmable Gate Arrays (FPGAs) provide the benefits of custom

CMOS VLSI, while avoiding the initial cost, time delay, and inherent risk of a
conventional masked gate array. The FPGAs are customized by loading configuration
data into the internal memory cells.
 Complex Programmable Logic Devices (CPLDs) and Field Programmable Gate
Arrays (FPGAs) are becoming a critical part of every system design. There are many
different FPGAs with different architectures / processes but all of them have the same
common feature: that the layout of unit is repeated in matrix form. In this case, the unit is
consisting of PLDs, logic gates, RAM, and many other type of components.
There are four main classes of FPGAs currently commercially available:
symmetrical array, row-based, hierarchical PLD, and sea-of-gates.

In all of these FPGAs the interconnections and how they are programmed vary.
Currently there are four technologies in use. They are: static RAM cells, anti-fuse,
EPROM transistors, and EEPROM transistors. Depending upon the application, one
FPGA technology may have features desirable for that application.

Static RAM Technology

In the Static RAM FPGA programmable connections are made using pass-
transistors, transmission gates, or multiplexers that are controlled by SRAM cells. This
technology allows allows fast in-circuit reconfiguration. The major disadvantage is the
size of the chip required by the RAM technology and that the chip configuration needs to
be loaded to the chip from some external source (usually external non-volatile memory
chip). The FPGA can either actively read its configuration data out of external serial or
byte-parallel PROM (master mode), or the configuration data can be written into the
FPGA (slave and peripheral mode). The FPGA can be programmed an unlimited number
of times.
 Anti-Fuse Technology

An anti-fuse resides in a high-impedance state; and can be programmed into low

impedance or "fused" state. This technology can be used to make program once devices
that are less expensive than the RAM technology.

EPROM Technology

This method is the same as used in the EPROM memories. The programming is
stored without external storage of configuration. EPROM based programmable chip
cannot be re-programmed in-circuit and need to be cleared with UV erasing.

Characteristics of FPGA Technology

Technology Volatile Re-Prog Chip Area R (ohm) C (ff)
Static RAM Yes in-circuit Large 1 -2 K 10 - 20 ff
PLICE Anti- anti-fuse --- small -------
No No 300 - 500 3 – 5 ff
Fuse - prog. trans.--- large
ViaLink Anti- anti-fuse --- small -------
No No 50 - 60 3 – 5 ff
Fuse - prog. trans.--- large
out of
EPROM No Small 2-4k 10 -20 ff
circuit
out of
EEPROM No 2x EPROM 2-4k 10 -20 ff
circuit

EEPROM Technology

This method is the same as used in the EEPROM memories. The programming is
stored without external storage of configuration. EEPROM based programmable chips
can be electrically erased but generally cannot be re-programmed in-circuit.

Commerical FPGAs
Company Architecture Logic Block Type Programming Technology
Actel Row-based Multiplexer-Based anti-fuse
Altera Hierarchial-PLD PLD Block EPROM
QuickLogic Symmetrical Array Multiplexer-Based anti-fuse
Xilinx Symmetrical Array Look-up Table Static RAM

Many emerging applications in communication, computing and consumer

electronics industries demand that their functionality stays flexible after the system has
been manufactured. Such flexibility is required in order to cope with changing user
requirements, improvements in system features, changing protocol and data-coding
standards, demands to support variety of different user applications, etc.
An FPGA has a large number of these cells available to use as building blocks in
complex digital circuits. Custom hardware has never been so easy to develop. Like
microprocessors, RAM based FPGAs can be infinitely reprogrammed in-circuit in only a
fraction of a second. Design revisions, even for a fielded product, can be implemented
quickly and painlessly. Taking advantage of reconfiguration can also reduce hardware.
Although reconfigurable FPGA technologies have been commercially available
for over a decade, the number of available tools capable of supporting reconfigurable
system design is still very limited. Many such existing tools are based on conventional
static FPGA design flows, and demand expert skills and improvisation in order to
produce a working reconfigurable system. FPGAs are extremely cost-effective at
surprisingly high production volumes FPGA makes simple FIFO - FPGA-based,
synchronous FIFO that uses the same clock for read and write operations.
Logic networks realized in FPGA are slower by two or three orders of magnitude
than those realized in full custom design, but are much faster by several orders than
simulation of logic functions by software. Even application programmers can be run on
FPGAs and performed much faster than on general purpose computers in many cases.
With FPGAs, debugging or prototyping of new design can be done as easily and quickly
as software.
As the price of FPGAs goes down with higher speed, FPGAs are replacing other
semi-custom design approaches in many applications. If we order semiconductor
manufacturer to make ASIC, CMOS VLSI, we have to wait several weeks and pay
twenty thousand to hundreds of thousands of dollars. But with FPGAs we can program
FPGAs in minutes by ourselves and need to pay in few tens of dollars. But FPGA can be
pack only about one-tenth of the number of logic gates in ASIC, CMOS VLSI because
devices for user programmability such as SRAMs, non-volatile memory, and anti-fuses,
take-up large areas. Thus, for debugging or verifying logic design that needs to be done
quickly, FPGAs are used, and then ASIC,CMOS VLSI are used for large volume
production after completing debugging or verification.
 Handel-C
The Language
Handel-C is a truly innovative language for implementing algorithms in hardware,
architectural design space exploration, and hardware/software co-design. Based on
ISO/ANSI-C, it has extensions required for hardware development. Therefore programs
designed for Handel-C, are inherently sequential. It includes flexible data widths, parallel
processing and communications between parallel elements. The language is designed
around a simple timing model that makes it very accessible to system architects and
software engineers.
Handel-C provides special constructs, which enable expressions to be evaluated in
parallel. It also provides the ability to specify the width of a data variable.

Sequential Expressions Parallel Expressions

{
..... par {
a = 1; a = 1;
b = 2; b = 2;
..... }
}
This executes the two statements, This executes both statements in
one after the other sequentially parallel
Handel-C also enables the use of user defined variable sizes. E.g.:-

Int n x;
This defines a variable x of type int and size of n
bits.
When expressions are evaluated in parallel, communication between the parallel
branches becomes a problem due to synchronization. Handel-C provides a design
construct known as a channel to get around this.

Similarities with ANSI C

Handel-C has many similarities with C. At the same time Handel-C has many
features which are not found in C and vice versa. Handel-C doesn't support a large
variety of data types as C does, the only data types supported by Handel-C are Integers
and Characters. But unlike C, the users can specify the width of Integers. This is possible
as the implementation is directly in Hardware.
 Datatypes of Handel-c and ANSI-C

Handel-C Only ANSI-C Both

double

float

Chan enum

Ram register Int

Rom static unsigned

chanin extern Char

chanout struct Long

undefined volatile Short

interface void

const

union

Handel-C also doesn't support pointers, as these cannot be implemented in

Hardware. The Handel-C compiler allows the definition of macro functions. This enables
the same hardware to be reused. This increases the hardware usage efficiency.

Design Procedure
Handel-C provides a simulator to test the program implementation before
implementing it in Hardware. The simulator can step through each cycle of execution,
and display the values of the variables after each cycle.
Once the designer is satisfied with his/her design, it can be compiled in to
hardware. When compiling in to hardware the designer can target a specific hardware
platform. Handel-C compiler currently produces net lists for Xilinx and Altera devices.
The following design procedure is followed in Handel-
 Comparison Between Handel-C And VHDL
Prototyping new concepts or building first generation electronic devices is time
consuming and costly, and in some cases high risk. Most algorithms are prototyped in C
and then translated into VHDL or Verilog—a process that introduces risks and errors.
Handel-C avoids this problem because it is a language based on C and
designed to describe algorithms, which are subsequently compiled down to
hardware. Changes to the Handel-C code produce predictable changes in the
resulting hardware. By targeting FPGAs directly, Handel-C provides a fast route
for hardware prototyping and development of first generation electronic products.
The development process is carried out in a single software environment, with
debug/edit/build loop measured in minutes rather than weeks and months. This
provides the ideal tool for evaluating performance trade-off decisions and validating
the final designs. Handel-C supports a software methodology of design reuse.
Functions can be compiled into libraries and used in other projects, with a simple
declaration providing the interface to other code. Cores written in Handel-C can be
exported as EDIF or VHDL “black boxes” for design reuse.

Features Benefits
High level language solution Allows rapid development of multi-million
gate FPGA designs and system-on-chip
solutions
Based on ISO/ANSI-C Allows application engineers to migrate
concepts directly to hardware, for rapid
prototyping and first generation electronics
products
Well defined timing Fast external I/O
Simplifies pipeline
Explicit parallelism ‘par’ statement
Simultaneous assessment
Supports complex C functionality Shallow learning curve for software
including structures ,pointers and engineers, allows rapid implementations of
functions(shared and inline) very complex, modular systems
Includes extended operators for bit Allows rapid translation of DSP
manipulation, and high level mathematical Algorithms to efficient hardware
macros(including floating point)
No state machines to design, control flow Simplifies design of complex sequential
comes from C statements like if, case and control flows, intuitive to software
while engineers
Simple and consistent syntax extensions for Enables efficient use of available hardware
specific hardware features like without cumbersome syntax
RAMs/ROMs, signals and external pin
connections
Automatically deals with clocks, clock Abstracts away much of the complexity of
enables, and data transfers across clock hardware design
domain boundaries
 As systems increase in size and complexity, designers will benefit from a new
breed of tools that complement those they use today. These new tools simplify the
process of describing functionality in hardware through the application of a high level
approach to EDA that is inspired by the software world. Fusing software and hardware
methodologies, these tools introduce three aspects of software development to the
designer: a C-based language for describing functionality; a design system with
symbolic debugging; and libraries of predefined functions including access to
peripherals and processors in hardware via common APIs.

A C-Based Language Approach

Hardware design methodologies, from schematic capture which hardware

functionality is developed by describing circuit structure. To this end such approaches
have focused on maintaining low-level design control but there are limitations if such
methods are used exclusively to address a large design area. One of the first problems
arises because most functionality is comprised of both sequential and parallel logic and
yet HDLs have evolved from an exclusively parallel world for describing the hardware
rather than describing the desired function. What is needed is a language the raises the
level of abstraction sufficiently to enable the designer to describe in the briefest possible
way the desired function rather than its underlying structural detail.
While Register Transfer Level (RTL) subsets of HDLs, such as VHDL and
Verilog, do provide a functional interpretation of the hardware description to enable the
generation of hardware structure at compile time, their parallel nature requires the design
engineer to add extra logic for sequential execution, for example; an FSM expressed as a
case statement. Code is cut up in pieces and put into the case statement depending in
which clock cycle it is to be executed. The order of execution is then controlled by
conditional settings of the state in each of these pieces. This is essentially GOTO
programming. With the inadequacies of GOTO programming, something that was
abandoned decades ago in the software world, the code becomes less readable and
potentially dangerous, for instance creating infinite loops. By introducing a language that
is similar to ANSI-C to the hardware design process, designers gain a language that is
sequential by default with a high-level flow that is geared for programming functionality.
But hardware is parallel and this needs to be accounted for if a software-influenced
hardware design methodology based entirely on C is going to succeed at the RTL level.
There are two high-level alternatives: behavioral compilation; or, the addition of a
simple way to express parallelism. Behavioral compilers seem ideal, automating the
processes between software input and hardware output. But today’s compilers give the
user little control over the quality of the output.
 The Design Environment

Today’s hardware design methodologies are computer-based interpretations of

early tools such as bread-boards and logic analyzers. Although hardware design has
progressed in abstraction to RTL, the methodologies reflect their origins from the
structural world. There are significant benefits to an approach that is derived from the
software world. One important methodology is enumerated below;

Celoxica DK1 Design Suite

The Celoxica DK1 design suite is a unique C direct-to-hardware solution that

enables application specialists to migrate concepts directly to hardware without requiring
the generation, simulation, or synthesis of hardware description languages (HDLs). The
DK1 design suite focuses on the design, validation, iterative refinement and
implementation of complex algorithms in hardware. It includes built-in design entry,
simulation, and synthesis, driven directly by Handel-C, a programming language based
on ISO/ANSI-C. The output of the compiler is either architecture optimized EDIF netlist
appropriate for FPGAs, or RTL VHDL for existing tool suites.
The DK1 design suite has the look and feel of a software environment. The
debugger provides in-depth features normally found only in software development. These
include breakpoints, single stepping, variable watches, and the ability to follow parallel
threads of execution. The hardware designer can step through the design just like a
software design system using this approach. Co-simulation and verification facilities are
built into the tool-chain, facilitating co-design with instruction set simulators, VHDL
simulators such as ModelSim. A key benefit of this is that hardware/software partitioning
decisions can be changed at any stage in the design process.
Synthesis in this design system correlates to software compilation in that it is very
fast; software designers are accustomed to compiling changes to their designs very
quickly and testing the results. This enables them to take many turns, make smaller
changes and quickly recompile. The speed of Celoxica’s design system brings this benefit
to hardware design as well.

Predefined Hardware Libraries

Predefined libraries much like the standard libraries of ANSI-C and other
software environments to hardware design create opportunities for simplifying the
development of new functionality as well as encouraging design reuse. Handle-C has
capabilities for accessing internal and external memory as well as registers. Via libraries
of predefined functions, common APIs shield users from low level interfaces to ease the
integration of FPGAs to physical resources including both peripherals and processors –
the latter enabling hardware/software co design. It is an approach that can mean
significant time savings, giving the designer more time to concentrate on core
functionality.
 The Benefits of Using Handel-C
Apart from the obvious benefit of using a high level language based design
method to a low-level language based method. Handel-C provides a very powerful
method of Hardware implementation, which is very useful especially in Custom
Computing applications.
Since Handel-C supports a large set of ANSI C constructs ,easy porting between
the two languages is possible.

In Custom Computing applications, part of the Design is implemented in

Hardware while part of it is implemented in software .Since Handel-C is itself very
similar to an imperative language, it makes the task of dividing the original design into
a Hardware section and a Software section that much easier.
The imperative nature of Handel-C also makes it easier to debug and upgrade
the hardware design. This means that the Hardware component can be easily modified
to take in to account modifications made to the Software component and vice versa.
Due to Handel-Cs high level nature it makes it possible for the same person to do
both the Hardware and Software implementation. This greatly reduces the
development cost as you do not need a two people to handle the Hardware and Software
design separately.
 Implementations

A Real-World FPGA Design Example

A European Commission funded “ESPRIT project” called SEHaD (Software
Engineering for Hardware Design) afforded Celoxica the opportunity to demonstrate the
value of Handel-C. As part of the project, two Ericsson design teams participated in a
parallel design effort to develop an IPv6 header compression function on an FPGA. One
team used Handel-C and the other a traditional hardware design methods and tools
(Verilog/Leonardo).

 The Application
Routers are critical components of Internet Protocol networks. In order to handle
the increasing demands on performance, modern routers are increasingly based on
hardware implementations of the protocol stack. For transfer of real-time information
such as voice over the Internet, the payload-to-packet size ratio is unsatisfactory in terms
of both real-time characteristics and bandwidth utilization. IPv6 has accentuated this
problem further. In order to alleviate this for point-to-point links, schemes to represent
unchanging parts of the headers in a packet stream by an 8 to 16-bit number (CID) have
been devised. The compressed header contains this number and absolute or delta
representations of non-constant data fields of the headers in the stream. The reverse
operation is called decompression and is performed at the receiving end of the link. On
each Internet link, many sessions are transmitted simultaneously. Each session payload-
to-packet ratio.
The idea behind header compression is to enable the transmitting and the
receiving router to agree on a short representation of the headers. The headers are
compressed to the short form when transmitted and decompressed to the original form
when received. This reduces the required bandwidth of the link and improves real-time
characteristics of the data stream. As an example: Compressing IPv6, half-rate voice
packets will lead to a 65% bandwidth saving. Consists of a stream of IP packets with
almost identical headers and often a poor payload-to-packet ratio. The idea behind header
compression is to enable the transmitting and the receiving router to agree on a short
representation of the headers. The headers are compressed to the short form when
transmitted and decompressed to the original form when received. This reduces the
required bandwidth of the link and improves real-time characteristics of the data stream.
As an example: Compressing IPv6, half-rate voice packets will lead to a 65% bandwidth
saving.
  The Results
Two designers comprised the team using Handel-C.One had some experience
using an earlier version of Handel-C and some design experience in the application area,
while the other, a college graduate, had no experience with Handel-C or the
application.The table below summarizes the results of the Handel-C implementation
compared to the results in the parallel project.

* Distributed memory. No block memory used

** A conscious choice. Used all logic to increase speed. All block memory used.
The most striking result is the difference in design time, a factor 3-4 shorter
design time using Handel-C, with similar results in terms of speed and a greatly reduced
area. An analysis of the results of the project attributed the difference in design time to
three key advantages demonstrated by Handel-C: its support for sequential logic, its
compact representation of functionality, and its software-like design methodology
which provided fast turnarounds in the design environment. According to the SEHaD
report, these results were consistent with the experience of other users in the project, as
well as of smaller examples done by Ericsson. “The difference in program size reflects
the conciseness of the C syntax and the higher level of abstraction of Handel-C. An
example of this is the style of describing serial/parallel code in Handel-C versus
controlling sequencing using finite-state machines in Verilog or VHDL. The small
program size and algorithmic expressiveness of Handel-C made it easy for us to make
drastic experimental changes to the Handel-C code. This allowed us to explore a larger
solution space.” Another major difference commented on in the report findings involved
the software-like design style supported by Celoxica’s DK1 design suite, which integrates
project management, simulation, synthesis and optimization into a single development
environment. “Verification was primarily done using the software debugger paradigm.
Compilation to real hardware was done very early and after each major addition of
functionality using an incremental design style. This created confidence in the solution
and enabled us to run large test sets in real time.”
 For designing functionality of similar complexity, the world of software design is
simpler than its hardware counterpart. The possibility of using software design
methodologies to create hardware solutions may seem almost heretical. But as
demonstrated in the above example it resolves many issues inherent to modern IC
development. It shortens design time by a factor of 3-4 times, the language and design
systems are easily adopted and the small efficient code makes radical system-level
changes simple. In the software design paradigm, we have what we need to raise the level
of abstraction sufficiently to describe in the briefest possible way the desired function
rather than its underlying structural detail and overcome many of the difficulties and
inefficiencies in contemporary hardware design.
 Converting MP3 Software to Hardware

 Overview
MP3 encoding is normally implemented in software, but in the search for higher
performance and lower cost encoders, moving to hardware is increasingly attractive.
Taking advantage of the boost to performance this approach generates, the designer has
greater freedom to reduce the encoding time, improve the final music quality or fix an
optimal trade-off between the two.
In this example, the design team already had available an existing software based
implementation of the MP3 encoding algorithms, comprising over 40,000 lines of C
code. The objective was to convert this software implementation to hardware to yield
significant improvements in performance.
During this process, it was essential to evaluate the effects of the different trade-
offs possible in the encoding process. This would enable both optimisation of the
encoding and also the opportunity to review the feasibility of producing several variants
for different markets.
Taking the conventional route of converting the existing C code to an HDL
environment would have been cumbersome and time-consuming. Instead Handel-C was
used. This took the large body of IP and evaluated multiple variants before producing
netlists for prototype silicon place and route, all within a single environment and without
requiring translation to HDL. A prototype of an MP3 hardware implementation using
Handel-C demonstrates how the integrated software environment speeds development
and provides the efficiency and flexibility to optimise a design.

 What Is MP3?
MP3, MPEG Audio Layer 3, is the world-wide standard for audio compression of
complex sources, such as music. It is used for the audio channel in digital television, for
streaming audio across the Internet and for capturing music from CDs and other sources
for use in small, low-cost personal players or on personal computers.
The standard provides compression in excess of 10 to 1 while maintaining CD
sound quality. The approach is deliberately lossy but, by using a psycho-acoustic model,
the result appears transparent and lossless to the listener.
The two richest areas for optimisation are the filtering and the application of the
psycho-acoustic model. In order to improve encoding speed, software implementations
have tended to use a very simplified psycho-acoustic model, which can produce a quality
drop in the final signal.

 The Psycho-Acoustic Model

Experiments have shown that the ear has limits to its ability to resolve different
frequencies when they are close together. This resolution varies according to the
frequencies involved, with acuity of less than 100 Hz for the lowest audible
frequencies, while it is more than 4kHz for the highest. This relationship can be
represented by dividing the audible spectrum into bands, the width of each band being
determined by the resolving power of the ear in that region. Each of these bands
can be treated as single unit for many compression algorithms.
Related to this is audio masking. When a human ear is listening to a complex
signal, such as music, a strong audio signal will mask weaker audio signals when they are
close in frequency. If these smaller signals are dropped as part of the compression
process, they are not missed when the decompressed signal is played back.
MP3 uses these phenomena to provide significant compression without perceived loss of
quality.

 MP3 Encoding
A simplified MP3 encoding flow is shown in figure below. The sound source is
transformed from the time domain to the frequency domain as 32 frequency bands. These
are filtered using a Modified Discrete Cosine Transform (MDCT). In the software
implementation this is an extremely compute intensive activity. The psycho-acoustic
model is applied to the frequency bands to produce a simplified representation of the
signal, which undergoes a quantization process, before being Huffman coded. Finally, the
Huffman coding is converted to the MP3 bitstream. MP3 decoding is the reverse of
encoding, although without the psycho-acoustic model.

MP3 Encoding Flow

  The Implementation Project
A software implementation of MP3 exists as 40,000 lines of C code. Once the
significant number of very large tables were removed, the code of the core algorithm was
just over 10,000 lines and this was used as the basis for a hardware implementation.
All Handel-C conversions start by converting floating point to integer. This is
not a once-and-for-all decision, as the declared length of the integers can be changed as
part of optimisation and this was the case with the MP3 implementation. In particular, it
was possible to change integer lengths, recompile and listen to the resulting change in the
quality of the sound.
The nature of the MP3 algorithm automatically defines a top-level structure and
an underlying pipeline parallelism: these were used to define the implementation. There
was a key split into two halves, defined by processing load, which execute in parallel.
The first segment was the time to frequency domain conversion and the application of the
MDCTs. The second was the application of the psycho-acoustic model and the Hoffman
encoding.
Each module within these segments was converted line-for-line into Handel-C
and then either simulated or run directly in silicon. Once all the conversions were
completed and I/O modules developed and tested, the entire design was integrated on a
single FPGA.
MP3 coding makes heavy use of tables - the Huffman coding alone draws on 15
tables. Tables can be partitioned between on-chip RAM and ROM and off-chip RAM.
This partitioning can be revised to improve performance. MP3 coding also has a great
deal of multiplication and the implementation uses two multipliers within the target
FPGA in parallel to provide increased performance.

The Result
The project took a two man team less than eight weeks to produce a working silicon
prototype, including implementing a CD-ROM controller to allow management of the
input data stream.
 Hardware Implementation of Communications >: Author
Protocol in a “ Voice Over IP” Phone

 Overview
Internet Protocol (IP) telephony uses multiple algorithms to convert a voice signal
into the correct form for transmitting across the Internet. The Celoxica™ DK1 design
suite was used to implement these algorithms quickly and flexibly in silicon to make an
IP telephone, without using a hardware description language (HDL). DK1 provides an
ideal environment for enhancing the algorithms and creating new applications for the IP
telephone, such as MP3 music decoders. These new features can be downloaded using
the Internet to increase functionality of the IP phone.

 What is IP Telephony?
A normal voice telephone call is purely analogue and requires a dedicated end-to-
end connection between two instruments, which is set up for the conversation and then
torn-down when it is finished. (Although, for parts of its journey, traffic may be digitized
and multiplexed).
IP telephony takes the voice signal, digitizes and packetises it before entering it
into a packet-switched network such as the Internet. The packets share the network with
all the other traffic, of whatever kind, before undergoing a reverse process at the
receiving end.
For customers, IP telephony is seen as effectively free and, as such, users are
prepared to put up with lower sound quality caused by lost packets. Within businesses, it
allows telephony to use the infrastructure of the corporate Intranet, without the need for a
corporate telephone service.
  Requirements of IP Telephony
An IP telephone call goes through multiple stages, that involve different protocol
levels.The initial voice is captured and then compressed through a codec. This outputs a
bit stream optimized to run over a conventional telephone network at 48/56/64 kbps. C
implementations of audio codecs are available from a number of sources, including some
public domain software.
The next stage is conversion of the bitstream into RTP packets. This is an industry
standard protocol widely used by many applications, such as Microsoft’s NetMeeting
audio-conferencing software. The RTP packets are then passed up the TCP/IP stack using
UDP (User Datagram Protocol).
Finally, an IP header added before the package goes through an Ethernet or other
technology interface to enter the network. The initial call connection is handled by H323,
which uses TCP. This establishes the two one-way logical channels, one in each
direction, for the UDP that carries the RTP packets. Receiving a call is a straight reversal
of the sending process. Additionally, a telephone unit requires peripherals such as a
keypad or equivalent for setting up the call, a handset with microphone and speaker and
possibly hands-free operation through a speaker and microphone. An advanced IP phone
might also have a screen for information display.
  Implementation of the Phone
The IP phone uses a pair of FPGAs with shared RAM and flash memory. Using
two FPGAs allows new versions of the telephony application, or totally new applications,
to be downloaded as TCP/IP traffic under the control of one FPGA and targeted onto the
other, while the phone is in field service. Peripheral circuitry controls the handset and
touch-screen for entering data.
Algorithms for protocols such as RTP, TCP, IP and UDP were derived from a
range of public domain sources available as C source code.
The source code is adapted to exploit the features of Handel-C, such as its ability
to support parallelism. For example, in some telecoms protocols a series of fields in the
packet header are read in succession and actions taken based on the field values. This can
be structured as a pipeline, with each clock tick advancing a packet one stage through the
pipe. Once parallelism is implemented, then the code can be compiled for simulation or
for passing to hardware place and route tools.
The different algorithms were each implemented and tested by simulation and
then in hardware before integration. The overall flow of messages through the different
layers of the protocols determined the structure of the implementation and the output and
input of these layers effectively defined the interfaces between layers. The RAM is
shared between different modules.
Additional Handel-C code was written to take care of the interfacing to the
peripherals and to take care of housekeeping tasks, like generating a ringing tone when an
incoming call arrived. While most of these elements can be handled in software, the
overall computing load can become quite heavy and transferring them to silicon becomes
an attractive way of improving performance.

 The Result

An IP telephone prototype was able to take and send voice calls within 3 months.
The development team was then able to begin a process of optimization and tuning,
merely downloading the latest version of the implementation through the Ethernet port
onto one of the FPGAs in the phone. The IP telephone used algorithms that were
available in C with others that were developed specifically for the phone.
These were integrated, simulated and tested within a single Handel-C
environment, without the need to translate into another language. The same environment
is being used to optimize the core application and to develop other applications that can
run on the phone unit.

.
 CONCLUSION

The presented programming methodology and platform offers several

unique features such as:
 The small program size and algorithmic expressiveness of Handel-C
makes it easy for us to make drastical experimental changes to Handel-C
code.
 The difference in program size compared to C reflects the conciseness of
the C syntax and the higher level of abstraction of Handel-C.
 Design time reduced by the factor of 3-4 times.
 Compilation time is reduced to a great extent.
 Allows rapid development of multi-million gate FPGA designs and
system-on-chip solutions.
 REFERENCE

 The VLSI Handbook

Wai-Kai Chem
University of Illinois
Chicago, Illinois
2000 by CRC Press LLC
 www.Celoxica .com
 oldwww.comlob.ox.ac.uk
 web.comlab.ox.ac.uk
 Kalle Tammenae
 Department of CE, Tallinn Technical University 2001/02
 University of Applied Sciences, George Simon-Ohm
 University of Illinois, Saburo Muroga