Design & Verification of 16 Bit RISC Processor

Seung Pyo Jung, Jingzhe Xu, Donghoon Lee, Kang-joo Kim, Koon-shik Cho
Ju Sung Park R&D Department
School of Electronic and Electrical Engineering Samsung Electro-Mechanics
Pusan National University Suwon, Korea
Busan, Korea [email protected]
[email protected]

Abstract— The procedure of design and verification for a 16-bit

RISC processor is introduced in this paper. The proposed
processor has Harvard architecture and consists of 24-bit
address, 5-stage pipeline instruction execution, and internal
debug logic. ADPCM vocoder and SOLA algorithm are
successfully carried out on the processor made with FPGA.

16bit RISC Processor Harvard architecutre, 5 stage pipeline,

Multiplier, Block Repeater

I. INTRODUCTION
The portable multimedia player (PMP) and the personal
digital assistant (PDA) are not special item of people. So the
low power processor and small size processor are made as SOC
level ASIC (Application Specific Integrated Circuits). The
popular processors on SOC level ASIC are the 8051 processor
and the ARM 7 processor. The ARM 7 is used on SOC level
ASIC which is millions gates size. And the 8051 processor is
used on simple system which needs the small size. But the bit
size of simple system is changing 8 into 16. So the 8051 Figure 1. Proposed processor architecture
processor calculation time is increasing. To replace the 8051
processor the new 16bit RISC processor is proposed in this
paper.
To use 24bit address program memory in simple operation,
II. DESIGN OF 16BIT RISC PROCESSOR it has a 2word absolute jump instruction and 1word relative
jump instructions. So it is not needed to control the high 8bit of
The 16bit RISC processor has the Harvard architecture
the program address for branch instruction.
which uses separate memory access ports for program and data.
And the address of each memory is extended to 24bit by To support the multi core system operation, the core has a
internal segment register. So the core has enough memory swap instruction which organizes atomic instructions. The
space to operate a reasonable program. swap instruction’s operation is that the core changes the
memory value and do not accept the interrupt signal to
The processor use 5-stage pipeline structure for efficient
guarantee the operation of it.
data processing. [1] And two block repeater is prepared to
reduce redundant stage of the looping program. These parts The addressing mode of the processor has register mode,
help to minimize processing time of a complicate program immediate value mode, indirect mode and auto increment
execution. mode. The register mode use internal register number as
operand. The immediate value mode uses the part of the
For the calculation it has a 16bit arithmetic logic unit, a
opcode. And the indirect mode and the auto increment mode
16bit multiplier, a 16bit barrel shifter. The 16bit multiplier
use register value as the address of the operand and the auto
result is saved to the general register of it. When the operation
increment mode increase or decrease register value.
code is multiply-long the core save the result to target register
and higher register. And the 16bit barrel shifter reduces shift For program debugging the processor has an on chip debug
operation cycle to 1cycle. The figure 1 shows the architecture logic. External interface uses JTAG protocol and internal
of the proposed processor architecture. interface uses scan chain. And AMBA AHB master wrapper is
included for the interface to AMBA system.

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 III. VERIFICATION OF 16BIT RISC PROCESSOR IV. CONCLUSION
The proposed processor is verified through 3 step test. First, The proposed processor is designed to embed on SOC at
an instruction set simulator was made as a reference model to ASIC. The core execution test is done. But for on-chip
the processor. The figure 2 shows the instruction set simulator. debugging GDB server program is needed for application
The simple instruction HDL simulation of processor is debugging. The figure 5 shows the connection of the GDB
compared with it of instruction set simulator. server program, the SW debugger and the new core.

Figure 5. GDB Server Program

And for fast programming compiler is also needed. Next

target of the proposed processor is to develop a compiler and
GDB server program for high level user.

Figure 2. Instruction set simulator ACKNOWLEDGMENT

This work was supported by Samsung Elector-mechanics
and IC Design Education Center(IDEC).
Second, to check 5stage pipeline architecture a complex
algorithm test is accomplished by the instruction set simulator REFERENCES
and the HDL simulator. The algorithms used are ADPCM
vocoder and SOLA (synchronized overlap and add) and are [1] David A. Paatterson, John L. Hennessy, Computer Organization &
programmed in assembly language. [2] Design, Morgan Kaufmann Publishers, 1999
Third, to check the HDL code simulation error by [2] Tae Hoon Kim, Ju Sung Park, The Design of Chorus DSP chip Using
Psychoacoustic Model and SOLA Algorithm
unsynthesisable code the processor is downloaded on FPGA.
The Sola algorithm is executed on FPGA board and output data
is checked on speaker. The Figure 3, 4 shows downloaded
processor SOLA test result.

Figure 3. SOLA input data

Figure 4. SOLA output data

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