INSTRUCTOR'S GUIDE FOR MICROPROCESSORS AND INTERFACING PROGRAMMING AND HARDWARE SECOND EDITION DOUGLAS V. HALL GLENCOE ‘Macmillan/MeGraw-Hill Mission Hil, Cer SCM FGIT. IM PCIAT, aM PS, and MtroChanne rchisctre are eto trademarks of BM Corporaton The leson ig6TA4 860TH, CE NOK Borers, Geert 8 1882 by he Glencoe Divison of Macrae Hl Scho! Publishing Gemptny. Copyright © 1965 by Mecraw-Hl nc. Alihisresoved. Except sere sean, the United States Copyright Act, no parol Wis publication may be toded ietivtod in ny form orb any means, or stored ina calabsse or eave srcn without te prior written prmission of ta pubisher ‘Send al iruies to GLENCOE DIVISION MacmilantAcGraw-+) 896 Eastin Orv Westorvile, OH 4308) ISBN 0.07 0257442 Petes inthe United States of America. 129456789 SEM 9908.0796 05 94 3.9201CONTENTS Introduction ANSWERS TO CHAPTER REVIEW QUESTIONS IN THE TEXT Chapter Page 1 3 2 5 3 7 4 al 5 13 6 There are no questions for this chapter. 7 15 8 19 9 23 10 27 ul 31 12 35 13 37 4 41 15 45 EXPERIMENT NOTES AND ANSWERS TO SELECTED QUESTIONS IN THE EXPERIMENTS SUPPLEMENT Experiment Page Experiment Page a 50 21 ci 2 50 22 61 3 50 23 61 4 51 24 62 5 52 25 62 6 52 26 62 7 53 27 64 8 53 28 64 9 53 29 64 10 54 30 65 n 54 31 66 12 35 52 66 13 56 33 66 4 56 34 66 15 57 35 66 16 58 36 67 17 59 37 67 18 59 38 67 19 60 39 68 20 60 40 68INTRODUCTION In addition to the answers contained In this instructor's guide, I have prepared a set of IBM PC:compatible disks which contain the source files for: All the example programs in the text All the program answers for end-of-chapter problems. All the programs for the experiments, except those for a couple of open- ended exercises. 4. A program called SDKCOM1.EXE, which can be used to download binary programs to an SDK-86 board at 4800 Bd. 1 think you will find that having these programs on disks is much more ‘useful than simply having program listings, because: 1. You can assemble, link, download, and run these programs for demonstrations and/or further experimentation. 2, You can print out listings of selected programs as needed for use in class discussions. 3. You can give students part of the solution to a problem and let them fill in the missing pieces. This allows you (o adapt the text problems and experiments to a wide range of student abilities. 1 initially give an assignment without hints; then, after students have worked on the problem for awhile, I give hints or program fragments as needed to allow the majority of students in a particular elass to experience a feeling of success, This approach helps avoid the tendeney of many students to wait until one of the “sharp” students figures out the solution and then just copy the solution from him or her without trying, to solve the problem independently. 4, You can use these “known good" programs to test the hardware modules used in the laboratory exercises. This last use allows you to quickly deal with the common student complaint, “My program doesn't work; the hardware must be broken.” have tried to make this instructor's guide as accurate as possible. If you nd any errors, have any further questions, or have any suggestions for improving the book or the lab manual, | would appreciate hearing from you. Notes about the Program Disks 1. The directory called TEXTXMPL contains the source code for all the program examples used in the text. 2. The directory called TEXTANS contains the source code for all the programs required as answers to problems ‘The directory called LABANS contains the source code for al the programs for the experiments. ‘The SDACOMIEXE download program s in the root directory, so you can easily copy it to your hard disk. For all the systems I tried SDKCOML.EXE works perfectly, but the older SDKDMP.EXE is included in . Use whichever program works better on your systems. Also, the source programs and .PRJ file for SDKCOMI are in the LABANS directory if you want to experiment with improving the program. 5, These programs were all compiled with TASM, MASM, or the Turbo Cl Integrated Environment compiler. To the best of my knowledge, they all work, Please let me know about any problems you encounter. Douglas V. HallAnswers to Chapter Review Questions in the TextCHAPTER 1 COMPUTER NUMBER SYSTEMS, CODES, AND DIGITAL DEVICES is 21 = 2048 212 = 4096 2M = 5192 2M = 16,384 16 219 2 32.768 32 2192 65,536 61 217 = 131,072 128 218 = 262.144 2P = 256, 219 524,288 B12 220 1,048,576 1024 4G. 22 decimal = 10110 binary b, 76 decimal = 1001100 binary © 500 decimal = 111110100 binary a 11 dectmat b. 11010001 = 209 decimal © 1110111001011001 = 61.017 decimal @. 83 decimal = 3511 >, 786 decimal = 2F4H © 011 0110 0010 = 362 @. 110 0001 0111 = 6171, > DSH = 211 decimal SPEH = 1022 decimal 44H = 68 decimal @. 86 decimal = 1000 0110 BCD >, 62 decimal = 0100 0010 BCD © 83 decimal = 0011 0011 BCD ‘The 1 key produces the pattern 0101100 (4CH. ‘A carriage return (ODH) would give the pattern (00001101, ‘The term parity is used to show if a data word hhas an even number of 1's, Even parity means fan even number of 1's, Errors in transmitted data are detected as follows. The system sending a data word checks the parity of the word. I there s an odd number of 1's in the word, the system will set the parity bit (bit 7) to @ 1 otherwise it will reset the parity bit. Either way, the parity of the word plus the parity bit Decomes even. The data word is transmaitted and the parity is checked at the other end. I the parity of the word is odd, st can be assumed that {an error ocurred in transmitting the data. @ 10011 + 1011 = 11110 oi 0111 b. 37+25 262 40010 0101 ‘0101 1100 add 6 because > 8 + _on0 ‘1100010 AH + 77H =ClH 0. n 2 B. 14 Decimal __S.Bit eit Sign Magnitude and Magnitude a 426 000110100001 1010 bor (0000 0111 1111 1001 © 26 00011010 11100110 "125 0111 1101 1000 0011 Decimal Pencil _2°s Complement if Sign Bit = 0, Result +, Ignore Carry a out oun 0100 +1100 ‘oO TOON ». 0100101 00100101 90011010 41100110 (00001011 10000 1011 e o1tt tot ont 1101 oloL 101 + 1010 0011 (00100000 10010 0900, a @x3=27) 3001 10010 nol 11010 (26x58 = 130) 101 1i010 11010._ 0000015, 3010 (100/10 = 10) 1010FFTOTOO 1010 1010 4010 69000 a SAH + 94H = CEH b, TAH - 4CH = 12EH © 01011001 BeD-——(59-+ 42= 101) 1001 1011 £0110.0110 {add a correction of 6 6} 10000 6001 4 0111 1001BCD (79+ 49 128) +0100 1001, BCD 1100 0010, +OL100110 (add a correction of 6 6) 1.0010 1000 NUMBER SYSTEMS, CODES, AND DEVICES 315 16 uw. © 0101 1001 BCD =0010 0110 BCD 011 OO1T f 0110 0111 BCD. 0011 100] BCD (0010-1110 = ___ouo ‘0010 1000 For the circuit in Figure 1-23: a. The output fs active high. B. ‘The C signal is active high, The ¥ output is asserted when As high, Bis low, and C is high: or when Ass low, Bis high, and € 4s low. (69-26 = 33) (67-39 = 28) (subtract a correction of 6} When the D lateh is enabled, the @ output follows the D input. in the D fp-flap, the output ‘only follows the D Input on the rising edge of the lock signal ‘Thirteen address lines are fone of the 8192 bytes in a INSS298, (2° 19 address lines, 0 through 12.) $ cHaPrER 1, 20, ‘Most ROMS and RAMs have three-state outputs (logic low, logic high, and floating high- impedance’ states) bevatise usually more than one device is connected to a bus, Only one device at a time can have its outputs active on the bus: all others must be floating. s3_s2 si so m hee. Osco ose) DB A-B-1 0 1 1 0.0 © BHA 1 0 0 0 0 @. 1010 AND 0111 = 0010 1010 OR Ol = UD >. 1011 AND 1100= 1000 10M OR 00 = © 11010111 AND 0011 1000 = 0001 0000 11010111 OR 0011 1000 = 1421 TH An 8-bit mumber ANDed with 1111 0000 will Teave the upper 4 bits the same and zero masi) the lower 4 bits.CHAPTER 2 COMPUTERS, MICROCOMPUTERS, AND MICROPROCESSORS—AN INTRODUCTION 1. Advantages of a distributed processing system over a time-sharing system are as follows: If the large computer goes down, the local microcomputers can continue working until it Is necessary to access the large computer: (b) the Durden on the large computer is greatly reduced: and (c) the system can be designed to use a local ‘microcomputer best suited to the task ft has to do. ‘The sequence of signals Is as follows: 4G. An address is sent out on the address bus. b, A memory-read signal is sent out on the control bus. The memory outputs the instruction byte on the data bus. d. The CPU reads in the instruction and decodes it. 3. The number of bits a microprocessor's ALU can work with at a time determines whether the nleroprovessor Is considered an &-bit, 16-bit, or 82-bit system. 4. @ The 8086 has 20 address lines. b, Twenty address lines allow the 8086 to access 1,048,576 memory addresses eurecly © Each segment contains 64K bytes within this IM-byte range 5. The 8088 has an &-bit data bus, 0 it ean read data from or write data to memory and ports ‘oly 8 bits at a time. The 8086 ean read or write tlther 8 oF 16 bits at a time, @ The 8086 queue holds the next six instruction bytes from memory. +b. The queue speeds up processing because the EU reads the next instruetion from the queue. This is much faster than sending out an address to the system memory and walling for the memory to send back the next instruction byte or bytes, 7. a The CS register will hold 7040H. b. ‘The next code byte fetched from the physteal address » 70400 + 539CH = 7578CH, 8. a 4970:561EH represents 43700H + 561EH 48DIEH, b, 7A32,0028H represents 7A320H + 0028H TAS4BH. 9. The advantage of using a CPU register ts that the data is already in the EU; therefore, it ean be wo, un 2. 1 1B 16. 1, 18. accessed much more quickly than it could in external memory. SS = 3000H and SP = 8434H, TOS = 30000 + 8434H = 88434H or 3000:8434. @ tis very difficult to memorize the thousands of binary instruction codes for a CPU and very easy for an error to occur when working with the long series of I's and 0's required by machine language. Assembly language ‘makes programming easier and less prone to 1b, When an 8086 executes the instruction ADD AX, BX, the contents of the BX register are faded to the contents of the AX register and the result is left in the AX register. BX is leit unchanged, Programs which require a lot of hardware contro! or programs which must run as quickly as possible are usually best written in assembly language. @ MOV BX, OSFFH :Load the number OaFFH Into the BX register. . MOV AL, ODBH jLoad the number DBH Into the AL register. © MOVDH,CL ‘The contents of the CL register are copied into the DH register. CL is unchanged, d. MOV BX, AX :The contents of the AX register are copied into the BX register, AX 1s unchanged, &. MOV BP, 7986 b. MOV SP. BP © MOV DS, AX d. MOV AL, OFSH EA = 14A3H and DS = 7000H, address produced by the BIU = 714A3H, DS = 4000H, physical address for (23481) = 40000 + 2S4BH = 4234BH, MOV [482011], DL MOV AX, 2497H1 = loads the AX register with the number 2437H. MOV AX, [2497H] copies the conterits of memory location DS + 2437H into AL and the contents of memory location DS + 2487H + 1 into AH (Le., loads the 16-bit AX register from vo 8-bit memory locations) CCOMPUTERS:INTRODUCTION. 5CHAPTER 3 8086 FAMILY ASSEMBLY LANGUAGE PROGRAMMING—INTRODUCTION 1. The main steps in developing an assembly language program are: 4. Define the problem, b, Write down, in general terms, the algorithm for what the program has to do, using a flowehart, a sequential list. or pseudocode (Le., represent the structure of the program In some way that Is very clear to you ancl (0 anyone else who might have to work on the program), ¢. Write an initialization checklist for your program. 4, Determine the instruction statements ‘required to do each part of the program. fe, Start writing the assembly language for the program, 2. The top-down design approach produces easy to understand, modular program representations that may be programmed in either high- or low- level languages. A detailed algorithm enables you to break & programming probiem into small modules which can easily be written, tested, and debugged. The more time you spend organizing your programs, the less time it will take you to write and debug them, 4. a@ Sequence, Selection, and Repetition (or Sequence, IF-THEN-ELSE, andl WHILE-DO} b, The advantage of using only these structures when writing the algorithm for a program 1s that the algorithm is easy to understand, Implement, and debug favolds spaghett). 5. Pacudacode: Look in your kitchen for peanut brittle recipe ingredients, IF any of the ingredients are missing THEN go to the store and buy the missing ingredients. Find a teaspoon, a I-cup measure, a 1.5-quart casserole, and a nonstick cookie sheet Measure 1 cup of sugar and pour it into the casserole. Measure 0.5 cup of com syrup and pour it into the casserole. WHILE not mixed DO stir the contents of the casserole Mlerowave on HIGH for 4 minutes. WHILE microwave stil cooking DO sit and read ‘newspaper. Add peanuts. REPEAT stir the contents of casserole UNTIL mixed 6 ‘Microwave on HIGH for 4 minutes. WHILE microwave still cooking DO look out of the window. ‘Add 1 teaspoon of butter. ‘Add 1 teaspoon of vanilla REPEAT siir contents of the casserole UNTIL mixed. Microwave on HIGH for 2 minutes. WHILE microwave still cooking DO start to clean up. ‘Adel 1 teaspoon of baking soda. WHILE not light and foamy DO gently stir mixture. Pour mixture onto nonstick cookie sheet. WHILE minutes passed < 60 DO go do something else. IF mixture not cool THEN wait Tonger ELSE break into pieces. Eat peanut brittle, a. Pseudocode: Get number from memory location and put into a_ register, ‘Subtract 20H from the number tn the register. IF number in register > 25H THEN output 1H to port SAK, b, Flowchart: See Figure 3-1, ‘GetNuwern FRow era FIGURE 3-1. Flowchart for algorithm for question 6. PROGRAMMING INTRODUCTIONNext instruction fetehed from 4000:43E8H or 443E8H. TOS address 7000:0000 or 70000. MOV AX. BX:Copy the contents of BX to AX. AX = BX = 075A. MOV CL, 37H:Load CL with 87H. CL = 37H, INC BX:Increment BX. BX » O75BE. MOV CX, [246BH):Copy the contents of ‘memory at 5246BH and §246CH into the CX register, MOV CX, 246BH;Load CX with 246BH. ADD AL, DH:Add contents of DH to AL and leave result i AL, AL = 85 + 38 = 68H, DH = 33H) MUL BX;Multiply the contents of AX with BX: the result is the high word im DX and the low word In AX. DX = O1EGH, AX BOAZH, DEC BP:Decrement the contents of BP. BP 2467H. DIV BL:Divide AX by BL, quotfent in AL, remainder in AH, AX = BCSBH. SUB AX, BX:AX - BX; result in AX (075A = SADBI OR CL, BCE ts ORed with BL: result in CL 5EH. NOT AH;Complement AH, AH = 1011 1101 ROL BX, 1:BX Is rotated left once. BX was (0000 0111 0101 1010, BX now 0000 1110 1011 0100, CF =0. AND AL, CH:AL is ANDed with CH; AL = 00. MOV DS, AX:Instislize the data segment at 423514 copy contents of AX into DS. ROR BX, CL:Rotate the contents of the BX register right, 4 tumes (CL = 4). BX was 0000 0111 0101 1010, BX now 1010 0000 0111 0101, CF= 1. AND AL, OFH:AL is ANDed with OFH AL OSH. MOV AX, [BXI:Copy the contents of memory fn data Segment, pointed to by BX, into the AX register. AX'= contents of 50754H and S075BH. MOV [BXI[SII. CL:Copy the contents of CL ‘nto memory in data segment at an offset of BX + SI. Memory at S885AH will contain oan. MOV BH, AX:Register size doesn't match Should be MOV BX, AX or MOV BH, AL or MOV BH, AH. ‘MOV DX, CLiRegister size doesn't match. ADD AL, 2073H:Number is too large for AL- ‘Should be ADD AX, 2073H, MOV 7632H, CX:Cannot move a register’s contents into an immediate number. Decide if you want to MOV CX, 7632H or If you ‘want to copy the contents of CX to memory. IN BL, 04F:Can only transfer from a port to the AL or AX registers. 8 cHamTER s 10. 2 13 @ ADDBLAl {BL = SA + 35 = 8FH MOV [0004 BL :50004H = SFH b. MOVCL, 04 :CL=04 RORDLCL — :DI = O7D0H ° ‘AL = 35H + 07H = SCH “AL = 42H 4d. MOV BX, OOOAH :BX = 0008H MOV AL, IBX] GAL = contents of 5000AH =7cH SUBAL,.CL — :AL=7C_04= 78H INC BX SEX = 000BH MOV [BX], AL ;:5000BH = 7811 @ MOVBL.AL — (Copies AL to BL b. MOVCL. 43H ‘Loads CL with 43H e mNcex ‘Increments CX by one. d MOVBP, SP ;Copies SP to BP @ ADDDL,O7H {Adds 07 to DL f MULBE ‘Multiples AL times BL, reault in AX 4g. MOV ASAHI], AX Copies AX to a memory locas at offset of DS:245A81 h DECSP Decrements SP by one £ ROLAL,O1 Rotates the MSB of AL {nto the LSB of AL :Copies DL to memory location pointed to by BX ‘Masi lower 4 bits of BL 'Sets the MSB of AX to 1, doesn't affect other bits sInverts lower 4 bits of AL rbut doesn’t affect otter J. MOY [BXI, DL. ke AND BL, OFOK, L ORAX. BOK m. XORAX, OFH bits Inetretion Binary Code Hx MOVIEXL.CX 10901001 00001 11-89 OF AD Bx, S01] 00000011 01 O11 10108 559 ‘sus ost co10100000 110 11028864820 XCHG CH, E5188) 90100110 100001 1026 862 RORAK. 1 11010001 11601 000 BL es OUTDK.AL snio1ni8 = AND ALG aLa0100 OF 2606 DATA_HERE SEGMENT (0 DATA_HERE ENDS sets up a logical segment for the data called DATA HERE.PRESSURE DB 0 assigns the name PRESSURE to a byte type variable and initializes that variable with the value of zero. PRESSURE is a variable in the DATA. HERE segment, PRESSURE_PORT EQU 04H and CORRECTION FACTOR EQU 07H gives the values of 04 and 07 to the constants PRESSURE_PORT and CORRECTION. FACTOR, CODE_HERE SEGMENT and CODE_HERE ENDS sets up a logical segment called ‘CODE_HERE for the code in the program, ASSUME CS:CODE_HERE, DS:DATA HERE tells the assembler which cade and data segments are to be used. MOV AX, DATAHERB and MOV DS, Ax initializes the data segment register with the starting address of DATA HERE. IN AL, PRESSURE_PORT brings a byte of data into the AL register through the port addressed by PRESSURE, PORT (04H), ADD AL. CORRECTION_FACTOR AND MOV PRESSURE, AL adds a correction of O7H to the contents of AL, and it Is then copied to the variable called PRESSURE in the data segment called DATA_HERE. The last line, END, tells the assembler there aze xno more instructions to assemble, ‘An assembly Janguage program is developed and debugged using system tools m the following way! @. Build an algorithm for your program. b. Decide on the instructions required to build the program. © Build the assembly language source file in the correct format using an editor. @ Assemble the source file by using an assembler which produces an object and list fe ©, Wi necessary, correct the source program using the editor J Print out the assembler list le 3. Use a linker which joins together several object Mes, if necessary. and produces a link file which eantains the binary code for the program, A. If necessary for your system, use a locator program to assign the specific addresses in ‘memory for the object code, 4 If your program requires no external hardware, or requires only hardware accessible directly from your system, use a debugger to run and debug your program. J. Wyour program is intended to work with external hardware, use an emulator to ran and debug your program. Pseudocode for flowchart: REPEAT. REPEAT Create source fle with editar Assemble source fle UNTIL no assembly errors Link Locate * external system THEN Load emitlator Load program Run and test program 1 errors THEN use ermulator tools to find errors SE do nothing ELSE Load debugger ‘Load program Run and test program IF exrors THEN tase debugger tools to find errors BLSE do nothing UNTIL no errors STOP PROGRAMMING INTRODUCTION. 9CHAPTER 4 IMPLEMENTING STANDARD PROGRAM STRUCTURES IN 8086 ASSEMBLY LANGUAGE a a. ROLAX,CL: The accumulator is rotated left twice (CL = 02), which leaves AX = 901EH. b. INAL,DX: A byte Is copied to AL from port DX (FFFAH. 6 MOV CX, [BX]: The contents of memory in the data segment at addresses 324B3H and 24141 are moved into cx ‘The contents in the data segment of memory at address 366B3H (BX + SI = 2483 + 4200 = 66BSH, which is then added to 30000 to give the physical address) and address 36684H are added to the AX register. The result te left in the AX register, d. ADD AX, [BXI(SI} © JMPO23AH; The contents of the Instruction pointer are replaced with the value O23AH, and the program execution jumps to address 2028AH. Jf IMPBX; The contents of the instruction pointer are replaced with the contents of the BX register, and the program execution jumps to address 224B3H. Inetruction __Blaary Code Hes ROLAK.CL 12010011 1 000.000 sco BALE — 11201100 Be Mov ex, jx) 10001011 o0 001 111 sor ADD AX, [BRIS 000000 11 60 400 000 0300 LIMP @aAH (1191001 0011 1010-0000 4010 EBSAC2 Inctraction| lag Contents ORC, BORO, 2483.00 14, a Time for one clock eyele = 1/ 5M Each me the loop Is executed, BL is loaded with 72H, Therefore, BL never reaches zero land execution never Teaves the loop. b, Cannot mix bytes and words in instructions, Use elther CX, AX of Cl, Aly or CH, AL- UMP needs a word, or for an indirect jum address, BLis only a byte. ._JNZ can only go to a label in the range +127 to -128 from current IP; cannot use indirect addressing modes, 5.4, b, See the program A04-05B.ASM. © To add 2 BCD bytes, add the instruction DAA after the line ADD AL, NUM2. 6, See program A04-06.8SM, ‘See program A04-07 ASM. 8. Sce program AD4-08.ASM, 9, See program A04-09.ASM. 10, See program A04-10.ASM. 11, See program AO4-11.ASM, 12, See program A04-12.ASM. 13, See program A04-13.ASM. O2s Number of clock cycles required = 300usec/0-2use¢ = 2500 The following code is used for the delay loop: MOV OX, N 14 clock cycles ‘KILL_TIME:NOP, ‘3 clock eyetes LOOP KILL TIME: 17 or S lock cycles N #(C,-C,+DV/C, ©, = overhead eyeles ‘number of eyeles in loop total mumber of eycles wait 1300 1D. =dlfference between LOOP executing or not = 17-5 = 12. ‘Therefore: N= (2500 - 4 + 12}/20= 125, ._ See program A04-14.ASM, o7DH 06 ASSEMBLY LANGUAGE 14CHAPTER 5 STRINGS, PROCEDURES, AND MACROS ‘a. See program A05-01A.ASM. b b, See program A05-018.ASM. See program AQ5-02.ASM. MOV AX, 40001 MOV $5. AX MOV SP, 8000H CALL FIXIT ;Call a near procedure, FIXTT. PUSH BX Save BX and BP PUSH BP at start of procedure POP EP :At end of procedure, POP BX jnotice order of POPS RETS Return from a procedure and Increment SP by 8, See Figure 5-1. If the POPF instruction was accidentally left out of the procedure, the RET instruction would place the contents of the saved flag registers into the IP register. This means that execution would continue, not just after the place where the procedure was called but at some other place. One way to track down this problem is to Keep a map of the stack. Ifyou make a mistake with the stack map, you can run the program to the end of the procedure wnd then examine the registers to see if the RET instruction occurred at the correct SP. Another way to debug this type of problem is to use the single-step facility of the debugger, although this takes much longer: ‘The binary code for the instruction whieh will call a procedure which is 97 addresses higher 2 memory than the call instruction is 11101000 01011111 RET 4; 11000010 0000100 00000000 ‘Three methods of passing parameters to a procedure include: Using general memory and named memory locations. One advantage of thls method 1s thal it makes programs easier to understand, The disadvantage 4s that you cannot use this method for procedures that call themselves or from procedures that will be called from a higher-level language. Using registers to pass values of varlables. The advantage of this method 4s speed —the parameters are immed: ately available in the procedure. The disadvantage is that you cannot pass a large number of parameters unless you use a reuister to just hold a pointer to, for example, an array of data in memory. Note: Recursive and reentrant procedures can use registers, because the register contents will be pushed on the stack during each call. Also note that some higher-level languages for specific machines do allow a few parameters ta be passed in registers Using the stack to pass values of variables. One advantage of this method is that It does not depend on the architecture of the specific processor, 50 it helps make a program “portable Also, this method can be used for reentrant procedures. The disadvantages are the time overhead involved and the complexity of using a pointer and an offset to access the passed parameters, 2000 sp SP initialized by MOV $P, 40008 SPF AH SFFE AL SP -2 then PUSH AX. AL at SP, AH at SP+2 SEED IP HIGH BFFC PLOW SP -2 then PUSH IP Jor CALL MULTO SFFB F HIGH FFA FLOW — SP-2 then PUSH F SFO BH 3FF8. BL SP- 2 then PUSH BX SFF9 POPBX BX = contents of 3FFS & 3FF9 3FFB POPF Flags = contents of 3FFB & 3FFA SFPD RET 1P tents of SPFD & SEFC BFF POPAX AX = contents of SEFF & aFFE FIGURE 5-1. Stack map for question 4 STRINGS, PROCEDURES, AND MACROS. 1310. n, , The term reentrant means a procedure can be interrupted by another procedure at any time, used by the interrupting procedure, and then pick up where it left off in its first execution. You must use the stack or registers to pass parameters to a reentrant procedure. See program A05-07.ASM, See program AO5-08.ASM, For the algorithm, see Figure 6-28 on page 130 of the text. See program A0S-09.ASM, See program A05-10.ASM. 4a, To tell the assembler to make the label BINADD available to other assembly modules, the statement PUBLIC BINADD ‘would have to be added to the part of the program calling the label ». To tell the assembler to look for a byte type data item named CONVERSION FACTOR in some other assembly module, you would have to add the statement EXTRN CONVERSION FACTOR:BYTE, surrounded by the name of the data segment it was declared in, For instance, if st was declared in the data segment DATA HERE, you would have fo add the lines: DATA_HERE SEGMENT PUBLIC EXTRN CONVERSION FACTOR : BYTE DATA_HERE ENDS, 2 POP_ALL MACRO PoP ss POP ES POP DS POP DI POP SI Por BP POP DX, POP CX POP BX PoP AX POPP ‘THERE ARE NO QUESTIONS FOR CHAPTER 6. 14 CHAPTERSCHAPTER 7 8086 SYSTEM CONNECTIONS, TIMING, AND TROUBLESHOOTING 1, The start of an 8086 state is measured from the 50 percent point of the falling edge of the clock. ‘waveform, 2 Latches hold the address information so that the 8086 can float the address lines and then use them for data input and output. 3. The ALE high signal is used to enable the latches s0 that the address information Is passed through to the latch outputs. When ALE goes low, tte address information is held on the Tateh outputs. a ‘The sequence of events on the 8086 data/address bus and the ALE, M/IO and RD lines as the 8086 fetches an instruction word is: 2. M/TO goes high so that memory is accessed, 1b, ALE qoes high wo enable latehes, An address is sent out on the data/address bus. 4 ALE goes low, the audress ts latched on the latch outputs, the latches are disabled, and the data/address bus ts floated, e. RD goes low, causing the addressed device to put data on the bus. f Data comes in on the data/address bus, 9. RD goes high. = A. The word or byte is read. depending on BAB and AO. ‘When writing to memory, WR = 0, RD = 1, and M/IO = 1. When reading from a port. WR = 1. RD = 0, and M/10 = 0. 6 Minimim mode ts used when there is only one ‘microprocessor on the system buses. Maximum ‘mode Is used when two or more microprocessors share the system buses. 7. When RESET = 1, DS, SS, ES, IP, and the flag registers = 0, and CS = FFFFE. 8. Buffers are often needed on the address/data Unes and control buses in a mleroprocessor system because as more devices are added to the system, each device iput or output acts like & capacitance of a few picofarads connected to ground. To change the logie states up/down, all Of the added capacitance has to be charged/ discharged. The 8086 cannot supply enough _ current to charge or discharge the circuit capacitance rapidly, so high-current drive Dutfers are added to da the Job, 9. @ If the READY input is made low, the 8086 “will enter a WATT state ” 10. a a 1B. 14 4. 16. b, An 8086 enters & WAIT state after the falling ‘edge of T, ¢. Information on the buses remains the same during a WAIT state as iL was at the start of the WAIT state d. The 6086 stays in the WAIT state as long as READY = 0. © The 8086 can have any number of WAIT states, J WAIT states are needed if the system contains devices which cannot respond fast, ‘enough for the processor. ‘The DTV signal is used to specify the direction in_which the buffers are enabled. DT/R high + ‘DEN low = transmit data to memory/ports. DI/R low + DEN low = receive data from smeraory /ports The DEN signal ts used to enable the bidirectional buifers on the data bus, ‘The transition at the tail of the arrow causes the transition at the tip. ‘See Chapter 7 tn the text and Figure 7-4 on text age 169. The clock function tells the analyzer how often to take samples. The trigger tells the analyzer when to display the samples stored in its internal RAM. For detalled dming measurements, use the iogie analyzer’s internal clock. a. Use the falling edge of the ALE si trigger on address FFFFOH te see the sequence of addresses output after a RESET. b. Use the rising edge of RD as a clock signal and trigger on instruction OEAH to see the sequence of instructions read in after a RESET. Use the clock signal as clock (falling edge] to see both the addresses sent out and the words read in. - 4. Clock on the rising edge of RD, clock qualifier input connect to M/IO. Set the analyzer to accept clocks when M/TO Is low. It fs possible for a logic analyzer to display data that occurred before the trigger because ‘whenever it receives a clock, it stores samples in its internal RAM. The trigger position specification is used to tell the analyzer to display samples pre-trigger, post-trigger. or center-tigger. Wire-wrap jumpers are shown as, for instance, wor, CONNECTIONS, TIMING, AND TROUBLESHOOTING 15n B 8. 2. ‘The /8 means thet this one line represents & lines. Address decoders in & microprocessor system are used to: 4. Produce a signal which selects the device to be used when you send out an address in ‘the range assigned for that device. Make sure that only one device at a time is ‘outputting onto the data bus. ‘A memory device with 18 address lines and 8 data outputs connected to it will store 32.768 bytes or &-bit words, 'S255As give the SDK-86 programmable parallel ports which can be used individually to Input/output parallel bytes or together to input/output words (high byte to PIA. low byte to P2A), The 8251A 1s a UART used for serial data communication. The 8279 is a eyboard/display interface device. 27883 indicates that the lines come from zone BS (on sheet 2 of the schematics, Seiossesas Stere esses etigsssses 2, J identifies a jack which a connector plugs into, P Identifies a plug which plugs into another connector. |. The small capacitors are used to bypass high- frequency noise on the power supply lines {produced by devices switching from one logic level to another). The large capacitors filter out the low-frequency noise on the power lines. ‘To enable the 748198 you need GUA (A15) low, 2B (RD) tow, and G1 (450) high. The SELECT inputs are A}2, 13, and A14. Figure 7-1 shows the address decoder worksheet RD is used as one of the enable inputs of the ROM decoder to prevent writing to ROM. The decoder is disabled If RD Is high. ‘The memory map for ROM in Problem 24 is: 7000 - 7FFH (8000 - 6FFFH 3000 - 5FFFH 4000 - 4FFFH 3000 - SFFFH 2000 - 2FFFH ree FIGURE 7-1. Address decoder worksheets for question 24 1eseseesoosecee Pes et ek kek ek ks @ woes ST i FIGURE 7-2, Address decoder worksheet and circult for question 26. 16 cHaPreR1000 - FFF (0000 - OFFFH 25, See Figure 7-2 for the address decoder worksheet and the circuit. 2, Many addresses will select one of the port devices connected to the port decoder in Figure 7-12 a because AG-ALL are not connected to the port device or the decoder. They have no effect, ‘on selecting a port, so they ean have any value. 28, Memory-mapped 1/0 is done by using a decoder which translates memory addresses to chip select signals for part devices. The advantage of this is that any instruction which references: memory can be used for 1/0 to ports. The disadvantage is that some system memory address space Js used up for ports and is therefore not available for memory. Direct 1/0 ‘uses a separate address space for [/0. tt has the advantage of not using the system memory M1G-A1s 415 8 ANE AO Of 62 02 01 Addroes stock 2 ¢ 6 9 0 r1e0 Hed ds o- unre 8 oo fo tite 8 ete op oekd 8 9 1 8 ft ef at 2e00~ oer Hee ea bo an fs s e co 0 bis a o FIGURE 7-3, Truth table and ciccuit for question 22. 30. a 23 38 address space and the disadvantage that only IN ‘and OUT instructions can be used for 1/0 of data, @. The memory 18 set up es 2-bytewide banks 50 that it is possible to read/write elther ‘words or individual bytes, b, When writing a byte to 01274H, BE = 1 and AD = 0, When writing a word (0 04274H, BEE = Oand AO =0, Two machine cycles required to write a word to address 04973H are as follows: i, During the first machine cycle, the 8086 vill output the address 04378, make BHE , and £0 = 1. A byte will be written to 04973, WA = 0 and M/IO = 1 4. During the second machine cycle, the ‘BOSE outputs the address 04974, makes BHE = 1, AO = 0, The second byte will be waitien (6 04874, WR = 0, and M/IO = 2. ‘You cannot accidentally waite a byte or word to ROM because RD = 0 enables the 3625 PROM decoder, If RD = 1. the decoder is disabled and ROM cannot be selected. Some ROM is put at the top of the address space because the 8086, when reset, goes to address FRFFOH to get its first mstruction. a. For the truth table and ctreutt, see Figure 7-3. Reading a word from ports FFFSH and FFFOH requires the loge levels shown on the following staat: ‘BEE = m/G AD-A2 «0 ALAIB = 1 AIG-AIS =0 Ports are direct 1/0. Reo | Wet ‘The instructions to do the read operation are MOV DX, OFFFSH IN AX, DX a. The OFF BOARD signal will be asserted low if the 8086 is doing a memory operation and the address sent is not in one of the ranges decoded for the on-board RAM/ROM. b. The purpose of the OFF BOARD signal is to enable buffers for devices added to the ‘expansion area of the SDK-86 board ‘There is only one memory bank in the 8088 system. Because the 8088 has only one memory bank which contains both odd and even addresses, the BHE signal is not necessary. a. Maximum clock frequency Is 8 MHz b. TCLRL » 100 ns. TCLDX (Data Hold Time) = 10 ns d. TLLAX = TCHCL - 10 = 44- 10= 84 ns, CONNECTIONS, TIMING, AND TROUBLESHOOTING 1737. For the 27128-25: yoo ® 250 NS: tog = 250 nst fog = 20 Address latches propagation delsy =, = 12 ns ©. Use a working system to systematically test the ICs from the nonworking system, An oscilloscope checks the power supply for oo excessive noise or nipple For the 8086+ = Ty =Ty= Ty = state time 40, Mark each IC from the good system with a wide- TCLAV = 60 ns up, water-soluble marking pen. TDVCL = 20 ns i : TOLRL= 100 ns 4, Soe Figure 7-4a for @ routine to test the systern ‘Time available for tage OF tx! RAM at addresses 0200-O7FFFH, T, +1 4T,~ (ICLAV-T, -TDVCL) 42. See Figure 7-4 for a routine to output 375-92 = 283 ns, altemating pattems of all 1's and all Os to port This time is greater than tyoe OF lop required by FFRFOH over and over. the 2726-28, 43. a. If pin 8 of ALS (2205) ts stuck low, the ‘Time available for tgs: 1) +7,-(CLRL-T, + TVCL} = 250 ~ 150 = 100 ns. This me equals top, 50 It fs not considered an adequate available time for memory access for the 27128-25. The device may not work correctly in the system. A WAIT state can be inserted to ‘ensure proper operation. ‘To troubleshoot the microcomputer system: & Identify the symptoms. Male a careful visual and tactile inspection. Check the power supply. ‘Check the control signals such as RD, WR, ALE, RDY, and RESET. FIGURE 7-4. Routines to test system RAM, la} For question 41 (b) For question 42, processor is in a NOT READY state and will keep inserting WAIT states. The signals on the buses will all be at constant logic levels. If the RESET key is stuck on, DS, ES, SS, IP, and the flag registers will be zero and CS will be FFFFH. There will be no activity on the buses. = If none of the outputs of A29 (6ZD7) ever go low, nothing will be read from or written to RAM, RAM is never selected. Hf pin G of AS {5ZAS) Is stuck low, off-board devices will never be accessed because OFF BOARD ts always high, b o we HATER 7—_—_—_—_— CHAPTER 8 8086 INTERRUPTS AND INTERRUPT APPLICATIONS 1, The 6056 will push the flag register on the stack, Gisabie the single-step function and the INTR input, and do an indirect far call to the start of the interrupt procedure that was written to ‘respond to the interrupt. 2 The 8086 interrupt-vector table stores the starting addresses of the interrupt-service procedures. 3. Type 2 imterrupt-vector IP at. 00008H, CS at 000A, 4 Type 4 interrupt-service procedure starting address is 0010:0082. Put 0010 ai address (000121 and 0082 at address 00010H. S @ The locations correspond to a type 82 intesrupt, b, The starting address is 0040:4424 (048-241). See Figure 6-2 on page 208 of the text. 6 A type 0 interrupt is caused when the quotient from a DIV’ ov IDIV operation 1s'too large to ft in the result register. Dividing by zero is @ special case of ths, Ape 1, single-step interrupt is enabled when the TRAP lag is set. A'ype 2, nonmaskable Interrupt results when ‘the 8086 recetves a low to high transition on its [NMI input pin. ‘A type 3, breakpoint interrupt is caused by the execution af the INT instruction, ELTm\ PouGR ese sFan NeSPROG_MERE ENDS ENRSSUNE COsCODE Mere Store ascress for piv cove_vent Bibs w= for POUER FAIL pracedu ‘ion ‘ete eciocont, See PoveR Fale ORD PIR Eeiococn, OePSET POoER FAIL 10. oe ‘DIv_0-ERROR and Pout A ‘type 4, overflow interrupt Is caused when an INTO instruction executes after an overflow error sets the overflow flag. If the overflow flag is not set, INTO acts as a NOP. PUSH and POP all the registers-used in the procedure so that the interrupted program will Tesume with its regisiers the same as they were before the intermapt. ‘You should use an IRET instruction because, as part of Its interrupt response, the 8086 pushes the flag register on the stack and IRET pops the flag register and the return address off the stack. RET pops only the return address. ‘The assembler directive and instructions are shown in Figure 8-1 1. The main use of the 8086 type 1 interrupt is to implement single stepping in a debug program. >. PUSHF :Push flags on stack MOV BP, SP BY SP to BP for use as OR [BP + 0}, 0100H :an index. Set the TF bit. POPF store the flag register. ‘The mainline program {s in AO8-11A.ASM: the procedure is in A08-11B.ASM. 4. The 8086 INTR input is disabled to allow you to initialize ports, timers, registers, and interrupt controllers without being disturbed by interrupts. b, The INTR input fs enabled by setting the IF ‘with the STI instruction, word 1 esro002H, sep o1v_0_exROR FIGURE 8-1. Assembler directives and instuctions to intalize an interrupt pointer table for 2 type 0 and a type 2 Interrupt INTERRUPT APPLICATIONS 188. M, 5 2 The CLI (Clear Interrupt) instruction will disable the INTR input, 4. Disabling INTR ensures that the INTR input signal does not cause the 8086 to continuously interrupt itself €. The INTR is automatically reenabled by the IRET instruction, which restores the flags to the condition they were in before the procedure. ‘The 8086 will push the flags on the stack, clear ‘TP and IF, push the return address on the stack, 9 te the start of the divide error ftype 0) service procedure. The 8086 will then respond to the NMI (type 2) interrupt. When the 8086 finishes the NMI procedure, it will return to the divide error procedure, finish executing that procedure, and then return to the mainline rogram, ‘The algorithm and mainline program are in AOB- 14K.ASM: the procedure ts m A08-14B.ASM, ‘The algorithm and mainline program are in AOS- 15A.ASM; the procedure is In AOS-15B,ASM, ‘The algorithm and programa are in ADE-16.4SM. Break at @ HERE-JMP HERE to see ifthe vector table is initialized correctly. b, the start of the interrupt procedure to see if execution gets there. © after AND AL, 7FH to see the character loaded into the buffer. 4d, alter POP AX to see if the retum address 4s comet. @ The base address for the added 8254 will be FFOOH. b, The eight data lines should be connected to the upper half of the 8086 data bus (AO » 1) © Counter O—address FFOOH; counter 1— address FFOBH: counter 2—address FFODH: control word—address FFOFH, The control word is 01 11 011 1. MOV AL, 7H :Control word 01110111 MOV DX, OFFOFH ;Point at control register OUTDX, AL Send control word MOV DX ORFOB :Point at counter } register MOVAL, 56H Load LSB OUT DX, AL Send LSB to counter 4 MOVAL.03H Load MSB OUT DX, AL Send MSB to counter 1 Jf Assuming the GATE input is high, the count 4s loaded on_the next falling edge of the CLK Input after WR goes high. The counter will start counting down in MODE: 3 on the next clock pulse after that. 49. The waveform will be a symmetrical square ‘wave {the number is even} with a frequency of 2 kia (712000/356 Hz}, 2 period af 0.5 ms {2/2000 sees), and a 50 percent duty cycle cuapren 8 8, 20, 2 A. This control word will set counter 2, read/write LSB only, MODE 0 (interrupt on terminal count), with a binary count, ‘The calculation to find the value to be written to ‘the counter is: Clock signal 2.456 MH 456,000 Hz Frequeney Required = 1/0.0012 Hz 133.833 Ha, Count Required = 2,456,000/893.33 » 2047 MODE 1 (one shot), write LSB and MSB, count m BCD. Contral word 0.110011 MOV AL, OB3H Load control word MOV DX, OFFOTH :Point at control register OUTDX, AL Send control word MOV DX, OFFOSH :Point at counter 2 register MOV AL. 47H Load LSB of count OUPDX, AL and send to counter 2 MOV AL, 29H Load MSB of count OUTDX. AL jand send to counter 2 Assuming the 8264 was programmed for read unite the LSB and MSB when initialized: MOV AL, 010000008 :Counter 1 latch command MOV DX, OFFO7H © :Point at controt register OUT DX, AL ‘Send latch command MOV DX, OFFOSH — :Point at counter | address IN AL, DX ‘Read LSB of latched count MOV BL, AL rand save in BL IN AL. DX ‘Read MSB of latched count MOV BH, AL ‘Count now in BX When an 82594 receives an interrupt signal on ts IR2 input, (assuming 1R2 ts unmasked in the 82594 and the 8086 INTR Input has been chabled with an STI instruction). the priority resolver checks the bits in the IRR (interrupt request register) to see if the interrupt is unmasked. As IR2 is unmasked, the priority resolver checks the ISR (In the service register) to see tf g higher-priority input is being serviced. FR2 has the highest priority (all other interrupts are masked), 80 the priority resolver seis bit 2 in the TSR and activates the clreultry, whieh sends an INT signal to interrupt ie 8086. When the ‘8086 sends out an INTA pulse in response to ‘his interrupt, the 8259A responds with the type ‘number for the IR2 service procedure. The 8086 uses this type number to find and execute the TR2 service procedure, ‘The cascade pins (CASO, CASI, CAS2} from the master 8259A. are connected to the corresponding pins of an 82394 slave. For the master these pins function as output, and for the slave they function as inputs. When the master receives the first INTA pulse from the 8086, #t outputs a 3-bit slave identification ® 1a the CAS lines fo enable the slave that has been given that ID number with an ICWS23. Assuming a fixed priority for the IR inputs, the 825A will service an intermupt on its [RB input bbefore st services an interrupt on its IRS input coven if they are received at the same time. if 0 interrupt signals occur at the same time, the 8259A will service the one with the higher Priority first, assuming both inputs are unmasked. If the 8259A is servicing an IRS interrupt and an IR3 interrupt ocenrs, the Priority resolver will check to see if the IRS is unmasked. It then checks to see if ¢ higher Priority interrupt fs being serviced. As the new Interrupt has higher priomty, the priority resolver sets the appropriate bit in the ISR and activates, the circuitry, which sends a new INT signal to the 8086, f the 8086 INTR input was reenabled with an STi instruction at the start of the IRS service routine, the IRS will interrupt the IRS service subroutine, When the IRS subroutine is ver, control is returned to the IRS routine. Pion one FF ien Pats sobtsot i DUT Das aL. 24, An EO! command resets the in-service register 80 that the higher-priority interrupts may be serviced, 25, Sec Figure 8-2 for the sequence of command ‘words and instructions, ‘The advantage fs that you don't need to worry about the absolute address where the procedure actually resides or about trying to link the Procedure into your program. All you have to ‘now Io the interrupt iype for the procedure and hhow to pass parameters to the progedure 26. enone sesoe ing E598 for conditiens above 1 Tyee 40 te tno FIGURE 8.2. Command words and instructions to inialize an 62594, INTERRUPT APPLICATIONS. 21CHAPTER 9 DIGITAL INTERFACING 1, Date ts sent on a handshake basis to prevent the sending system from sending data bytes faster than the printer can read them. 2. a. The sending device asserts tts STB signal: the receiving device asserts its ACK signal. . The sending device asserts its STE signal low to determine if the recelving device 1s ready. ‘The receiving device indicates it is ready by ralsing its ACK signal. The sending device then sends a byte of data and raises its STR high te indicate that valid data ts on its way. After the receiving device has read in the data, It drops its ACK line low to tell the sending system that it has the data and is ready for more. 3, Port lines are inputs on reset to prevent ports from outputting into the outputs of a device connected to the port and possibly destroying ‘one or both outputs, 4, Port A-FFPOU: port B-FFPBH: port C—FFFDH: control—FFFFHE input; port B—handshake output; port (C=PC6 and PC? outputs 10110100 handshake | | Port C lower not used Port B output (port B movie 1 {_____ Pcs P07 outputs: Port A input Port A mode 1 ‘Mode set flag active Input control signal definition: INTR A controtied by bit set/reset of PCS go001001 Bit set (enable interrupe) Set bit PC4 Don't care Bit set/resot lag active Output control signal definition: INTR'B controlled by bit set/reset of PC2 99000101 ‘Ltt set enable interrupt) Set bit PC2 Don't care Bil set/reset ag active MOV DX.OFFFFH :Point to 8255A control register MOV AL, 101101008 ;Ports control mode-set word OUT DX, AL. MOV AL. 000010018 OUT DX, AL MOV AL, 000001018 OUTDX, AL ‘Set up an interrupt jump table for the ‘interrupt procedure, 4i, Initialize the 82594. edge triggered, ADI = X, singe. ii, Tew = 6088 mode. fv. Unmask the IRS input. ¥. Enable 8085 INTR input with STI -Set/reset word for INTR & :Sel/reset word for INTR B instruction. MOV DX, OFFFFH —— ;Point DX at control register MOV AL, 000011015 ‘Set/reset word {set PC) our Dx. AL ‘Send set/reset word 4, The tape ceader sends a byte of data to port A on its 8 data line, & then asserts its STB signal low to tell the 82554 that a new byte of data has ‘been sent. In response, the 8255A raises its [BF signal on PCS high to tell the tape reader its ready for the data, When the tape reader sees the IBF is high, t raises tts STB signal high agen ‘The rising cage of this signal causes the data to be latched on the input latches of the 8255A and, if the interrupt signal output has been enabled, causes the 8255A to output an interrupt request signal to the 8086 on bit PCS. ‘The tape reater can then remove the data byte in preparation for the next data byte. When the 086 reads a byte of data from the 8255, the falling edge of RD causes the 8255 to resct its INTR output. The rising edge of RD causes the 8255 to reset the IBF signal, telling the tape reader to send the next byte. 7. When connecting peripheral devices to a computer, connecting the logic and chassis ‘grounds together only at the computer prevents Targe noise currents from flowing in the logic ground wire. & @ STROBE computer -> printer; character available. b. AGRNEG printer > computer: data accepted, ready for the next character. ¢. BUSY printer -> computer; not ready to recetre character (e.g. out of papent. i. INIT computer -> printer; perform printer internal altialzation sequence, 9, For the algorithen, see Figure 9-15a on page 266 DIGITAL INTERFACING 28of che text. Programs AO9-09A.ASM and AO9- (093.4SM show the printer driver mainline and printer driver procedure. 10, Yes. There has to be a 0.5 ys wail before the STROBE Is asserted low. The instructions © desert the STROBE low take" 16 clock cycles. (MOV DX, OFFFH = 4, MOV AL 000000120 = 4. and QUT DX, AL = 8 clock eycies) ‘The time for } clock cycle with an 8-MEz 8086 = 0.125 us. ‘The time for 16 clock cycles = 2 ys, which fs greater than the minimum time required (0.5 ys) Fpefore asserting the STROBE low. uh MOV DX, OFFFDH Point at port C mab, DX "Read status word from C AND AL, 001L1111B iMask o/p lines of ‘word 12, ‘The three major tasks are detect, debounee, and encode, 1S, The compare method works as follows. The Ireypress codes are placed in a table tn the order Of the hex codes they represent. Once a code 18 Ghtained for the keypress row and column, thet Cade ‘= compared with each value in the table Soil a match is found, A counter is used to keep te of how fa down the table you have to go t@ ide match for @ particular input code, When & match is found, the counter wil contain the hes code for the key pressed. 14 Error trapping is necessary in real code: conversion programe so that, if no match 1s found when all code comparisons have been nade, the program gives an error message rather Shan conlinuting to compare after it has reached the end of the code table. In the program in Figure 0-20 fn the text, if BX ss decremented below zero, the sign flag will be set (BX = PEEFED, The program wil fall through the INS fnsteuotion and the error code Joaded in AH (AR wpi-—invalid code, AH = 00—valid, code). AK is Fetumned to the calling program. which checks to Ser if the code in AL fs valid by checking the contents of AH, ts See program A09-L5.ASM. XLAT fe more efietent ‘because it requires the execution of only two Joads and one XLAT instruction. The compare method would have to scan the table until it found a matching entry. 36, a The answer is 770. The calculation 18 28 1 = 40 mA per segment Vy, = vollage drop across LED when lit = 1.5.V Vi = output low voltage for 7447 ts max of 0.4 V @ 40.mA fg VirVq2 50-15-04 2 3.1 TR rclared reftstance = Vail = 77-50 (appzox. 779) b. The enswer is approximately 100 mA. The 36 CHAPTERS -08 Y, Wy= 15 Vono apa = 04 VE tnlting Fedistor, R= 220) Va Vor 1 = VR = 2°3.v/200 = 100 mA approx. 17. a. See program A08-}7.ASM. b, See programs A09-17A.ASM and A09- {SB.ASM. The procedure Is called every 2 ms bby an interrupt signal to IRS of an 82594. 18, See programs A0-18A.ASM and A0®-18B-ASM. 38. a. Look at the output line from the ULN20034 aga) to see If it changes. Also, try another ED: that segment could be burnt out. b. Alow may never be sent to the digit-driver transistor on Hine 07 from the 7445. Put a Scape on te digit-8 Iine out of the 7446 (432) fo nee if it ever goes low. Ifa signal is present ton O7, cheek to see if the collector of the PNF Gnwer transistor goes to approximately +4.2 indicating that the transistor fs on. c All the digits must be lit at the same time, heck the outputs of the 7445 to see tf any Gre Os. if they are all 0, all digits are being Geven, An alternative possibility is chat che Slenidng code of FPH 3s not being sent. This ‘would produce a ghosting effect on the LEDS. 26. Seq Figure 9-1 on the next page, Zi, See program [email protected]. LOD displays deteriorate rapidly if the backplane ‘and segment-line signals are not pulsed, 2a. The circuit n Figure 9-86 on page 279 of the text an be aitached to an 82558 port & pin to drive SA solenoid valve from a +12 V supply if 10- {ual resistor is connected from the input base to 2 v and the transistor is mounted on & Ineatsink. 24, This placement of reverse-biased diodes i6 hhesessary to stop the induced voltage inductive ick) caused by the collapsing magnetic field. which will usually be large enowgh to break ‘own the transistor. 28 a, MOSFET = metal oxide semiconductor Held Eifect transistor: IGBT = Ssolated gate bipolar tansistor: b. These devices have high-input impedances, so they require only ar input voltage to tum them on, Darlington bipolar transistors require an input current. 2s, G Disadvantages of mechanical relays include treing between contacts and switching on/off ft any point in the ac cycle. bb. Golidestate relays produce less BMI, have no mechanteal contacts to are, and are eastly Shiven from microprocessor ports.27. a, Blecirical teolntion is achieved optically. b, The zero-crossing detector turns on the current at the zero voltage point of the ac cycle, © A snubber circult prevents dV/éP taming on the tri, 28, See program A09-28.ASM. eyboand/ display mode set command word DD.= I6scharnctercispey, lft entry 2, When reading the shaft position, gray code reduces the size of the largest possible error to the value of the least significant bit. ‘The angular resolution is 360/2* = 360/64 = 5.625", ‘The waveforms represent clockwise rofation, ‘See program A09-B0B. ASM. See program AO9-30C.ASM. ore (000 Dp HK 1 ‘Encoded scan keyboard, W-key rallover KKK = 010 Program clock command word = 001 PPPPP. 1 Miz clock divided by 10 PRPEP= 01010 (Clear Control Word = uecee 011 Blanking character of 11 CCC = 000) Data address 081 Control address = 82H MOV AL. 000010108 _:Load Keyboard/Display command word our sit. aL and send to 6279 contrat MOV AL, 001010103 Load program clock cortiand word OUT 62H, aL and send J 08279 control MOV AL, 110000008 :Lad blanking command word OUraai, AL + and send | b ‘Write 89H to frst leeation in dleplay RAM ‘and autoinerement display RAM pointe, MOV AL. 10010008 OUT S2H, aL MOV AL, 96H (OUT 80H. AL ‘Read frst byte from 8279 FIFO RAM. ‘MOV AL, 010000008 ‘Load waite display RAM eantrol iword and send to 8279 control ‘Load 7-segment code for 99 and ‘send to display RAM date adress ‘Loa real FIFO RAM contr! word ourszit aL land send to 6279 contro) WAL, 50H, Read FIPO RAM 4 Segments to be Mt: H= glecb, E= gleda, L= fed, P= gfeba Code on data fe deba nes for H = O1lL o1l0 = 76H B = 011 1001 = 7oH L = 0011 1000 » seit P= O11 ool = 7aH :Clear control word = 110 {CdCHCa = blanking code = 100 ‘Cf = Clear FIFO =1 Ca = Clearall= 1 MOV AL, 110100118; Clear mode wort our sat, a1, + Send to 8979 contra eddress FIGURE 9-1, Answer to question 20 DIGITAL INTERFACING 25,CHAPTER 10. ANALOG INTERFACING AND INDUSTRIAL CONTROL 1, a. The comparator will putput (+15 ~ V = 14. b, Closed-loop voltage gain = Ayo, = (RI + ROY/RI = 20. Voor = Viy ¥ Avg, = 0.08-V X20 =0.6 V. Vie = Voltage on inverting input = 0.03 V. TER2 = OM, then Aya, = (10K + 0/10 ° Ry/R1 = 784/ 15k = 5. Voor = Vpe % Agcy = —0.73 X 5 = ~3.65 V. Zero volts is always measured on the inverting input of this amplifier. 4. Vogr # (V2 ~ VIRYRI = (5.1 ~ 4.9}1M/100k Vv. €. ‘The instrumentation amplifier provides better rejection of the common-mode signal. J. The closed-loop bandwidth ts f,= 1 MBz/20 = 50 KHz. In part 2 of question 10-16, f, a MEz/1. 2. The elrcutt is shown in Figure 10-1. wx a vei FIGURE 10-1. Circutfor question 2 3. Voltage on inverting input = -2 V. An FET input smplifer short be used because the photodiode leakage eurrent is very small and the FET input amplifier does not require an input-bias current. ‘The electrons will flow from the output of the amplifier through the resistor and then through the photodiode to ground. This current is the leakage current for the diode. 4, A temperarure-dependent current device would bbe used for applications where long wires are necessary for connecting the device to the rest of the cireuft. A temperature-dependent voltage fevice would not suit these applications because of the voltage drop along the wires. 5. Assecond junction provides a reference, and that reference is held at a constant temperature. The nonlinearity can be corrected with analog lreutry which changes the gain of an amplifier ‘according to the value of the signal or by using = lookup table in ROM, 6, Strain gages are usually connected in a bridge configuration so that temperature-caused cchanges tn the unstressed! gage compensate for 4 Bw 2 temperature-caused changes in the stressed gage. You use a differentia) amplifier because you want to amplily the difference in voltage between the reference strain gage and the measuring strain gage. ‘The full-scale output voltage is: Voor = Veer (1/R1 + 1/R2 + 1/R3 + 1/R8) x = S'VUL/100k + 1/S0K + 1/25k + 1/12.5h) x 10k = 510.01 + 0.02 + 0.04 + 0.08) x 10 = 8x 015x10V = 75V ‘The resolution Is 1 part in 2° = 0,012 percent. ‘The alze of each step is 10.000/8192 = 1.22 mV. ‘The actual maximum output voltage = (10.000 ~ 1.22 mV) = 9.9988 V. The converter should have an accuracy of (100 X 0.8 x 0,00123/10} = 0.01 erent, Latehes on D/A inputs prevent incorrect output values caused by the time between the two ‘urttes required to get all of the information to the D/A See the seetion Parallel Comparater A/D Converter on page 304 of the text. The main advantage is speed of conversion. The main disadvantage is that this type of converter has ‘many parts and so is relatively expensive. ‘The number of counts displayed is directly ‘proportional to the input voltage. An input of LV = 1000 counts: therefore, an input of 2.972 V = 2372 counts. The resolution of a 4.5-diait, slope- type A/D converter Is I part in 19,999 or between 14 and 16 bits, ‘The conversion requires 12 clock cycles. Note: Some converters use one additional clock pulse for Internal housekeeping, ‘The number of clock eyoles required for @ 12-bit, ual-slope type has diflerent values in diferent systems, but is fixed for a given system, ‘Assume 5.12 V full scale: Clock cycles = full-scale count Viy/Vinu sae For 0.1 V, clock eyeles = 4096 x O11 /5.12V = 80 counts 4096 «5.0 /5.12V = 4000 counts 4. See program A10-13.ASM. ‘See program A10-13B.ASM. The successive- approximation algorithm Is much faster, because ft only takes 8 cycles through the ‘conversion loop to do an 8-blt conversion. For 5 V, clock cycles [AVIALOG INTERFACING AND INDUSTRIAL CONTROL 271, Te aigorta flow: 17, The voltage measured on the inet input of Full dig 1 ISD) suobe ust hgh the NGOS shold be 8. Unth so loa et Read Me es Fouts BOD nibble o high ble Soave ey Must iow able Move wit 18, See progam AIO-18ASME Pol ig 2 robe ut gh 18 See the section Oseriew of dust Process Read igh Conrton page 37 ete tee OR with digit 1 in BH 20, Integral feedback helps eliminate restdusl error, Poll digit 3 strobe until high but the effect of integral feed is slow. Derivative ead taigt 9 a —E_ Rouse BOD able to upper ie eda Mek iver ae Move wo Bt 21 The major advantage of a microcomputer: Puli strobe unt high tontolcd lop is Versi Proceos vain ead aie the rate mt which cord lope ave seeded i the feedback aigoritins an be edotee By Oren gt 3 mbm BL Ll spetuedtiis 22. @. See Figure 10-20. Dl Output code = 644 1648+3=91 +b, See Figure 10-2b. Fe s=—=‘=‘‘OWYCSCSCSCNYRSC OCR You could convert to 2's complement gee ae ecueaeang tie Eee Fepreventation by inverting the MBB of the speed from the setpoint and using the _ iference ae a pelmter into w table to Getesmine the ow value (eB ee 16 See the program A1O-16.A5M. bia vipveran we one 7 28 CHAPTER 10 © FIGURE 10-2. Question 22 (a) Circuit. (b) Algosthr,23.2, b, See the section Tine-domain and Frequency domain View of a Square Wave on age 337 of the text . Ste the section Digital Alters on page 388 of the . The output value of an IR filter is saved to be used in computing feedback terms. In the FIR filter, the samples from the A/D converter are directly saved to be used in later computations. See the section Digttal Filter Hardware on page 839 of de text, ». Features of a digital signal processing microprocessor inelude sizable amounts of ‘on-chip registers. ROM and RAM; separate ‘nes for code words and for data words: an ‘optimized multiplier: a 92-bit barrel shifter: a 16-bit or 42-bit CPU, an imetruction set optimized for DSP applications; and, sometimes, = floating-point processor, 26, 2 a ‘The sampling theorem says 2 samples/eycle, but the more samples per cycle, the easier It {sto reconstruct the sine wave, b. An analog low-pass flier prevents altasing by filtering ont signals that have a frequency greater than half the sampling rate. ¢. The sample-and-hold clreuit ts used to keep the value on the input of the A/D constant ‘during the conversion eyee. In writing the program for a digita? filter, determine the coefficients that the terms in the ‘equation will be multiplied by to implement the desiced filter. Write a program which reads im values from the A/D, computes an output value, and sends the computed value to the D/A ‘converter at the right time. ANALOG INTERFACING AND INDUSTRIAL CONTROL 29——— CHAPTER 17 DMA, DRAMs, CACHE MEMORIES, COPROCESSORS, AND EDA TOOLS Peripheral expansion slots let you easily customize the system based on your applfcation and financial state. Then you won't have to pay Jor features you won't use. In an 8086 operating in maximum mode, the control bus signals are sent out in coded forin on the status tine $0, 31, and 52, An external controller, such as the Intel 8288, decades these lines to produce the required contral ius signals, DMA data transfer is faster because the data does not have to go through the microprocessar {is transferred directly between the peripheral and memory. * The series of actions performed by a DMA controlier is as follows: @ if that channel of the DMA is unmasked, the DMA controller sends a hold request (FRG) to ‘the microprocessor HOLD input, b, The microprocessor Moats its buses and sends out a hold acknowledge (HLDA) signal ‘to the DMA controller. © The controller outputs on the address bus the memory address for the data to be transferred. & The controller then sends a DMA ‘acknowledge signal [DACKO) to the peripheral Geviee to tell it to get ready to output a byte. #. The controller asserts MEMW to enable ‘addressed memory for writing data to it. JS. The controller then asserts TOR to enable the peripheral device to output data. The data is ‘then transferred, ‘The 20-bit address ts produced as follows: @ The DMA controller disables UI so that address lines A7-AO no longer come from the 8086 bus. The controller directly outputs these bits of the memory address, b. The controller then outputs bits A1S-A8 of ‘the memery address on its data bus pins and latches this address on the outprts of U2. © Bits A19-A16 are produced elther by hard ‘wiring the inputs of U3 to give fixed values for these addresses or by specifying the bits under program control by connecting the inputs of US to an output port, ‘The deviees US and US act as a switch whict nr route data to/from the disk controller 10. m from/to ether odd or even addresses im memory. AO determines which half of the data bus is ‘connected to the eight disk controller data pins. ‘The sequence of signals is shown in Figure 11-8 on page 354 of the tex, ‘The major tasks to be done when using dynamic RAM in @ microprocessor system are: & To refresh each RAM location at the proper ‘time interval. ‘5 To funnel the two halves of the address into gach device with the appropriate RAS and EAS strobes. © To ensure that a read or write operation and a refresh operation do not take place at the ‘same time, 4, To provide a read/write control signal to ‘enable data thto/out of the devices 1¢ 8086 to insert a WAIT state which gives the controller enough time to Dish Its refresh eyele. 4 The time parameter ts the read-oyele time, ‘wt D. If successive date words are read from locations in the same page (row), no precharge time is required. Also, if successive ‘data words are read from the seme page, the row address is the same, so a new row address does not have to be sent out and strobed in with another RAS signal, With the roper controller, these two factors make it Dossible to read data from a page without WAIT states, 6. In page mode operation, as long as the Inlcroprocessor continues to access memory locations inthe seme page, the controller a hold RAS low. send out the column part of {he addresses to the DRAMSs, and pulse CAS low for each new column address. Static column mode operation operates se pase ‘node forthe fist memory acces. Ifthe next address Is In the same tow, the DRAM controller wil hold both RAS and CAS iow and send outa sequence of column addresses & See the section Cache Mode DRAM Systems (on page 358 of the text OMA, DRAM, CACHE MEMORIES, COPROCESSORS, AND EDA TOOLS 31 A nceRB 1. is 1, 16. ” B, A cache controller uses a cache tag RAM (cache directory} to keep track of which Blocks from the main memory aze present in the cache, Bech entry in the cache tag RAM contains the upper bits or base address of @ page in the main memory. In the case of the intel 182985 cache controller, each directory entry also contains a tag valid bit and eight line valid bite for the eight lines represented by shat entry. . The two-way set associative cache approach ‘tts up two separate caches and two separate lrectaries so that the same lines from two tlfferent pages can be cached at the same time. In microcomputers aueh as the IBM PC, the DRAM memory banks are 9 bits wide. A parity generator/checker eireult determines the parity of an 8-bit data word as ft $8 being wntten to a ‘memory location. A parity Dit Is generated such that the averall parity of the 8 data bits plus the parity bit 1s always, for example, add. When the data byte and paztty bit are read from memory, the parity of the 9 bits is checked. Ifthe parity of these bits ts not as st should be, an error has been introduced somewhere, ‘The major shortcoming of this method of error eiection Js that two errors in a data word can cancel each other. Also, you know only that an error fas occurred, not which bits are in error. Seven encoding bits are required to detect and correct & single-bit errar in a G4-bit data word ‘The 8088 Is configured in maximum mode because the MN/MX pin Is tied to ground, You would look on schematic sheet 2 to see how the AEN signal is produced. Coprocessors are specialized microprocessors. A standard microprocessor Instruction set is general purpase. A standard microprocessor can operate alone, whereas a coprocessor needs a standard processor as @ host. "y: 8488,5625 = 100110000011.1002, Normalized binary: 2435.5625 = 1,00110000011 1001 E11 (OBE) Long-real format: 2435.5625 = 40A3 0720 (0000 0000 (Exponent = 3FF + OBH = 404H; ‘magnitude = 011 0000 0111 0010 + $6 zeros) a Bi ‘Temporary-real format: 2495.5625 = 4004 9829 0000 0000 0000 (Exponent bits « OBH 4 SPFFH = 400AH; number = 1001 1000 0011 1002 + 48 zeros. Note: MSB = 1) bo Most floating-point numbers are appraximations because you need an infinite number af digits to represent some of the numbers you work with. 32 CHAPTER HT 18 a. 1. a. Register 0 is TOS after the 8087 Is reset. b. Register 7 will be ST after one data item is read, © The contents of the ST) location are added to the contents of the ST(Q} location. The result Is lelt in the ST(2) location. d. The stack will be popped once after the instruetion. The result will be in ST11). G. FLD TAX_RATE: Decrements pointer and pushes the contents of memory called ‘TAX RATE on stack at new STIO). , FMUL INFLATION FACTOR: ST ts raultiphied by INFLATION FACTOR. and the result is placed in ST. © FSQRT: Replaces contents of ST with square root af ST. 4. FLDPI: Decrements pointer and pushes the value of on the stack. € PSTSW CHECK ANSWER: Copies 8087 status word to CHECK_ANSWER and inerements pointer. J. FPTAN. Produces tangent ratio (¥/X) for angle in ST. ¥ value replaces the angle, X 1s pushed on the stack. Therefore, X ends up at TIO) and ¥ at STU) ‘The assembler inserts 9BH to allow the 8087 to nish the instruction before allowing the 8085 to ‘continue with its next instruction. ‘See program Ai1-21.ASM, @ The standard microprocessor and the coprocessor share status, QS1-QS0, address, and data lines, so they have to be connected ‘together. The fact that the status and queue ‘status lnes are connected allow the 8087 ta wack the 8086 queue. b. The 8087 coprocessor gets its instructions from memory as they are fetched by the 8088 and puts them in its own queue. © The main processor distinguishes its instructions from these for the 8087 by the fact that the 8087 instruction codes have NOL! as the most significant bits of their first code byte. 4, To load 2 long-real data item from memory to ‘the 8087 ST, the 8086 outputs the address of the first data word on the address bus and outputs the appropriate control signals. The 8087 reads a data word from the data bus and the 20-bit physical address output by the 8088. The 8087 then takes over the bus ‘from the 8086 to transfer the remaining data words it needs from memory directly to the 5087. , The 8087 sends out 2 low-going pulse on its Q/GTO pin to signal the 8088 that it needs to use the buses, fF You can prevent the 8088 from going on with, its next Instruction before the 5087 hasM a completed an instruction by putting an FWAIT instruction before the 8087 instruction in your program. The FWAIT struction causes the 8088 to sit in a loop until its TEST mput is asserted low when the 5057 unasserts fls BUSY signal. See the section tnitial Design and! Schematic Generation on page $79 of the text. A circuit diagram can be easily and quickly hiodified and resimulated. Also, a design fle containing the logical and timing parameters for the devices is created. Software breadbourding means using a simulator to test the operation of a eirenit. ‘Simulation allows you to change the design and resimulate the circuit in a shorter time. Also, you can pick out marginal timing errors, don’t have to wait for parts, and can generate complex test signals easily, © A simulation model for a device contains a software description of the characteristics of the device, These mokude a picture file with the schematic symbol, the logical characteristics (truth table), and the timing parameters, 4. See the section 4 Mlcrocomputer Siniulatton Example on page S83 of the text Simulation telis you ifthe eireuit connections land the timing of the cireuit are correet. ‘See the section Design for Test beginning on page 384 of the text, DMA, DRAM, CACHE MEMORIES, COPROCESSORS, AND EDA TOOLS 33 peinCHAPTER 12 C, A HIGH-LEVEL LANGUAGE FOR SYSTEM PROGRAMING ‘The index value of the first element is zero, During the second execution of the loop index = 1, so the second element in cost will bbe accessed. c. The #includecstdio.h> directive tells the compiler that the declaration for any predefined functions used are In the file stdio.b. d. The word printf, followed by parentheses, calls the predefined printf fumetion to display the information passed to the function in parentheses on the screen, ye 2 a. The integrated environment saves the time required to switch among the diferent tools ‘and displays error messages on the screen vwith the program you are working on. >, The IDE compiler displays error messages in a window at the bottom of the sereen, Tt highlights one error message at a time and highlights the program line which caused that errer. c. When you put a watch om a variable in the te environment, the value of that variable is sisplayed In the watch window as you step ‘through the program. 3 Range actually depends somewhat on the compiler and machine used, but most common values are: a Char -128-> +127 b, Int -82,768 -> + 32,767 © Unslgned int 0 -> 65,535 i. Long-2,147,489,648 > +2,147,488,647 ¢. Float 3.95 -38-> 3.45 +38 ‘nt total_boards: char no = '': float body_temp = 98.6: int scores{5I: ‘nt scoresi6) int ‘ptr = scores; char screent25]180| char screen_buffer (4251180 ‘unsigned int monitor_start « OxFE00; char *answer: int tptr = érsetpoint: float “wptr = net_weights: Multiply 4 by 7, divide result by @, subtract quotient from 5. >. Add 4 to a, muluply eum by 17, subtract quotient of B/2, ada 6 to result Add y to x, increment y by one, Decrement y, subtract decremented value of y feom x, 5, 89, 84, 98, 92I: eRe Pane nese ® 8 Ro Count = count +4. add 4 to value of count. [AND value af strobe_val with 0003H, Rotate the a value 4 bit positions to the right and assign the result to ¥. Rematnder produced by dividing 99 by 4 is ‘assigned to b, The value of b then is 3. £ The value of ch is compared with the ASCIL codes for ¥ and y. If ch is equal to either code, execution will go the statement at the label start. If ch is not equal to either code, execution will simply go on to the next program statement. Po eae 1 printf-séd",counth: b, printiPlease enter your weight in Kg, and press enter) . printi'%610.4P-cotiversfon_factor): d._printif‘e" average lunar _distaneel: 1% See program A12-07.C on the dist. \> Program ta average 4 numbers and print result */ fimemdeestdio b> int index, sum = 0, av: int numsl] = 15, 65. 88, 72 matn{) i forlindex » 0: index < 4: indext+) sum = sum + nums[index}: av = sum/4; printi‘The average of 45. 65, 88, and 72 is 96d. \n" avs 8. See program A1-08.C on the disk. /* Program to read and average 5 test scores */ nt scorest6}: int *spntr = scores: int, sum = 0; main() ‘ printi'Bnter 6 scores. After each score press space or enter.\n, for 20: 1 <5: i++") fi scant, spntt apts: ) spnitr = scores; /* reset pointer to start of array ¢/ for (a0 <5: 4) 1 PROCRAMMINGING 35sum + sum + “epntr: Spates: ' spur = sum/5: spn = scores: /* reset pointer to start of aray */ Printi'For scores of 95d, S60, Sha, od, and %d the average’ Is %d.\n","spnir. *(epntr+ 1), Stspntr+2), epatrs3}, "tspntrea), “spntrsih 9. See program A12-09.C and alternate A12-098.C fon the diste 10, a. See program Al2-10A.C on the disk. See program A12-10B.C on the disk. / program seetion to read up to 1000 characters and ut in array */ sincludecstdto h> char butfer{1000}; ‘char ch = Ox0 int index = 0; maint) ( printi'Enter up to 10 characters. Enter Z to fexit-\n’y; fortindex=0; index < 10: tndexe} 1 ‘ch=getchar( | tfichne EOF} ‘ printi("Goodbye.\ns exit ) Dbulferlindex! = ch: etchar(}; /* clear carriage retum from butfer*/ rinti‘Buffer fal \n"}: Tor{index = 0; index < 10: index) prinue", bulferiindes)) Hi, See program A12-11.C on the disk. 12, See program A12-12.C on the disk. 13, See program A12-19.C on the disk. 14, Formal arguments are declared tn the funetfon, definition header. They identify the variable that will receive the values passed during the function call. Actual arguments are the values ppassed {0 the function during the function eall 15, See program A12-15.C on the disk. 36 CHAPTER 12 6 ”. 1. B ‘See program A12-16.C on the disk. ‘See program A12-17.C on the disk. ‘See program A12-18.C on the dist. program, global program, global program, global program: this source module only program, this funetion only {his function only, this function only {his function only ehis function enly ‘See program A12-20.C on the disk, ‘The main advantage of using predefined © brary functions ts that these functions have already been uaitten, tested, and debugged. All you have to do is call them and make sure the lubraries containing the functions are available to the linker. The main disadvantage Js that the predefined functions often do not perform the exact task you need done. The solution to this problem is to obtain a copy of the source sting for the desired function and generate a modified version that meets your needs. ‘See program A12-22.C on the disk. Identify the function as extern in the C module. ‘maintain the segment naming structure in the assembly language module, declare the assembly language procedure public in the assembly language module, access parameters on stack, retum value in AX. ehaaoee 4, Tiny, small, mediam, compact, large, and huge. 1b, The distinguishing features are the number of segments and the size of the pointers used for code and data references. . Small model: One 84-Kbyte code segment, one 64-Kbyte data segment shared by data segment, stack segment, and extra segment. d. DOSSEG MODEL SMALL ‘CODE DATA ‘See the discussion on page 432 of the text, ‘See programs A12.26.C and A12-26.ASM on the disk,CHAPTER 132. MICROCOMPUTER SYSTEM PERIPHERALS NOTE: The end-of-chapter questions for this chapter relate mostly to factual information from the text. The experiments manual contains more complex programming problems based on the concepts and. examples in the chapter. 1. @ Seanf and getche are not always suttable because they read codes only in the range (OH-7FH. . See program A13-01B.C on the disk, 2 A noninteriaced raster is produced on a CRT as follows. An electron gun at the rear of a vacuum tube produces a beam of electrons directed toward the front of the tube. The inside surface of the front of the tube is coated with a phosphor substance which gives off light when struck by electrons. The beam is swept back and forth from the top to the bottom of the screen, as shown in Figure 13-4b on page 429 of the text. To produce an Image, the electron beam is fumed on or off as st 8 swept across the sereen. For a more detailed explanation, see pages 439-440 of the text. 3. Refer to Figure 13-5 on page 440 of the text. As the beam sweeps actoss the first scan line of the character row containing the X, Its turned on to produce the dots at the upper corners of the X. On the next sweep of the beam, the beam is tumed on to produce the two dots for that scan line of the X. The process continues until all the sean lines of the X have been swept out. When all of the rows of the characters have been swept through, the beam is retraced to the top of the screen to start over. 4. Refer to Figure 13-6 on page 441 of the text ‘when reading the answers to this problem. @ ‘The purpose of the RAM in this circutt is 10 hold the codes for the characters to be aisplayed. ‘The address inputs of the RAM are changed with each move from one character to the next along a scan line, each horizontal retrace, each Increment to the next row of characters, and each vertical retrace. The RO-R3 address inputs of the character generator ROM are changed when the dot- row counter ehanges. . The shift register on the output of the character generator ROM is used to convert the parallel data from the ROM into serial ¢ Horizontal syne pulses are produced to cause the beam to sweep back to the left of the screen, that is, retrace at the end of a sean line. f. Vertical-syne pulses are produced when the beam reaches the bottom of the screen and needs to be retraced back to the top. 5, NOTE: This problem uses 8 character times for horizontal overscan, but a more reasonable ‘gure ts 20 character times. a. 80 +3 averscan = 83 character times per b, (12 lnes/eharacter x 25 rows) + 120 ‘overscan = 420 sean lines per frame. © 60 frames/second x 40 lines/frame = 25,200 lines per second. 25,200 lines/second % 88 characters/line x 9 dots/character = 18,824,400 dote/second. 95-10 Milz minimum bandwidth, 25,200 lines/second x 63 eharacters/line = 2,091,600 characters/second = 1 character /478 as, me 6 @ (14,000,000 dots/second)/15.750 lines/second = 889 number of dot umes per san line b Active display = 80 characters x 8 dots/character = 640; 889 total dots/line — 40 dots/line active © 249 dot Umes lef for horizontal overscan. © (16,750 lines/second)/(60 frames/seconé) = 262 scan lines per frame + oversean. @. Active scan lines = 25 rows x & lines/ro 200; 262 lines — 200 active = 62 left for vertical oversean., 7H the 6845 CRT controller and the ilcroprocessor want to access the display RAM ‘at the same time, the CRT display system in Figure 13-8 of the text arbitrates the dispute by interleaving the 6845 accesses and CPU accesses. The character clock signal going ta the 6845 and the multiplexers allows the CPU to access the RAM only during one half of the clock signal and the 6845 only during the other half of the clock signal. If the CPU tries to access the display RAM during the controller's half of the character clock cycle, a not ready signal from the CRT controller will cause the processor to fnsert WAIT states until the balf of the character lock signal when it can access the display refresh RAM. 8 See the program A13-8.ASM for the algorithm and progam. MICROCOMPUTER SYSTEM PERPHERALS 37,9. 10, 2. B 4 re 6 ‘The memory required to store the pel data for a bit-mapped display of 840 x 480 is (640 ¥ 480)/8 = 88,400 bytes, or about 40 Kbytes. ‘Three electron beams are used to produce all possible colors on a color CRT screen by using Gifferent intensity ratios for each beam, See Figure 13-10 on page 444 and Figure 13-21 on age 445 of the text. a Bight bits are required to specify one of 256 colors for a pixel b, 1024 x 768 = 786.482 pixels. 786.492 pixels % 4 bits/pixel = 9,245,728 bits = 393,216 bytes, or about 400 Kytes ©. See Figure 13-12 on page 446 of the text. In packed pixel storage, all data for the pixel is {n one nibble of a memory location. In planar pixel storage, data for the pixel comes fram four bytes in four different areas of memory (planes ‘See Figure 18-17 on page 449 of the text, Four data bits for a pixel select one of 16 locations in the palette register. The palette register contains 8 G-bit code for 6 color outpuls. Only 16 of 64 possible colors are in the palette register at one lime, 80 only 16 exlore are produced, @ Eighteen bits are required for one of 256K colors. b. There ts too much memoxy, and the memory access rate is toa high, © See Figure 18-18 on page 450 of the text, Fight-bit pixel data selects ene of 256 color registers. Calor registers contain 18-bit codes for 256 out of 256K possible colors, ad. A 6-bIt D/A converter is used to convert each group of 6 bits to an equivalent analog value ‘which Is used to drive @ color gun, ‘See program A1S-14.ASM on the disk. 4 Initialize the graphies adapter Board for 640 x 480 % 16 colar mode. 'b, Call the windovsize function to determine the number of bytes required to save pixel data {for desired window. Save a copy of the pixe} data for the window area in a memory buffer named window buffer, which was created with malloc. a. Restore the original display for the area covered by the window. @ Release the memory. allocated to window_bulfer by malloe so that it ean be reallocated to some other use, Complex graphics images require so much computation that if the main processor Were ‘used, it would not have time to do anything else. b. Mantpuiation of complex graphics {mages requires many floating-point computations, S02 math coprocessor is Included to handle these computations efficiently. 3a CHAPTER 12 v7, 18, ‘9, 26, a. ‘The major advantages of LCD displays are that they require very Tow power, are lightweight, and are flat. Disadvantages are higher cost and the need for back lighting, ‘See programs A1S-18A.ASM and A13-18B.4SM ‘on the disk. ‘To make an image sensor. several hundred CCD shift registers are built in parallel on the same chip. A photodiode Is doped in under every gate, When all of the gates with photodiodes under them are made positive, potential wells are treated. A camera ts used to focus an image on the surface of the chip, and light shining om the photodiodes causes a charge proportional to the light imtenstty to be put in each well that has a diode, These charges ean be shifted out to produce the dot-by-dot values for the sean lines of a picture. The video information must then be passed through an A/D converter to conwert it to digital information so that it can be stored in memory. a. The read/write head for a disle drive is moved into position over a specified track tsing a stepping motor. See also Figure 13-32 on age 466 of the text , ‘The rigid medium allows tracks to be closer {ogether so that more data can be stored. It also allows the disk (o be rotated faster, Permitting the data ¢o be read off the disk aster, The actual rate at which data Is coming off the disic varies with the position of the head oon the disk and changes in disk speed. A phase-locked loop circuit is required to produce a clocking signal which is ‘synchronized with the data being read, 4d. RLL 2,7 encoding allows more data to be stored in a given track than MFM does, a. The main improvement of an ESDI interface Is a greater data rate and the ability to Interface with larger hard disks, D, See Figure 13-390 on page 472 of the text for 4 separate I/O bus which can be used for disks and other peripherals. @ Use (0 check whether there are any errors in the data read from the block. If an error 1s found, another attempt to read the block ean be made. b, Put a disk in, for example, the A: drive, ‘ype FORMAT A:, and press the Enter key. © i, Use DEBUG to do the low-level format, 4, Use the DOS FDISK command to partition the disk into logical drives such a8 C:, Ds, B, ete. iit, Use the BOS FORMAT command to format each partition,23. RRR mn, B . The file allocation table keeps track of which clusters are allocated to Which file and which chasters are available, b. The first FAT entry for a file contains the number of the cluster which contains the next section of the file; the FAT entry for the second section of the file contains the umber of the cluster which holds the next section of the file; ete ©. Types of information include Filename, extension, file attribute (read, hidden, system, volume), time, date, starting cluster, and size n bytes, : See program A13-24.ASM on the disk. See program A13-25.ASM on the disk. e FILE -clares fp as a special type of pointer called a file pointer, which points to & data structure which duplicates the file control block. . fopen (Blename,"wt") opens the specified file for write operations. If the function call returns a 0 to fp, an error occurred during the attempt to open the file. In this case, the predefined function perror is called (0 write ‘an error message {o the sereen. c. Marks the fle represented by Ale pointer ip closed and closes the stream associated with tp. . While not end of file reads a character from the fle stream with the {gete(} function and sends the returned character to the screen {sdtout) with the fputel) function. a ARAM disk program configures a section of RAM as a virtual disk drive so that data can be read from it and written to it using the ‘same procedures used for magnetic disks. A RAM disk fs much faster than 2 magnetic disk drive because It does not have the ‘mechanical access time. b. A disk cache functions similarly to the way ‘an SRAM cache does for a DRAM system. When a program requests, for example, the Gast few blocks of a file, the cache program reads a large part of the file into the cache. ‘Then, when the program needs the next part of the file, & will already be present in the ‘eache and a new read from the hard disk will rot be needed, A RAM disk Is referred to as D:, ete. A disk cache is transparent to the @. With an optical disk, data is read by bouncing a tiny laser beam off the track as the disk rotates. One advantage of this method is that there Is no chance of the head “crashing” on the disk and destroying tt b, Advantages of optical disk storage include a greater amount of storage capacity per system, removability, and imperviousness 10 magnetic felds and humidity, B. 2 3. ce. Data bits are recorded in magneto-optic read/write optical disk systems using a disk coated with an exotic metal alloy which has the required magnetic properties. The read/vnite head has a laser diode and a coil of wire. A current is passed through the coll to produce a magnetic field perpendicular to the disk. To record a ] at a spot in a data track, @ pulse of light from the laser diode is used to heat up that spot. Heating the spot makes it possible for the applied magnetic field to flip Ute magnetic domains around at that spot and create a tiny vertical magnet. When heated with no fleld present. the magnetism of the spot will lip around in line swith the horizontal field on the disk A fbuman brain oan store about 102° bits of data and has an access time of about 1 second. Optical disksystems such as the Maxtor Tahiti store 10° bits with an access time of about 30 ms and transfer data at a maximum rate of about 10 Mbite/second. For a description of the print mechanisms and their advantages/disedvantages, see pages 479- 481 of the text. Figure 13-45 on page 481 of the text shows a block diagram of waveform-modification type of speech synthesizer. LPC synthesizers use a ‘igi filter to modify the signals from & pulse ‘and a white-noise source. Formant synthesizers ‘use several resonant filters to massage the signals from a varlable-frequency signal source and a white-noise source. In phoneme synthesizers, a 6-bit code controls the characteristics of some formant ders. The major difference between an LPC and a formant synthesizer is the type of filter used to modify the signal. In a direct digitization speech synthesizer, an |A/D converter 1s used to take samples of actual speech signals from a microphone. These samples are stored In memory. To reproduce ‘speech, the samples from memory are applied to the mputs of a D/A converter, The advantage of this method is very accurate reproduction. The disadvantage is the large amount of data that rust be stored to record even a small amount of speech, a. The main storage technique is data compression. For both audio and video information, only the changes from previous values are stored, so Tach less data storage Js required. b, The system uses signals from controls you ‘aperate co choose “out the window" view and instrument displays. The system can be programmed to insert emergency conditions ‘that you must respond to. MICROCOMPUTER SYSTEM PERIPHERALS. 39CHAPTER 14 DATA COMMUNICATION AND NETWORKS 1, The bit format used for asynchronous serial data 1s shown In Figure 14-1 on page 488 of the text. 2 a Ia terminal is transmitting asynchronous serial data at 1200 Bd, the bit time is 0.833 ‘ms (1/1200). b. Assuming 7 data bits, 1 parity bit, 1 start bit, and 1 stop bit, it takes (0.893 x (7+ 1+ 1+ 1) of 8.83 ms to transmit one character. 3. The main difference between a UART and a USART Is that a UART can only do asynebronous communication, while a USART can be programmed todo either asynchronous or synchronous communication. 4 4 modem, which stande for modulator- Semodulator, is a device used to convert digital signals to audio frequency tones {in the frequency range which phone lines can transmit) and to convert transmitted tones back to digital information. A modem is needed to send digital data over standard suitched phone lines becxu: ‘these phone lines have a bandwidth of only about 300-3000 Hz. This is not enough Dendwidth to transmit digital signals directly. 5, After the terminal power is tumed on and the terminal runs any self-checks. it asserts the BTR signal to tell the modem it 1s ready, When #t is powered up and ready to transmit or receive ata, the modem asserts the DTR signal to the terminal. When the terminal has a character to send, it asserts an RIS signal to the modem, The modem then asserts its CD to the terminal to indieate that It has made contact with the computer. When the modem is ready to transmit data, tt asserts the CTS signal back to the terminal, The terminal then sends serial data ‘characters to the modem. When the terminal has sent all the characters it needs to, it makes RTS hnigh, which eauses the modem to unassert its signal and stop transmitting. See also igure 14-2 on page 489 of the text, %. In order for an 82514 to transmit data at 4800 Bd with a baud rate factor of 16, the transmit clock frequency rust he (4800 x 16), or 76,800 Hz. 4. The bit patterns for the mode and command ‘words for the 82514 are shown in Figure 14-1 b. The sequence of instructions required to initialize an 8251A at addresses 80H and SIH are shown in Figure 14-5 on page 492 of the text. 6. See Figure 14-5b on page 499 of the text for ‘the sequence of instructions that can be used to poll this 8251A to determine when the recelver butfer has a character to be read. 4. You can determine whether a character received by an S251A contains @ parity error bby checking the DS bit in the status word. A Lin this bit indicates a parity error. e. The frequency transmit and receive clock required to send data at 2400 Bd using this 251A with a baud rate factor of 64 is 153.500 He. Jf Characters can be sent to and read from the 8251A on an interrupt basis. To send characters on an interrupt basis, the TxRDY pin of the 8251A is connected to an interrupt input on the processor or an IR input on an £82594 priority interrupt controller. S-292C loge high-voltage range = ~3 to ~15 V ‘under load RS.232C loge low-voltage range = 3 to 15 V under load a. When you attempt to connect together two R5-232C devices that are both configured as DTE, the TxD pin on one device will drive data into the TxD pin on the other device. Likewise, the RxD pins and the handshake signal pins will be mismatched, b. The problem can be solved by making an adapter called a null modem as shown in Figure 14-10 on page 496 of the text. FIGURE 141. Bit foxmat forthe made ani command wort for question 14-72 DATA COMMUNICATIONS AND NETWORKS. 4110, a, The two ground pins on an RS-232C connector are connected together only at the power supply in the terminal or the computer {o prevent large accinduced ground currents oon the signal ground. b, Ifthe wire connected to pin 5 of an RS-292C terminal is broken, the clear-to-send signal ‘will not be received. Most terminals wall send no data unless they receive the CTS signal. 11, The higher transmission rate of the RS-422A is possible because the differential lines are terminated by resistors, so they act as proper transmission lines instead of simply as open ‘wires, The RS-423 also uses a transmission line, sa it foo can transmit at higher rates. 12, @ An PSK modem uses one tone to represent a © and another tone to represent a 1 in the signal it sends out on a phone line. , Pull-duplex communication over standard phone lines can be achieved by using one pair of tones for communication in one ‘direction and a different pair of tones for ‘communication in the other direction. ¢. The maximum PSK data rate is about 1200 Baud. IX @. Figure 14-2 shows the waveform of a signal that a simple PSK modem will send out 10 represent the binary data 011010100, FAVAVATANAVATAUAUATAVAWAN Le FIGURE 14.2. Waveform ofa signal that a simple PSK medem will send out forthe binary data (011010100. (Answer to question 14-132.) 1b, Use four different phase shifts to represent the four possible combinations of two data bits as shown in Figure 14-18a on page 499 of the text, ¢ Eight different phase angles and two amplitude values are used to represent 16 possible combinations of a group of 4 data bits. See Rigure 14-16 on text page 500, 14 a. Digital signals have much better nolse rejection than analog signals and can more cestly be regenerated as needed along the b. Cade stands for coder-decoder. ‘The coder Is an A/D converter that converts the analog signal into digital form. The decoder is a D/A converter thal converts the digital signal back to analog, Codecs are designed with a nonlinear response (small stepe for small signals, large ‘steps for large signals) to reduce the dynamic 42 CHAPTIR 14 1s, 16. n Be 1. range of the signals and provide greater accuracy for small signals with a minimem number of converter bis, 4 Telephone companies use ime division multiplexing or frequency division ‘multiplexing to transmit many signals on the ‘same wite, ber, or radio channel. @ The ISDN converts analog voice signals to digital form at the user's site instead of in the local branch office. A basic service supplies two 64 Kbit/s data channels and a 16 bits/second control channel. b. The significance of the ISDN for computer communication Is that the ISDN allows computers to communicate directly in digital form instead of using modems with audio tones. This provides higher speed and better error rates. ‘See Figure 14-226 on page 506 of the text. LEDs and ILDs (infrared injection laser diodes) are two types of devices used to produce the light beam for a fiber optic eable. Darlington photodetectors (Le., the MFOD73} or avalanche photodiodes (APDs) are used 10 detect the light at the receiving end of the Aber. ¢. You should never look into the end af a Sher optic cable Decause the light beam may be strong enough to permanently damage your Pe ye. @. Aber with a diameter large enough to allow ‘beam with several different entry angles to propagete through it te a multimode fiber. Single-mode fibers only allow beams very nearly parallel to the axis of the Biber to be trenamnitted through them, The multimode fibers are easy 10 male but have problems at high data rates. The single-mode fbers can franemit at very high rates, but itis difficult to make low lose connections with che ny fibers. See page 506 of the text. ©. The major advantages of fiber optic cables over metallle conductors are that they are smaller, are Immune to electrical noise, send longer distances without repeaters, and can accommodate a large number of fibers. See program AI4-17.ASM on the disk. See program A14-18.ASM for the answer to this problem. This would be inserted in the program of Figure 14-25 after the INT 16H, just below the RDKY! label A clreular budfer js a special (ype of queue that hhas @ tail pointer which is used to keep track of ‘where the next byte is to be written to the buffer and a head pointer to keep track of where the pext character to be read from the buffer is located. The buffer 1s circular because when the tall polmier reaches the highest location in the memory space set aside for it, it is wrapped around te the beginning of the buffer again. The2. a. ‘uifer-empty condition is indicated when the ead pointer is equal to the tai) potnter. The Duifer-full condition is indicated when the (tail pointer + 1) is equal to the head pointer. See Figure 14-20 on page 517 of the text. Tt is necessary to disable the UART interrupt, Input of the 8259A during part of the CHK_W_DISPLAY procedure so that an interrupt from the UART cannot eall the SERIAL_IN procedure while CHK_N_DISPLAY is using the ‘head and tail pointers of the circular buffer. a. When changing a bit in a control word or interrupt mask, you should not change the ‘other bite because it would change {mask or unmask) other interrupts. b, The assembly language instructions to unmask IRS of an 8259A at base address 80H without changing the interrupt status of any other bits are as follows: IN ALSLH sRead 8259A mask register AND AL, 110121118 ;Unmasie 183 ‘OUT SIAL ‘Send new mask register to 82594, No start or stop bits are needed for individual data cheracters in synchronous serial data communication because the receiver ‘automatically knows that every 8 bits received after synchronization represents a dats character. This Is more efficient than asynchronous serial transmission, which requires total of 10 bits to be sent for each 8 ‘ott data character, hence wasting 20 percent of the transmission tine. 1. a. If an S251 is being used in synchronous mode fer a BISYNC data link, the additional {initialization words to send ta the device are the desired syne character(s)—depending on whether the mode specified one or two syne characters—to the eontrol address. 1b, The S251A detects the start of a message by detecting a syne character, SOH, STX, ENQ. ETX, and BOC bytes. c The 6251 asserts Its SYNDET output pin and sets bit 6, the SYNDET bat, im tts status register 4, The receiving station in a BISYNC link indicates that it found an error in the received data by sending out an NAK message. See Figure 14-80 on page 518 of the text, The start of a message frame is indicated in a bit-ortented protocol such as HDLC by detecting a specific pattern, 01111110, ealled + flag. See Figure 14-82 on text page 521 2 A special circuit stufls zeros in any data bytes that contain more than 5 1's in a sequence, The extra zeros are removed when the data Is received, ‘The receiver in an HDLC system tells the 25, n tansmitter that an error was found in a wansmitted frame by sending an $ frame containins the number of the last information irame that was correctly received, a. See Figure 14-88 on page 622 of the text for a agram of the networlc topologies. b, The commercial systems that use the topologies are as follows: Star: PABX phone system Loop: GPIB Ring: Apollo/HP Domain ‘Tree: Wangnet Common-bus: Bthernet Bascband transmission transmits one digital data signal directly. Broadband transmission allows voice, data, and video signals to be twansmitted at the same time throughout the network by modulating a carrier frequency signal, See Figure 14-33 on page 522 of the text. a. See Figure 14-34 an text page 523. The seven layers of the 180 open systems model are ‘application, presentation, session, transport, network, data link, and physical. b, The data-link layer of the protocol ts responsible for assembling messages into Jrames or packets. @ The transport layer of the protocol ts responsible for ensuring that a message 1s transmitted and received correct. a. Ethernet is Implemented in a common-bus topology with a single 50-obm coaxial cable using baseband transmission at 10 Mbits/second. b, The method used by @ unit on Ethernet to ‘gain access to the network for transraltting a message Is called CSMA/CD (carrier sense-imultiple access-eollision detection), ‘The unit looks at the coax to see if'a carrier Is present, If there Js no carrier on the line, the unit starts transmitting. If a carrier 1s present, the unit waits for a time and trles again, 6. If a transmitting station finds that another slaiion starts transmitting after it starts, it ‘will stop transmitting and try again after a random period of time. . The condition that occurs when two units transmit at the same time is called a collision. a, The method used by a unit on a token passing ring to take control of the network for ‘transmitting a message frame Is as follows: It ‘withdraws the not busy token and changes it ta 2 busy token, which ft sends on around the ring. The transmitting unit then sends a frame of data around the ring to the intended DATA COMMUNICATIONS AND NETWORES 433h ‘The advantage of this scheme over the method used in Ethernet 1s that because signals travel in only one direction around the ring, It 1s ideally suited for fiber optic transmission, Ifa token is lost while being passed around the ring (ie., a token in the data stream is not detected in a specific period of time), the token ring network assumes the token was lost and recovers by clearing any leflover data from the ring and sending out a new not- busy signal. See Figure 14-39a on text page 528. The interceptor determines that the Mle Is in the ‘workstation, so the request is passed on to DOS to read the file into memory. >. Figure 14-39b, The interceptor part of the ‘user ayster determines that the requested fle 1s in the file server. The request is Formatted and sent by netbios to the fle server over the network. If the requesting user has access rights to the file, the file server will convert the file to packets and send the packels back to the user over the network. ‘The GPIB was designed to interface smart test istruments with a computer. See page 529) “The three types of devices which the GPIB defines are listeners, talkers, and contsollers. ‘See page 580. se CHAPTER 14 @ The three signal groups of the GPIB are data bus, date byte transfer control, and general interface management, The data bus transfers data, addresses, commands, and status bytes among Instruments. The data byte transfer control group consists of three handshake lines that coordinate the transfer of data bytes on the data bus. The general Interface management lines are used to reset all units, request use of the bus, etc. See Figure 14-20 on page 530 of the text, a. The sequence of handshake signals that take place when a talker on a GPIB transfers data {o several listeners is as follows. When all listeners have released the NRED line, the talker asserts the DAV line Iow to Indicate that a valid data byte 1s on the bus. All de addressed listeners then pull NRFD low and sslart accepting the data. When the slowest Listener has accepted the data, the NDAC line ‘wil be released high. The talker senses NDAC ‘becoming high and wnasserts its DAV signal All the listeners pull NDAC low again, and the sequence is repeated until the talker has sent all of the data bytes it has to send, This handshake scheme allows talkers and Usteners with very different data rates to operate correctly because the rate of data wransfer {s determined by the rate at which the sloszest listener ean accept the data. See Figure 14-40 on text page 590.CHAPTER 15 THE 80286, 80386, AND 80486 MICROPROCESSORS 1. a. When a TSR program is loaded into memory and run, it remains resident in memory when it terminates. In other words, the memory allocated to the program when it was loaded is not dealtocated when the program Is ‘terminated. This means the program can be rran again by simply pressing some “hot key" sequence which vectors to the program through the keyboard interrupt handier. Figure 15-1b on page 535 of the text shows a memory map of haw @ TSR is loaded into the DOS system, b, Figure 15-24 on text page 536 shows how a passive TSR gets executed. Basically a passive TSR Intercepts the keyboard Interrupt, calls the Keyboard read procedure, and interrupts the key code passed back from the keyboard procedure. If the keycode is a “standard” code, execution is simply d back to the program in keypress. If the cade 16 a “spect TSR carries out the action specified by that code and then returns execution to the smterrapted program. 2, ‘The two types of scheduling commonly used in multiuser/mulutasking operating systems are Ume-slice and preemptive priority-based scheduling. In time-slice scheduling, the CPU executes one task for perhaps 20 me, then cowfiches to the next task. Alter all the tasks have hhad their tum, execution retums to the first. In the preemptive priority-based scheduling method, en executing task can be interrupted by fa higher priority task, 3. If two users in a time-share computer system, ‘each want to print out a file, a ilag in memory is used to indicate if the printer is in use. If the printer 1s 1p use, the printing task becomes locked and the users will have to line up to use the printer, i.e. Join the queue of tasks. 4. Deadlock occurs when two tasks each control a resource that the other task needs to complete some action. For example, one task controls the printer and another tase controls the disk drive, and each needs both resources to print a file, (One way to prevent deadlock is to link resources together under one semaphore so that the two resources are accessed with a single action, Another way to prevent deadlock is to set up a hierarchy among tasks so that if deadlock ‘occurs, the higher-priority task can gain access to all ofthe resources i¢ needs, & A critical region is a plece of code for an operation that must be protected from access by other tasks until the operation is completed. A technique called mutual exclusion is used to prevent two tasks from accessing a critical region at the same time. Figure 15-3 on page 588 of the text shows assembly language instructions which use a semaphore to protect a critical region. 6, An oveslay scheme is used to run programs, such as compilers, which are too large to be Tonded into physical memory all at once. The compiler is written in modules, and its executive module is initially loaded into memory, An additional memory space, the overlay area, is then loaded with the module that the compiler requires at a particular time, When the compiler needs another module, that module is loaded into the overlay area, 7. a. An output port is used to enable one of several banks of physical memory at a ume (eee Figure 15-5 on text page 540). Each block maps into the same system address space when enabled. Thus, many blocks can ‘be mapped into the systemn address space. fone block at a time. b. LIM 4.0 allows 16-Kbyte blocks of memory to be bank switched into address spaces with the basic 1-Mbyte addressing range of # 8086 and 8088. The primary address windows used are the four pages between system address C800H and DS00H. This effectively Increases the amount of memory available for large programs, because megabytes of memory can be switched, in four pages at a time, as needed. ¢ Expanded memory involves switching blocks of memory into windows within the basic 1- Mbyte addressing range of the 8086 as desertbed in part b. Extended memory means directly addressing memory in the address space abave the basic I-Mbyte space. An 80286 operating in protecied made activates 24 address lines, so tt can directly address up to 16 Mbytes of memory, An 80356 fopereting in protected mode activates 32 address lines, 90 i ean directly address up (© 4 Ghytes of memory. a: Virtual memory that ean be logleally referred to in programs, but is not all present in physical memory at one time. Segments or pages of virtual memory are loaded from disk 80286, 80306, 0446 450. Ba Into the actual physical memory as needed co execute @ program. Figure 16-6 in the text shows how a logical address is converted to a physical address by a memory management Unit using a descriptor table, The selector in. the logical address is used to access a descriptor in a table of descriptors in memory. The desertptor contains the physical base address, the privilege level, and some control bits for the segment. This base address 1s then added to the segment offset to produce the physical address. b, Ifthe MMU finds that a requested segment or page is not present in physical memory, it sends an interrupt to the CPU, which will ‘then read the desired cade or data segment from a disk or other secondary storage and load it into the physieal memory. The MMU then computes and outputs the physical address, ‘Two other major advantages provided by indirect addressing are privilege levels and rogram protection. |. The four main processing units tn the 80286 are the bus unit, the instruction unit, the execution nit, and the address unit. The bus unit performs all memory reads and writes. The Instruction unit fully decodes up to three prefetched instructions and holds them in a ‘queue. The execution unit sequentially executes instructions it receives from tie instruction unit. ‘The address unit computes physical addresses in the real address mode; in the PVAM mode, It acts as ant MMU, See Figure 15-8 on text page 542, When an 80286 Is operated in tts real address ‘mode, physical memory addresses are produced directly by adding an offset to a segment base, Just as the 8086 does. In Uus mode, che S086 ‘acts like a “souped-up" S086. In protected mode, the 80286 uses the selector part of the logical address to access a deseriptor for a segment in a descriptor table. The descriptor contains the physical base address for the segment and the privilege level for the requested segment. If the taser program has a high enough privilege level and the segment Is present in physical memory, the address unit in the 80286 will add the segment base from the descriptor to the offset from the original instruction to produce the physical address. ‘An interrupt is caused by some external condition applted to INTR or NMI input. An Jon is caused by an error condition during execution of an instruction. A fault is detected and signaled before an instruction executes (e.g segment not present exception). A trap Is detected and signaled after an instruction executes (e.g. divide hy zero exception) An 80286 may be swliched from real address mode 10 PVAM operation by setting the cHapTeR 15 a 15. protection enable bit of the machine status word ‘The MSW is transferred from a register or memory location to the 80286 with the LMSW mstruction. The only way the 80286 may be switched back to real address mode operation 1s ‘by resetting the system. a. Fourteen bits in the selector part of the Jogieal address specify one of 16.384 possible segment deseriplors. The offset part of the logical address contains 16 bite, s0 each segment ean be up to 65,596 bytes in length. 16,384 segments x 65,536 byles/segment = 1 Gbyte virtual memory ». Ineal mode only 16 address lines are active. so only } Mbyte of memory can be accessed. In PVAM 24 address lines are active, 80 Up 16 Mbytes of physical memory can be addressed. Of course, the actual memory addressable is limited by the amount of physical memory present im a given system, @. Three major advantages of the 80386 over the 80286 are: (1} it executes instructions Faster due to a faster clock and more extensive pipelining; (2) for the DX version, tt can address about 4 Gbytes of physical memory and about 64 Thytes of virtual ‘memory; and (8) it can access virtual memory on a demand paged basis as well as on 2 segment basis. b, The S86DX has a $2-bit address bus and a S2-bit data bus, so {t ean directly access 4 Gbytes of physical memory and directly sead/write 82-bit data words. The 386K Is a lower-cost version which has the same instruction set and basie internal architecture as the DX, but has a 16-bit data bus and a 24-bit address bus. The reduced uses mean ft can directly access only 16 Mbytes of physical memory and can read/write at most 18- rather than 92-bit words. © The BEO-BES signals are the bank enable sigaals. The memory for a S86DX system is set up as 4 byte-wide banks, and these signals are used to enable individual banks so the processor can read bytes, words, or double words 4. The main difference is that the ISA has 24 address lines and 16 data lines, whereas the BISA has 32 data lines and $2 address lines. b, MCA boards are smaller and use different edge connectors than those on an EISA board. See Figure 15-18a on text page 550 and Figure 15-19 on text page 852. . With the BISA, a master asserts an individual MEQ line if ¢ needs (o use the buses. IF ts ‘the highest master requesting service, the ‘bus controller will respond with a MACK ‘signal to tell that master it can use the buses,16, wm With the MCA, any master can assert a common PREEMP line low (0 request use of the buses. The central control circuitry asserts the ARB/GNT line, and then each master attempts ta put its preassigned arbitration code on the common ARBO-ARB4 lines. The master with the lowest arbitfation code will be granted control ofthe buses. Fourteen bits in the selector part of a virtual address spectly one of 16,884 segments. The ‘offset part of the virtual address is 22 bits, so each segment can be as large as 4 Gbytes. 16,984 segments x 4 Gbytes/segment = about 64 Toytes of virtual memory, In real mode only the lower 20 adress lines ‘are active, so a S86DX or S86SX can access only 1 Mbyte of physical memory. In protected mode all 22 address lines of a SB6DX are active, so about 4 Gbytes of physical memory can be accessed. A 3865X in protected mode activates all 24 address lines, $0 up {0 16 Mbytes of physical memory can be accessed, ‘The two parts of an 80386 virtual address are the selector and the offset. ‘The 8O38E axtomatically multiplies the Indes. value in the upper 13 bits of the selector by 8 and adds the results to a descriptor table ‘base address. Ifthe TI bit in the selector is a 0, the result will be added to the global descriptor table base contained in the global descriptor table register. If the TL bit in the selector is a 1, the result will be added to the Jocal descriptor table base address contained in the local descriptor table register. The 80386 then fetches the indexed segment descriptor from the specified descriptor table and loads it into the hidden part of the Segment register. The 82-bit segment base address, Joscied In as part of te descriptor, Is added directly to the 92-bit offset part of the virtual address to produce the physical address of the desired byte or word. If the memory location is in the global memory area, the 80386 will use the same ‘overall method of accessing It, except that the index value multiplied by 8 will be added to the global descriptor table base address in the GDT register instead of to the base address in the LDT register. ‘The 386 holds the base address for the global descriptor table im the global deseriptor table register. The base address for the currently ‘used local descriptor table is held in the local descriptor table register. ‘The length of a segment ts contained in the segment desertpior, so the 386 can generate an exception if a program instruction attempts to access a location outside the segment. 8. B User tasks are protected from one another in an [5OSBE system by the fact that a task cannot irectly access descriptors in the local deseriptor table that belongs to another task. Im an 80386 protected-mode operating system, kernel procedures are put at the highest privilege evel. Application programs operate at a lower privilege level. A task operating at a lower privilege level cannot directly access a procedure ata higher privilege level. Access (0 a higher privilege level ean be done only through some Controlled mechanism such as a call gate. ‘The mechanism used to allow a task at a level 2 privilege to call a procedure at a higher privilege level is referred to as a gate. A gate is simply a special type of descriptor. When a call fs made to 2 procedure at enother privilege level, the selector is loaded into the CS register and a call {gate descriptor Is loaded tnto the hidden part of the CS register. ifthe cal is legal, the selector for the procedure (contained in the call gate