1. Explain about Code generation and Instruction Selection?

In code Generation the following steps must be followed

• output code must be correct

• output code must be of high quality
•
• code generator should run efficiently

As we see that the final phase in any compiler is the code generator. It takes as input an
intermediate representation of the source program and produces as output an equivalent target
program, as shown in the figure. Optimization phase is optional as far as compiler's correct
working is considered. In order to have a good compiler following conditions should hold:

1. Output code must be correct: The meaning of the source and the target program must remain
the same i.e., given an input, we should get same output both from the target and from the source
program. We have no definite way to ensure this condition. What all we can do is to maintain a
test suite and check.

2. Output code must be of high quality: The target code should make effective use of the
resources of the target machine.

3. Code generator must run efficiently: It is also of no use if code generator itself takes hours or
minutes to convert a small piece of code.

2. What are the Issues in the design of code generator?

. Input: Intermediate representation with symbol table assume that input has been validated by
the front end

. Target programs :

- Absolute machine language fast for small programs

- Reloadable machine code requires linker and loader

- Assembly code requires assembler, linker, and loader

Let us examine the generic issues in the design of code generators.

• Input to the code generator: The input to the code generator consists of the intermediate
representation of the source program produced by the front end, together with the
information in the symbol table that is used to determine the runtime addresses of the
data objects denoted by the names in the intermediate representation. We assume that
prior to code generation the input has been validated by the front end i.e., type checking,
syntax, semantics etc. have been taken care of. The code generation phase can therefore
proceed on the assumption that the input is free of errors.
• Target programs: The output of the code generator is the target program. This output may
take a variety of forms; absolute machine language, relocatable machine language, or
assembly language.
• Producing an absolute machine language as output has the advantage that it can be placed
in a fixed location in memory and immediately executed. A small program can be thus
compiled and executed quickly.
• Producing a relocatable machine code as output allows subprograms to be compiled
separately. Although we must pay the added expense of linking and loading if we
produce relocatable object modules, we gain a great deal of flexibility in being able to
compile subroutines separately and to call other previously compiled programs from an
object module.
• Producing an assembly code as output makes the process of code generation easier as we
can generate symbolic instructions. The price paid is the assembling, linking and loading
steps after code generation.

3. Write a note on Instruction Selection?

The nature of the instruction set of the target machine determines the difficulty of instruction
selection. The uniformity and completeness of the instruction set are important factors. So, the
instruction selection depends upon:

• Instructions used i.e. which instructions should be used in case there are multiple
instructions that do the same job.
• Uniformity i.e. support for different object/data types, what op-codes are applicable on
what data types etc.
• Completeness: Not all source programs can be converted/translated in to machine code
for all architectures/machines. E.g., 80x86 doesn't support multiplication.
• Instruction Speed: This is needed for better performance.
• Register Allocation:
• Instructions involving registers are usually faster than those involving operands memory.
• .Store long life time values that are often used in registers.
 • Evaluation Order: The order in which the instructions will be executed. This increases
performance of the code.

4. Give an example for Instruction Selection?

Straight forward code if efficiency is not an issue

Eg:

a=b+c Mov b, R 0
d=a+e Add c, R 0
Mov R0 , a
Mov a, R0 can be eliminated
Add e, R0
Mov R 0 , d

a=a+1 Mov a, R0 Inc a

Add #1, R 0
Mov R 0, a

Here, "Inc a" takes lesser time as compared to the other set of instructions as others take almost 3
cycles for each instruction but "Inc a" takes only one cycle. Therefore, we should use "Inc a"
instruction in place of the other set of instructions.

Target Machine

. Byte addressable with 4 bytes per word

. It has n registers R0 , R1 , ..., R n-l

. Two address instructions of the form opcode source, destination

. Usual opcodes like move, add, sub etc.

. Addressing modes

MODE FORM ADDRESS

Absolute M M
register R R
index c(R) c+cont(R)
indirect register *R cont(R)
indirect index *c(R) cont(c+cont(R))
 literal #c c

Familiarity with the target machine and its instruction set is a prerequisite for designing a good
code generator. Our target computer is a byte addressable machine with four bytes to a word and
n general purpose registers, R 0 , R1 ,..Rn-1 . It has two address instructions of the form

op source, destination

In which op is an op-code, and source and destination are data fields. It has the following op-
codes among others:

MOV (move source to destination)

ADD (add source to destination)

SUB (subtract source from destination)

The source and destination fields are not long enough to hold memory addresses, so certain bit
patterns in these fields specify that words following an instruction contain operands and/or
addresses. The address modes together with their assembly-language forms are shown above.

5. Explain about Flow graphs?

In Flow graph Add control flow information to basic blocks

 nodes are the basic blocks

 there is a directed edge from B1 to B2 if B 2can follow B1 in some execution sequence
o there is a jump from the last statement of B1 to the first statement of B2
o B2 follows B 1 in natural order of execution
 initial node: block with first statement as leader

We can add flow control information to the set of basic blocks making up a program by
constructing a directed graph called a flow graph. The nodes of a flow graph are the basic nodes.
One node is distinguished as initial; it is the block whose leader is the first statement. There is a
directed edge from block B1 to block B2 if B2 can immediately follow B1 in some execution
sequence; that is, if

• There is conditional or unconditional jump from the last statement of B1 to the first
statement of B2 , or
• B2 immediately follows B1 in the order of the program, and B1 does not end in an
unconditional jump. We say that B1 is the predecessor of B 2 , and B 2 is a successorof B 1

Next use information

. for register and temporary allocation

. remove variables from registers if not used

. statement X = Y op Z defines X and uses Y and Z

. scan each basic blocks backwards

. assume all temporaries are dead on exit and all user variables are live on exit

The use of a name in a three-address statement is defined as follows. Suppose three-address

statement i assigns a value to x. If statement j has x as an operand, and control can flow
from statement i to j along a path that has no intervening assignments to x, then we say
statement j uses the value of x computed at i. We wish to determine for each three-address
statement x := y op z what the next uses of x, y and z are. We collect next-use information
about names in basic blocks.

Example

1: t1 = a * a

2: t 2 = a * b

3: t3 = 2 * t2

4: t4 = t 1 + t3

5: t5 = b * b

6: t6 = t 4 + t5

7: X = t 6

For example, consider the basic block shown above.

 We can allocate storage locations for temporaries by examining each in turn and assigning a
temporary to the first location in the field for temporaries that does not contain a live temporary.
If a temporary cannot be assigned to any previously created location, add a new location to the
data area for the current procedure. In many cases, temporaries can be packed into registers
rather than memory locations, as in the next section.

The six temporaries in the basic block can be packed into two locations. These locations
correspond to t 1 and t 2 in:

1: t 1 = a * a

2: t 2 = a * b

3: t2 = 2 * t2

4: t1 = t 1 + t2

5: t2 = b * b

6: t1 = t1 + t 2

7: X = t1