Native Clock Concurrent

(CCOpt) Optimization
Rapid Adoption Kit (RAK)

Click to get the test case

CCOpt L ab Data

Enco unt er Digital Impleme ntation Versi on 13.2

Jan , 2014

1/13/2014 1 For EDI System 13.2

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Contents

Module 1: Introduction and Setup ...................................................................................... 4

1-1 Introduction .................................................................................................................. 4
1-2 Leon Design Information.............................................................................................. 4
1-3 Setting up EDI System and the Lab Directory ............................................................. 5

Module 2: Configuring and Running Native CCOpt .......................................................... 6

2-1 Configuring
2-2 Creating CCOpt Spec
the CCOpt ......................................................................................................
File ...................................................................................... 76
2-3 Running CCOpt ............................................................................................................ 8

Module 3: Analyzing the CCOpt Results ........................................................................... 9

3-1 Analyzing the Log File ................................................................................................. 9
3-2 CCOpt Analysis Commands ......................................................................................... 9
3-3 CCOpt Clock Tree Debugger ..................................................................................... 10

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Modu le 1: Introd uct ion and Se tup

1-1 Introduction

The Clock Concurrent Optimization (CCOpt) Rapid Adoption Kit (RAK) introduces you
to running native CCOpt in EDI System. It shows the basics on how to configure and run
native CCOpt plus tools and commands to analyze and debug the results. It assumes you
are familiar with running EDI System.

1-2 Leon De sign Informatio n

The design in this lab is a Leon processor. The Leon design is a block level design with
35K instances, 4 memories, and 1500 IO pins. The library used is a Cadence Generic
45nm library using 9 routing layers.

There are three main clocks in this design ( test_clk, my_clk and div_clk) as defined by the
following SDCs:

cr eat e_cl ock - name {t est _cl k} - per i od 8. 000 \

- wavef or m { 0. 000 4. 000 } [ l i st [ get _por t s {sca n_cl k}] ]

cr eat e_cl ock - name {my_cl k} - per i od 4. 000 \

- wavef or m { 0. 000 2. 000 } [ l i st [ get _por t s {cl k}] ]
cr eat e_gener at ed_cl ock - name di v_cl k - sour ce \
[ get _por t s {cl k}] - di vi de_by 2 [ get _pi ns {cl k_di v_r eg/ Q}]

A schematic of the clock structure is below:

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1-3 Settin g u p EDI System and t he Lab Directory

1. Download and install the EDI System 13.2 software from

http://downloads.cadence.com.

2. Extract the RAK database and change directory to the work directory:

l i nux% t ar xf z RAK_13. 2_CCOpt . t gz

l i nux% cd RAK_13. 2_c coCCOpt

3. Verify the encount er executable is in your path by typing:

l i nux% whi ch encount er

4. Start EDI System:

l i nux% encount er

5. Load in the starting design by running the following in the EDI System console:

sour ce DATA/ pr ect s. enc

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Modu le 2: Confi gur ing and Runnin g Nativ e CCOpt
2-1 Conf igu ri ng CCO pt

Before running CCOpt, you will need to configure a number of settings that control how
CCOpt will optimize the design. These settings include:

•
• Post-CTS
CCOpt timing
control settings
settings
• NanoRoute settings for clock routing
• CTS settings

The configuration settings for this lab are all contained in the file config.tcl.

1. Source the config.tcl file:

sour ce SCRI PTS/ conf i g. t cl

The following describes the settings configured by config.tcl.

The following is set to configure CCOpt to run in native mode:

set _ccop t _mode –i nt egr at i on nat i ve

Because CCOpt is timing-driven, you need to configure CCOpt to use post-CTS timing.
That is, you need to configure CCOpt to use post-CTS SDC files, timing derates, and
CPPR settings. This post-CTS timing configuration change needs to be done before
running CCOpt.

The relevant commands in config.tcl are as follows:

### Post - CTS t i mi ng set up

updat e_const r ai nt _mode - name f unct i onal _f unc_s l ow_max \
- sdc_f i l es [ l i st DATA/ l eon_f unc_sl ow_max_post ct s. sdc]
set Anal ysi sMode - anal ysi sType onChi pVar i at i on - cppr bot h

There are a number of CCOpt control settings you will need to configure to specify the
buffers, inverters and clock gating cells to use:

### CCOpt cont r ol set t i ngs

set _cc opt _pr oper t y buf f er _ce l l s \
{CLKBUFX8 CLKBUFX12 CLKBUFX16 CLKBUFX20}
set _cc opt _pr oper t y i nver t er _ce l l s \
{CLKI NVX8 CLKI NVX12 CLKI NVX16 CLKI NVX20}
set _cco pt _pr oper t y cl ock_gat i ng_ce l l s {TLAT*}

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By default, CCOpt attempts to automatically find suitable cells, but it is strongly
recommended that you supply lists of suitable cells. This is because in many libraries the
cells you want to use for CTS will be marked as don’t use, and CCOpt will not use these
cells automatically.

Set slew and skew targets by setting the respective properties:

set _ccop t _pr oper t y t ar get _s kew 0. 200

set _ccop t _pr oper t y t ar get _sl ew 0. 200

Tip: Use get _ccop t _pr oper t y to get help on properties:

• get _cco pt _pr oper t y * - hel p to list all properties
• get _cco pt _pr oper t y *st r i ng* - hel p for help on properties matching
*str i ng* . For example, get _pr oper t y *ske w* - hel p .
• get _ccop t _pr oper t y pr oper t y_nam e –hel p for help on a specific
property.

In order to route clock trees correctly, you will need to configure NanoRoute settings. Of
particular interest is the set NanoRout eMode -
dr out eUseMul t i Cut Vi aEf f or t [ hi gh| l ow] command, since CCOpt uses this
to predict whether NanoRoute will use double vias (high) or single (low).

The relevant commands in config.tcl are as follows:

### NanoRout e set t i ngs f or cl ock r out i ng

set NanoRout eMode - dr out eUseMul t i Cut Vi aEf f or t " hi gh"

The CTS configuration settings in config.tcl specify preferred layer routing controls and
tell EDI System to route clock nets using the CTS-generated route guide file:

### CTS set t i ngs

set CTSMode - r out eTopPr ef er r edLayer 6
set CTSMode - r out eBot t omPr ef er r edLayer 5
set CTSMode - r out eLeaf TopPr ef er r edLayer 5
set CTSMode - r out eLeaf Bot t omPr ef er r edLayer 4
set CTSMode - r out eGui de t r ue

2-2 Creati ng th e CCOpt Spec File

The CCOpt specification file is created using the

cr eat e_cco pt _cl ock_t r ee_sp ec command. This command can generate the
spec file in-memory using the –i mmedi at e option or output to a file using the –file
option.

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1. Run the following to output a CCOpt spec file:

cr eat e_cco pt _cl ock_t r ee_sp ec –f i l e ccopt . spec

CCOpt will analyze the SDC constraints and the design logic to define the clock tree
specifications and respective properties.

2. Open the ccopt.spec file and review its contents. Close the file once you’re done.

2-3 Run ni ng CCOpt

The ccopt _desi gn command performs CCOpt optimization on the currently loaded
design in EDI System. There are two ways to run native CCOpt depending on how the
spec file is generated:

Method 1 – In-memory spec file:

set _ccop t _mode –i nt egr at i on nat i ve

cr eat e_ccop t _cl ock_t r ee_s pec –i mmedi at e
ccopt _desi gn

Method 2 – Output a spec file:

set _ccop t _mode –i nt egr at i on nat i ve

cr eat e_cco pt _cl ock_t r ee_sp ec –f i l e ccopt . spec
sour ce cco pt . spec
ccopt _desi gn

1. Run CCOpt using method 2 since you generated the spec file in the previous section:

sour ce cco pt . spec

ccopt _desi gn

When CCOpt completes review the timing summary to evaluate the overall timing
results.

2. Save the design:

saveDesi gn DBS/ post ct s. enc

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Modul e 3: Analyzing th e CCOpt Resu lt s
This module explains commands and tools you can utilize to analyze and debug the
CCOpt results.

3-1 Analyzin g t he Log File

This section highlights parts of the log file you can review to analyze the CCOpt run.

1. Open the log file with your editor of choice.

With the log file open search for the following sections:

Section Description
I ni t i al Summar y Initial timing before optimization
Skew gr oup i nser t i on del ays Insertion delay for each skew group
Cl ock DAG st at s at end of CTS Count and area of cells used in initial clock
tree
Cl ock DAG capaci t ances at end Wire and Gate capacitance of initial clock
of CTS tree
Gui ded max pat h l engt hs Breakdown of route guide lengths
Devi at i on of r out i ng f r om Shows how actual routing deviates from
gui ded max pat h l engt hs route guides
Top 10 not abl e devi at i ons of Specific nets whose length deviates most
r out ed l engt h f r om gui ded from their route guides
l engt h
Gi gaOpt + CCOpt summar y WNS, TNS and runtime summary of
i nf or mat i on GigaOpt + CCOpt optimization
opt Desi gn Fi nal Summar y Final timing results including WNS, TNS,
and DRV information

3-2 CCOpt Analys is Commands

This section introduces you to some common commands to report the results of CCOpt.

Skew groups specify which sinks should be balanced together (balancing of clock trees
and balancing between clock trees).

1. Run r epor t _ccop t _s kew_gr oups to report the minimum and maximum paths
and skews for all skew groups.

r epor t _ccop t _s kew_gr oups

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 Review these sections output by r epor t _ccop t _s kew_gr oups :

• Skew Group Structure – Info on number of sources and sinks for each skew
group.
• Skew Group Summary – Insertion Delay (ID) and skew information for each
skew group respective to each delay corner.
• Skew Group Min/Max path pins – End points with minimum and maximum
insertion delay for each skew group respective to each delay corner. Followed

by the detailed path information.

Clock trees define the connectivity between cells and sinks.

2. Run r epor t _cco pt _cl ock_t r ees to report the slew, area and buffer count for
each clock tree:

r epor t _cco pt _cl ock_t r ees

Review the information output by report_ccopt_clock_trees.

3. Run r epor t _cco pt _wor st _ch ai n to report the worst chain for the design.

r epor t _cco pt _wor st _ch ai n

Review the information output by r epor t _cco pt _wor st _ch ai n. You can
reference the Reporting on the Worst Chain section of the EDI System User Guide.

3-3 CCOpt Cloc k Tree Debu gg er

The CCOpt Clock Tree Debugger is a graphical tool for analyzing and debugging the
clock tree results. It is available under the Clock menu and becomes available once the
CCOpt clock tree constraints are defined (i.e. after running
cr eat e_cco pt _cl ock_t r ee_sp ec).

1. Select Clock – CCOpt Clock Tree Debugger.

The CCOpt Clock Tree Debugger appears.

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The debugger shows the logic in the clock tree with the clock roots at the top and the leaf
cells at the bottom. Analysis is performed by coloring the clock tree based on selected
criteria such as objects, paths, groups, etc.

Following are the basics to navigate the GUI. These are the same as the EDI System GUI.

• Use Z and Shift+Z to zoom-in and zoom-out, respectively.

• Click and drag RMB to zoom to a specific area
• Press F12 to cycle through the 3 brightness levels
• Use F to fit the design
• Open the World View by clicking the green arrow that is in the lower right
corner. You can click and drag RMB within the World View to zoom to a specific
area.
• Hovering over an instance displays properties for that instance.

The Key Panel provides a key showing what the colors represent. The Key Panel
contents will vary depending on the type of data that is colored.

2. Display the Key Panel by selecting View – Key Panel or by selecting the Key tab in
the upper left corner.

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 Initially, the clock tree is colored based on cell type. Use the Key Panel to determine
what symbol represents each cell type.

The Visibility menu filters which colored objects are visible.

3. Select the checkbox next to Visibility – Cell type – Clock sink to disable the
coloring of all clock sinks.

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 Observe the clock sinks at the bottom of the tree are no longer colored.

4. Select Color by – Transition Time to color the clock tree based on transition time
arrival at each cell.

Observe the Key Panel changes to show a gradient of colors representing the
transition times. You can hover over an instance to see its transition time and confirm
its color corresponds to the color in the Key Panel.

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When you select a net or instance in the debugger the object the EDI System GUI will
automatically select and zoom to that object. This cross probing makes it easy to
determine the location of the object in the floorplan.

5. Select an instance or net in the debugger and observe its selection in the EDI GUI.

Tip: Cross-probing can be enabled/disabled using View – Select – Enable crossprobing.

The Control Panel combines the functionality of the Visibility and Color by menus into
a single form.

6. Select View – Control Panel or click the Control tab in the upper right to open the
Control Panel.

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7. Expand the object Clock tree by selecting the ‘+’ next to it.

The radio buttons specify what the coloring is based on.

8. Select the radio button next to Clock tree. Notice nothing is colored because for
clock trees you specify the desired color for each tree.

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9. Select the swatch next to div_clk and select a color.

Observe div_clk is now colored (You may need to zoom out to see the entire tree). Do
the same for my_clk and test_clk.

Timing windows show the target delays that the CCOpt algorithm is aiming for as a
range.

10. Select the checkbox next to Timing windows in the Control Panel

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 Observe the timing windows are shown for each sink.

11. Unselect the checkbox next to Timing windows in the Control Panel.

12. Select No Color in the Control Panel in preparation for the next steps.

The Clock Path Browser displays the clock path data in a table and provides the option
for bringing up a clock path analyzer either from its context menu or by double-clicking
on a row in the table.

13. In the Browser minimize the Analysis Views except for slow_max:setup:late by
clicking the ‘-‘ sign.

14. Right-click on my_clk/functional_func_slow_max and select a color under Highlight

– Max Path.

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 Observe the path with the longest delay for my_clk is highlighted.

15. Highlight the minimum path in a similar way by right-clicking on

my_clk/functional_func_slow_max and selecting a color under Highlight – Min Path.

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16. Clear the highlighting by right-clicking in the display area and select Dehighlight
All.

The Path Browser allows you to see the detailed path delays for the min and max paths.

17. Double-click on my_clk/functional_func_slow_max in the Browser to drill down to

see the details of the min and max paths.

18. Select on an instance in the path and observe it is highlighted in the display.

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This concludes this lab. Below are additional resources you can utilize to learn more
about native CCOpt in EDI System:

• CCOpt Clock Tree Debugger in the EDI System Menu Reference

• Clock Concurrent Optimization in the EDI System User Guide
• Clock Concurrent Optimization (CCOpt) Commands in the EDI System
Command Reference

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