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DRV8301
SLOS719F – AUGUST 2011 – REVISED JANUARY 2016

DRV8301 Three-Phase Gate Driver With Dual Current Shunt Amplifiers

and Buck Regulator
1 Features 3 Description
•
1 6-V to 60-V Operating Supply Voltage Range The DRV8301 is a gate driver IC for three-phase
motor drive applications. The device provides three
• 1.7-A Source and 2.3-A Sink Gate Drive Current half-bridge drivers, each capable of driving two N-
Capability channel MOSFETs. The DRV8301 supports up to
• Slew Rate Control for EMI Reduction 1.7-A source and 2.3-A peak current capability. The
• Bootstrap Gate Driver With 100% Duty Cycle DRV8301 can operate off of a single power supply
Support with a wide range from 6-V to 60-V. The device uses
a bootstrap gate driver architecture with trickle charge
• 6- or 3-PWM Input Modes circuitry to support 100% duty cycle. The DRV8301
• Dual Integrated Current Shunt Amplifiers With uses automatic handshaking when the high-side or
Adjustable Gain and Offset low-side MOSFET is switching to prevent flow of
• Integrated 1.5-A Buck Converter current. Integrated VDS sensing of the high-side and
low-side MOSFETs is used to protect the external
• 3.3-V and 5-V Interface Support power stage against overcurrent conditions.
• SPI
The DRV8301 includes two current shunt amplifiers
• Protection Features: for accurate current measurement. The amplifiers
– Programmable Dead Time Control (DTC) support bidirectional current sensing and provide an
– Programmable Overcurrent Protection (OCP) adjustable output offset up to 3 V.
– PVDD and GVDD Undervoltage Lockout The DRV8301 also includes an integrated switching
(UVLO) mode buck converter with adjustable output and
– GVDD Overvoltage Lockout (OVLO) switching frequency. The buck converter can provide
up to 1.5 A to support MCU or additional system
– Overtemperature Warning/Shutdown power needs.
(OTW/OTS)
The SPI provides detailed fault reporting and flexible
– Reported Through nFAULT, nOCTW, and SPI parameter settings such as gain options for the
Registers current shunt amplifiers and slew rate control of the
gate drivers.
2 Applications
• 3-Phase BLDC and PMSM Motors Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
• CPAPs and Pumps
DRV8301 HTSSOP (56) 14.00 mm × 8.10 mm
• E-bikes
(1) For all available packages, see the orderable addendum at
• Power Tools the end of the data sheet.
• Robotics and RC Toys
• Industrial Automation
Simplified Schematic
6 to 60 V

PWM DRV8301
SPI Gate Drive
3-Phase
N-Channel
MOSFETs

Diff Amps Brushless

MCU

Pre-Driver M
nFAULT Sense
Buck
nOCTW Converter

Vcc (Buck)

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
DRV8301
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Table of Contents
1 Features .................................................................. 1 7.3 Feature Description................................................. 15
2 Applications ........................................................... 1 7.4 Device Functional Modes ....................................... 20
3 Description ............................................................. 1 7.5 Programming........................................................... 21
7.6 Register Maps ......................................................... 22
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3 8 Application and Implementation ........................ 24
8.1 Application Information............................................ 24
6 Specifications......................................................... 6
8.2 Typical Application .................................................. 25
6.1 Absolute Maximum Ratings ...................................... 6
6.2 ESD Ratings.............................................................. 6 9 Power Supply Recommendations...................... 28
9.1 Bulk Capacitance .................................................... 28
6.3 Recommended Operating Conditions....................... 7
6.4 Thermal Information .................................................. 7 10 Layout................................................................... 29
6.5 Electrical Characteristics........................................... 8 10.1 Layout Guidelines ................................................. 29
6.6 Current Shunt Amplifier Characteristics.................... 9 10.2 Layout Example .................................................... 30
6.7 Buck Converter Characteristics .............................. 10 11 Device and Documentation Support ................. 31
6.8 SPI Timing Requirements (Slave Mode Only) ........ 10 11.1 Documentation Support ....................................... 31
6.9 Gate Timing and Protection Switching 11.2 Community Resources.......................................... 31
Characteristics ......................................................... 11 11.3 Trademarks ........................................................... 31
6.10 Typical Characteristics .......................................... 12 11.4 Electrostatic Discharge Caution ............................ 31
7 Detailed Description ............................................ 13 11.5 Glossary ................................................................ 31
7.1 Overview ................................................................. 13 12 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram ....................................... 14 Information ........................................................... 31

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (October 2015) to Revision F Page

• Changed VEN_BUCK in Buck Converter Characteristics From: MIN = 0.9 V and MAX = 1.55 V To: MIN = 1.11 V and
MAX = 1.36 V. ..................................................................................................................................................................... 10

Changes from Revision D (August 2015) to Revision E Page

• Corrected table note for dead time programming definition ................................................................................................. 11

• Updated description of gate driver power-up sequencing errata ........................................................................................ 24
• Fixed connections for pin 25 in Figure 7 ............................................................................................................................. 25

Changes from Revision C (January 2015) to Revision D Page

• VPVDD absolute max voltage rating reduced from 70 V to 65 V ............................................................................................. 6

• Clarification made on how the OCP status bits report in Overcurrent Protection and Reporting (OCP) ............................ 17
• Update to PVDD1 undervoltage protection in Undervoltage Protection (PVDD_UV and GVDD_UV) describing
specific transient brownout issue. ........................................................................................................................................ 18
• Update to EN_GATE pin functional description in EN_GATE clarifying proper EN_GATE reset pulse lengths. ................ 20
• Added gate driver power-up sequencing errata .................................................................................................................. 24
• Added Community Resources ............................................................................................................................................. 31

Changes from Revision B (August 2013) to Revision C Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section ................................................................................................. 6

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5 Pin Configuration and Functions

DCA Package
56-Pin HTSSOP with PowerPAD™
Top View

RT_CLK 1 56 SS_TR
COMP 2 55 EN_BUCK
VSENSE 3 54 PVDD2
PWRGD 4 53 PVDD2
nOCTW 5 52 BST_BK
nFAULT 6 51 PH
DTC 7 50 PH
nSCS 8 49 VDD_SPI
SDI 9 48 BST_A
SDO 10 47 GH_A
SCLK 11 46 SH_A

GND (57) - PWR_PAD

DC_CAL 12 45 GL_A
GVDD 13 44 SL_A
CP1 14 43 BST_B
CP2 15 42 GH_B
EN_GATE 16 41 SH_B
INH_A 17 40 GL_B
INL_A 18 39 SL_B
INH_B 19 38 BST_C
INL_B 20 37 GH_C
INH_C 21 36 SH_C
INL_C 22 35 GL_C
DVDD 23 34 SL_C
REF 24 33 SN1
SO1 25 32 SP1
SO2 26 31 SN2
AVDD 27 30 SP2
AGND 28 29 PVDD1

Pin Functions
PIN
TYPE (1) DESCRIPTION
NAME NO.
Resistor timing and external clock for buck regulator. Resistor should connect to GND (PowerPAD™)
RT_CLK 1 I
with very short trace to reduce the potential clock jitter due to noise.
COMP 2 O Buck error amplifier output and input to the output switch current comparator.
VSENSE 3 I Buck output voltage sense pin. Inverting node of error amplifier.
An open-drain output with external pullup resistor required. Asserts low if buck output voltage is low
PWRGD 4 O
due to thermal shutdown, dropout, overvoltage, or EN_BUCK shut down
Overcurrent and/or overtemperature warning indicator. This output is open drain with external pullup
nOCTW 5 O
resistor required. Programmable output mode via SPI registers.
nFAULT 6 O Fault report indicator. This output is open drain with external pullup resistor required.
DTC 7 I Dead-time adjustment with external resistor to GND
nSCS 8 I SPI chip select
SDI 9 I SPI input
SDO 10 O SPI output

(1) KEY: I =Input, O = Output, P = Power

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Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NAME NO.
SCLK 11 I SPI clock signal
When DC_CAL is high, device shorts inputs of shunt amplifiers and disconnects loads. DC offset
DC_CAL 12 I
calibration can be done through external microcontroller.
GVDD 13 P Internal gate driver voltage regulator. GVDD cap should connect to GND
CP1 14 P Charge pump pin 1, ceramic capacitor should be used between CP1 and CP2
CP2 15 P Charge pump pin 2, ceramic capacitor should be used between CP1 and CP2
EN_GATE 16 I Enable gate driver and current shunt amplifiers. Control buck through EN_BUCK pin.
INH_A 17 I PWM input signal (high side), half-bridge A
INL_A 18 I PWM input signal (low side), half-bridge A
INH_B 19 I PWM input signal (high side), half-bridge B
INL_B 20 I PWM input signal (low side), half-bridge B
INH_C 21 I PWM input signal (high side), half-bridge C
INL_C 22 I PWM input signal (low side), half-bridge C
Internal 3.3-V supply voltage. DVDD cap should connect to AGND. This is an output, but not specified
DVDD 23 P
to drive external circuitry.
Reference voltage to set output of shunt amplifiers with a bias voltage which equals to half of the
REF 24 I
voltage set on this pin. Connect to ADC reference in microcontroller.
SO1 25 O Output of current amplifier 1
SO2 26 O Output of current amplifier 2
Internal 6-V supply voltage, AVDD cap should always be installed and connected to AGND. This is an
AVDD 27 P
output, but not specified to drive external circuitry.
AGND 28 P Analog ground pin. Connect directly to GND (PowerPAD).
Power supply pin for gate driver, current shunt amplifier, and SPI communication. PVDD1 is
PVDD1 29 P
independent of buck power supply, PVDD2. PVDD1 cap should connect to GND
Input of current amplifier 2 (connecting to positive input of amplifier). Recommend to connect to ground
SP2 30 I
side of the sense resistor for the best common mode rejection.
SN2 31 I Input of current amplifier 2 (connecting to negative input of amplifier).
Input of current amplifier 1 (connecting to positive input of amplifier). Recommend to connect to ground
SP1 32 I
side of the sense resistor for the best common mode rejection.
SN1 33 I Input of current amplifier 1 (connecting to negative input of amplifier).
Low-Side MOSFET source connection, half-bridge C. Low-side VDS measured between this pin and
SL_C 34 I
SH_C.
GL_C 35 O Gate drive output for low-side MOSFET, half-bridge C
High-side MOSFET source connection, half-bridge C. High-side VDS measured between this pin and
SH_C 36 I
PVDD1.
GH_C 37 O Gate drive output for high-side MOSFET, half-bridge C
BST_C 38 P Bootstrap cap pin for half-bridge C
Low-side MOSFET source connection, half-bridge B. Low-side VDS measured between this pin and
SL_B 39 I
SH_B.
GL_B 40 O Gate drive output for low-side MOSFET, half-bridge B
High-side MOSFET source connection, half-bridge B. High-side VDS measured between this pin and
SH_B 41 I
PVDD1.
GH_B 42 O Gate drive output for high-side MOSFET, half-bridge B
BST_B 43 P Bootstrap cap pin for half-bridge B
Low-side MOSFET source connection, half-bridge A. Low-side VDS measured between this pin and
SL_A 44 I
SH_A.
GL_A 45 O Gate drive output for low-side MOSFET, half-bridge A
High-side MOSFET source connection, half-bridge A. High-side VDS measured between this pin and
SH_A 46 I
PVDD1.
GH_A 47 O Gate drive output for high-side MOSFET, half-bridge A

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Pin Functions (continued)

PIN
TYPE (1) DESCRIPTION
NAME NO.
BST_A 48 P Bootstrap cap pin for half-bridge A
SPI supply pin to support 3.3-V or 5-V logic. Connect to the same supply that the MCU uses for SPI
VDD_SPI 49 I
operation.
PH 50, 51 O The source of the internal high side MOSFET of buck converter
BST_BK 52 P Bootstrap cap pin for buck converter
PVDD2 53, 54 P Power supply pin for buck converter, PVDD2 cap should connect to GND.
Enable buck converter. Internal pullup current source. Pull below 1.2 V to disable. Float to enable.
EN_BUCK 55 I
Adjust the input undervoltage lockout with two resistors
Buck soft-start and tracking. An external capacitor connected to this pin sets the output rise time.
SS_TR 56 I Because the voltage on this pin overrides the internal reference, it can be used for tracking and
sequencing. Cap should connect to GND
GND pin. The exposed power pad must be electrically connected to ground plane through soldering to
GND
57 P PCB for proper operation and connected to bottom side of PCB through vias for better thermal
(PowerPAD)
spreading.

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6 Specifications
6.1 Absolute Maximum Ratings
(1)
see
MIN MAX UNIT
Supply voltage Relative to PGND –0.3 65 V
VPVDD
Maximum supply voltage ramp rate Voltage rising up to PVDDMAX 1 V/µS
VPGND Maximum voltage between PGND and GND –0.3 0.3 V
IIN_MAX Maximum current for all digital and analog inputs (INH_A, INL_A, INH_B, INL_B,
–1 1 mA
INH_C, INL_C, SCLK, SCS, SDI, EN_GATE, DC_CAL, DTC)
ISINK_MAX Maximum sinking current for open-drain pins (nFAULT and nOCTW Pins) 7 mA
VOPA_IN Voltage for SPx and SNx pins –0.6 0.6 V
VLOGIC Input voltage range for logic/digital pins (INH_A, INL_A, INH_B, INL_B, INH_C,
–0.3 7 V
INL_C, EN_GATE, SCLK, SDI, SCS, DC_CAL)
VGVDD Maximum voltage for GVDD pin 13.2 V
VAVDD Maximum voltage for AVDD pin 8 V
VDVDD Maximum voltage for DVDD pin 3.6 V
VVDD_SPI Maximum voltage for VDD_SPI pin 7 V
VSDO Maximum voltage for SDO pin VDD_SPI + 0.3 V
VREF Maximum reference voltage for current amplifier 7 V
IREF Maximum current for REF pin 100 µA
TJ Maximum operating junction temperature –40 150 °C
Tstg Storage temperature –55 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, and functional operation of the device at these or any other conditions beyond those indicated under Recommended Operating
Conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Electrostatic Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all pins (1) ±2000
V(ESD) V
discharge Charged device model (CDM), per JEDEC specification JESD22-C101, all pins (2) ±500

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

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6.3 Recommended Operating Conditions

MIN MAX UNIT
VPVDD1 DC supply voltage PVDD1 for normal operation Relative to PGND 6 60 V
VPVDD2 DC supply voltage PVDD2 for buck converter 3.5 60 V
IDIN_EN Input current of digital pins when EN_GATE is high 100 µA
IDIN_DIS Input current of digital pins when EN_GATE is low 1 µA
CO_OPA Maximum output capacitance on outputs of shunt amplifier 20 pF
Dead time control resistor range. Time range is 50 ns (-GND) to 500 ns (150 kΩ) with a linear
RDTC 0 150 kΩ
approximation.
IFAULT nFAULT pin sink current, open-drain V = 0.4 V 2 mA
IOCTW nFAULT pin sink current, open-drain V = 0.4 V 2 mA
VREF External voltage reference voltage for current shunt amplifiers 2 6 V
Qg(TOT) = 25 nC or total 30-mA gate
ƒgate Operating switching frequency of gate driver 200 kHz
drive average current
Igate Total average gate drive current 30 mA
TA Ambient temperature –40 125 °C

6.4 Thermal Information

DRV8301
THERMAL METRIC (1) DCA (HTSSOP) UNIT
56 PINS
RθJA Junction-to-ambient thermal resistance 30.3 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 33.5 °C/W
RθJB Junction-to-board thermal resistance 17.5 °C/W
ψJT Junction-to-top characterization parameter 0.9 °C/W
ψJB Junction-to-board characterization parameter 7.2 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance 0.9 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

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6.5 Electrical Characteristics

PVDD = 6 to 60 V, TC = 25°C, unless specified under test condition
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
INPUT PINS: INH_X, INL_X, nSCS, SDI, SCLK, EN_GATE, DC_CAL
VIH High input threshold 2 V
VIL Low input threshold 0.8 V
RPULL_DOWN – INTERNAL PULLDOWN RESISTOR FOR GATE DRIVER INPUTS
REN_GATE Internal pulldown resistor for EN_GATE 100 kΩ
Internal pulldown resistor for high-side PWMs
RINH_X EN_GATE high 100 kΩ
(INH_A, INH_B, and INH_C)
Internal pulldown resistor for low-side PWMs
RINH_X EN_GATE high 100 kΩ
(INL_A, INL_B, and INL_C)
RnSCS Internal pulldown resistor for nSCS EN_GATE high 100 kΩ
RSDI Internal pulldown resistor for SDI EN_GATE high 100 kΩ
RDC_CAL Internal pulldown resistor for DC_CAL EN_GATE high 100 kΩ
RSCLK Internal pulldown resistor for SCLK EN_GATE high 100 kΩ
OUTPUT PINS: nFAULT AND nOCTW
VOL Low output threshold IO = 2 mA 0.4 V
External 47 kΩ pullup resistor connected
VOH High output threshold 2.4 V
to 3-5.5 V
Leakage Current on Open-Drain Pins When
IOH 1 µA
Logic High nFAULT and nOCTW)
GATE DRIVE OUTPUT: GH_A, GH_B, GH_C, GL_A, GL_B, GL_C
PVDD = 8 to 60 V, Igate = 30 mA,
9.5 11.5
CCP = 22 nF
VGX_NORM Gate driver Vgs voltage V
PVDD = 8 to 60 V, Igate = 30 mA,
9.5 11.5
CCP = 220 nF
PVDD = 6 to 8 V, Igate = 15 mA,
8.8
CCP = 22 nF
VGX_MIN Gate driver Vgs voltage V
PVDD = 6 to 8 V, Igate = 30 mA,
8.3
CCP = 220 nF
Ioso1 Maximum source current setting 1, peak Vgs of FET equals to 2 V. REG 0x02 1.7 A
Iosi1 Maximum sink current setting 1, peak Vgs of FET equals to 8 V. REG 0x02 2.3 A
Ioso2 Source current setting 2, peak Vgs of FET equals to 2 V. REG 0x02 0.7 A
Iosi2 Sink current setting 2, peak Vgs of FET equals to 8 V. REG 0x02 1 A
Ioso3 Source current setting 3, peak Vgs of FET equals to 2 V. REG 0x02 0.25 A
Iosi3 Sink current setting 3, peak Vgs of FET equals to 8 V. REG 0x02 0.5 A
Gate output impedence during standby mode
Rgate_off 1.6 2.4 kΩ
when EN_GATE low (pins GH_x, GL_x)
SUPPLY CURRENTS
IPVDD1_STB PVDD1 supply current, standby EN_GATE is low. PVDD1 = 8 V. 20 50 µA
EN_GATE is high, no load on gate drive
IPVDD1_OP PVDD1 supply current, operating output, switching at 10 kHz, 15 mA
100 nC gate charge
IPVDD1_HIZ PVDD1 Supply current, Hi-Z EN_GATE is high, gate not switching 2 5 10 mA
INTERNAL REGULATOR VOLTAGE
PVDD = 8 to 60 V 6 6.5 7
AVDD AVDD voltage V
PVDD = 6 to 60 V 5.5 6
DVDD DVDD voltage 3 3.3 3.6 V
VOLTAGE PROTECTION
PVDD falling 5.9
VPVDD_UV Undervoltage protection limit, PVDD V
PVDD rising 6
VGVDD_UV Undervoltage protection limit, GVDD GVDD falling 8 V

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Electrical Characteristics (continued)

PVDD = 6 to 60 V, TC = 25°C, unless specified under test condition
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VGVDD_OV Overvoltage protection limit, GVDD 16 V
CURRENT PROTECTION, (VDS SENSING)
PVDD = 8 to 60 V 0.125 2.4
VDS_OC Drain-source voltage protection limit (1)
V
PVDD = 6 to 8 V 0.125 1.491
Toc OC sensing response time 1.5 µs
nOCTW pin reporting pulse stretch length for
TOC_PULSE 64 µs
OC event
TEMPERATURE PROTECTION
Junction temperature for resetting
OTW_CLR 115 °C
overtemperature warning
Junction temperature for overtemperature
OTW_SET/O
warning and resetting over temperature shut 130 °C
TSD_CLR
down
Junction temperature for overtemperature shut
OTSD_SET 150 °C
down

(1) Reduced AVDD voltage range results in limitations on settings for overcurrent protection. See Table 13.

6.6 Current Shunt Amplifier Characteristics

TC = 25°C unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
G1 Gain option 1 TC = –40°C to 125°C 9.5 10 10.5 V/V
G2 Gain option 2 TC = –40°C to 125°C 18 20 21 V/V
G3 Gain Option 3 TC = –40°C to 125°C 38 40 42 V/V
G4 Gain Option 4 TC = –40°C to 125°C 75 80 85 V/V
tsettling Settling time to 1% TC = 0 to 60°C, G = 10, Vstep = 2 V 300 ns
tsettling Settling time to 1% TC = 0 to 60°C, G = 20, Vstep = 2 V 600 ns
tsettling Settling time to 1% TC = 0 to 60°C, G = 40, Vstep = 2 V 1.2 µs
tsettling Settling time to 1% TC = 0 to 60°C, G = 80, Vstep = 2 V 2.4 µs
Vswing Output swing linear range 0.3 5.7 V
Slew rate G = 10 10 V/µs
DC_offset Offset error RTI G = 10 with input shorted 4 mV
Drift_offset Offset drift RTI 10 µV/C
Ibias Input bias current 100 µA
Vin_com Common input mode range –0.15 0.15 V
Vin_dif Differential input range –0.3 0.3 V
0.5 ×
Vo_bias Output bias With zero input current, Vref up to 6 V –0.5% 0.5% V
Vref
Overall CMRR with gain resistor
CMRR_OV CMRR at DC, gain = 10 70 85 dB
mismatch

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6.7 Buck Converter Characteristics

TC = 25°C unless otherwise specified
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VUVLO Internal undervoltage lockout threshold No voltage hysteresis, rising and falling 2.5 V
ISD(PVDD2) Shutdown supply current EN = 0 V, 25°C, 3.5 V ≤ VIN ≤ 60 V 1.3 4 µA
INON_SW(PVDD2) Operating: nonswitching supply current VSENSE = 0.83 V, VIN = 12 V 116 136 µA
VEN_BUCK Enable threshold voltage No voltage hysteresis, rising and falling 1.11 1.25 1.36 V
RDS_ON On-resistance VIN = 3.5 V, BOOT-PH = 3 V 300 mΩ
ILIM Current limit threshold VIN = 12 V, TJ = 25°C 1.8 2.7 A
OTSD_BK Thermal shutdown 182 °C
Fsw Switching frequency RT = 200 kΩ 450 581 720 kHz
VSENSE falling 92%
VSENSE rising 94%
PWRGD VSENSE threshold
VSENSE rising 109%
VSENSE falling 107%
Hysteresis VSENSE falling 2%
VSENSE = VREF, V(PWRGD) = 5.5 V,
Output high leakage 10 nA
25°C
On resistance I(PWRGD) = 3 mA, VSENSE < 0.79 V 50 Ω

6.8 SPI Timing Requirements (Slave Mode Only)

PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
SPI ready after EN_GATE transitions to
tSPI_READY PVDD > 6 V 5 10 ms
HIGH
tCLK Minimum SPI clock period 100 ns
tCLKH Clock high time See Figure 1 40
tCLKL Clock low time See Figure 1 40
tSU_SDI SDI input data setup time 20 ns
tHD_SDI SDI input data hold time 30 ns
SDO output data delay time, CLK high to
tD_SDO CL = 20 pF 20 ns
SDO valid
tHD_SDO SDO output data hold time See Figure 1 40
tSU_SCS SCS setup time See Figure 1 50 ns
tHD_SCS SCS hold time 50 ns
SCS minimum high time before SCS active
tHI_SCS 40 ns
low
SCS access time, SCS low to SDO out of
tACC 10 ns
high impedance
SCS disable time, SCS high to SDO high
tDIS 10 ns
impedance

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6.9 Gate Timing and Protection Switching Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
TIMING, OUTPUT PINS
tpd,If-O Positive input falling to GH_x falling CL = 1 nF, 50% to 50% 45 ns
tpd,Ir-O Positive input rising to GL_x falling CL = 1 nF, 50% to 50% 45 ns
td_min Minimum dead time after hand shaking (1) 50 ns
tdtp Dead time With RDTC set to different values 50 500 ns
tGDr Rise time, gate drive output CL = 1 nF, 10% to 90% 25 ns
tGDF Fall time, gate drive output CL = 1 nF, 90% to 10% 25 ns
Not including handshake
tON_MIN Minimum on pulse communication. Hi-Z to on state, 50 ns
output of gate driver
Propagation delay matching between high
tpd_match 5 ns
side and low side
tdt_match Deadtime matching 5 ns
TIMING, PROTECTION, AND CONTROL
PVDD is up before start-up, all charge
Start-up time, from EN_GATE active high
tpd,R_GATE-OP pump caps and regulator caps as in 5 10 ms
to device ready for normal operation
recommended condition
If EN_GATE goes from high to low and
back to high state within quick reset time, it
will only reset all faults and gate driver
tpd,R_GATE-Quick Maximum low pulse time 10 µs
without powering down charge pump,
current amp, and related internal voltage
regulators.
tpd,E-L Delay, error event to all gates low 200 ns
tpd,E-FAULT Delay, error event to nFAULT low 200 ns

(1) Dead time programming definition: Adjustable delay from GH_X falling edge to GL_X rising edge, and GL_X falling edge to GH_X rising
edge. In 6-PWM input mode, this adjustable value is added to the timing delay between inputs as set by the microcontroller externally.

tHI_SCS
_

tSU_SCS tHD_SCS
SCS

tCLK

SCLK
tCLKH tCLKL

MSB in
SDI (must be valid) LSB

tSU_SDI tHD_SDI

SDO Z MSB out (is valid) LSB Z

tACC tD_SDO tHD_SDO tDIS

Figure 1. SPI Slave Mode Timing Definition

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1 2 3 4 X 15 16
SCS

SCLK

SDI MSB LSB

SDO MSB LSB

Receive
latch Points

Figure 2. SPI Slave Mode Timing Diagram

6.10 Typical Characteristics

10.0 12.0
9.8 11.8
9.6 11.6
9.4 11.4
GVDD (V)

11.2
IPVDD1 (µA)

9.2
9.0 11.0
8.8 10.8
8.6 10.6
8.4 10.4
8.2 10.2
8.0 10.0
-40 0 25 85 125 -40 0 25 85 125
Temperature (ƒC) C001
Temperature (ƒC) C002

Figure 3. IPVDD1 vs Temperature (PVDD1 = 8 V, EN_GATE = Figure 4. GVDD vs Temperature (PVDD1 = 8 V, EN_GATE =
LOW) HIGH)
12.0
11.8
11.6
11.4
GVDD (V)

11.2
11.0
10.8
10.6
10.4
10.2
10.0
-40 0 25 85 125
Temperature (ƒC) C001

Figure 5. GVDD vs Temperature (PVDD1 = 60 V, EN_GATE = HIGH)

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7 Detailed Description

7.1 Overview
The DRV8301 is a 6-V to 60-V gate driver IC for three-phase motor drive applications. This device reduces
external component count by integrating three half-bridge drivers, two current shunt amplifiers, and a switching
buck converter. The DRV8301 provides overcurrent, overtemperature, and undervoltage protection. Fault
conditions are indicated through the nFAULT and nOCTW pins in addition to the SPI registers.
Adjustable dead time control and peak gate drive current allows for finely tuning the switching of the external
MOSFETs. Internal hand-shaking is used to prevent flow of current.
VDS sensing of the external MOSFETs allows for the DRV8301 to detect overcurrent conditions and respond
appropriately. Individual MOSFET overcurrent conditions are reported through the SPI status registers.
The highly configurable buck converter can support a wide range of output options. This allows the DRV8301 to
provide a power supply rail for the controller and lower voltage components.

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7.2 Functional Block Diagram

PVDD2

DRV8301
PVDD2
EN_BUCK

VSENSE
PWRGD
VCC
BST_BK
COMP Buck Converter

PH
SS_TR

RT_CLK
GVDD

DVDD GVDD
DVDD AVDD Trickle Charge
DVDD
CP1
Charge
DVDD AVDD Trickle
AVDD Pump
LDO LDO Charge CP2 PVDD1
AGND Regulator
AVDD
PVDD1

PVDD1

AGND
GVDD Trickle Charge

PVDD1 BST_A
AGND

nOCTW GH_A
HS VDS HS
Sense
SH_A
nFAULT
GVDD
LS VDS
Sense
nSCS GL_A
SPI LS
Communication,
SDI Registers, and SL_A
Fault Handling
PVDD1
SDO GVDD Trickle Charge

PVDD1 BST_B
SCLK

GH_B
HS VDS HS
VDD_SPI Sense
SH_B

GVDD
LS VDS
Sense
EN_GATE GL_B
LS

INH_A SL_B
PVDD1
INL_A GVDD Trickle Charge

PVDD1 BST_C
INH_B Gate Driver
Control and GH_C
HS VDS HS
INL_B Timing Logic Sense
SH_C
INH_C
GVDD
LS VDS
Sense
INL_C GL_C
LS

DTC
SL_C
REF

REF REF
SN1
GND
RISENSE

Offset Current Sense

SO1
½ REF Amplifier 1 SP1

DC_CAL
REF
SN2
RISENSE

Offset Current Sense

SO2
½ REF Amplifier 2 SP2

GND
(PWR_PAD)

GND
PGND

AGND GND PGND

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7.3 Feature Description

7.3.1 Three-Phase Gate Driver
The half-bridge drivers use a bootstrap configuration with a trickle charge pump to support 100% duty cycle
operation. Each half-bridge is configured to drive two N-channel MOSFETs, one for the high-side and one for the
low-side. The half-bridge drivers can be used in combination to drive a 3-phase motor or separately to drive
various other loads.
The peak gate drive current and internal dead times are adjustable to accommodate a variety of external
MOSFETs and applications. The peak gate drive current is set through a register setting and the dead time is
adjusted with an external resistor on the DTC pin. Shorting the DTC pin to ground will provide the minimum dead
time (50ns). There is an internal hand shake between the high side and low side MOSFETs during switching
transitions to prevent current shoot through.
The three-phase gate driver can provide up to 30mA of average gate drive current. This will support switching
frequencies up to 200 kHz when the MOSFET Qg = 25nC.
Each MOSFET gate driver has a VDS sensing circuit for overcurrent protection. The sense circuit measures the
voltage from the drain to the source of the external MOSFETs while the MOSFET is enabled. This voltage is
compared against the programmed trip point to determine if an overcurrent event has occurred. The high-side
sense is between the PVDD1 and SH_X pins. The low-side sense is between the SH_X and SL_X pins.
Ensuring a differential, low impedance connection to the external MOSFETs for these lines will help provide
accurate VDS sensing.
The DRV8301 allows for both 6-PWM and 3-PWM control through a register setting.

Table 1. 6-PWM Mode

INL_X INH_X GL_X GH_X
0 0 L L
0 1 L H
1 0 H L
1 1 L L

Table 2. 3-PWM Mode

INL_X INH_X GL_X GH_X
X 0 H L
X 1 L H

Table 3. Gate Driver External Components

NAME PIN 1 PIN 2 RECOMMENDED
(1)
RnOCTW nOCTW VCC ≥10 kΩ
(1)
RnFAULT nFAULT VCC ≥10 kΩ
RDTC DTC GND (PowerPAD) 0 to 150 kΩ (50 ns to 500 ns)
CGVDD GVDD GND (PowerPAD) 2.2 µF (20%) ceramic, ≥ 16 V
CCP CP1 CP2 0.022 µF (20%) ceramic, rated for PVDD1
CDVDD DVDD AGND 1 µF (20%) ceramic, ≥ 6.3 V
CAVDD AVDD AGND 1 µF (20%) ceramic, ≥ 10 V
CPVDD1 PVDD1 GND (PowerPAD) ≥4.7 µF (20%) ceramic, rated for PVDD1
CBST_X BST_X SH_X 0.1 µF (20%) ceramic, ≥ 16 V

(1) VCC is the logic supply to the MCU

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7.3.2 Current Shunt Amplifiers

The DRV8301 includes two high-performance current shunt amplifiers to accurate low-side, inline current
measurement.
The current shunt amplifiers have four programmable GAIN settings through the SPI registers. These are 10, 20,
40, and 80 V/V.
The current shunt amplifiers provide output offset up to 3V to support bidirectional current sensing. The offset is
set to half the voltage on the reference pin (REF).
To minimize DC offset and drift overtemperature, a calibration method is provided through either the DC_CAL pin
or SPI register. When DC calibration is enabled, the device will short the input of the current shunt amplifier and
disconnect the load. DC calibration can be done at any time, even during MOSFET switching, because the load
is disconnected. For the best results, perform the DC calibration during the switching OFF period, when no load
is present, to reduce the potential noise impact to the amplifier.
The output of the current shunt amplifier can be calculated as:
V
VO = REF - G ´ (SNX - SPX )
2
where
• VREF is the reference voltage (REF pin)
• G is the gain of the amplifier (10, 20, 40, or 80 V/V)
• SNX and SPX are the inputs of channel x. SPX should connect to the ground side of the sense resistor for the
best common mode rejection. (1)
Figure 6 shows the current shunt amplifier simplified block diagram.
400 kW S4

200 kW S3

100 kW S2

DC_CAL 50 kW S1

SN 5 kW
_ AVDD

100 W
DC_CAL SO
5 kW
+
SP
50 kW S1
DC_CAL
100 kW S2

200 kW S3

400 kW S4
Vref /2

REF AVDD
_

50 kW

50 kW

Figure 6. Current Shunt Amplifier Simplified Block Diagram

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7.3.3 Buck Converter

Table 4. Buck Regulator External Components

NAME PIN 1 PIN 2 RECOMMENDED
RRT_CLK RT_CLK GND (PowerPAD) See Buck Converter
CCOMP COMP GND (PowerPAD) See Buck Converter
RCCOMP COMP GND (PowerPAD) See Buck Converter
RVSENSE1 PH (Filtered) VSENSE See Buck Converter
RVSENSE2 VSENSE GND (PowerPAD) See Buck Converter
(1)
RPWRGD PWRGD VCC ≥ 10 kΩ
LPH PH PH (Filtered) See Buck Converter
DPH PH GND (PowerPAD) See Buck Converter
CPH PH (Filtered) GND (PowerPAD) See Buck Converter
CBST_BK BST_BK PH See Buck Converter
CPVDD2 PVDD2 GND (PowerPAD) ≥4.7 µF (20%) ceramic, rated for PVDD2
CSS_TR SS_TR GND (PowerPAD) See Buck Converter

(1) VCC is the logic supply to the MCU

7.3.4 Protection Features

7.3.4.1 Overcurrent Protection and Reporting (OCP)

To protect the power stage from damage due to excessive currents, VDS sensing circuitry is implemented in the
DRV8301. Based on the RDS(on) of the external MOSFETs and the maximum allowed IDS, a voltage threshold can
be determined to trigger the overcurrent protection features when exceeded. The voltage threshold is
programmed through the SPI registers. Overcurrent protection should be used as a protection scheme only; it is
not intended as a precise current regulation scheme. There can be up to a 20% tolerance across channels for
the VDS trip point.
VDS = IDS × RDS(on) (2)
The VDS sense circuit measures the voltage from the drain to the source of the external MOSFET while the
MOSFET is enabled. The high-side sense is between the PVDD1 and SH_X pins. The low-side sense is
between the SH_X and SL_X pins. Ensuring a differential, low impedance connection to the external MOSFETs
for these lines will help provide accurate VDS sensing.
Four different overcurrent modes (OC_MODE) can be set through the SPI registers. The OC status bits operate
in latched mode. When an overcurrent condition occurs the corresponding OC status bit will latch in the
DRV8301 registers until the next SPI read command. After the read command the OC status bit will clear from
the register until another overcurrent condition occurs.
1. Current limit mode
In current limit mode the device uses current limiting instead of device shutdown during an overcurrent event.
In this mode the device reports overcurrent events through the nOCTW pin. The nOCTW pin will be held low
for a maximum 64-µs period (internal timer) or until the next PWM cycle. If another overcurrent event is
triggered from another MOSFET, during a previous overcurrent event, the reporting will continue for another
64-µs period (internal timer will restart) or until both PWM signals cycle. The associated status bit will be
asserted for the MOSFET in which the overcurrent was detected.
There are two current control settings in current limit mode. These are set by one bit in the SPI registers. The
default mode is cycle by cycle (CBC).
– Cycle by cycle mode (CBC): In CBC mode, the MOSFET on which overcurrent has been detected on will
shut off until the next PWM cycle.
– Off-Time Control Mode: In Off-Time mode, the MOSFET in which overcurrent has been detected is
disabled for a 64-µs period (set by internal timer). If overcurrent is detected in another MOSFET, the
timer will be reset for another 64-µs period and both MOSFETs will be disabled for the duration. During
this period, normal operation can be restored for a specific MOSFET with a corresponding PWM cycle.
2. OC latch shut down mode

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When an overcurrent event occurs, both the high-side and low-side MOSFETs will be disabled in the
corresponding half-bridge. The nFAULT pin and nFAULT status bits will be asserted along with the
associated status bit for the MOSFET in which the overcurrent was detected. The OC status bit will latch until
the next SPI read command. The nFAULT pin and nFAULT status bit will latch until a reset is received
through the GATE_RESET bit or a quick EN_GATE reset pulse.
3. Report only mode
No protective action will be taken in this mode when an overcurrent event occurs. The overcurrent event will
be reported through the nOCTW pin (64-µs pulse) and SPI status register. The external MCU should take
action based on its own control algorithm.
4. OC disabled mode
The device will ignore and not report all overcurrent detections.

7.3.4.2 Undervoltage Protection (PVDD_UV and GVDD_UV)

To protect the power output stage during start-up, shutdown, and other possible undervoltage conditions, the
DRV8301 provides undervoltage protection by driving the gate drive outputs (GH_X, GL_X) low whenever PVDD
or GVDD are below their undervoltage thresholds (PVDD_UV/GVDD_UV). This will put the external MOSFETs in
a high impedance state. When the device is in PVDD_UV it will not respond to SPI commands and the SPI
registers will revert to their default settings.
A specific PVDD1 undervoltage transient brownout from 13 µs to 15 µs can cause the DRV8301 to become
unresponsive to external inputs until a full power cycle. The transient condition consists of having PVDD1 greater
than the PVDD_UV level and then PVDD1 dropping below the PVDD_UV level for a specific period of 13 µs to
15 µs. Transients shorter or longer than 13 to 15 µs will not affect the normal operation of the undervoltage
protection. Additional bulk capacitance can be added to PVDD1 to reduce undervoltage transients.

7.3.4.3 Overvoltage Protection (GVDD_OV)

The device will shut down both the gate driver and charge pump if the GVDD voltage exceeds the GVDD_OV
threshold to prevent potential issues related to the GVDD pin or the charge pump (e.g. short of external GVDD
cap or charge pump). The fault is a latched fault and can only be reset through a reset transition on the
EN_GATE pin.

7.3.4.4 Overtemperature Protection

A two-level overtemperature detection circuit is implemented:
• Level 1: Overtemperature warning (OTW)
OTW is reported through the nOCTW pin (overcurrent and/or overtemperature warning) for default settings.
OCTW pin can be set to report OTW or OCW only through the SPI registers. See SPI Register section.
• Level 2: Over Temperature Latched Shut Down of Gate Driver and Charge Pump (OTSD_GATE)
OTSD_GATE is reported through the nFAULT pin. This is a latched shut down, so the gate driver will not
recover automatically, even if the overtemperature condition is not present anymore. An EN_GATE reset or
SPI (RESET_GATE) is required to recover the gate driver to normal operation after the temperature goes
below a preset value, tOTSD_CLR.
SPI operation is still available and register settings will be remaining in the device during OTSD operation as long
as PVDD1 is within the defined operation range.

7.3.4.5 Fault and Protection Handling

The nFAULT pin indicates when a shutdown event has occurred. These events include overcurrent,
overtemperature, overvoltage, or undervoltage. Note that nFAULT is an open-drain signal. nFAULT will go high
when the gate driver is ready for PWM inputs during start-up.
The nOCTW pin indicates when a overcurrent event or over temperature event has occurred. These events are
not necessary related to a shutdown.
Table 5 provides a summary of all the protection features and their reporting structure.

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Table 5. Fault and Warning Reporting and Handling

REPORTING ON REPORTING ON REPORTING IN SPI
EVENT ACTION LATCH
nFAULT PIN nOCTW PIN STATUS REGISTER
External FETs Hi-Z;
PVDD
Weak pulldown of all gate N Y N Y
undervoltage
driver output
External FETs Hi-Z;
DVDD Weak pulldown of all gate
N Y N N
undervoltage driver output; When recovering,
reset all status registers
External FETs Hi-Z;
GVDD
Weak pulldown of all gate N Y N Y
undervoltage
driver output
External FETs Hi-Z;
Weak pull down of all gate driver
output
GVDD
Shut down the charge pump Y Y N Y
overvoltage
Won’t recover and reset through
SPI reset command or
quick EN_GATE toggling
Y (in default
OTW None N N Y
setting)
Gate driver latched shut down.
Weak pulldown of all gate driver
OTSD_GATE output Y Y Y Y
to force external FETs Hi-Z
Shut down the charge pump
OTSD_BUCK OTSD of Buck Y N N N
Buck output
UVLO_BUCK: auto-restart N Y (PWRGD pin) N N
undervoltage
Buck current limiting
Buck overload (Hi-Z high side until current reaches N N N N
zero and then auto-recovering)
External FET
External FETs current Limiting
overload – current N N Y Y
(only OC detected FET)
limit mode
Weak pulldown of gate driver
External FET
output and PWM logic “0” of
overload – Latch Y Y Y Y
LS and HS in the same phase.
mode
External FETs Hi-Z
External FET
overload – Reporting only N N Y Y
reporting only
mode

7.3.5 Start-up and Shutdown Sequence Control

During power up all gate drive outputs are held low. Normal operation of gate driver and current shunt amplifiers
can be initiated by toggling EN_GATE from a low state to a high state. If no errors are present, the DRV8301 is
ready to accept PWM inputs. Gate driver always has control of the power FETs even in gate disable mode as
long as PVDD is within functional region.
There is an internal diode from SDO to VDD_SPI, so VDD_SPI is required to be powered to the same power
level as other SPI devices (if there is any SDO signal from other devices) all the time. VDD_SPI supply should
be powered up first before any signal appears at SDO pin and powered down after completing all
communications at SDO pin.

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7.4 Device Functional Modes

7.4.1 EN_GATE
EN_GATE low is used to put gate driver, charge pump, current shunt amplifier, and internal regulator blocks into
a low-power consumption mode to save energy. SPI communication is not supported during this state and the
SPI registers will revert to their default settings after a full EN_GATE reset. The device will put the MOSFET
output stage to high-impedance mode as long as PVDD is still present.
When the EN_GATE pin goes low to high, it will go through a power-up sequence, and enable gate driver,
current amplifiers, charge pump, internal regulator, and so forth and reset all latched faults related to gate driver
block. The EN_GATE will also reset status registers in the SPI table. All latched faults can be reset when
EN_GATE is toggled after an error event unless the fault is still present.
When EN_GATE goes from high to low, it will shut down gate driver block immediately, so gate output can put
external FETs in high impedance mode. It will then wait for 10 µs before completely shutting down the rest of the
blocks. A quick fault reset mode can be done by toggling EN_GATE pin for a very short period (less than 10 µs).
This will prevent the device from shutting down the other functional blocks such as charge pump and internal
regulators and bring a quicker and simple fault recovery. SPI will still function with such a quick EN_GATE reset
mode. To perform a full reset, EN_GATE should be toggled for longer than 20 µs. This allows for all of the blocks
to completely shut down and reach known states.
An EN_GATE reset pulse (high → low → high) from 10 to 20 µs should not be applied to the EN_GATE pin. The
DRV8301 has a transition area from the quick to full reset modes that can cause the device to become
unresponsive to external inputs until a full power cycle. An RC filter can be added externally to the pin if reset
pulses with this period are expected to occur on the EN_GATE pin.
The other way to reset all of the faults is to use SPI command (RESET_GATE), which will only reset gate driver
block and all the SPI status registers without shutting down the other functional blocks.
One exception is to reset a GVDD_OV fault. A quick EN_GATE quick fault reset or SPI command reset will not
work with GVDD_OV fault. A complete EN_GATE with low level holding longer than 20 µs is required to reset
GVDD_OV fault. TI highly recommends to inspect the system and board when GVDD_OV occurs.

7.4.2 DTC
Dead time can be programmed through DTC pin. A resistor should be connected from DTC to ground to control
the dead time. Dead time control range is from 50 ns to 500 ns. Short DTC pin to ground will provide minimum
dead time (50 ns). Resistor range is 0 to 150 kΩ. Dead time is linearly set over this resistor range.
Current shoot through prevention protection will be enabled in the device all time independent of dead time
setting and input mode setting.

7.4.3 VDD_SPI
VDD_SPI is the power supply to power SDO pin. It has to be connected to the same power supply (3.3 V or 5 V)
that MCU uses for its SPI operation.
During power up or down transient, VDD_SPI pin could be zero voltage shortly. During this period, no SDO
signal should be present at SDO pin from any other devices in the system because it causes a parasitic diode in
the DRV8301 conducting from SDO to VDD_SPI pin as a short. This should be considered and prevented from
system power sequence design.

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7.5 Programming
7.5.1 SPI Communication

7.5.1.1 SPI
The DRV8301 SPI operates as a slave. The SPI input (SDI) data format consists of a 16 bit word with 1
read/write bit, 4 address bits, and 11 data bits. The SPI output (SDO) data format consists of a 16 bit word with 1
frame fault bit, 4 address bits, and 11 data bits. When a frame is not valid, frame fault bit will set to 1 and the
remaining bits will shift out as 0.
A valid frame must meet following conditions:
• Clock must be low when nSCS goes low.
• Should have 16 full clock cycles.
• Clock must be low when nSCS goes high.
When nSCS is asserted high, any signals at the SCLK and SDI pins are ignored and SDO is forced into a high
impedance state. When nSCS transitions from HIGH to LOW, SDO is enabled and the SDO response word
loads into the shift register based on the previous SPI input word.
The SCLK pin must be low when nSCS transitions low. While nSCS is low, at each rising edge of the clock the
response word is serially shifted out on the SDO pin with the MSB shifted out first.
While SCS is low, at each falling edge of the clock the new input word is sampled on the SDI pin. The SPI input
word is decoded to determine the register address and access type (read or write). The MSB will be shifted in
first. Any amount of time may pass between bits, as long as nSCS stays active low. This allows two 8-bit words
to be used. If the input word sent to SDI is less than 16 bits or more than 16 bits, it is considered a frame error. If
it is a write command, the data will be ignored. The fault bit in the next SDO response word will then report 1.
After the 16th clock cycle or when nSCS transitions from LOW to HIGH, the SDI shift register data is transferred
into a latch where the input word is decoded.
For a READ command (Nth cycle) sent to SDI, SDO will respond with the data at the specified address in the
next cycle. (N+1)
For a WRITE command (Nth cycle) sent to SDI, SDO will respond with the data in Status Register 1 (0x00) in the
next cycle (N+1). This feature is intended to maximize SPI communication efficiency when having multiple write
commands.

7.5.1.2 SPI Format

The SDI input data word is 16 bits long and consists of:
• 1 read/write bit W [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]
The SDO output data word is 16 bits long and consists of:
• 1 fault frame bit F [15]
• 4 address bits A [14:11]
• 11 data bits D [10:0]
The SDO output word (Nth cycle) is in response to the previous SDI input word (N-1 cycle).
Therefore each SPI Query/Response pair requires two full 16 bit shift cycles to complete.

Table 6. SPI Input Data Control Word Format

R/W ADDRESS DATA
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command W0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

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Table 7. SPI Output Data Response Word Format

R/W DATA
Word Bit B15 B14 B13 B12 B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
Command F0 A3 A2 A1 A0 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

7.6 Register Maps

7.6.1 Read / Write Bit
The MSB bit of the SDI input word (W0) is a read/write bit. When W0 = 0, the input word is a write command.
When W0 = 1, input word is a read command.

7.6.2 Address Bits

Table 8. Register Address

REGISTER
ADDRESS [A3..A0] REGISTER NAME DESCRIPTION READ AND WRITE ACCESS
TYPE
Status 0 0 0 0 Status Register 1 Status register for device faults R
Register 0 0 0 1 Status Register 2 Status register for device faults and ID R
Control 0 0 1 0 Control Register 1 R/W
Register 0 0 1 1 Control Register 2 R/W

7.6.3 SPI Data Bits

7.6.3.1 Status Registers

Table 9. Status Register 1 (Address: 0x00) (All Default Values are Zero)
REGISTER
ADDRESS D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
Status
0x00 FAULT GVDD_UV PVDD_UV OTSD OTW FETHA_OC FETLA_OC FETHB_OC FETLB_OC FETHC_OC FETLC_OC
Register 1

Table 10. Status Register 2 (Address: 0x01) (All Default Values are Zero)
ADDRESS REGISTER D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NAME
Status Device ID Device ID Device ID Device ID
0x01 GVDD_OV
Register 2 [3] [2] [1] [0]

7.6.3.2 Control Registers

Table 11. Control Register 1 for Gate Driver Control (Address: 0x02) (1)
ADDRESS NAME DESCRIPTION D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Gate drive peak current 1.7 A 0 (1) 0 (1)
Gate drive peak current 0.7 A 0 1
GATE_CURRENT
Gate drive peak current 0.25 A 1 0
Reserved 1 1
Normal mode 0 (1)
GATE_RESET
Reset gate driver latched faults (reverts to 0) 1
0x02 6 PWM inputs (see Table 1) 0 (1)
PWM_MODE
3 PWM inputs (see Table 2) 1
Current limit 0 (1) 0 (1)
OC latch shut down 0 1
OCP_MODE
Report only 1 0
OC disabled 1 1
OC_ADJ_SET See OC_ADJ_SET table X X X X X

(1) Default value

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Table 12. Control Register 2 for Current Shunt Amplifiers and Misc Control (Address: 0x03) (1)
ADDRESS NAME DESCRIPTION D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Report both OT and OC at nOCTW pin 0 (1) 0 (1)
Report OT only 0 1
OCTW_MODE
Report OC only 1 0
Report OC only (reserved) 1 1
Gain of shunt amplifier: 10 V/V 0 (1) 0 (1)
Gain of shunt amplifier: 20 V/V 0 1
GAIN
Gain of shunt amplifier: 40 V/V 1 0
Gain of shunt amplifier: 80 V/V 1 1
0x03
Shunt amplifier 1 connects to load through input pins 0 (1)
DC_CAL_CH1 Shunt amplifier 1 shorts input pins and disconnects from load
1
for external calibration
Shunt amplifier 2 connects to load through input pins 0 (1)
DC_CAL_CH2 Shunt amplifier 2 shorts input pins and disconnects from load
1
for external calibration
(1)
Cycle by cycle 0
OC_TOFF
Off-time control 1
Reserved

(1) Default value

7.6.3.3 Overcurrent Adjustment

Table 13. OC_ADJ_SET Table

Control Bit (D6–D10) (0xH) 0 1 2 3 4 5 6 7
Vds (V) 0.060 0.068 0.076 0.086 0.097 0.109 0.123 0.138
Control Bit (D6–D10) (0xH) 8 9 10 11 12 13 14 15
Vds (V) 0.155 0.175 0.197 0.222 0.250 0.282 0.317 0.358
Control Bit (D6–D10) (0xH) 16 17 18 19 20 21 22 23
Vds (V) 0.403 0.454 0.511 0.576 0.648 0.730 0.822 0.926
Code Number (0xH) 24 25 26 27 28 29 30 31
Vds (V) 1.043 1.175 1.324 1.491 1.679 (1) 1.892 (1) 2.131 (1) 2.400 (1)

(1) Do not use settings 28, 29, 30, 31 for VDS sensing if the IC is expected to operate in the 6-V to 8-V range.

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8 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

The DRV8301 is a gate driver designed to drive a 3-phase BLDC motor in combination with external power
MOSFETs. The device provides a high level of integration with three half-bridge gate drivers, two current shunt
amplifiers, and overcurrent protection.

8.1.1 Gate Driver Power-Up Sequencing Errata

The DRV8301 gate drivers may not correctly power up if a voltage greater than 8.5 V is present on any SH_X pin
when EN_GATE is brought logic high (device enabled) after PVDD1 power is applied (PVDD1 > PVDD_UV).
This sequence should be avoided by ensuring the voltage levels on the SH_X pins are less than 8.5 V when the
DRV8301 is enabled through EN_GATE.

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8.2 Typical Application

The following design is a common application of the DRV8301.

6800 pF 16.2 kΩ

205 kΩ
VCC

0.015 µF
120 pF
10 kΩ 31.6 kΩ
MCU DRV8301 PVDD

10 kΩ

10 kΩ

10 kΩ
1 56
VCC RT_CLK SS_TR

0.1 µF

4.7 µF
2 55
POWER COMP EN_BUCK X
3 54
VSENSE PVDD2
4 53
PWRGD PVDD2
5 52 0.1 µF 22 µH
VCC
GPIO nOCTW BST_BK
6 51
nFAULT PH
1Ω

47 µF
7 50 +
DTC PH
8 49 VCC
nSCS VDD_SPI
9 48 0.1 µF
SDI BST_A
SPI 10 47
SDO GH_A GH_A
11 46
SCLK SH_A SH_A
12 45
DC_CAL GL_A GL_A
13 44
GVDD SL_A SL_A
2.2 µF 0.022 µF 14 43 0.1 µF
GPIO CP1 BST_B
15 42
CP2 GH_B GH_B
16 41
EN_GATE SH_B SH_B
17 40
INH_A GL_B GL_B
18 39
INL_A SL_B SL_B
19 38 0.1 µF
INH_B BST_C
PWM 20 37
INL_B GH_C GH_C
21 36
INH_C SH_C SH_C
22 35
INL_C GL_C GL_C
1 µF 23 34
PVDDSENSE DVDD SL_C SL_C
24 33
ASENSE REF SN1 SN1
ADC 56 Ω 25 32
BSENSE SO1 SP1 SP1
56 Ω 26 31
CSENSE SO2 SN2 SN2 PVDD
1 µF 27 30
2200 pF

AVDD SP2 SP2

2200 pF

PPAD

28 29
AGND PVDD1

0.1 µF

4.7 µF
57

PVDD
AGND GND PGND
VCC
3.3 Ω 0.01 µF

34.8 kΩ
220 µF

220 µF

0.1 µF

+ +

PVDDSENSE
4.99 kΩ

0.1 µF

PVDD PVDD PVDD

2.2 µF

2.2 µF

2.2 µF

10 Ω 10 Ω 10 Ω
GH_A GH_B GH_B

VCC VCC VCC

SH_A SH_B SH_B
34.8 kΩ

34.8 kΩ

34.8 kΩ

10 Ω 10 Ω 10 Ω
GL_A GL_B GL_B
4.99 kΩ

4.99 kΩ

4.99 kΩ
0.1 µF

0.1 µF

0.1 µF
ASENSE

CSENSE
BSENSE

SL_A SL_B SL_B

SN1 SN2
1000 pF

1000 pF
10 mΩ

10 mΩ

Diff. Pair Diff. Pair

SP1 SP2

AGND GND PGND

Figure 7. Typical Application Schematic

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Typical Application (continued)

8.2.1 Design Requirements
Table 14 shows the design parameters for this application.

Table 14. Design Parameters

DESIGN PARAMETER REFERENCE VALUE
Supply voltage PVDD 24 V
Motor winding resistance MR 0.5 Ω
Motor winding inductance ML 0.28 mH
Motor poles MP 16 poles
Motor rated RPM MRPM 4000 RPM
Target full-scale current IMAX 14 A
Sense resistor RSENSE 0.01 Ω
MOSFET Qg Qg 29 nC
MOSFET RDS(on) RDS(on) 4.7 mΩ
VDS trip level OC_ADJ_SET 0.123 V
Switching frequency ƒSW 45 kHz
Series gate resistance RGATE 10 Ω
Amplifier reference VREF 3.3 V
Amplifier gain Gain 10 V/V

8.2.2 Detailed Design Procedure

8.2.2.1 Gate Drive Average Current Load

The gate drive supply (GVDD) of the DRV8301 can deliver up to 30 mA (RMS) of current to the external power
MOSFETs. Use Equation 3 to determine the approximate RMS load on the gate drive supply:
Gate Drive RMS Current = MOSFET Qg × Number of Switching MOSFETs × Switching Frequency (3)
Example:
7.83 mA = 29 nC × 6 × 45 kHz (4)
This is a rough approximation only.

8.2.2.2 Overcurrent Protection Setup

The DRV8301 provides overcurrent protection for the external power MOSFETs through the use of VDS monitors
for both the high side and low side MOSFETs. These are intended for protecting the MOSFET in overcurrent
conditions and not for precise current regulation.
The overcurrent protection works by monitoring the VDS voltage of the external MOSFET and comparing it
against the OC_ADJ_SET register value. If the VDS exceeds the OC_ADJ_SET value the DRV8301 takes action
according to the OC_MODE register.
Overcurrent Trip = OC_ADJ_SET / MOSFET RDS(on) (5)
Example:
26.17 A = 0.123 V/ 4.7 mΩ (6)
MOSFET RDS(on) changes with temperature and this will affect the overcurrent trip level.

8.2.2.3 Sense Amplifier Setup

The DRV8301 provides two bidirectional low-side current shunt amplifiers. These can be used to sense a sum of
the three half-bridges, two of the half-bridges individually, or in conjunction with an additional shunt amplifier to
sense all three half-bridges individually.
1. Determine the peak current that the motor will demand (IMAX). This will be dependent on the motor
parameters and your specific application. I(MAX) in this example is 14 A.
2. Determine the available voltage range for the current shunt amplifier. This will be ± half of the amplifier
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reference voltage (VREF). In this case the available range is ±1.65 V.

3. Determine the sense resistor value and amplifier gain settings. There are common tradeoffs for both the
sense resistor value and amplifier gain. The larger the sense resistor value, the better the resolution of the
half-bridge current. This comes at the cost of additional power dissipated from the sense resistor. A larger
gain value will allow you to decrease the sense resistor, but at the cost of increased noise in the output
signal. This example uses a 0.01 Ω sense resistor and the minimum gain setting of the DRV8301 (10 V/V).
These values allow the current shunt amplifiers to measure ±16.5 A (some additional margin on the 14 A
requirement).

8.2.3 Application Curves

Figure 8. Motor Spinning 2000 RPM Figure 9. Motor Spinning 4000 RPM

Figure 10. Gate Drive 20% Duty Cycle Figure 11. Gate Drive 80% Duty Cycle

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9 Power Supply Recommendations

9.1 Bulk Capacitance

Having appropriate local bulk capacitance is an important factor in motor drive system design. It is generally
beneficial to have more bulk capacitance, while the disadvantages are increased cost and physical size.
The amount of local capacitance needed depends on a variety of factors, including:
• The highest current required by the motor system
• The capacitance of the power supply and its ability to source or sink current
• The amount of parasitic inductance between the power supply and motor system
• The acceptable voltage ripple
• The type of motor used (brushed DC, brushless DC, stepper)
• The motor braking method
The inductance between the power supply and motor drive system will limit the rate current can change from the
power supply. If the local bulk capacitance is too small, the system will respond to excessive current demands or
dumps from the motor with a change in voltage. When adequate bulk capacitance is used, the motor voltage
remains stable and high current can be quickly supplied.
The data sheet generally provides a recommended value, but system-level testing is required to determine the
appropriate sized bulk capacitor.

Parasitic Wire
Inductance
Power Supply Motor Drive System

VM

+ + Motor
– Driver

GND

Local IC Bypass
Bulk Capacitor Capacitor

Figure 12. Example Setup of Motor Drive System With External Power Supply

The voltage rating for bulk capacitors should be higher than the operating voltage, to provide margin for cases
when the motor transfers energy to the supply.

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10 Layout

10.1 Layout Guidelines

Use these layout recommendations when designing a PCB for the DRV8301.
• The DRV8301 makes an electrical connection to GND through the PowerPAD. Always check to ensure that
the PowerPAD has been properly soldered (See PowerPAD™ Thermally Enhanced Package application
report, SLMA002).
• PVDD bypass capacitors should be placed close to their corresponding pins with a low impedance path to
device GND (PowerPAD).
• GVDD bypass capacitor should be placed close its corresponding pin with a low impedance path to device
GND (PowerPAD).
• AVDD and DVDD bypass capacitors should be placed close to their corresponding pins with a low-impedance
path to the AGND pin. It is preferable to make this connection on the same layer.
• AGND should be tied to device GND (PowerPAD) through a low impedance trace/copper fill.
• Add stitching vias to reduce the impedance of the GND path from the top to bottom side.
• Try to clear the space around and underneath the DRV8301 to allow for better heat spreading from the
PowerPAD.

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10.2 Layout Example

Figure 13. Top and Bottom Layer Layout Schematic

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11 Device and Documentation Support

11.1 Documentation Support

11.1.1 Related Documentation
For related documentation see the following:
• Semiconductor and IC Package Thermal Metrics application report, SPRA953
• PowerPAD™ Thermally Enhanced Package application report, SLMA002

11.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

11.3 Trademarks
PowerPAD, E2E are trademarks of Texas Instruments.
All other trademarks are the property of their respective owners.
11.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

11.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2011–2016, Texas Instruments Incorporated Submit Documentation Feedback 31

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead/Ball Finish MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) (6) (3) (4/5)

DRV8301DCA ACTIVE HTSSOP DCA 56 35 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV8301
& no Sb/Br)
DRV8301DCAR ACTIVE HTSSOP DCA 56 2000 Green (RoHS CU NIPDAU Level-3-260C-168 HR -40 to 125 DRV8301
& no Sb/Br)

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 22-Jan-2016

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF DRV8301 :

• Automotive: DRV8301-Q1

NOTE: Qualified Version Definitions:

• Automotive - Q100 devices qualified for high-reliability automotive applications targeting zero defects

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jul-2016

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DRV8301DCAR HTSSOP DCA 56 2000 330.0 24.4 8.6 15.6 1.8 12.0 24.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 12-Jul-2016

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DRV8301DCAR HTSSOP DCA 56 2000 367.0 367.0 45.0

Pack Materials-Page 2
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