EEE 343: Embedded Microcontrollers

Lecture 2: Communication Protocols in Embedded Systems

Ikechi A. Ukaegbu

Embedded Microcontrollers
 Modes of Communication

●
Simplex

●
Half Duplex

● Duplex

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 ES Communication Interfaces

• On-board communication interfaces

– These are used for internal communication of the
embedded system
• Communication between different components present on
the system

• External or peripheral communication interfaces

– These are used for external communication of the
embedded system
• Communication of different components present on the system with
external or peripheral components/devices

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 On-board Communication Interfaces

• Device/Board level communication interface

– I2C (Inter Integrated Circuit)

– SPI (Serial Peripheral Interface)

– UART (Universal Asynchronous Receiver and Transmitter)

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I2C
 On-board Communication Interfaces

• I2C (Inter Integrated Circuit)

– It is synchronous
– Two-wire serial interface bus
– Bi-directional, half duplex
– Uses multi Master/Slave
– Developed by Phillips semiconductors in 1980

Multiple Devices on Common I2C Bus

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 I2C (Inter Integrated Circuit)

Vdd

R1 R2
Master

SCL

Slave
SCL

SDA SDA

If Vdd is 5V, then it is common to use

SCL - Serial Clock Line
• 2K for 400 Kbps
SDA - Serial Data Line • 10K for 100 Kbps

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 I2C (Inter Integrated Circuit)

Multiple Slaves

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 I2C (Inter Integrated Circuit)

• Advantages
– Low cost (due to low gate count)
– Low pin count (just 2!)
– Addressing built-in
– Ubiquitous

• Disadvantages
– Half-duplex (about 400 kbps max)
– Careful consideration of hardware
– More complicated than SPI and UART

N.B.: I2C can reach up to 1MHz ~ 5 MHz but these speeds are not very common

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 I2C (Inter Integrated Circuit)

Logic Logic Logic Logic

Device 1 (Master) Device 2 (Slave)

“Open Drain” I2C Architecture

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 I2C (Inter Integrated Circuit)
Control Byte Data Byte

SDA

SCL

Slave Address
(Each slave must have a fixed and different address)

Start condition:
• Master SDA = High to Low Initiated from idle bus state
• Master SCL = Hold High

ACK/NACK:
• R/W: High = read data request • Receiving device sends ACK/NACK
• R/W: Low = data will be sent • ACK = Acknowledge = Low (zero)
• NACK = No Acknowledgement = High (one)

Stop condition:
• Master SDA = Low to High
• Master SCL = Hold High
Bus becomes idle
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SPI
 On-board Communication Interfaces

• SPI (Serial Peripheral Interface)

– It is synchronous
– Faster than I2C (20MHz vs 1MHz)
– Requires twice more logic gates than I2C
– Uses additional links to isolate data to and from the slave
– More expensive than I2C
– Can use Dual SPI and Quad SPI to achieve higher speed of up
to 144 MHz
– Developed in 1985
– Found in NOR flash, EEPROM, EERAM, Serial SRAM, Secure
digital memory cards, LCD crystal displays, ADC, DAC, Real
time clocks

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 SPI (Serial Peripheral Interface)

SCLK SCLK
Master

Slave
SPI

MOSI

SPI
MOSI
MISO MISO
SS SS

SCLK - Serial Clock

MOSI - Master Out Slave In
MISO - Master In Slave Out
SS - Slave Select (Chip Select, active low)

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 SPI (Serial Peripheral Interface)

Multiple Slaves

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 SPI (Serial Peripheral Interface)

• Advantages
– Full duplex
– Higher speed than UART and I2C
– No start and stop bits (data can be streamed without
interruptions)
– No complicated slave addressing system like the I2C
– Ubiquitous

• Disadvantages
– More pins than UART and I2C
– Short distances

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 SPI (Serial Peripheral Interface)

• Steps of SPI data transmission:

1. The master outputs the clock signal

2. The master switches the SS/CS pin to a low voltage state which
activates the slave

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 SPI (Serial Peripheral Interface)

• Steps of SPI data transmission:

3. The master sends the data one bit at a time to the slave along
the MOSI line. The slave reads the bits as they are received

4. If a response is needed, the slave returns data one bit at a time to the
master along the MISO line. The master reads the bits as they are
received

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 SPI (Serial Peripheral Interface)

• Data transmission:

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 SPI (Serial Peripheral Interface)

• Data transmission:

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 SPI (Serial Peripheral Interface)

• Data transmission:

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 SPI (Serial Peripheral Interface)

• Data transmission:

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 SPI (Serial Peripheral Interface)

• Data transmission:

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 SPI (Serial Peripheral Interface)

• Data transmission:

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 SPI (Serial Peripheral Interface)

• Data transmission:

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 SPI (Serial Peripheral Interface)

• Data transmission:

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 SPI (Serial Peripheral Interface)

• Data validity:

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UART
 On-board Communication Interfaces

• UART (Universal Asynchronous Receiver/Transmitter)

– Sometimes called Serial Port, COM port, etc
– Very common and simple
– Requires twice more logic gates than I2C
– Useful for communication to:
• Microcontroller
• Computer
• Other FPGAs

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 UART (Universal Asynchronous Rx/Tx)

Device FPGA
UART Tx UART Rx

UART Rx UART Tx

GND GND

UART Communication

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 UART (Universal Asynchronous Rx/Tx)

• UART communication scheme

– One chip’s Tx pin connects directly to the other’s Rx pin and vice versa
• The transmission will take place at 3.3. or 5V
• UART is a single-master, single-slave protocol (one device is set up to communicate with
only one partner)

– Data travels in parallel to and from the UART to the controlling device (ex.
a CPU)

– When sending on the Tx pin, the first UART translates this parallel
information into serial and transmits it to the receiving counterpart

– The second UART receives this data on its Rx pin and transforms it back
into parallel to communicate with its controlling device

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 UART (Universal Asynchronous Rx/Tx)

• UART
– The transmitter and receiver use start bit, stop bit and timing parameters to
synchronize with each other
– The original data is in parallel form
– We need a parallel to serial converter

How can we achieve this?

D flip-flops are used to design the

converters!

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 Recap – [D-type Flip-flop]

• D-FF is one of the most widely used flip-flops

SR Flip-flop TT

Clk S R Q+
0 x x Q D S Qn D Qn
Memory
1 0 0 Q
Clk
1 0 1 0
Q’n Q’n
1 1 0 1 R

1 1 1 Not used
D Flip-flop TT

Clk D Q+
0 x Q
1 0 0
1 1 1
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 Recap – [D-type Flip-flop]

• In D-FF, D stands for “Data”

D Flip-flop TT Characteristic Table of D-FF Excitation Table of D-FF

Clk D Q+ Q D Q+
Q Q+ D
0 x Q 0 0 0 0 0 0
1 0 0 0 1 1 1
0 1
1 1 1 1 0 0 1 0 0
1 1 1 1 1 1
Q+ = D

D S Q

Clk

R Q’

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 Recap – [Classification of Registers]

• Classification based on applications:

– Shift registers

– Storage registers

• Classification based on input and output (I/O):

– Serial input, serial output (SISO)

– Serial input, parallel output (SIPO)

– Parallel input, serial output (PISO)

– Parallel input, parallel output (PIPO)

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 Recap – [Classification of Registers]

• Data can be entered in serial form (one bit at a time)

• Data can be entered in parallel form (all bits at a time)

Clk
Serial 1 1 1
Parallel Input Input D 0
1
1 1 0 1
D3
Serial Serial
FF3 FF2 FF1 FF0 1
Input Output D2
Parallel
Input D1
0
Parallel Output 1
D0

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 Recap – [Shift Registers (SISO)]

• They are sequential circuits that are used for data storage, data
transfer and certain arithmetic and logic operations
1 1 1 1
1 1 1 1 1
1111 1 1 1 1 1 1 0 0
1 1 1 1 0 0 0 0
0 1 0 0 0 0 0 0
Din D3 Q3 D2 Q2 D1 Q1 D0 Q0 Serial
Output

FF3 FF2 FF1 FF0

Clk

Clk
Clk Q3 Q2 Q1 Q 0
D Flip-flop TT Din
Clk D Q+ Initial 0 0 0 0 Q3 1 1 1 1
First clk 1
0 x 1 1
Q edge 1 0 0 0 Q2 0
0 0
Next clk
Q1 1 1
1 edge 1 1 0 0 0 0
Next clk
1 1 1 Q0 1
edge 1 1 1 0 0 0 0
Next clk
edge 1 1 1 1
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 Recap – [Shift Registers (SIPO)]

• They are sequential circuits that are used for data storage, data
transfer and certain arithmetic and logic operations

Din D3 Q3 D2 Q2 D1 Q1 D0 Q0

FF3 FF2 FF1 FF0

Clk

Parallel Output
Clk
Din SISO
Q3 1 1 1 1
1 1 1
Q2 0
Q1 1 1
0 0 SIPO
1
Q0 0 0 0

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 Recap – [Storage Registers (PIPO)]

• They are sequential circuits that are used for data storage, data
transfer and certain arithmetic and logic operations

Parallel Input

D3 Q3 D2 Q2 D1 Q1 D0 Q0

FF3 FF2 FF1 FF0

Clk

Parallel Output

PIPO

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 Recap – [Storage Registers (PISO)]

Operating modes:
1. Load Mode PISO
2. Shift Mode

1 1 0 1
Load/ A3
A2 A1 A0
Shift 0
1 01 0
1 0
1
0 10
10 10
1 01
1 2 3 4
5 6
0 A20 0 A01 0 A00
Q3 Q2 Q1

QA32 QA21 Serial

D3 Q3 D2 Q2 D1 Q1 QA
1
0
D0 Q0
Output
0 1
1 1

FF3 FF2 FF1 FF0

Clk

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 UART (Universal Asynchronous Rx/Tx)

• Start Bit
– The first bit of one-byte UART transmission
– Indicates that the data line is leaving its idle state
– Idle state is logically high (start bit is logic low)
– Its an overhead bit and facilitates communication between the receiver and
the transmitter but does not transfer meaningful data

• Stop Bit
– The last bit of one-byte UART transmission
– The same level as the idle state

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 UART (Universal Asynchronous Rx/Tx)

• Baud Rate
– The approximate rate (in bits per second or bps) at which data can be
transferred
– It is the frequency (in bps) corresponding to the time (in seconds) required
to transmit one bit of digital data
– Ex., with 9600-baud system, one bit requires 1/(9600 bps) ~ 104.2 us.

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 UART (Universal Asynchronous Rx/Tx)

• Parity Bit
– An error detection bit is added at the end of the byte
– There are “even parity” and “odd parity”
– “Even parity” means that the parity bit will be logic high if the data byte
contains even number of logic-high bits
– “Odd parity” means that the parity bit will be logic high if the data byte
contains odd number of logic-high bits

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 UART (Universal Asynchronous Rx/Tx)

• Sampling and Synchronization

– A typical data signal is simply a voltage that transitions between logic low
and logic high
– The receiver can correctly converts the logic states into digital data only if it
knows when to sample the data
– The transmitter generates a bit stream based on its clock
– The receiver uses its internal clock signal to sample the signal in the middle
of each bit period

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 UART (Universal Asynchronous Rx/Tx)

• Sampling and Synchronization

– To ensure that the active edge of the receiver clock can occur near the
middle of the bit period, the frequency of the baud-rate clock sent to the
receiver module is much higher than the actual baud rate
– Ex. If one bit period corresponds to 16 receiver clock cycles:
• The receive process is initiated by the falling edge of the start bit
• The receiver waits for 8 clock cycles, in order to establish a sampling point that is near
the middle of the bit period
• The receiver then waits 16 clock cycles , which brings it to the middle of the first data-
bit period
• The first data bit is sampled and stored in the receive register, and then the module
waits for another 16 clock cycles before sampling the second data bit
• This process repeats unitl all data bits have been sampled and stored
• Then the rising edge of the stop bit returns the UART interface to its idle state.

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Other Communication Interfaces
 External/Peripheral Communication Interface

• Common example include:

– Universal Serial Bus (USB)
– Infrared (IrDA)
– Bluetooth
– Wi-Fi
– Zig Bee
– General Packet Radio Service (GPRS)

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 I/O Subsystem

• Examples of some sensors and actuators used in

embedded systems
– LED
– 7 segment LED display
– Optocoupler
– Stepper motor
– Relay
– Piezo buzzer
– Push button switch
– Keyboard
– Programmable Peripheral Interface (PPI)

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 LED (Light Emitting Diode)

• It is an important output device for visual indication in any embedded

system

• LED can be used as in indicator for the status of various signals or

situations

• Typical examples are indicating the presence of power conditions like

“Device ON”, “Battery Low”, or “Charging of Battery”, for battery
operated handheld embedded devices

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 7 Segment LED Display

• It is an output device for displaying alpha numeric characters

• It contains 8 light emitting diode (LED) segments arranged in a special

form

• Out of 8 LED segments 7 are used for displaying alpha numeric

characters and 1 LED is used for representing “decimal point” in
decimal numbers

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