31

CHAPTER 2

DESIGN OF SRAM CELL USING TRANSISTORS

2.1 INTRODUCTION

Static random-access memory (SRAM) is a type of semiconductor

memory that uses bistable (logic 1 or logic 0) latching circuitry to store each
bit. The term ‘static’ differentiates it from dynamic RAM (DRAM) which
must be periodically refreshed. SRAM exhibits data reminisce, but it is still
volatiles in the conventional sense that data is eventually lost when the
memory is not powered. Compared to Dynamic RAM (DRAM), SRAM
doesn’t have a capacitor to store the data, hence SRAM works without
refreshing. In SRAM, the data are lost when the memory is not electrically
powered. SRAM is faster and more reliable than the common DRAM. In
addition, its cycle time is much shorter than that of DRAM because it does
not need to pause between accesses. Due to DRAM’s high cost, SRAM is
often used only as a memory cache.

SRAM is designed to fill two needs: to provide a direct interface

with the CPU at speeds not attainable by DRAMs and to replace DRAMs in
systems that require very low power consumption. In the first role, the SRAM
serves as cache memory, interfacing between DRAMs and the CPU. In the
second, driving force for SRAM technology is the low power applications. In
this case, SRAMs are used as the most portable equipment because the
 32

DRAM refresh current is several orders of magnitude more than the low-
power SRAM standby current.

SRAM is used in personal computers, workstations, routers and

peripheral equipment: internal CPU caches and external burst mode SRAM
caches, hard disk buffers, router buffers, etc. LCD screens and printers also
normally employ SRAM to hold the image displayed or to be printed. Small
SRAM buffers are also found in CDROM and CDRW drives to buffer track
data, which is transferred in blocks instead of a single value. The same applies
to cable modems and its similar equipment connected to the computers.

Static RAM cells are also used in a wide variety of applications

such as different categories of industrial and scientific subsystems,
automotive electronics, digital cameras, cell phones, synthesizers, etc., As the
demand for reduced power and delay in components containing SRAMs
increases, adjustments are to be made to meet these requirements.

2. 2 SRAM CELL

The SRAM cell consists of a bistable flip-flop connected to the

internal circuitry by two access transistors. When the cell is not addressed, the
two access transistors are closed and the data is kept to a stable state, latched
within the flip-flop. The flip-flop needs the power supply to keep the
information. The data in an SRAM cell is volatile (i.e., the data is lost when
the power is removed). However, the data does not "leak away" like in a
DRAM, so the SRAM does not require a refresh cycle shown in Figure 2.1.
 33

Figure 2.1 Pictorial representation of SRAM cell

Random access means that the locations in the memory can be

written to or read from in any order, regardless of the memory location that
was last accessed. Earlier asynchronous static RAM chips performed read and
write operations sequentially. Newer synchronous static RAM chips overlap
reads and writes. The operation of SRAM cell is explained in the next section.

2.3 SRAM CELL OPERATION

An SRAM cell operates in one of three possible states. It can be in

the stable state with the cell holding a value or it can be in the process of
carrying out a read or a write. The stable state of the cell occurs with the
wordline connected to T1/T2 being driven low(WL=0). The cell is effectively
disconnected in this mode of operation.

A read operation is initiated by precharging the bitlines high and

activating the wordline. One of the bitlines discharges through the bit cell, and
a differential voltage is set up across the bitline. This voltage is sensed and
amplified to logic levels. A write to the cell is carried out by driving the
bitlines to the required state and activating the wordline (WL=1).
 34

In standard logic, energy consumption is reduced by reducing one

of the four factors: total switched capacitance, voltage swing, activity factor
and frequency of operation. In memory cells, it is usually the voltage swing at
various points that can be easily manipulated by a circuit designer without
impacting other specifications of the memory. It is clear that to achieve the
goal for lower power, reduced voltage swings on bitlines and wordlines are
essential. The lower limit of supply voltages is determined by our inability to
resolve small voltage differentials at adequate speed, degraded signal integrity
and increasing soft error rates (SERs).

Four-transistor SRAM is quite common in stand-alone SRAM

devices (as opposed SRAM used for CPU caches), implemented in special
processes with an extra layer of polysilicon, allowing for very high-resistance
pull-up resistors. Each bit in an SRAM is stored on four transistors (M1, M2,
M3, and M4) that form two cross-coupled inverters. This storage cell has two
stable states which are used to denote 0 and 1. Two additional access
transistors serve to control the access to a storage cell during read and write
operations. In addition to this, other kinds of SRAM chips use
4T,5T,6T,7T,8T,9T and 10T or more transistors per bit.

2.3.1 Read Operation

Considering the case of reading Q=0; before reading a value from

the storage nodes, the bitline BL is pre-charged to VDD. The read wordline RL
is then asserted to VDD. The storage node QB that stores a 1 is statically
connected to the gate of MRA (Read Access Transistor) and will drain the
charges on the bitline through MRD to GND as the RL is 1, which means that
the bitline has just read a 0. On the contrary, when Q=1, QB will be 0 and
MRA will be in cutoff and the bitline BL will not be able to discharge through
MRD to GND, and it would read a 1.
 35

Figure 2.2 shows the 6T SRAM equivalent schematic diagram

during read operation. Bitlines are pre charged to supply voltage before read
operation. The read operation is initiated by enabling the word-line (WL) and
thereby connecting the internal nodes of the SRAM bitcell to bit-lines. The
bitline voltage is pulled down by the transistor at the ‘0’ storage node and the
difference between two bitline voltages will be detected by sense amplifier.
When the wordline (WL) is high, one of the bitline voltages is pulled down
through transistors M2 and M6 or M1 and M4. The transistors M2 and M6
forms a voltage divider, because of current flowing through M2, the potential
at node QB is no longer at ‘0’V. Also, it should not go beyond switching
threshold of inverter (INV1) to avoid destructive read. The rising of potential
depends on sizing of access transistor and pull down transistor, which is
defined as a bitcell ratio.

Figure 2.2 Memory read and write equivalent circuit

2.3.2 Write Operation

The word-line WL is charged to VDD as in 6T Standard SRAM.

Since NMOS is a stronger driver than PMOS, no problem is incurred while
writing a 0 into the cell. The absence of the pull down NMOS for memory
node, Q allows writing a 1 into the cell easily. Writing a 1 is done by
 36

pre-charging bit-line BL to VDD. While writing 0, the bit-line BL is

discharged and then word-line WL is charged to VDD as in 6T Standard
SRAM. The write operation begins by forcing a differential voltage (VDD and
0) at the bitline pairs (BLB and BL). This differential voltage corresponds to
the data to be written at the storage nodes (Q and QB) and it is controlled by
the write drivers. The WL is then activated to store the information from the
bit-line pairs to corresponding storage nodes. Assume the nodes Q and QB
initially store values ‘1’ and ‘0’ respectively. When the WL is asserted the
access transistor (M1) connected to BL (at ‘0’) is turned ON, a current flows
from VDD to BL through M3 and M1. This current flow lowers the potential at
Q. The potential at the node Q has to go below the trip point of the inverter
(INV2) for a successful write operation and this depends on the ratio of
pull-up transistor (M3) and the access transistor (M1). This ratio is referred to
as the pull-up ratio.

2.3.3 Hold Operation

If the cell content is a 1 (Q=VDD, QB=0), both memory nodes will

lock each other at their respective voltages. However, if the cell content is a 0
(Q=0, QB= VDD), Q is floating. Referring to Figure 2.2, the leakage current
through M5 must be greater than that of M2 to ensure Q stays at 0.
Fortunately, since NMOS (M5) is a stronger current driver than PMOS (M2),
this condition is satisfied. When WL goes low, SRAM bitcell data is in
retention mode. Two cross coupled inverters hold the data, through bistable
action. There is destruction in data stored when VDD goes below certain
voltage, which is called data retention voltage of SRAM bitcell. A standard
6T SRAM shows poor read stability as technology scale down to
nano-regime.

To increase the read stability (measured by read SNM)

conventional device sizing can be followed by increasing the bitcell ratio. By
 37

increasing the bitcell ratio, read SNM and critical charge (node capacitance)
will increase which are desirable. However, at the same time, power
consumption and write time increase, which are not desirable features, as they
incur loss of power, performance and increase in area overhead. When the
bitcell ratio increases, there is significant increase in write time, which will
affect the performance of SRAM bitcell.

2.4 SRAM OPERATION STATES

An SRAM cell has three different states. It can be in: standby (the
circuit is idle), reading (the data has been requested) and writing (updating the
contents). The SRAM to operate in read mode and write mode should have
"readability" and "write stability" respectively. The three different states work
as follows.

2.4.1 Standby State

If the wordline is not asserted, the access transistors M5 and M6

disconnect the cell from the bitlines. The two cross-coupled inverters formed
by M1 – M4 will continue to reinforce each other as long as they are
connected to the supply.

2.4.2 Reading State

Assume that the content of the memory is a 1, stored at Q. The read

cycle is started by pre-charging both the bitlines to a logical 1, then asserting
the wordline WL, enabling both the access transistors. The second step occurs
when the values stored in Q and QB are transferred to the bitlines by leaving
BL at its pre-charged value and discharging BLB through M1 and M5 to a
logical 0 (i.e. eventually discharging through the transistor M1 as it is turned
on because the Q is logically set to 1). On the BL side, the transistors M4 and
 38

M6 pull the bitline toward VDD, a logical 1 (i.e. eventually being charged by
the transistor M4 as it is turned on because Q is logically set to 0). If the
content of the memory was a 0, the opposite would happen and BL would be
pulled toward 1 and BL toward 0. Then, these BL and BLB will have a small
difference of delta between them and then these lines reach a sense amplifier,
which will sense the higher voltage line and thus will tell whether there was 1
stored or 0. The higher the sensitivity of sense amplifier, the faster the speed
of read operation.

2.4.3 Writing State

The start of a write cycle begins by applying the written value to

the bitlines. If we wish to write a 0, we would apply a 0 to the bitlines, i.e.
setting BL to 1 and BLB to 0. This is similar to applying a reset pulse to an
SR-latch, which causes the flip flop to change state. A 1 is written by
inverting the values of the bitlines. WL is then asserted and the value that is to
be stored is latched in. Note that the reason this works is that the bitline input
drivers are designed to be much stronger than the relatively weak transistors
in the cell itself, so that they can easily override the previous state of the
cross-coupled inverters. Careful sizing of the transistors in an SRAM cell is
needed to ensure proper operation.

2.5 OPERATION OF CONVENTIONAL 4T SRAM CELL

4T SRAM cell is the key SRAM component storing binary

information. A typical SRAM cell uses two PMOS and two NMOS transistors
forming a latch and access transistors. Access transistors enable access to the
cell during read and write operations and provide cell isolation during the
unaccessed state an SRAM cell is designed to provide non-destructive read
access, write capability and data storage (or data retention) for as long as cell
is powered. The conventional 4T-SRAM consists of both NMOS and PMOS.
 39

In general, the cell design must strike a balance between cell area,
robustness, speed, leakage and yield. Power reduction is one of the most
important design objectives. However, power cannot be reduced indefinitely
without compromising with other parameters like cell area and speed of
operation. The mainstream four-transistor (4T) CMOS SRAM cell is shown
in Figure 2.3, four transistors (M1 M4) comprise cross-coupled CMOS
inverters and two NMOS transistors M2 and M4 provide read and write
access to the cell.

Figure 2.3 Conventional 4T SRAM cell

2.6 DESIGN OF 5T SRAM CELL

In a normal 4T cell, both storage nodes are accessed through

NMOS pass-transistors. This is necessary for the writing of the cell, since
none of the internal cell nodes can be pulled up from a stored ’0’ by a high
ON the bitline. If this was not the case, an accidental write could occur, when
reading a stored ’0’ value. However, if the bitlines are not pre-charged to VDD
this is no longer true. With an intermediate precharge voltage, VPC, the cell
could be constructed so that a high ON the bitline would write a ’1’ into the
 40

cell, but a pre-charged bitline with a lower voltage would not. Also, a low ON
the bitline could write a ’0’ into the cell, whereas the intermediate precharge
voltage would not, thus giving the cell a precharge voltage window where
correct operation is assured. This would eliminate the need for two NMOS
transistors, since the cell now can be written both high and low from one side.
In turn, that would also result in one less bitline. From a high density point of
view, this is very attractive. Figure 2.4 shows the structure of the proposed
five-transistor (5T) SRAM cell.

Figure 2.4 Conventional 5T SRAM cell

With one less bitline, the 5T cell also shares a sense amplifier
between two cells. This further reduces the area giving the 5T memory block
an even greater advantage over the 6T SRAM. One version of a 5T SRAM
was presented (Tran 1996). That cell differs fundamentally from the cell
proposed in this thesis, in that the latch of the cell is disconnected from the
gnd supply to facilitate write. This requires an additional metal wire and also
destabilizes all cells on the bitline during write. The approach in this thesis is
 41

instead to mimic the behavior of the well proven 4T cell as close as possible,
while still reducing the area (Jarollahi & Hobson 2010).

2.7 DESIGN OF 6T SRAM CELL

A typical SRAM cell is made up of six MOSFETs. Each bit in an

SRAM is stored on four transistors (M1, M2, M3 and M4) that form two
cross-coupled inverters. This storage cell has two stable states which are used
to denote 0 and 1. Two additional access transistors serve to control the access
to a storage cell during read and write operations. In addition to such six-
transistor (6T) SRAM, other kinds of SRAM chips use 4T, 8T, 10T SRAMs
per bit. Conventional 6-Transistor (6T) cell, shown in Figure 2.5, uses a cross-
coupled inverter pair, which is the de facto memory bitcell used in the current
SRAM designs.6T cell mainly utilizes differential read operation. The
memory cell in SRAM consists of two static inverters that feed into each
other creating a latch. Access transistor logic is used for controlling the access
into the memory cell and the switching for the transistor logic is controlled by
wordlines (Gupta & Anis 2010).

By modulating the virtual-VDD and virtual-VSS of one of the

inverters, the write ability will be achieved. In all the existing bit cells,
configuration of the cross-coupled inverter pair plays a vital role. To decouple
the read and write operations, we need to add the extra transistors. None of
the existing bit cells incorporate process variation tolerance for improving the
stability of an SRAM bit cell. The stability of the cross-coupled inverter will
decide the SRAM operation under PVT variations. However, the bit cell
stability cannot be affected by the device sizing at very low supply voltage.
Due to its performance, this is most widely used in all types of processors,
FPGAs and other memory devices.
 42

Figure 2.5 Conventional 6T SRAM cell

2.8 DESIGN OF 7T SRAM CELL

7T bitcell consists of single-ended write operation and a separate

read port. The single-ended write operation in this 7T bitcell needs either
asymmetrical inverter characteristics or differential VSS and VDD bias. In the
proposed single-ended 7T bitcell, an extra transistor is added in the pull-down
path of one of the inverters. During the read mode, isolate the corresponding
storage node from VSS when the extra transistor is turned OFF. This gives
results in read-disturb-free operation shown in Figure 2.6. The feedback
between the two inverters is cut off during the write operation in differential
7T bitcell. The successful write operation in an inverter sizing produces
asymmetrical noise margins. The extra transistors, added to the conventional
6T bitcell to separate read and write operations, gives the single-ended 7T
bitcell.
 43

Figure 2.6 Conventional 7T SRAM Cell

2.9 CONVENTIONAL 8T SRAM CELL

Figure 2.7 shows the architecture of new 8T SRAM cell. It consists

of two extra transistors MN5 and MN6 as compared to conventional 6T
SRAM cell. Transistor MN5 is used to reduce gate leakage, while transistor
MN6 is used to make cell SNM free in the zero state.

Figure 2.7 Conventional 8T SRAM Cell design

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2.9.1 Operations of 8T SRAM Cell

Interestingly, transistor MN5 also helps in improving SNM when

cell holds logic ‘1’. The sign WLB is the complement of wordline (WL)
signal. The timing diagram for signal WL and WLB in read/write cycle and
standby mode is shown in Figure 2.8. In this work, the basic read/write
operations of 8T SRAM cell are preformed using single ended sense amplifier
which is described as follows.

Figure 2.8 Timing Diagram

2.9.2 Write Operation of 8T SRAM Cell

In write ‘0’ operation, the bitline BT is pulled down to logic ‘0’. As

soon as the signal WL rises from logic ‘0’ to logic ‘1’, transistor MNWL is
turned OFF. The node XT starts discharging which turns ON transistor MP2
causing cell to flip and logic ‘0’ is written into the cell. In write ‘1’ operation,
the bitline BL is pulled down to -Vt, where Vt is the threshold voltage of
transistor MN4. The node XB starts discharging which turns ON transistor
MP1. Once transistor MP1 is turned ON, the node XT is at logic ‘1’ and
hence logic ‘1’ is written into the cell. In read operation, the bitlines BL and
BLb are held at logic ‘1’ by the pre charged circuitry. In read ‘0’ operation,
the bitline BL starts discharging through transistors MN3 and MN1.
 45

Since the usage of SRAM cell is in cache memory, the single ended
8T SRAM circuitry is being used to store the required data. For generating a
memory, there is a requirement of Address decoder, Data Write Circuitry and
Data Read Operation. Since the proposed circuitry does not require pre charge
circuit, there is no elaboration of pre charge circuitry as in 6T SRAM Cell.
The memory has been designed for 32 bit storing capacity for the read and
write operations. At a time, 8 bits will be activated for read or write purpose.

The selection of wordline represents the selection of a particular

row. The data lines of the cells form the column of the memory matrix. For
read operation, the Read Bitline (RBL) is also included to form a separate
read column of the memory matrix. The data flow is thus visualized to be
vertical for both read and write operations. Once a wordline is driven high by
the row decoder, every cell in the row is accessible. 8T SRAM cell has the
normal 6T SRAM design with a read decoupled path consisting of two
NMOS transistors M5 & M6.

2.9.3 Read Operation of 8T SRAM Cell

Read operation of 8T SRAM is initiated by pre-charging the read

bitline to full swing voltage. After pre-charging read bitline, RWL is asserted
that drives access transistor MN5 ON. If Q=0, then MN6 is ON& RBL
discharges through transistors MN5 & MN6 to ground. This decrease in the
voltage of RBL is sensed by the sense amplifier. During read “1” operation,
when Q=1, MN6 remains OFF, so there will be no discharge current flow
through the read path. In this situation, only a very small amount of leakage
current flows, which is called bitline leakage. Write operation of 8T cell is
similar to 6T cell, but the pre-charge circuitry at the bitlines is replaced by
write driver.
 46

2.10 DESIGN OF 9T SRAM CELL

Standard 6T bitcell along with three extra transistors were

employed in nine-transistor (9T) SRAM bitcell, to bypass read-current from
the data storage nodes, as shown in Figure 2.9. This arrangement yields a non-
destructive read operation or SNM-free read stability. However, it leads to
extra area overhead and a complex layout. This cell layout structure does not
fit in this design and introduces jogs in the poly layer.
gnd

gnd
gnd

gnd

Figure 2.9 Conventional 9T SRAM cell

2.11 DESIGN OF 10T SRAM CELL

In the 10T bit cell, as shown in Figure 2.10, a separate read port
comprising of 4-transistors was used, while write access mechanism and basic
data storage unit are similar to the standard 6T bit cell. This bit cell also offers
the same benefits as the 8T bit cell, such as a non-destructive read operation
and ability to operate at ultra low voltages (Singh et al 2012). But the 8T bit
cell does not address the problem of read bitline leakage current, which
 47

degrades the ability to read data correctly. In particular, the problem with the
isolated read-port 8T cell is analogous to that with the standard (non-isolated
read-port) 6T bit cell. The only difference here is that the leakage currents
from the unaccessed bit cells sharing the same read bit-line, RBL, affect the
same node as the read-current from the accessed bit cell. As a result, the
aggregated leakage current, which depends on the data stored in all the
unaccessed bit cells, can pull-down RBL even if the accessed bit cell based on
its stored value should not do so. This problem is referred as an erroneous
read. The erroneous read problem caused by the bitline leakage current from
the unaccessed bit cells is managed by this 10T bit cell by providing two extra
transistors in the read-port. These additional transistors help to cut-off the
leakage current path from RBL, when RWL is low and makes it independent
of the data storage nodes content.

Figure 2.10 Conventional 10T SRAM cell

 48

2.12 SIMULATION RESULTS

Figure 2.11 shows the design of 4T SRAM using EDA tool. The
4 transistors has equal W/L ratio and 2 transistors connected to wordline and
2 transistors are connected to bitline to increase the speed of operation.
Figure 2.12 shows the 5T SRAM cell design at room temperature. In this
connection, 2 transistors for wordline and 2 transistors for bitline and
additional one transistor is connected to bitline to increase the speed of
operation and also to reduce the total power consumption.

Figure 2.13 gives an idea about simulation of 6T SRAM circuit and

its structure at room temperature condition. From the simulation, it is proved
that slight modifications occurs in read state for a 6T SRAM cell. Figure 2.14
and Figure 2.15 show the design of 7T SRAM and 8T SRAM cell with EDA
tool. Figure 2.16 and Figure 2.17 show the design of 9T and 10T SRAM cell
using 180 nm CMOS technology.

Figure 2.11 Simulation of 4T SRAM cell

 49

Figure 2.12 Simulation of 5T SRAM cell

Figure 2.13 Simulation of 6T SRAM cell

 50

Figure 2.14 Simulation of 7T SRAM cell

Figure 2.15 Simulation of 8T SRAM cell

 51

Figure 2.16 Simulation of 9T SRAM cell

Figure 2.17 Simulation of 10T SRAM cell

 52

Figure 2.18 shows the characteristics of 4T SRAM, which shows

the relationship between voltage and time for read and write operation.
Normally, standby mode is not used in practical applications of any memory
devices. So, this work concentrates on write state and read state alone.

Figure 2.19 depicts the simulation of 5T SRAM cell with its input
voltage and output voltage with respect to time. The speed of response is high
compared to conventional 4T SRAM cell.

Module
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)

Figure 2.18 Output Waveform of 4T SRAM Cell

 53

Module
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)

Figure 2.19 Output Waveform of 5T SRAM cell

Figure 2.20 and Figure 2.21 show the response of 6T and 7T

SRAM cell. It is observed that the responses are equal, but the changes given
to conventional 6T output voltage is due to some transient delay present in the
design itself.
 54

Module
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)

Figure 2.20 Output waveform of 6T SRAM Cell

The characteristics of 8T SRAM cell is slightly modified because it

consists of more number of transistors so the speed of operation increases. It
is proved in Figure 2.22.

Similarly the output waveforms of 9T and 10T SRAM cell are

obtained and that should be shown in Figure 2.23 and 2.24.All the simulations
shows that the relationship betweent input voltage,output voltage Vs time for
only three modules in case 9T and 10T SRAM shows four module.
 55

Module

Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)

Figure 2.21 Output waveform of 7T SRAM cell

The performance of the SRAM cell is degraded, when more

number of transistors are included in the design with various temperature
conditions. The quantitative comparison of various powers like static,
dynamic (maximum and minimum) and total power consumption of all
SRAM cell are presented in Table 2.1 and Table 2.2, which show the power
calculations for all circuits with various temperature conditions.
 56

Module
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)

Figure 2.22 Output Waveform of 8T SRAM cell

In Table 2.2, only 4T,6T,8T and 10T circuits are considered for
power and delay calculations, because for a perfect power reduction in any
SRAM cell design includes one transistor in wordline and one transistor in
bitline. That is the reason only a selected SRAM cell is designed. Table 2.3
shows same 10T SRAM cell with various configurations.
 57

Module
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Figure 2.23 Output waveform of 9T SRAM cell

 58

Module
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)
Voltage (V)

Time (sec)

Figure 2.24 Output Waveform for 10T SRAM cell design

 59

Table 2.1 Power Calculations of various SRAM cells

No. of Static Power Dynamic Power Average power

S.No.
transistors (watts) (watts) (watts)
1 4T 0.2470 0.0245 11.3494
2 5T 0.0884 0.0720 10.1419
3 6T 0.2538 0.3842 13.766
4 7T 0.2539 0.8785 11.654
5 8T 0.2999 0.6119 11.377
6 9T 0.0656 0.0216 1.1049
7 10T 0.0351 0.0764 1.6739

Table 2.2 Power Calculations of 4T,6T,8T and 10T SRAM cell with
various temperature conditions

Type of Temperature Static Power Dynamic Power Average Power

Circuit (°C) (watts) (watts) (watts)
25 0.0470 0.0245 1.3494
50 0.0745 0.0252 4.0706
4T 75 0.0765 0.0321 4.1630
100 0.2488 0.1006 10.5854
25 0.0824 0.0720 0.1419
50 0.0886 0.1256 1.1463
6T
75 0.0959 0.1596 5.1516
100 0.0901 0.7274 6.1563
25 0.2538 0.0843 10.7660
50 0.2770 0.1468 7.2018
8T
75 0.5324 0.2252 12.8209
100 0.6206 0.2963 13.3411
25 0.0206 0.1060 6.9180
50 0.0220 0.2121 9.0040
10T
75 0.0460 0.2860 10.3360
100 0.0790 0.4560 11.3690
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Table 2.3 Power Calculations of 10T SRAM cell with various

configurations

Static Power Dynamic Power Average

S.No Cell Structure
(watts) (watts) Power (watts)
1 Differential design 0.0352 0.0765 1.6739
2 Single ended normal
0.1324 0.0608 4.5022
design
3 Transmission gate
0.1367 0.0982 4.1806
design
4 Single ended (Kim)
0.1537 0.0274 4.5022
design
5 Single Ended
0.1489 0.0147 4.5022
(Calhoun) design

2.13 SUMMARY

In this chapter, the simulation circuits and waveforms show that

the proposed 10T SRAM cell design cell dissipates lesser power at different
bitcell design and better stability than the other existing SRAM cells.
Although transistor count and area are increased in comparison to those of
other SRAM cells, total low power dissipation and supply voltage variation
can easily dominate over this drawback. Supply voltage scaling has
significant impact on the overall power dissipation. With the supply voltage
reduction, the dynamic power reduces quadratically. However, as the supply
voltage is reduced, the sensitivity of circuit parameters, especially
temperature, to process variations increase. Lowering the supply voltage is an
effective way to achieve ultra-low-power operation. In this work, we have
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evaluated different types of SRAM bit cells using 4T,5T,6T,7T,8T,9T and

10T for ultra-low voltage applications. The conventional SRAM cell
consumes 98% power, while 8T consumes 97% power and 10T consumes
88% power in room temperature. The proposed 10T SRAM cell can be
designed with several benchmark configurations and that provides low power
solution in high speed devices and achieving low voltage and low power
operation.