A study of the Alpha 21364 Processor

Arul Prakash
CS6810: Advanced Computer Architecture
Table of Contents
1 Introduction .............................................................................................................3
2 History ....................................................................................................................3
3 21264 Instruction Set Architecture...........................................................................3
3.1 Registers ..........................................................................................................3
3.2 Data Types.......................................................................................................3
3.3 Addressing Modes ...........................................................................................4
3.4 Instruction format: ...........................................................................................4
3.5 Instruction Set:.................................................................................................5
4 Alpha 21364 micro-architecture...............................................................................5
4.1 21364 Pipeline .................................................................................................6
4.1.1 Fetch: .......................................................................................................6
4.1.2 Register Renaming ...................................................................................7
4.1.3 Instruction Issue .......................................................................................7
4.1.4 Register Read ...........................................................................................7
4.1.5 Execute ....................................................................................................7
4.1.6 Memory ...................................................................................................8
4.2 21364 Memory System: ...................................................................................8
4.3 Integrated Memory Controller:.........................................................................9
4.4 Integrated Network Interface............................................................................9
5 Memory Management..............................................................................................9
5.1 Address Tranlation...........................................................................................9
6 I/O System.............................................................................................................10
7 Analysis.................................................................................................................10
7.1 Strengths........................................................................................................10
7.2 Weaknesses....................................................................................................12
8 Conclusion ............................................................................................................12
9 References .............................................................................................................12
 around 500,000 alpha based servers were sold till
1 Introduction 2000. Due to the low market demand, the prices
My interest in the Alpha processor was sparked of Alpha based systems have been high resulting
when I came across the following sentence: in a cycle.
“Where Intelx86 is CISC to the extreme, Alpha
is RISC to the extreme.” DEC was acquired by Compaq in 1998, which
Curious on what ‘extreme RISC’ meant, I started was later purchased HP in 2002. In October
collecting information on the Alpha 21364 2002, HP announced that in 2004 the line would
processor and present my findings in this paper. see its final upgrade to the faster EV79
I was not aware at that time that development on processor, and then advancements in the
the Alpha processor has ceased, but my feeling is platform would cease in favor of Intel Itanium-
that it is more because of the DEC’s lack of based servers. Ironically, even though the Alpha
enough infrastructure and marketing skills to processor is about to be phased out, 4 of alpha
compete with Intel than any architectural flaw. servers were ranked 2nd, 12th, 15th and 32nd in the
The paper is organized as follows. In Section 2, I latest Top500 list.
describe a brief history of the processor. Section
3 describes the ISA of the processor. Section 4
talks about the Alpha 21364 processor. Section 5 3 21264 Instruction Set
deals with the memory system and Section 6 Architecture
describes the I/O system. Finally in section 7, I
The Alpha 21264 ISA is 64 bit load-store RISC
describe the strengths and weaknesses of the
architecture. All instructions are 32 bits in
architecture.
length. Memory operations are either loads or
stores. All data manipulation is done between
registers.
2 History
Digital Equipment Corporation (DEC) had been 3.1 Registers
dominating the minicomputer marked during the
The Program Counter (PC) is a 64 bit register
80s with their PDP11 and VAX. By the late 90s
that keeps track of the next instruction to be
the VAX was becoming untenable and it was
executed. The PC uses bits <63, 2> with bits <1,
very difficult to implement using advanced
0> treated as RAZ/IGN.
pipelined or superscalar techniques. In an
There are 32 64 bit integer (R0, …R31) and
attempt to regain their dominance, they
floating point (F0, …F31) registers each. The
developed the MicroVAX in which they
registers R31 and F31 always contain 0 when
included a subset of the VAX instructions and
specified as a source operand.
data types. The first alpha processor (Alpha
There are 2 lock registers associated with the
21064) was introduced in 1992, and was the
load and store instructions, the lock flag and the
most powerful microprocessor available at that
locked_physical_addres register.
time. The alpha (RISC based) was a significant
In addition, the Alpha contains a PCC (Processor
departure from the VAX architecture (CISC
Cycle Counter), a few memory prefetch registers
based).
and a VAX compatibility register.
The alpha processors are named 21x64EVx. The
21 stands for the 21st century. The 64 indicates 3.2 Data Types
that it is 64 bit architecture. EV stands for The following are the Alpha architecture data
extended VAX (though it was significantly types:
different from the VAX). The two xs stand Byte: A byte is an 8 bit value. It is supported by
represent the generation of the processor and the the load, store, sign-extend, extract, mask, insert,
bus respectively. and zap instructions only.
Word: A word is 2 contiguous bytes starting on
Unfortunately, Alpha did not have the an arbitrary byte boundary. The word is only
infrastructure to compete with the production supported in Alpha by the load, store, sign-
cycles that Intel and later AMD had. Samsung, extend, extract, mask, and insert instructions.
the main Alpha licensee, did not have the Longword: A word is 4 contiguous bytes
resources to mass produce them. Hence, the starting on an arbitrary byte boundary. When
alpha processor never got very popular and only interpreted arithmetically, a longword is a two’s-
complement integer with bits of increasing IEEE T_floating
significance from 0 through 30. Bit 31 is the sign An IEEE double-precision, or T_floating, datum
bit. The longword is only supported in Alpha by occupies 8 contiguous bytes in memory starting
sign-extended load and store instructions and by on an arbitrary byte boundary. The form of a
longword arithmetic instructions. T_floating datum is sign magnitude with bit 63
Quadword: A quadword is 4 contiguous bytes the sign bit, bits <62:52> an excess-1023 binary
starting on an arbitrary byte boundary. When exponent, and bits <51:0> a 52-bit fraction.
interpreted arithmetically, a quadword is either a IEEE X_floating
two’s-complement integer with bits of increasing An IEEE extended-precision, or X_floating,
significance from 0 through 62 and bit 63 as the datum occupies 16 contiguous bytes in memory.
sign bit, or an unsigned integer with bits of The form of an X_floating datum is sign
increasing significance from 0 through 63. magnitude with bit 127 the sign bit, bits
<126:112> an excess–16383 binary exponent,
The floating point formats are: and bits <111:0> a 112-bit fraction.
VAX F_Floating: An F_floating datum is 4
contiguous bytes in memory starting on an There are a few more data types that are not
arbitrary byte boundary. The F_floating load directly supported by the hardware:
instruction reorders bits on the way in from • Octaword
memory, expands the exponent from 8 to 11 bits, • H_floating
and sets the low-order fraction bits to zero. This • D_floating
produces in the register an equivalent G_floating • Variable-Length Bit Field
number suitable for either F_floating or • Character String
G_floating operations. • Trailing Numeric String
VAX G_floating: A G_floating datum in The data types can either be little-endian byte
memory is 8 contiguous bytes starting on an addressing or big-endian addressing, though the
arbitrary byte boundary. The former is generally preferred.
form of a G_floating datum is sign magnitude
with bit 15 the sign bit, bits <14:4> an excess-
1024 binary exponent, and bits <3:0> and
<63:16> a normalized 53-bit fraction with the 3.3 Addressing Modes
redundant most significant fraction bit not The Alpha architecture provides only one
represented. Within the fraction, bits of addressing mode – displacement. Register
increasing significance are from 48 through 63, deferred is accomplished by using 0 in the base
32 through 47, 16 through 31, and 0 through 3. register.
The 11-bit exponent field encodes the values 0
through 2047. An exponent value of 0, together 3.4 Instruction format:
with a sign bit of 0, is taken to indicate that the There are five basic instruction formats –
G_floating datum has a value of 0. memory, branch, operate, floating point operate
VAX D_floating: A D_floating datum in and PAL code. All instruction formats are 32 bits
memory is 8 contiguous bytes starting on an long with a 6-bit major opcode filed in bits
arbitrary byte boundary. The memory form of a <31:26> of the instruction.
D_floating datum is identical to an F_floating Memory Instruction Format:
datum except for 32 additional low significance
fraction bits. Within the fraction, bits of
increasing significance are from 48 through 63,
32 through 47, 16 through 31, and 0 through 6.
IEEE S_floating: An IEEE single-precision, or
Ra is the destination/origin and Rb indicates an
S_floating, datum occupies 4 contiguous bytes in
address with a displacement offset indicated in
memory starting on an arbitrary byte boundary.
the displacement field.
The S_floating load instruction reorders bits on
Memory format instructions with a function code
the way in from memory, expanding the
replace the memory displacement field in the
exponent from 8 to 11 bits, and sets the low-
memory instruction format with a function code
order fraction bits to zero. This produces in the
that designates a set of miscellaneous
register an equivalent T_floating number,
suitable for either S_floating or T_floating
operations.
instructions as shown in the figure below: • Logical and shift
• Byte manipulation
• Floating point load and store
• Floating point control
• Floating point branch
Branch Instruction Format: • Floating point operate
• Miscellaneous
• VAX compatibility
• Multimedia(graphics and video)

Ra is a 5 bit register address field, and the 4 Alpha 21364 micro-architecture

displacement field is 21 bits wide.
Operate Instruction Format: The 21364 is a superscalar microprocessor that
can fetch and execute up to four instructions per
cycle. It also features out-of-order execution and
employs speculative execution to maximize
performance.
An Operate format instruction contains a 6-bit
opcode field and a 7-bit function code field. Ra
specifies a source operand. Rb can specify a
source operand or a literal in case of integer
operands. Rc specifies the destination operand.
Floating Point Operation Format:

It contains a 6 bit opcode and a 11 bit function

field. Fa and Fb are source registers and Fc is
destination register.
PALcode Instruction Format:
Figure 1: Alpha 21364 internal distribution

A block diagram of the processor is show below:

The Privileged Architecture Library (PALcode)

format is used to specify extended processor
functions. The 26-bit PALcode function field
specifies the operation. The source and
destination operands for PALcode instructions
are supplied in fixed registers that are specified
in the individual instruction descriptions.
An opcode of zero and a PALcode function of
zero specify the HALT instruction.

3.5 Instruction Set:

The instruction set is divided into the following
sections:
• Integer load and store
• Integer control The main components are:
• Integer arithmetic • Instruction fetch, issue, and retire unit
(IBOX) :
• Integer execution unit (EBOX) choices allowed by two-way associative cache)
• Floating point execution unit (FBOX) should be used. These predictors are loaded on
• On chip caches (Icache and Dcache) cache fill and dynamically re-trained when they
• Memory reference unit (MBOX) are in error. The mispredict cost is typically a
• External cache and system interface unit single-cycle bubble to re-fetch the needed data as
(CBOX) shown in Figure 2.
Branch Prediction: The 21264 implements a
sophisticated tournament branch prediction
scheme. The scheme dynamically chooses
4.1 21364 Pipeline between two types of branch predictors—one
The basic 21364 pipeline has 7 stages as shown using local history, and one using global
in the figure below. In this section, I describe history—to predict the direction of a given
each of these stages in more detail.

4.1.1 Fetch: branch. Together, local and global correlation

techniques minimize branch mispredicts.
The fetch stage delivers four instructions to the
out-of-order execution engine each cycle. The
processor speculatively fetches through line,
branch, and jump predictions. Two architectural
techniques increase fetch efficiency: line and
way prediction, and branch prediction. A 64-
Kbyte, two-way set-associative instruction cache
offers much improved level-one hit rates.
Line and set prediction
The 21264 instruction cache implements two-
way associatively via a line and set prediction
technique that combines the speed advantage of a
direct-mapped cache with the lower miss ratio of Figure 2: Alpha 21364 instruction fetch
a two-way set-associative cache. Each fetch The processor adapts to dynamically choose the
block of four instructions includes a line and set best method for each branch. Figure 3 shows the
prediction. This prediction indicates from where local history prediction path—through a two-
to fetch the next block of four instructions, level structure—on the left. The first level holds
including which set (i.e., which of the two 10 bits of branch pattern history for up to 1,024
branches. This 10-bit pattern picks from one of 4.1.3 Instruction Issue
1,024 prediction counters. The global predictor is The instructions from the queues are issued at
a 4,096-entry table of 2-bit saturating counters this stage. The integer queue issues four
indexed by the path, or global, history of the last instructions per cycle and the floating point one
12 branches. The choice prediction, or chooser, issue two. Issued instructions remain two more
is also a 4,096-entry table of 2-bit prediction cycles in the queues.
counters indexed by the path history. There are two instruction queues that issue
instruction - a 20-entry integer and a 15-entry
floating point. Each cycle the issue logic selects
from the queued instructions when all their
operands become available using register
scoreboards.

Figure 4: Block diagram of the 21264 4.1.4 Register Read

tournament branch predictor. The local history
The issued instructions read the necessary
prediction path is on the left; the global history
registers and receive bypassed data.
prediction path and the chooser (choice
prediction) are on the right.
4.1.5 Execute
The accuracy of these predictors on most The integer instructions are sent to the EBOX
applications is in the range of 90-100%. and the floating point instructions are sent to the
FBOX pipeline. Figure 5 shows the four integer
execution pipes (upper and lower for each of a
4.1.2 Register Renaming left and right cluster) and the two floating-point
pipes in the 21264, together with the functional
Register renaming exploits application
units in each.
instruction parallelism since it eliminates
unnecessary dependencies (WAW and WAR)
and allows speculative execution. It also
preserves all RAW dependencies that are needed
for correct computation. Register renaming
assigns a unique storage location with each
write-reference to a register. The 21264
speculatively allocates a register to each
instruction with a register result.

Figure 5: Four integer execution pipelines and

two floating point pipes together with the
functional units in each
Figure 4: Block diagram of the register rename The integer register file is split into two clusters
stage that contain duplicates of the 80-entry register
41 integer and 41 floating-point registers are file. Two pipes access a single register file to
available to hold speculative results prior to form a cluster, and the two clusters combine to
instruction retirement. The register mapper stores support four-way integer instruction execution.
the register map state for each in-flight This clustering makes the design simpler and
instruction so that the machine architectural state faster, although it costs an extra cycle of latency
can be restored in case a mis-speculation occurs. to broadcast results from an integer cluster to the
Also, an ID number is added to each instruction other cluster.
during this stage.
4.1.6 Memory
Memory reference instructions access the
Dcache and data translation buffers. Store data is
written to the store queue where is held until the
instruction retires.

Instruction retire and exception handling

Although instructions issue out of order,
instructions are fetched and retired in order. The
in-order retire mechanism maintains the illusion
of in-order execution to the programmer even
though the instructions actually execute out of
order. The retire mechanism assigns each
mapped instruction a slot in a circular in-flight
window (in fetch order). After an instruction
starts executing, it can retire whenever all Figure 6: Organization of data cache
previous instructions have retired and it is The L2 cache is six-way set associative with a
guaranteed to generate no exceptions. The size of 1.75MB. It has 16 GB bandwidth.
retiring of an instruction makes the instruction The victim cache for L1 cache has 16 entries and
nonspeculative. The 21264 implements a precise that for L2 cache has 32 entries.
exception model using inorder retiring. The 21264 memory core logics up to 32 in-flight
loads, 32 in-flight stores, 8 in-flight (64-byte)
The retire mechanism also tracks the internal cache block fills, and 8 cache victims. This
register usage for all in-flight instructions. An allows a high degree of parallel memory system
exception causes all younger instructions in the activity to the cache and system interface. It
in-flight window to be squashed. These translates into high memory system performance,
instructions are removed from all queues in the even with many cache misses.
system. The register map is backed up to the The data path for the system is in Figure 7. Here
state before the last squashed instruction using we can see that the system also includes a
the saved map state. The retire mechanism has a speculative store data buffer. A store first writes
large, 80-instruction in-flight window. This into this buffer. The written data stays
means that up to 80 instructions can be in partial speculative until the store retires. Once this
states of completion at any time, allowing for happens the data is dumped into the DCache.
significant execution concurrency and latency
hiding.

4.2 21364 Memory System:

The memory system in the 21264 is high-

bandwidth, supporting many in-flight memory
references and out-of-order operation. It receives
up to two memory operations (loads or stores)
Figure 7: The 21364’s internal memory system
from the integer execution pipes every cycle.
data paths.
This means that the on-chip 64 KB two-way set-
The 21364 memory system supports the full
associative data cache is referenced twice every
capabilities of the out-of-order execution core,
cycle, delivering 16 bytes every cycle.
yet maintains an in-order architectural memory
The L1 cache contains 64k bytes of data in 64-
model.
byte blocks with 2-way set associative
The 21364 provides cache prefetch instructions
placement, write back, and write allocate on a
that allow the compiler and/or assembly
write miss. The data cache of the 21364 is show
programmer to take full advantage of the
in Figure 6.
parallelism and high-bandwidth capabilities of
the memory system. These prefetches are
particularly useful in applications that have loops
that reference large arrays.
4.3 Integrated Memory Controller: 6.4 GB/s bandwidth. Each network router
provides buffer space for over 300 packets.
While previous processor generations were
relying on an external support logic chip set for
controlling the computer's memory, 21364 5 Memory Management
integrates two 800 MHz Direct RAMbus The Alpha architecture uses a combination of
controllers onto the die. Each controller connects segmentation and paging, providing protection
to 4 RDRAM channels. Integration of the while minimizing page table size.
memory controllers onto the processor die boosts Virtual Address: The Alpha 21364 uses a 64 bit
the memory bandwidth to 12.8 GB/s and a 30 ns virtual address. The virtual address consists of
access latency for open memory pages. three level-number fields and a
byte_within_page field, as shown in Figure

4.4 Integrated Network Interface

The Alpha 21364 processor provides a high- The byte_within_page field can be either 13, 14,
performance, highly scalable and highly reliable 15, or 16 bits depending on a particular
network architecture. The router runs at 1.2GHz implementation. Thus, the allowable page sizes
and routes packets at a peak bandwidth of 22.4 are 8K bytes, 16K bytes, 32K bytes, and 64
GB/s. The network architecture scales up to a Kbytes.
128-processor configuration, which can support Physical Address: Physical addresses are at
up to four terabytes of distributed RAMbus most 48 bits. The two most significant
memory and hundreds of terabytes of disk implemented physical address bits delineate the
storage. The distributed RAMbus memory is four regions in the physical address space.
kept coherent via a scalable, directory-based, Implementations use these bits as appropriate for
cache coherence scheme. The network their systems.
architecture of the Alpha 21364 is shown in Page Table Entries: The processor uses a
Figure 8. quadword Page Table Entry (PTE), as shown in
Figure to translate virtual addresses to physical
addresses. A PTE contains hardware and
software control information and the physical
Page Frame Number.

I am not explaining all the fields of the PTE

since they can easily be looked up in the manual.
There are four processor modes – kernel,
executive, supervisor and user mode.

Figure 8: Alpha 21364 network architecture 5.1 Address Tranlation

In order to make it easy to build large Physical address translation is performed by
multiprocessor systems, 21364 contains an on- accessing entries in a multilevel page table
chip interface and router for a direct processor- structure. The Page Table Base Register (PTBR)
to-processor interconnect. The interface consists contains the physical Page Frame Number (PFN)
of 4 32-bit ports with 6.4 GB/s bandwidth each
of the highest-level page table.
and a 15 ns processor-to-processor latency. The
Level1 is the highest-level page table. Bits
interconnect forms a 2-D torus network that
<Level1> of the virtual address are used to index
supports deadlock free adaptive routing in into the Level1 page table to obtain the physical
the integrated interface. The network PFN of the base of the next level (Level2) page
interface autonomously handles all protocol table. Bits <Level2> of the virtual address are
transactions necessary to build a cache-coherent used to index into the Level2 page table to obtain
nun-uniform memory access (ccNUMA) shared the physical PFN of the base of the next level
memory multi-processor (SMP) system. An (Level3) page table. Bits <Level3> of the virtual
additional 5th port on the processor provides a address are used to index into the Level3 page
similar interface to support an I/O channel with table to obtain the physical PFN of the page
being referenced. The PFN is concatenated with
virtual address bits <byte_within_page> to between PMI and I/O bus addresses and access
obtain the physical address of the location being to I/O bus operations.
accessed as shown in figure.

Fig 10: I/O System

Alpha I/O operations include:
• Accesses between the processor and an I/O
device across the PMI
• Accesses between the processor and an I/O
device across an I/O bus
• DMA accesses — I/O devices initiating
reads and writes to memory
Figure 9: Virtual address mapping • Processor interrupts requested by devices
In order to save actual memory references when • Bus-specific I/O accesses
repeatedly referencing the same pages, hardware
implementations include a translation buffer to
remember successful virtual address translations
and page states.
7 Analysis
The overall picture of the Alpha 21364 memory After studying the Alpha 21364 processor in
hierarchy is shown in figure .I am not including a some detail, I feel that it is very unfortunate that
full description of the address translation. any future development of the Alpha processor
Interested readers can read about in the computer has been stopped. Alpha microprocessors have
architecture book by Hennessy and Patterson. consistently outperformed their contemporary
processors in Spec benchmarks by a huge factor
The reduced page table (RPT) mode is an since their introduction in 1992. The reason for
optional extension of 64KB page size mode. A the failure of the Alpha series is DEC’s lack of
portion of the address space is mapped by one enough infrastructure and marketing skills.
fewer page table levels, allowing each of the Another reason for its failure is the outrageously
entries in the lowest-level page table to map a high prices of these processors resulting in a low
512MB page. In implementations that support market demand. This has become a cycle where
granularity hints in hardware, applications can the low demand has kept the price high.
use these hints to make more efficient use of the
translation buffer. In this section I try to analyze the strengths and
weaknesses of the processor:

6 I/O System 7.1 Strengths

Conceptually, Alpha systems consists of • Alpha was designed to have a life span of 25
processors, memory, a processor-memory years and was the first 64 bit ISA. Hence it
interconnect (PMI), I/O buses, bridges, and I/O used the latest ideas of the time and is easily
devices. As shown in Figure 10, processors, extendible. The good thing was that the
memory, and possibly I/O devices, are connected Alpha line of processors was totally
by a PMI. different from DEC’s previous VAX
A bridge connects an I/O bus to the system, architecture. This gave the designers lot of
either directly to the PMI or through another I/O freedom to design a better architecture
bus. The I/O bus address space is available to the unlike some of the other big companies
processor either directly or indirectly. Indirect which carry around flaws in their
access is provided through either an I/O mailbox architecture down many generations.
or an I/O mapping mechanism. The I/O mapping • High clock speeds. The first Alpha chip
mechanism includes provisions for mapping shipped in 1992, ran at a record-breaking
200MHz. Alpha was also the first mass-
 produced chip to reach a clock speed of registers. It uses a Tomasulo type approach
1GHz in 1999. for dynamic scheduling.
• It is RISC to the extreme. All the • Because Alpha does segmented paging,
instructions are very simple. No instruction providing protection is easier.
takes more than a few clock cycles leading • Extremely fast front and back side buses.
fewer stalls in the pipeline. • Highly scalable and fast microprocessor
• Employs cutting edge technology including systems. This is achieved by what is called
out-of-order, speculative and superscalar “system on a chip” design. The chip has an
execution, high memory bandwidth, large integrated L2 Cache, integrated memory
memory support and high clock speed for controller and an integrated network
high performance. interface. The integrated L2 cache and
• A number of Alpha instructions include memory controller result in outstanding
hints for implementations, all aimed at single processor performance. The
achieving higher speed. Calculated jump integrated network interface results in highly
instructions have a target hint that can allow scalable, high performance multi-processor
much faster subroutine calls and returns. systems.
There are prefetching hints for the memory • Uses SMT for maximum utilization of
system that can allow much higher cache hit function units by independent operations.
rates. There are granularity hints for the They do this by replicating resources like
virtual-address mapping that can allow program counters and increasing size of
much more effective use of translation shared resources like instruction queue, L1
lookaside buffers for large contiguous and L2 cache, TLB etc.
structures. • The Alpha series of processors maintain full
• PALcode implements some necessary low- binary compatibility with earlier Alpha
level hardware support functions, which are processors.
too complex, too costly, or otherwise • Though I have not described the Alpha’s
impractical to implement directly in the floating point performance in this report, it
microprocessor chip’s hardware, and which has been reported in many places that the
cannot be handled by normal operating Alpha’s floating point performance is
system software, including power-up excellent.
initialization, memory management control, In 1999, the Alpha 21264 @ 700 MHz had
interrupt and exception dispatching. It thus scores of 39 and 68 on SPECINT95 and
allows designers to create their own code to SPECFP95, while the comparable Intel Pentium
support their Alpha microprocessor system III @ 733MHz had scores of only 36 and 30.
designs. The use of PALcode eliminates the Alpha’s floating point performance is far
need for micro code. superior. The graphs below show the superior
• Extremely big on-processor cache. It has performance of the Alpha processor on both
128K L1 cache and an unbelievably huge SPECINT95 and SPECFP95benchmarks.
1.75MB on-chip L2 cache.
• Separate instruction and data cache: Having
separate instruction and data cache result in
a lower miss rate.
• Highly accurate line, way and branch
predictors. This helps keep the pipeline 50-
75% full at all times without any compiler
optimizations.
• The Alpha processor aggressively prefetches
instructions to keep the pipeline full at all
times.
• Highly parallel execution – The Alpha Fig 10: Specint95 benchmark
processor is able to keep its pipeline full
because of aggressive instruction fetch and
accurate branch prediction. It is able to
support 80 in flight instructions using a
number of pipelined execution units and
 8 Conclusion
The Alpha Architecture is an excellent example
of a high performance architecture using many
advanced techniques like out of order and
speculative execution, high clock speeds and
high bandwidth memory system. It is also a
classic example of a superior architecture loosing
out to competition.

9 References
1. John L Hennessy, David A Patterson,
Fig 11: Specfp95 benchmark Computer Architecture: A Quantitative
Approach.
7.2 Weaknesses 2. Alpha Architecture Reference Manual,
• Very expensive. This is partly because of the Fourth Edition
huge on-chip L2 cache and partly because of 3. 21264/EV68A Microprocessor Hardware
DEC’s inability to mass-produce the Reference Manual.
processor like Intel. 4. Thomas Daniels, Dharmesh Parikh, Matt
• DEC’s first Alpha was a big deviation from Ziegler, The Alpha 21264 ISA.
their previous VAX architecture. Even 5. Artur Klauser, Trends in High-Performance
though DEC management assured its Microprocessor Design
customers of an upgrade path, it lost a huge 6. Zarka Cvetanovic and R.E. Kessler,
customer base because of this radical Performance Analysis of the Alpha 21264
change. based compaq ES40 system.
• Some essential instructions have been left 7. Linley Gwennap, Digital 21264 Sets New
out because it took more than a certain Standard, Microprocessor Forum, Vol 10,
number of clock cycles. Sometimes, the No. 14
series of simpler instructions took 2x as long 8. PALcode for Alpha Microprocessors,
to execute as the single complex instruction. System Design Guide, May 1996
• Larger binary code because of the extreme 9. Shubhendu S. Mukherjee, Peter Bannon,
RISC approach. Some results show that the Steven Lang, Aaron Spink, and David
series of simpler instructions are 50-100% Webb, The Alpha 21364 Network
larger than x86. Architecture
10. http://www.alphaprocessors.com
• The 64 bit architecture was way ahead of its
11. http://www3.sympatico.ca/n.rieck/links/dec_
time. This was at a time when there were no
memorial_site.html
64-bit compilers and other tools. This was
12. http://web.singnet.com.sg/~duane/b1000005
one of the reasons why the Alpha
.htm
architecture did not become very popular.
13. http://h18020.www1.hp.com/alphaserver/per
However, the OpenVMS system became
formance/spec2000.html
very popular later.
14. http://www.macspeedzone.com/archive/4.0/
• The line and way predictors add to the
WinvsMacSPECint.html
complexity of the processor. An additional
15. http://www.extremetech.com/article2/0,3973
cycle is added to the load latency. However, ,1158263,00.asp
the overall performance seems to improve
16. http://www.macinfo.de/hardware/chips-
because of the highly accurate prediction.
top.html (Translated from german)
• The Alpha processor has a very aggressive
speculation approach because of its highly
accurate predictors. The penalty of a
wrongly taken branch is quite high in some
cases.
• I do not have the current feature size, but
because of DEC’s lack of infrastructure, the
Alpha was using a 0.35µm feature size when
Intel and AMD were on 0.25µm feature size.