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NOC Issues and Challenges

There are several issues related to network-on-chip (NOC) design, including whether to use serial or parallel links, how to optimize interconnects, and how to reduce leakage power consumption. Router architecture involves tradeoffs between performance and cost/power. Providing quality of service (QoS) for real-time applications while managing latency, cost and power consumption is also a challenge. Components of the NOC such as network interfaces and routers can significantly increase chip area, cost and power consumption.

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287 views

NOC Issues and Challenges

There are several issues related to network-on-chip (NOC) design, including whether to use serial or parallel links, how to optimize interconnects, and how to reduce leakage power consumption. Router architecture involves tradeoffs between performance and cost/power. Providing quality of service (QoS) for real-time applications while managing latency, cost and power consumption is also a challenge. Components of the NOC such as network interfaces and routers can significantly increase chip area, cost and power consumption.

Uploaded by

Mehul_Singh_7900
Copyright
© Attribution Non-Commercial (BY-NC)
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Download as DOC, PDF, TXT or read online on Scribd
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NOC Issues and Challenges

To enhance system productivity, it is very important that an architect be able to


abstract, represent and address most of the design issues and concerns at a
high level of abstraction. System-level design affords one the opportunity to
review several different software-hardware architectures that meet the functional
specifications equally well, to quickly trade-off among different QoS metrics such
as latency, power, cost, size and ease of integration. Similarly, there are several
issues related to NOC, such as the nature of the NOC link, link length, serial vs
parallel links, bus vs packet-based switching, and leakage currents. In this
section, we discuss these issues.

Serial vs Parallel Link


The transportation of data packets among various cores in a NOC can be
performed by the use of either a serial or a parallel link. Parallel links make use
of a buffer-based architecture and can be operated at a relatively lower clock rate
in order to reduce power dissipation. However, these parallel links will incur high
silicon cost due to inter-wire spacing, shielding and repeaters. This can be
minimized up to a certain limit by employing multiple metal layers. On the other
hand, serial links allow savings in wire area, reduction in signal interference and
noise, and further eliminate the need for having buffers. However, serial links
would need serializer and de-serializer circuits to convert the data into the right
format to be transported over the link and back to the cores. Serial links offer the
advantages of a simpler layout and simpler timing verification. Serial links
sometimes suffer from ISI (Inter-symbol Interference) between successive
signals while operating at high clock rates. Nevertheless, such drawbacks can be
addressed by encoding and with asynchronous communication protocols.

Interconnect Optimization
Communication in a NOC is based on modules connected via a network of
routers with links between the routers that comprise of long interconnects. Thus it
is very important to optimize interconnects in order to achieve the required
system performance. Timing optimization of global wires is typically performed by
repeater insertion. Repeaters result in a significant increase in cost, area, and
power consumption. Recent studies indicate that in the near future, inverters
operating as repeaters [58] will use a large portion of chip resources. Thus, there
is a need for optimizing power on the NOC. Techniques for reducing dynamic
power consumption include approaches discussed in [59], [60], [61]. Encoding is
another effective way of reducing dynamic power consumption [62]. In order to
make NOC architectures more effective, innovative ways will have to be
introduced to minimize the power consumed by the on-chip repeaters.

Leakage Power Consumption


The leakage current, which was negligible relative to the dynamic switching
current at larger transistor sizes (of 1 micron or more), is expected to dominate
the current drain at sub-100 nm technologies. In a NOC, the link utilization rates
vary and in many cases are very low, reaching a few percentage points.
Networks are designed to operate at low link utilization in order to meet worst
case scenario requirements, and thus having a higher link capacity helps reduce
packet collisions. However, even when NOC links are idle they still will consume
power in repeaters, due to the dominance of this leakage current at small feature
sizes. Thus, new techniques will have to evolve which will help reduce the
leakage power consumption to make the NOC architecture more effective.

Router Architecture
For embedded systems such as handheld devices, cost is a major driving force
for the success of the product and therefore the underlying architecture as well.
Along with being cost effective, handheld systems are required to be of small
size and to consume significantly less power, relative to desktop systems. Under
such considerations, there is a clear tradeoff in the design of a routing protocol. A
complex routing protocol would further complicate the design of the router. This
will consume more power and area without being cost effective. A simpler routing
protocol will outperform in terms of cost and power consumption, but will be less
effective in routing traffic across the system.

Quality of Service Challenges


QoS parameters for a NOC include latency, cost, power consumption, and silicon
overhead in terms of the area that is required to support the packet switched
network. It is expected that various applications such as real-time, multimedia
and control, and computation-intensive algorithms such as video encoding and
decoding algorithms, 3-D gaming, and speech recognition, will be supported on a
NOC environment. Under such a scenario, NOC should be able to provide
various levels of support for these applications.
The NOC infrastructure must be able to guarantee a timely exchange of data
packets for a real-time application.
However, given a certain network size, large latency fluctuations for packet
delivery could be experienced because of network congestion. Such variability
and non-determinacy are obviously not acceptable for real-time applications.
One possible solution to this problem is over-dimensioning the network by adding
some redundant paths (links), nodes and buffers. These paths can be utilized
when the main network is congested. Another possible solution to this problem
would be to reserve some paths for real-time applications in order to guarantee a
timely delivery of data packets from one node to another. Both solutions are able
to overcome the latency problem but increase the power consumption and the
cost of NOC. A cost effective solution would be to provide priority levels to the
data traffic. Real-time traffic can be guaranteed its on-time delivery to its
destination by either reserving some paths for real-time data, or implementing
priority-based scheduling criteria. In such systems, we would be able to route the
data packet for a real-time application in time but a data packet belonging to a
lower priority application may be starved, without appropriate scheduling
algorithms.
The NOC infrastructure includes components responsible for packetization,
transmission, and de-packetization of data. These components, respectively, are
the NI, the VC router, and the links. These components are repeated for every
grid element in NOC. So, if we consider a NOC with 3×3 mesh network, then it
will have nine sets of components of NI, VC router and links. It can be clearly
seen that these components will occupy a significant amount of silicon space on
the chip and therefore the cost and the power consumption of the chip would
increase.
However, it must be noted that serial packet-based communication will still
remain an optimum solution as compared to a bus-based system in terms of the
power consumption and will reduce the cost of system design in the longer run
due to the potential for reuse

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